[llvm-branch-commits] [llvm] 3c1d015 - [GlobalISel][TableGen] Fix ConstrainOperandRC bug
Author: Gabriel Hjort Åkerlund
Date: 2021-01-05T09:30:04+01:00
New Revision: 3c1d015edc755e8f3fa9c2a92d0b9bc81ba4d5fd
URL:
https://github.com/llvm/llvm-project/commit/3c1d015edc755e8f3fa9c2a92d0b9bc81ba4d5fd
DIFF:
https://github.com/llvm/llvm-project/commit/3c1d015edc755e8f3fa9c2a92d0b9bc81ba4d5fd.diff
LOG: [GlobalISel][TableGen] Fix ConstrainOperandRC bug
TableGen would pick the largest RC for constraining the operands, which
could potentially be an unallocatable RC. This patch removes selection
of unallocatable RCs.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D93945
Added:
Modified:
llvm/test/TableGen/GlobalISelEmitterSubreg.td
llvm/utils/TableGen/CodeGenTarget.cpp
llvm/utils/TableGen/CodeGenTarget.h
llvm/utils/TableGen/GlobalISelEmitter.cpp
Removed:
diff --git a/llvm/test/TableGen/GlobalISelEmitterSubreg.td
b/llvm/test/TableGen/GlobalISelEmitterSubreg.td
index e8dc4a9ac4a0..2865cbc70038 100644
--- a/llvm/test/TableGen/GlobalISelEmitterSubreg.td
+++ b/llvm/test/TableGen/GlobalISelEmitterSubreg.td
@@ -36,6 +36,11 @@ def SOME_INSN : I<(outs DRegs:$dst), (ins DOP:$src), []>;
def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>;
def SUBSOME_INSN2 : I<(outs SRegs:$dst), (ins SOP:$src), []>;
+// Adding this enables the tests below to check that we are not using this
class
+// for constraining the operand register classes, since it is unallocatable.
+let isAllocatable = 0 in
+def SuperDRegs : MyClass<32, [i32], (add DRegs, ERegs)>;
+
// We should skip cases where we don't have a given register class for the
// subregister source.
// SKIPPED: def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32
(IMPLICIT_DEF)), i16:$src, sub0)>;
diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp
b/llvm/utils/TableGen/CodeGenTarget.cpp
index 37bce3afa05a..2ed29b10fba6 100644
--- a/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/CodeGenTarget.cpp
@@ -344,7 +344,8 @@ CodeGenRegBank &CodeGenTarget::getRegBank() const {
Optional
CodeGenTarget::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy,
CodeGenRegBank &RegBank,
-const CodeGenSubRegIndex *SubIdx) const {
+const CodeGenSubRegIndex *SubIdx,
+bool MustBeAllocatable) const {
std::vector Candidates;
auto &RegClasses = RegBank.getRegClasses();
@@ -360,6 +361,10 @@ CodeGenTarget::getSuperRegForSubReg(const
ValueTypeByHwMode &ValueTy,
if (!llvm::is_contained(SubClassWithSubReg->VTs, ValueTy))
continue;
+// If necessary, check that it is allocatable.
+if (MustBeAllocatable && !SubClassWithSubReg->Allocatable)
+ continue;
+
// We have a register class which supports both the value type and
// subregister index. Remember it.
Candidates.push_back(SubClassWithSubReg);
diff --git a/llvm/utils/TableGen/CodeGenTarget.h
b/llvm/utils/TableGen/CodeGenTarget.h
index cc5bbe7a8bfe..1852bac15511 100644
--- a/llvm/utils/TableGen/CodeGenTarget.h
+++ b/llvm/utils/TableGen/CodeGenTarget.h
@@ -111,7 +111,8 @@ class CodeGenTarget {
/// covers \p SubIdx if it exists.
Optional
getSuperRegForSubReg(const ValueTypeByHwMode &Ty, CodeGenRegBank &RegBank,
- const CodeGenSubRegIndex *SubIdx) const;
+ const CodeGenSubRegIndex *SubIdx,
+ bool MustBeAllocatable = false) const;
/// getRegisterByName - If there is a register with the specific AsmName,
/// return it.
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp
b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 07130e4e0ab7..29ca558580fe 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -4998,7 +4998,8 @@ GlobalISelEmitter::inferSuperRegisterClass(const
TypeSetByHwMode &Ty,
// Use the information we found above to find a minimal register class which
// supports the subregister and type we want.
auto RC =
- Target.getSuperRegForSubReg(Ty.getValueTypeByHwMode(), CGRegs, SubIdx);
+ Target.getSuperRegForSubReg(Ty.getValueTypeByHwMode(), CGRegs, SubIdx,
+ /* MustBeAllocatable */ true);
if (!RC)
return None;
return *RC;
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[llvm-branch-commits] [llvm] 2654f33 - [VE] Support llvm.eh.sjlj.lsda
Author: Kazushi (Jam) Marukawa
Date: 2021-01-05T18:06:14+09:00
New Revision: 2654f33c47f44b05351422e61c94afa5a6d6afe5
URL:
https://github.com/llvm/llvm-project/commit/2654f33c47f44b05351422e61c94afa5a6d6afe5
DIFF:
https://github.com/llvm/llvm-project/commit/2654f33c47f44b05351422e61c94afa5a6d6afe5.diff
LOG: [VE] Support llvm.eh.sjlj.lsda
In order to support SJLJ exception, implement llvm.eh.sjlj.lsda first.
Add regression test also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D93811
Added:
llvm/test/CodeGen/VE/Scalar/builtin_sjlj_lsda.ll
Modified:
llvm/lib/Target/VE/VEISelLowering.cpp
llvm/lib/Target/VE/VEISelLowering.h
Removed:
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp
b/llvm/lib/Target/VE/VEISelLowering.cpp
index 5a3a9f504e30..10b99ac031b3 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -275,6 +275,9 @@ void VETargetLowering::initSPUActions() {
}
/// } Atomic isntructions
+
+ // Intrinsic instructions
+ setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
}
void VETargetLowering::initVPUActions() {
@@ -1525,6 +1528,37 @@ static SDValue lowerRETURNADDR(SDValue Op, SelectionDAG
&DAG,
MachinePointerInfo());
}
+SDValue VETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc DL(Op);
+ unsigned IntNo = cast(Op.getOperand(0))->getZExtValue();
+ switch (IntNo) {
+ default: // Don't custom lower most intrinsics.
+return SDValue();
+ case Intrinsic::eh_sjlj_lsda: {
+MachineFunction &MF = DAG.getMachineFunction();
+MVT VT = Op.getSimpleValueType();
+const VETargetMachine *TM =
+static_cast(&DAG.getTarget());
+
+// Create GCC_except_tableXX string. The real symbol for that will be
+// generated in EHStreamer::emitExceptionTable() later. So, we just
+// borrow it's name here.
+TM->getStrList()->push_back(std::string(
+(Twine("GCC_except_table") + Twine(MF.getFunctionNumber())).str()));
+SDValue Addr =
+DAG.getTargetExternalSymbol(TM->getStrList()->back().c_str(), VT, 0);
+if (isPositionIndependent()) {
+ Addr = makeHiLoPair(Addr, VEMCExpr::VK_VE_GOTOFF_HI32,
+ VEMCExpr::VK_VE_GOTOFF_LO32, DAG);
+ SDValue GlobalBase = DAG.getNode(VEISD::GLOBAL_BASE_REG, DL, VT);
+ return DAG.getNode(ISD::ADD, DL, VT, GlobalBase, Addr);
+}
+return makeHiLoPair(Addr, VEMCExpr::VK_VE_HI32, VEMCExpr::VK_VE_LO32, DAG);
+ }
+ }
+}
+
static SDValue getSplatValue(SDNode *N) {
if (auto *BuildVec = dyn_cast(N)) {
return BuildVec->getSplatValue();
@@ -1571,6 +1605,8 @@ SDValue VETargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
return lowerGlobalAddress(Op, DAG);
case ISD::GlobalTLSAddress:
return lowerGlobalTLSAddress(Op, DAG);
+ case ISD::INTRINSIC_WO_CHAIN:
+return lowerINTRINSIC_WO_CHAIN(Op, DAG);
case ISD::JumpTable:
return lowerJumpTable(Op, DAG);
case ISD::LOAD:
diff --git a/llvm/lib/Target/VE/VEISelLowering.h
b/llvm/lib/Target/VE/VEISelLowering.h
index b5e2a72887f4..eec4532ffa3a 100644
--- a/llvm/lib/Target/VE/VEISelLowering.h
+++ b/llvm/lib/Target/VE/VEISelLowering.h
@@ -115,6 +115,7 @@ class VETargetLowering : public TargetLowering {
SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
+ SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/test/CodeGen/VE/Scalar/builtin_sjlj_lsda.ll
b/llvm/test/CodeGen/VE/Scalar/builtin_sjlj_lsda.ll
new file mode 100644
index ..d3da4ce971aa
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Scalar/builtin_sjlj_lsda.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -mtriple=ve -exception-model sjlj | FileCheck %s
+
+; Function Attrs: noinline nounwind optnone
+define i8* @test_lsda() {
+; CHECK-LABEL: test_lsda:
+; CHECK: # %bb.0:
+; CHECK-NEXT:lea %s0, GCC_except_table0@lo
+; CHECK-NEXT:and %s0, %s0, (32)0
+; CHECK-NEXT:lea.sl %s0, GCC_except_table0@hi(, %s0)
+; CHECK-NEXT:b.l.t (, %s10)
+ %ret = call i8* @llvm.eh.sjlj.lsda()
+ ret i8* %ret
+}
+
+; Function Attrs: nounwind
+declare i8* @llvm.eh.sjlj.lsda()
___
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[llvm-branch-commits] [clang] 6725860 - Sema::BuildCallExpr - use cast<> instead of dyn_cast<> for dereferenced pointer. NFCI.
Author: Simon Pilgrim Date: 2021-01-05T09:34:00Z New Revision: 6725860d21a03741d6c3331ab0560416bb19e068 URL: https://github.com/llvm/llvm-project/commit/6725860d21a03741d6c3331ab0560416bb19e068 DIFF: https://github.com/llvm/llvm-project/commit/6725860d21a03741d6c3331ab0560416bb19e068.diff LOG: Sema::BuildCallExpr - use cast<> instead of dyn_cast<> for dereferenced pointer. NFCI. We're immediately dereferencing the casted pointer, so use cast<> which will assert instead of dyn_cast<> which can return null. Fixes static analyzer warning. Added: Modified: clang/lib/Sema/SemaExpr.cpp Removed: diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index 3992a373f721..28f4c5bbf19b 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -6484,7 +6484,7 @@ ExprResult Sema::BuildCallExpr(Scope *Scope, Expr *Fn, SourceLocation LParenLoc, "should only occur in error-recovery path."); QualType ReturnType = llvm::isa_and_nonnull(NDecl) -? dyn_cast(NDecl)->getCallResultType() +? cast(NDecl)->getCallResultType() : Context.DependentTy; return CallExpr::Create(Context, Fn, ArgExprs, ReturnType, Expr::getValueKindForType(ReturnType), RParenLoc, ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 52e4489 - SystemZTargetLowering::lowerDYNAMIC_STACKALLOC - use cast<> instead of dyn_cast<> for dereferenced pointer. NFCI.
Author: Simon Pilgrim
Date: 2021-01-05T09:34:01Z
New Revision: 52e448974b2ec826c8af429c370c4d6e79ce5747
URL:
https://github.com/llvm/llvm-project/commit/52e448974b2ec826c8af429c370c4d6e79ce5747
DIFF:
https://github.com/llvm/llvm-project/commit/52e448974b2ec826c8af429c370c4d6e79ce5747.diff
LOG: SystemZTargetLowering::lowerDYNAMIC_STACKALLOC - use cast<> instead of
dyn_cast<> for dereferenced pointer. NFCI.
We're immediately dereferencing the casted pointer, so use cast<> which will
assert instead of dyn_cast<> which can return null.
Fixes static analyzer warning.
Added:
Modified:
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
Removed:
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 663af1d64943..603446755aaf 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -3419,8 +3419,8 @@ lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
const {
// If user has set the no alignment function attribute, ignore
// alloca alignments.
- uint64_t AlignVal = (RealignOpt ?
- dyn_cast(Align)->getZExtValue() : 0);
+ uint64_t AlignVal =
+ (RealignOpt ? cast(Align)->getZExtValue() : 0);
uint64_t StackAlign = TFI->getStackAlignment();
uint64_t RequiredAlign = std::max(AlignVal, StackAlign);
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[llvm-branch-commits] [llvm] 84d5768 - MemProfiler::insertDynamicShadowAtFunctionEntry - use cast<> instead of dyn_cast<> for dereferenced pointer. NFCI.
Author: Simon Pilgrim
Date: 2021-01-05T09:34:01Z
New Revision: 84d5768d97635602225f5056da96b058e588b2f5
URL:
https://github.com/llvm/llvm-project/commit/84d5768d97635602225f5056da96b058e588b2f5
DIFF:
https://github.com/llvm/llvm-project/commit/84d5768d97635602225f5056da96b058e588b2f5.diff
LOG: MemProfiler::insertDynamicShadowAtFunctionEntry - use cast<> instead of
dyn_cast<> for dereferenced pointer. NFCI.
We're immediately dereferencing the casted pointer, so use cast<> which will
assert instead of dyn_cast<> which can return null.
Fixes static analyzer warning.
Added:
Modified:
llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
Removed:
diff --git a/llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
b/llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
index 56006bbc94c7..0e6a404a9e0b 100644
--- a/llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
+++ b/llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
@@ -577,7 +577,7 @@ bool
MemProfiler::insertDynamicShadowAtFunctionEntry(Function &F) {
Value *GlobalDynamicAddress = F.getParent()->getOrInsertGlobal(
MemProfShadowMemoryDynamicAddress, IntptrTy);
if (F.getParent()->getPICLevel() == PICLevel::NotPIC)
-dyn_cast(GlobalDynamicAddress)->setDSOLocal(true);
+cast(GlobalDynamicAddress)->setDSOLocal(true);
DynamicShadowOffset = IRB.CreateLoad(IntptrTy, GlobalDynamicAddress);
return true;
}
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[llvm-branch-commits] [clang] 02eb8e2 - Inform the consumer on invalid template instantiations.
Author: Vassil Vassilev
Date: 2021-01-05T09:43:38Z
New Revision: 02eb8e20b51b3ea263bbfe696241b8541c72ee7a
URL:
https://github.com/llvm/llvm-project/commit/02eb8e20b51b3ea263bbfe696241b8541c72ee7a
DIFF:
https://github.com/llvm/llvm-project/commit/02eb8e20b51b3ea263bbfe696241b8541c72ee7a.diff
LOG: Inform the consumer on invalid template instantiations.
Some clients which want to track state need the information whether a template
was instantiated and made invalid.
Differential revision: https://reviews.llvm.org/D92248
Added:
Modified:
clang/lib/Sema/SemaTemplateInstantiate.cpp
Removed:
diff --git a/clang/lib/Sema/SemaTemplateInstantiate.cpp
b/clang/lib/Sema/SemaTemplateInstantiate.cpp
index 39ea9e06e7b1..7e0cc2da2f58 100644
--- a/clang/lib/Sema/SemaTemplateInstantiate.cpp
+++ b/clang/lib/Sema/SemaTemplateInstantiate.cpp
@@ -2846,8 +2846,6 @@ Sema::InstantiateClass(SourceLocation
PointOfInstantiation,
SavedContext.pop();
if (!Instantiation->isInvalidDecl()) {
-Consumer.HandleTagDeclDefinition(Instantiation);
-
// Always emit the vtable for an explicit instantiation definition
// of a polymorphic class template specialization. Otherwise, eagerly
// instantiate only constexpr virtual functions in preparation for their
use
@@ -2859,6 +2857,8 @@ Sema::InstantiateClass(SourceLocation
PointOfInstantiation,
/*ConstexprOnly*/ true);
}
+ Consumer.HandleTagDeclDefinition(Instantiation);
+
return Instantiation->isInvalidDecl();
}
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[llvm-branch-commits] [llvm] 53a341a - [VE][NFC] Fix typo in comments
Author: Kazushi (Jam) Marukawa
Date: 2021-01-05T18:55:28+09:00
New Revision: 53a341a61d1fc2d0c455738a6a4d5f5d54a4e1d3
URL:
https://github.com/llvm/llvm-project/commit/53a341a61d1fc2d0c455738a6a4d5f5d54a4e1d3
DIFF:
https://github.com/llvm/llvm-project/commit/53a341a61d1fc2d0c455738a6a4d5f5d54a4e1d3.diff
LOG: [VE][NFC] Fix typo in comments
Added:
Modified:
llvm/lib/Target/VE/VEISelLowering.cpp
Removed:
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp
b/llvm/lib/Target/VE/VEISelLowering.cpp
index 10b99ac031b3..e83483dd13fb 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -257,7 +257,7 @@ void VETargetLowering::initSPUActions() {
// Support i8/i16 atomic swap.
setOperationAction(ISD::ATOMIC_SWAP, VT, Custom);
-// FIXME: Support "atmam" isntructions.
+// FIXME: Support "atmam" instructions.
setOperationAction(ISD::ATOMIC_LOAD_ADD, VT, Expand);
setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Expand);
setOperationAction(ISD::ATOMIC_LOAD_AND, VT, Expand);
@@ -274,7 +274,7 @@ void VETargetLowering::initSPUActions() {
setOperationAction(ISD::ATOMIC_LOAD_UMAX, VT, Expand);
}
- /// } Atomic isntructions
+ /// } Atomic instructions
// Intrinsic instructions
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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[llvm-branch-commits] [llvm] 9ad83fd - [WebAssembly] call_indirect causes indirect function table import
Author: Andy Wingo
Date: 2021-01-05T11:09:24+01:00
New Revision: 9ad83fd6dc46330dcdea8af36c435061a31ac0c5
URL:
https://github.com/llvm/llvm-project/commit/9ad83fd6dc46330dcdea8af36c435061a31ac0c5
DIFF:
https://github.com/llvm/llvm-project/commit/9ad83fd6dc46330dcdea8af36c435061a31ac0c5.diff
LOG: [WebAssembly] call_indirect causes indirect function table import
For wasm-ld table linking work to proceed, object files should indicate
if they use an indirect function table. In the future this will be done
by the usual symbols and relocations mechanism, but until that support
lands in the linker, the presence of an `__indirect_function_table` in
the object file's import section shows that the object file needs an
indirect function table.
Prior to https://reviews.llvm.org/D91637, this condition was met by all
object files residualizing an `__indirect_function_table` import.
Since https://reviews.llvm.org/D91637, the intention has been that only
those object files needing an indirect function table would have the
`__indirect_function_table` import. However, we missed the case of
object files which use the table via `call_indirect` but which
themselves do not declare any indirect functions.
This changeset makes it so that when we lower a call to `call_indirect`,
that we ensure that a `__indirect_function_table` symbol is present and
that it will be propagated to the linker.
A followup patch will revise this mechanism to make an explicit link
between `call_indirect` and its associated indirect function table; see
https://reviews.llvm.org/D90948.
Differential Revision: https://reviews.llvm.org/D92840
Added:
llvm/test/CodeGen/WebAssembly/call-indirect.ll
Modified:
llvm/lib/MC/WasmObjectWriter.cpp
llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
llvm/lib/Target/WebAssembly/WebAssemblyUtilities.cpp
llvm/lib/Target/WebAssembly/WebAssemblyUtilities.h
llvm/test/MC/WebAssembly/type-index.s
Removed:
diff --git a/llvm/lib/MC/WasmObjectWriter.cpp
b/llvm/lib/MC/WasmObjectWriter.cpp
index c8d2e5dbdbdc..683678b70ebc 100644
--- a/llvm/lib/MC/WasmObjectWriter.cpp
+++ b/llvm/lib/MC/WasmObjectWriter.cpp
@@ -405,6 +405,13 @@ void WasmObjectWriter::writeHeader(const MCAssembler &Asm)
{
void WasmObjectWriter::executePostLayoutBinding(MCAssembler &Asm,
const MCAsmLayout &Layout) {
+ // As a stopgap measure until call_indirect instructions start explicitly
+ // referencing the indirect function table via TABLE_NUMBER relocs, ensure
+ // that the indirect function table import makes it to the output if anything
+ // in the compilation unit has caused it to be present.
+ if (auto *Sym = Asm.getContext().lookupSymbol("__indirect_function_table"))
+Asm.registerSymbol(*Sym);
+
// Build a map of sections to the function that defines them, for use
// in recordRelocation.
for (const MCSymbol &S : Asm.symbols()) {
diff --git a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
index 55f79bafe414..18d7b642e044 100644
--- a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
+++ b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
@@ -160,6 +160,24 @@ struct WebAssemblyOperand : public MCParsedAsmOperand {
}
};
+static MCSymbolWasm *GetOrCreateFunctionTableSymbol(MCContext &Ctx,
+const StringRef &Name) {
+ // FIXME: Duplicates functionality from
+ // MC/WasmObjectWriter::recordRelocation, as well as WebAssemblyCodegen's
+ // WebAssembly:getOrCreateFunctionTableSymbol.
+ MCSymbolWasm *Sym = cast_or_null(Ctx.lookupSymbol(Name));
+ if (Sym) {
+if (!Sym->isFunctionTable())
+ Ctx.reportError(SMLoc(), "symbol is not a wasm funcref table");
+ } else {
+Sym = cast(Ctx.getOrCreateSymbol(Name));
+Sym->setFunctionTable();
+// The default function table is synthesized by the linker.
+Sym->setUndefined();
+ }
+ return Sym;
+}
+
class WebAssemblyAsmParser final : public MCTargetAsmParser {
MCAsmParser &Parser;
MCAsmLexer &Lexer;
@@ -531,6 +549,15 @@ class WebAssemblyAsmParser final : public
MCTargetAsmParser {
return true;
} else if (Name == "call_indirect" || Name == "return_call_indirect") {
ExpectFuncType = true;
+ // Ensure that the object file has a __indirect_function_table import, as
+ // we call_indirect against it.
+ auto &Ctx = getStreamer().getContext();
+ MCSymbolWasm *Sym =
+ GetOrCreateFunctionTableSymbol(Ctx, "__indirect_function_table");
+ // Until call_indirect emits TABLE_NUMBER relocs against this symbol,
mark
+ // it as NO_STRIP so as to ensure that the ind
[llvm-branch-commits] [llvm] 914066f - [DebugInfo] Avoid LSR crash on large integer inputs
Author: Jeremy Morse
Date: 2021-01-05T10:25:37Z
New Revision: 914066fe38a93c004b742a696ec337701eb738ec
URL:
https://github.com/llvm/llvm-project/commit/914066fe38a93c004b742a696ec337701eb738ec
DIFF:
https://github.com/llvm/llvm-project/commit/914066fe38a93c004b742a696ec337701eb738ec.diff
LOG: [DebugInfo] Avoid LSR crash on large integer inputs
Loop strength reduction tries to recover debug variable values by looking
for simple offsets from PHI values. In really extreme conditions there may
be an offset used that won't fit in an int64_t, hitting an APInt assertion.
This patch adds a regression test and adjusts the equivalent value
collecting code to filter out any values where the offset can't be
represented by an int64_t. This means that for very large integers with
very large offsets, the variable location will become undef, which is the
same behaviour as before 2a6782bb9f1 / D87494.
Differential Revision: https://reviews.llvm.org/D94016
Added:
llvm/test/Transforms/LoopStrengthReduce/dbg-preserve-1.ll
Modified:
llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Removed:
diff --git a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
index 7742ebafcac4..6e64a1ddf787 100644
--- a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
@@ -5796,8 +5796,9 @@ static void DbgGatherEqualValues(Loop *L, ScalarEvolution
&SE,
if (!SE.isSCEVable(Phi.getType()))
continue;
auto PhiSCEV = SE.getSCEV(&Phi);
-if (Optional Offset =
-SE.computeConstantDifference(DbgValueSCEV, PhiSCEV))
+Optional Offset =
+SE.computeConstantDifference(DbgValueSCEV, PhiSCEV);
+if (Offset && Offset->getMinSignedBits() <= 64)
EqSet.emplace_back(std::make_tuple(
&Phi, Offset.getValue().getSExtValue(), DVI->getExpression()));
}
diff --git a/llvm/test/Transforms/LoopStrengthReduce/dbg-preserve-1.ll
b/llvm/test/Transforms/LoopStrengthReduce/dbg-preserve-1.ll
new file mode 100644
index ..d651ff239a46
--- /dev/null
+++ b/llvm/test/Transforms/LoopStrengthReduce/dbg-preserve-1.ll
@@ -0,0 +1,73 @@
+; RUN: opt < %s -loop-reduce -S | FileCheck %s
+;
+; Test that LSR avoids crashing on very large integer inputs. It should
+; discard the variable location by creating an undef dbg.value.
+;
+; CHECK: call void @llvm.dbg.value(metadata i128 undef,
+
+source_filename = ""
+target datalayout =
"e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define dso_local void @qux() local_unnamed_addr !dbg !10 {
+entry:
+ br label %for.body, !dbg !17
+
+for.body: ; preds =
%for.body.for.body_crit_edge, %entry
+ %0 = phi i128 [ 0, %entry ], [ %.pre8, %for.body.for.body_crit_edge ], !dbg
!19
+ %add6.i.i = add i128 %0, 18446744073709551615, !dbg !35
+ call void @llvm.dbg.value(metadata i128 %add6.i.i, metadata !25, metadata
!DIExpression(DW_OP_LLVM_fragment, 0, 128)), !dbg !36
+ br label %for.body.for.body_crit_edge
+
+for.body.for.body_crit_edge: ; preds = %for.body
+ %.pre8 = load i128, i128* undef, align 16, !dbg !19, !tbaa !37
+ br label %for.body, !dbg !17
+}
+
+; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
+declare void @llvm.dbg.value(metadata, metadata, metadata)
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!7, !8, !9}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer:
"clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums:
!2, retainedTypes: !3, globals: !2, splitDebugInlining: false, nameTableKind:
None)
+!1 = !DIFile(filename: "/tmp/beans.c", directory: "/tmp")
+!2 = !{}
+!3 = !{!4}
+!4 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint64_t", file: !5, line: 1,
baseType: !6)
+!5 = !DIFile(filename: "/tmp/beans.c", directory: "")
+!6 = !DIBasicType(name: "long unsigned int", size: 64, encoding:
DW_ATE_unsigned)
+!7 = !{i32 7, !"Dwarf Version", i32 4}
+!8 = !{i32 2, !"Debug Info Version", i32 3}
+!9 = !{i32 1, !"wchar_size", i32 4}
+!10 = distinct !DISubprogram(name: "qux", scope: !5, file: !5, line: 27, type:
!11, scopeLine: 27, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags:
DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !2)
+!11 = !DISubroutineType(types: !12)
+!12 = !{null, !13, !13}
+!13 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !14, size: 64)
+!14 = !DIDerivedType(tag: DW_TAG_typedef, name: "croix", file: !5, line: 2,
baseType: !15)
+!15 = !DIDerivedType(tag: DW_TAG_typedef, name: "__uint128_t", file: !1,
baseType: !16)
+!16 = !DIBasicType(name: "unsigned __int128", size: 128, encoding:
DW_ATE_unsigned)
+!17 = !DILocation(line: 30, column: 3, scope: !18)
+
[llvm-branch-commits] [llvm] 7a97eeb - [Coroutines] checkAsyncFuncPointer - use cast<> instead of dyn_cast<> for dereferenced pointer. NFCI.
Author: Simon Pilgrim
Date: 2021-01-05T10:31:45Z
New Revision: 7a97eeb197a8023acbb800d40b3bb852fc2f5d60
URL:
https://github.com/llvm/llvm-project/commit/7a97eeb197a8023acbb800d40b3bb852fc2f5d60
DIFF:
https://github.com/llvm/llvm-project/commit/7a97eeb197a8023acbb800d40b3bb852fc2f5d60.diff
LOG: [Coroutines] checkAsyncFuncPointer - use cast<> instead of dyn_cast<> for
dereferenced pointer. NFCI.
We're immediately dereferencing the casted pointer, so use cast<> which will
assert instead of dyn_cast<> which can return null.
Fixes static analyzer warning.
Added:
Modified:
llvm/lib/Transforms/Coroutines/Coroutines.cpp
Removed:
diff --git a/llvm/lib/Transforms/Coroutines/Coroutines.cpp
b/llvm/lib/Transforms/Coroutines/Coroutines.cpp
index f0095a649b0c..6699a5c46313 100644
--- a/llvm/lib/Transforms/Coroutines/Coroutines.cpp
+++ b/llvm/lib/Transforms/Coroutines/Coroutines.cpp
@@ -676,8 +676,8 @@ static void checkAsyncFuncPointer(const Instruction *I,
Value *V) {
if (!AsyncFuncPtrAddr)
fail(I, "llvm.coro.id.async async function pointer not a global", V);
- auto *StructTy = dyn_cast(
- AsyncFuncPtrAddr->getType()->getPointerElementType());
+ auto *StructTy =
+ cast(AsyncFuncPtrAddr->getType()->getPointerElementType());
if (StructTy->isOpaque() || !StructTy->isPacked() ||
StructTy->getNumElements() != 2 ||
!StructTy->getElementType(0)->isIntegerTy(32) ||
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[llvm-branch-commits] [llvm] a000366 - [SimplifyIndVar] createWideIV - make WideIVInfo arg a const ref. NFCI.
Author: Simon Pilgrim
Date: 2021-01-05T10:31:45Z
New Revision: a000366d0502b35fc0d3b113ace7f0e3bbdc08cd
URL:
https://github.com/llvm/llvm-project/commit/a000366d0502b35fc0d3b113ace7f0e3bbdc08cd
DIFF:
https://github.com/llvm/llvm-project/commit/a000366d0502b35fc0d3b113ace7f0e3bbdc08cd.diff
LOG: [SimplifyIndVar] createWideIV - make WideIVInfo arg a const ref. NFCI.
The WideIVInfo arg is only ever used as a const.
Fixes cppcheck warning.
Added:
Modified:
llvm/include/llvm/Transforms/Utils/SimplifyIndVar.h
llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
Removed:
diff --git a/llvm/include/llvm/Transforms/Utils/SimplifyIndVar.h
b/llvm/include/llvm/Transforms/Utils/SimplifyIndVar.h
index 4599627b65f5..4ba56fb45afa 100644
--- a/llvm/include/llvm/Transforms/Utils/SimplifyIndVar.h
+++ b/llvm/include/llvm/Transforms/Utils/SimplifyIndVar.h
@@ -74,7 +74,7 @@ struct WideIVInfo {
/// Widen Induction Variables - Extend the width of an IV to cover its
/// widest uses.
-PHINode *createWideIV(WideIVInfo &WI,
+PHINode *createWideIV(const WideIVInfo &WI,
LoopInfo *LI, ScalarEvolution *SE, SCEVExpander &Rewriter,
DominatorTree *DT, SmallVectorImpl &DeadInsts,
unsigned &NumElimExt, unsigned &NumWidened,
diff --git a/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
b/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
index f3b198094bd1..290c04a7ad10 100644
--- a/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
@@ -2076,7 +2076,7 @@ void WidenIV::calculatePostIncRanges(PHINode *OrigPhi) {
}
}
-PHINode *llvm::createWideIV(WideIVInfo &WI,
+PHINode *llvm::createWideIV(const WideIVInfo &WI,
LoopInfo *LI, ScalarEvolution *SE, SCEVExpander &Rewriter,
DominatorTree *DT, SmallVectorImpl &DeadInsts,
unsigned &NumElimExt, unsigned &NumWidened,
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[llvm-branch-commits] [llvm] 38c6933 - [LV] Simplify lambda in all_of to directly return hasVF() result. (NFC)
Author: Florian Hahn
Date: 2021-01-05T10:34:06Z
New Revision: 38c6933dcc9660b0c00f00ae62345339010dc764
URL:
https://github.com/llvm/llvm-project/commit/38c6933dcc9660b0c00f00ae62345339010dc764
DIFF:
https://github.com/llvm/llvm-project/commit/38c6933dcc9660b0c00f00ae62345339010dc764.diff
LOG: [LV] Simplify lambda in all_of to directly return hasVF() result. (NFC)
The if in the lambda is not necessary. We can directly return the result
of hasVF.
Added:
Modified:
llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
Removed:
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
index a61a1454aee1..1795470fa58c 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
@@ -274,9 +274,7 @@ class LoopVectorizationPlanner {
bool hasPlanWithVFs(const ArrayRef VFs) const {
return any_of(VPlans, [&](const VPlanPtr &Plan) {
return all_of(VFs, [&](const ElementCount &VF) {
-if (Plan->hasVF(VF))
- return true;
-return false;
+return Plan->hasVF(VF);
});
});
}
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[llvm-branch-commits] [llvm] eba6dea - [SVE] Lower vector CTLZ, CTPOP and CTTZ operations.
Author: Paul Walker
Date: 2021-01-05T10:42:35Z
New Revision: eba6deab22b576004a209b3f42ccc5e58f7603bf
URL:
https://github.com/llvm/llvm-project/commit/eba6deab22b576004a209b3f42ccc5e58f7603bf
DIFF:
https://github.com/llvm/llvm-project/commit/eba6deab22b576004a209b3f42ccc5e58f7603bf.diff
LOG: [SVE] Lower vector CTLZ, CTPOP and CTTZ operations.
CTLZ and CTPOP are lowered to CLZ and CNT instructions respectively.
CTTZ is not a native SVE operation but is instead lowered to:
CTTZ(V) => CTLZ(BITREVERSE(V))
In the case of fixed-length support using SVE we also lower CTTZ
operating on NEON sized vectors because of its reliance on
BITREVERSE which is also lowered to SVE intructions at these lengths.
Differential Revision: https://reviews.llvm.org/D93607
Added:
llvm/test/CodeGen/AArch64/sve-bit-counting.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll
Modified:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/SVEInstrFormats.td
Removed:
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 2012f1247a0f..faed7c64a15e 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -184,6 +184,8 @@ static bool isMergePassthruOpcode(unsigned Opc) {
return false;
case AArch64ISD::BITREVERSE_MERGE_PASSTHRU:
case AArch64ISD::BSWAP_MERGE_PASSTHRU:
+ case AArch64ISD::CTLZ_MERGE_PASSTHRU:
+ case AArch64ISD::CTPOP_MERGE_PASSTHRU:
case AArch64ISD::DUP_MERGE_PASSTHRU:
case AArch64ISD::FNEG_MERGE_PASSTHRU:
case AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU:
@@ -1070,6 +1072,9 @@ AArch64TargetLowering::AArch64TargetLowering(const
TargetMachine &TM,
for (auto VT : {MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64}) {
setOperationAction(ISD::BITREVERSE, VT, Custom);
setOperationAction(ISD::BSWAP, VT, Custom);
+ setOperationAction(ISD::CTLZ, VT, Custom);
+ setOperationAction(ISD::CTPOP, VT, Custom);
+ setOperationAction(ISD::CTTZ, VT, Custom);
setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
setOperationAction(ISD::UINT_TO_FP, VT, Custom);
setOperationAction(ISD::SINT_TO_FP, VT, Custom);
@@ -1188,6 +1193,9 @@ AArch64TargetLowering::AArch64TargetLowering(const
TargetMachine &TM,
// These operations are not supported on NEON but SVE can do them.
setOperationAction(ISD::BITREVERSE, MVT::v1i64, Custom);
+ setOperationAction(ISD::CTLZ, MVT::v1i64, Custom);
+ setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
+ setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
setOperationAction(ISD::MUL, MVT::v1i64, Custom);
setOperationAction(ISD::MUL, MVT::v2i64, Custom);
setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
@@ -1223,6 +1231,7 @@ AArch64TargetLowering::AArch64TargetLowering(const
TargetMachine &TM,
for (auto VT : {MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16,
MVT::v2i32, MVT::v4i32, MVT::v2i64}) {
setOperationAction(ISD::BITREVERSE, VT, Custom);
+setOperationAction(ISD::CTTZ, VT, Custom);
setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
@@ -1338,6 +1347,9 @@ void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT
VT) {
setOperationAction(ISD::ANY_EXTEND, VT, Custom);
setOperationAction(ISD::BITREVERSE, VT, Custom);
setOperationAction(ISD::BSWAP, VT, Custom);
+ setOperationAction(ISD::CTLZ, VT, Custom);
+ setOperationAction(ISD::CTPOP, VT, Custom);
+ setOperationAction(ISD::CTTZ, VT, Custom);
setOperationAction(ISD::FADD, VT, Custom);
setOperationAction(ISD::FCEIL, VT, Custom);
setOperationAction(ISD::FDIV, VT, Custom);
@@ -1944,6 +1956,8 @@ const char
*AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
MAKE_CASE(AArch64ISD::STNP)
MAKE_CASE(AArch64ISD::BITREVERSE_MERGE_PASSTHRU)
MAKE_CASE(AArch64ISD::BSWAP_MERGE_PASSTHRU)
+MAKE_CASE(AArch64ISD::CTLZ_MERGE_PASSTHRU)
+MAKE_CASE(AArch64ISD::CTPOP_MERGE_PASSTHRU)
MAKE_CASE(AArch64ISD::DUP_MERGE_PASSTHRU)
MAKE_CASE(AArch64ISD::INDEX_VECTOR)
MAKE_CASE(AArch64ISD::UABD)
@@ -3577,6 +3591,17 @@ SDValue
AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::aarch64_sve_ptrue:
return DAG.getNode(AArch64ISD::PTRUE, dl, Op.getValueType(),
Op.getOperand(1));
+ case Intrinsic::aarch64_sve_clz:
+return DAG.getNode(AArch64ISD::CTLZ_MERGE_PASSTHRU, dl, Op.getValueType(),
+ Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
+ case Intrinsic::aarch64_sve_cnt: {
+
[llvm-branch-commits] [llvm] 313d982 - [IR] Add ConstantInt::getBool helpers to wrap getTrue/getFalse.
Author: Simon Pilgrim
Date: 2021-01-05T11:01:10Z
New Revision: 313d982df65a7a8f1da2da5f0e03e6b6e301ce3c
URL:
https://github.com/llvm/llvm-project/commit/313d982df65a7a8f1da2da5f0e03e6b6e301ce3c
DIFF:
https://github.com/llvm/llvm-project/commit/313d982df65a7a8f1da2da5f0e03e6b6e301ce3c.diff
LOG: [IR] Add ConstantInt::getBool helpers to wrap getTrue/getFalse.
Added:
Modified:
llvm/include/llvm/IR/Constants.h
llvm/lib/IR/Constants.cpp
llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
Removed:
diff --git a/llvm/include/llvm/IR/Constants.h
b/llvm/include/llvm/IR/Constants.h
index 3fbbf53c29b4..ac802232c23d 100644
--- a/llvm/include/llvm/IR/Constants.h
+++ b/llvm/include/llvm/IR/Constants.h
@@ -88,8 +88,10 @@ class ConstantInt final : public ConstantData {
static ConstantInt *getTrue(LLVMContext &Context);
static ConstantInt *getFalse(LLVMContext &Context);
+ static ConstantInt *getBool(LLVMContext &Context, bool V);
static Constant *getTrue(Type *Ty);
static Constant *getFalse(Type *Ty);
+ static Constant *getBool(Type *Ty, bool V);
/// If Ty is a vector type, return a Constant with a splat of the given
/// value. Otherwise return a ConstantInt for the given value.
diff --git a/llvm/lib/IR/Constants.cpp b/llvm/lib/IR/Constants.cpp
index 82a5f9db0bf7..a38302d17937 100644
--- a/llvm/lib/IR/Constants.cpp
+++ b/llvm/lib/IR/Constants.cpp
@@ -815,6 +815,10 @@ ConstantInt *ConstantInt::getFalse(LLVMContext &Context) {
return pImpl->TheFalseVal;
}
+ConstantInt *ConstantInt::getBool(LLVMContext &Context, bool V) {
+ return V ? getTrue(Context) : getFalse(Context);
+}
+
Constant *ConstantInt::getTrue(Type *Ty) {
assert(Ty->isIntOrIntVectorTy(1) && "Type not i1 or vector of i1.");
ConstantInt *TrueC = ConstantInt::getTrue(Ty->getContext());
@@ -831,6 +835,10 @@ Constant *ConstantInt::getFalse(Type *Ty) {
return FalseC;
}
+Constant *ConstantInt::getBool(Type *Ty, bool V) {
+ return V ? getTrue(Ty) : getFalse(Ty);
+}
+
// Get a ConstantInt from an APInt.
ConstantInt *ConstantInt::get(LLVMContext &Context, const APInt &V) {
// get an existing value or the insertion position
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index 83b310bfcd05..87d4b40a9a64 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -5037,11 +5037,9 @@ Instruction
*InstCombinerImpl::foldICmpUsingKnownBits(ICmpInst &I) {
llvm_unreachable("Unknown icmp opcode!");
case ICmpInst::ICMP_EQ:
case ICmpInst::ICMP_NE: {
-if (Op0Max.ult(Op1Min) || Op0Min.ugt(Op1Max)) {
- return Pred == CmpInst::ICMP_EQ
- ? replaceInstUsesWith(I, ConstantInt::getFalse(I.getType()))
- : replaceInstUsesWith(I, ConstantInt::getTrue(I.getType()));
-}
+if (Op0Max.ult(Op1Min) || Op0Min.ugt(Op1Max))
+ return replaceInstUsesWith(
+ I, ConstantInt::getBool(I.getType(), Pred == CmpInst::ICMP_NE));
// If all bits are known zero except for one, then we know at most one bit
// is set. If the comparison is against zero, then this is a check to see
if
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[llvm-branch-commits] [llvm] f784be0 - [VE] Support SJLJ exception related instructions
Author: Kazushi (Jam) Marukawa
Date: 2021-01-05T20:19:15+09:00
New Revision: f784be0777f34a5b3bc3da6892ca242de7840fce
URL:
https://github.com/llvm/llvm-project/commit/f784be0777f34a5b3bc3da6892ca242de7840fce
DIFF:
https://github.com/llvm/llvm-project/commit/f784be0777f34a5b3bc3da6892ca242de7840fce.diff
LOG: [VE] Support SJLJ exception related instructions
Support EH_SJLJ_LONGJMP, EH_SJLJ_SETJMP, and EH_SJLJ_SETUP_DISPATCH
for SjLj exception handling. NC++ uses SjLj exception handling, so
implement it first. Add regression tests also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D94071
Added:
llvm/lib/Target/VE/VEInstrBuilder.h
llvm/test/CodeGen/VE/Scalar/builtin_sjlj.ll
llvm/test/CodeGen/VE/Scalar/builtin_sjlj_bp.ll
llvm/test/CodeGen/VE/Scalar/builtin_sjlj_callsite.ll
llvm/test/CodeGen/VE/Scalar/builtin_sjlj_landingpad.ll
Modified:
llvm/lib/Target/VE/VEISelLowering.cpp
llvm/lib/Target/VE/VEISelLowering.h
llvm/lib/Target/VE/VEInstrInfo.td
Removed:
llvm/test/CodeGen/VE/Scalar/sjlj_except.ll
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp
b/llvm/lib/Target/VE/VEISelLowering.cpp
index e83483dd13fb..230ce42d46b3 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -13,6 +13,7 @@
#include "VEISelLowering.h"
#include "MCTargetDesc/VEMCExpr.h"
+#include "VEInstrBuilder.h"
#include "VEMachineFunctionInfo.h"
#include "VERegisterInfo.h"
#include "VETargetMachine.h"
@@ -276,6 +277,14 @@ void VETargetLowering::initSPUActions() {
/// } Atomic instructions
+ /// SJLJ instructions {
+ setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
+ setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
+ setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
+ if (TM.Options.ExceptionModel == ExceptionHandling::SjLj)
+setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
+ /// } SJLJ instructions
+
// Intrinsic instructions
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
}
@@ -864,6 +873,9 @@ const char *VETargetLowering::getTargetNodeName(unsigned
Opcode) const {
case VEISD::FIRST_NUMBER:
break;
TARGET_NODE_CASE(CALL)
+TARGET_NODE_CASE(EH_SJLJ_LONGJMP)
+TARGET_NODE_CASE(EH_SJLJ_SETJMP)
+TARGET_NODE_CASE(EH_SJLJ_SETUP_DISPATCH)
TARGET_NODE_CASE(GETFUNPLT)
TARGET_NODE_CASE(GETSTACKTOP)
TARGET_NODE_CASE(GETTLSADDR)
@@ -1487,6 +1499,28 @@ SDValue
VETargetLowering::lowerDYNAMIC_STACKALLOC(SDValue Op,
return DAG.getMergeValues(Ops, DL);
}
+SDValue VETargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc DL(Op);
+ return DAG.getNode(VEISD::EH_SJLJ_LONGJMP, DL, MVT::Other, Op.getOperand(0),
+ Op.getOperand(1));
+}
+
+SDValue VETargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc DL(Op);
+ return DAG.getNode(VEISD::EH_SJLJ_SETJMP, DL,
+ DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
+ Op.getOperand(1));
+}
+
+SDValue VETargetLowering::lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
+ SelectionDAG &DAG) const
{
+ SDLoc DL(Op);
+ return DAG.getNode(VEISD::EH_SJLJ_SETUP_DISPATCH, DL, MVT::Other,
+ Op.getOperand(0));
+}
+
static SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG,
const VETargetLowering &TLI,
const VESubtarget *Subtarget) {
@@ -1599,6 +1633,12 @@ SDValue VETargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
return lowerConstantPool(Op, DAG);
case ISD::DYNAMIC_STACKALLOC:
return lowerDYNAMIC_STACKALLOC(Op, DAG);
+ case ISD::EH_SJLJ_LONGJMP:
+return lowerEH_SJLJ_LONGJMP(Op, DAG);
+ case ISD::EH_SJLJ_SETJMP:
+return lowerEH_SJLJ_SETJMP(Op, DAG);
+ case ISD::EH_SJLJ_SETUP_DISPATCH:
+return lowerEH_SJLJ_SETUP_DISPATCH(Op, DAG);
case ISD::FRAMEADDR:
return lowerFRAMEADDR(Op, DAG, *this, Subtarget);
case ISD::GlobalAddress:
@@ -1699,6 +1739,677 @@ SDValue
VETargetLowering::getPICJumpTableRelocBase(SDValue Table,
return DAG.getNode(ISD::ADD, DL, PtrTy, GlobalBase, HiLo);
}
+Register VETargetLowering::prepareMBB(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I,
+ MachineBasicBlock *TargetBB,
+ const DebugLoc &DL) const {
+ MachineFunction *MF = MBB.getParent();
+ MachineRegisterInfo &MRI = MF->getRegInfo();
+ const VEInstrInfo *TII = Subtarget->getInstrInfo();
+
+ const TargetRegisterClass *RC = &VE::I64RegClass;
+ Register Tmp1 = MRI.createVirtualRegister(RC);
+ Regi
[llvm-branch-commits] [clang] 0e4d236 - [OpenCL] Warn about side effects for unevaluated vec_step arg
Author: Sven van Haastregt
Date: 2021-01-05T11:51:10Z
New Revision: 0e4d2361b817bd16f97cd45d5792017edc3891ee
URL:
https://github.com/llvm/llvm-project/commit/0e4d2361b817bd16f97cd45d5792017edc3891ee
DIFF:
https://github.com/llvm/llvm-project/commit/0e4d2361b817bd16f97cd45d5792017edc3891ee.diff
LOG: [OpenCL] Warn about side effects for unevaluated vec_step arg
The argument to the `vec_step` builtin is not evaluated. Hoist the
diagnostic for this in `Sema::CheckUnaryExprOrTypeTraitOperand` such
that it comes before `Sema::CheckVecStepTraitOperandType`.
A minor side-effect of this change is that it also produces the
warning for `co_await` and `co_yield` as `sizeof` arguments now, which
seems to be reasonable given that the warning is emitted for `typeid`
already.
Differential Revision: https://reviews.llvm.org/D91348
Added:
Modified:
clang/lib/Sema/SemaExpr.cpp
clang/test/SemaCXX/coroutines.cpp
clang/test/SemaOpenCL/vec_step.cl
Removed:
diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp
index 28f4c5bbf19b..d8bfd3f8b46a 100644
--- a/clang/lib/Sema/SemaExpr.cpp
+++ b/clang/lib/Sema/SemaExpr.cpp
@@ -4089,7 +4089,7 @@ bool Sema::CheckUnaryExprOrTypeTraitOperand(Expr *E,
bool IsUnevaluatedOperand =
(ExprKind == UETT_SizeOf || ExprKind == UETT_AlignOf ||
- ExprKind == UETT_PreferredAlignOf);
+ ExprKind == UETT_PreferredAlignOf || ExprKind == UETT_VecStep);
if (IsUnevaluatedOperand) {
ExprResult Result = CheckUnevaluatedOperand(E);
if (Result.isInvalid())
@@ -4097,6 +4097,16 @@ bool Sema::CheckUnaryExprOrTypeTraitOperand(Expr *E,
E = Result.get();
}
+ // The operand for sizeof and alignof is in an unevaluated expression
context,
+ // so side effects could result in unintended consequences.
+ // Exclude instantiation-dependent expressions, because 'sizeof' is sometimes
+ // used to build SFINAE gadgets.
+ // FIXME: Should we consider instantiation-dependent operands to 'alignof'?
+ if (IsUnevaluatedOperand && !inTemplateInstantiation() &&
+ !E->isInstantiationDependent() &&
+ E->HasSideEffects(Context, false))
+Diag(E->getExprLoc(), diag::warn_side_effects_unevaluated_context);
+
if (ExprKind == UETT_VecStep)
return CheckVecStepTraitOperandType(*this, ExprTy, E->getExprLoc(),
E->getSourceRange());
@@ -4133,16 +4143,6 @@ bool Sema::CheckUnaryExprOrTypeTraitOperand(Expr *E,
return true;
}
- // The operand for sizeof and alignof is in an unevaluated expression
context,
- // so side effects could result in unintended consequences.
- // Exclude instantiation-dependent expressions, because 'sizeof' is sometimes
- // used to build SFINAE gadgets.
- // FIXME: Should we consider instantiation-dependent operands to 'alignof'?
- if (IsUnevaluatedOperand && !inTemplateInstantiation() &&
- !E->isInstantiationDependent() &&
- E->HasSideEffects(Context, false))
-Diag(E->getExprLoc(), diag::warn_side_effects_unevaluated_context);
-
if (CheckObjCTraitOperandConstraints(*this, ExprTy, E->getExprLoc(),
E->getSourceRange(), ExprKind))
return true;
diff --git a/clang/test/SemaCXX/coroutines.cpp
b/clang/test/SemaCXX/coroutines.cpp
index f354b1f2a4bb..d7208f9a1010 100644
--- a/clang/test/SemaCXX/coroutines.cpp
+++ b/clang/test/SemaCXX/coroutines.cpp
@@ -328,6 +328,7 @@ void unevaluated() {
// expected-warning@-1 {{declaration does not declare
anything}}
sizeof(co_await a); // expected-error {{'co_await' cannot be used in an
unevaluated context}}
// expected-error@-1 {{invalid application of 'sizeof'
to an incomplete type 'void'}}
+ // expected-warning@-2 {{expression with side effects
has no effect in an unevaluated context}}
typeid(co_await a); // expected-error {{'co_await' cannot be used in an
unevaluated context}}
// expected-warning@-1 {{expression with side effects
has no effect in an unevaluated context}}
// expected-warning@-2 {{expression result unused}}
@@ -335,6 +336,7 @@ void unevaluated() {
// expected-warning@-1 {{declaration does not declare
anything}}
sizeof(co_yield 2); // expected-error {{'co_yield' cannot be used in an
unevaluated context}}
// expected-error@-1 {{invalid application of 'sizeof'
to an incomplete type 'void'}}
+ // expected-warning@-2 {{expression with side effects
has no effect in an unevaluated context}}
typeid(co_yield 3); // expected-error {{'co_yield' cannot be used in an
unevaluated context}}
// expected-warning@-1 {{expression with side effects
has no effect in an unevaluated context}}
// expected-warning@-2 {{expres
[llvm-branch-commits] [clang-tools-extra] 2f8d1e9 - [clangd] When querying drivers by binary, look in PATH too
Author: Giulio Girardi
Date: 2021-01-05T12:54:07+01:00
New Revision: 2f8d1e9eb27e111eb6dfd242d88dd7c98005fb5c
URL:
https://github.com/llvm/llvm-project/commit/2f8d1e9eb27e111eb6dfd242d88dd7c98005fb5c
DIFF:
https://github.com/llvm/llvm-project/commit/2f8d1e9eb27e111eb6dfd242d88dd7c98005fb5c.diff
LOG: [clangd] When querying drivers by binary, look in PATH too
Sometimes compile_commands.json databases are created without an
absolute path for the driver in the command field. By default the driver
name is appended to the current directory, however if no driver is found
in that location assume it was in the default PATH and try finding it
there
Reviewed By: sammccall
Differential Revision: https://reviews.llvm.org/D93600
Added:
Modified:
clang-tools-extra/clangd/QueryDriverDatabase.cpp
clang-tools-extra/clangd/test/system-include-extractor.test
Removed:
diff --git a/clang-tools-extra/clangd/QueryDriverDatabase.cpp
b/clang-tools-extra/clangd/QueryDriverDatabase.cpp
index 797771ce144e..f1a4b5fcbfc8 100644
--- a/clang-tools-extra/clangd/QueryDriverDatabase.cpp
+++ b/clang-tools-extra/clangd/QueryDriverDatabase.cpp
@@ -136,10 +136,26 @@ llvm::Optional
parseDriverOutput(llvm::StringRef Output) {
}
llvm::Optional
-extractSystemIncludesAndTarget(PathRef Driver, llvm::StringRef Lang,
+extractSystemIncludesAndTarget(llvm::SmallString<128> Driver,
+ llvm::StringRef Lang,
llvm::ArrayRef CommandLine,
const llvm::Regex &QueryDriverRegex) {
trace::Span Tracer("Extract system includes and target");
+
+ if (!llvm::sys::path::is_absolute(Driver)) {
+assert(llvm::none_of(
+Driver, [](char C) { return llvm::sys::path::is_separator(C); }));
+auto DriverProgram = llvm::sys::findProgramByName(Driver);
+if (DriverProgram) {
+ vlog("System include extraction: driver {0} expanded to {1}", Driver,
+ *DriverProgram);
+ Driver = *DriverProgram;
+} else {
+ elog("System include extraction: driver {0} not found in PATH", Driver);
+ return llvm::None;
+}
+ }
+
SPAN_ATTACH(Tracer, "driver", Driver);
SPAN_ATTACH(Tracer, "lang", Lang);
@@ -332,7 +348,11 @@ class QueryDriverDatabase : public
GlobalCompilationDatabase {
}
llvm::SmallString<128> Driver(Cmd->CommandLine.front());
-llvm::sys::fs::make_absolute(Cmd->Directory, Driver);
+if (llvm::any_of(Driver,
+ [](char C) { return llvm::sys::path::is_separator(C);
}))
+ // Driver is a not a single executable name but instead a path (either
+ // relative or absolute).
+ llvm::sys::fs::make_absolute(Cmd->Directory, Driver);
if (auto Info =
QueriedDrivers.get(/*Key=*/(Driver + ":" + Lang).str(), [&] {
diff --git a/clang-tools-extra/clangd/test/system-include-extractor.test
b/clang-tools-extra/clangd/test/system-include-extractor.test
index 59989be6ca6c..c861a2346470 100644
--- a/clang-tools-extra/clangd/test/system-include-extractor.test
+++ b/clang-tools-extra/clangd/test/system-include-extractor.test
@@ -3,21 +3,24 @@
# The mock driver below is a shell script:
# REQUIRES: shell
+# Create a bin directory to store the mock-driver and add it to the path
+# RUN: mkdir -p %t.dir/bin
+# RUN: export PATH=%t.dir/bin:$PATH
# Generate a mock-driver that will print %temp_dir%/my/dir and
# %temp_dir%/my/dir2 as include search paths.
-# RUN: echo '#!/bin/sh' >> %t.dir/my_driver.sh
-# RUN: echo '[ "$0" = "%t.dir/my_driver.sh" ] || exit' >> %t.dir/my_driver.sh
-# RUN: echo 'args="$*"' >> %t.dir/my_driver.sh
-# RUN: echo '[ -z "${args##*"-nostdinc"*}" ] || exit' >> %t.dir/my_driver.sh
-# RUN: echo '[ -z "${args##*"-isysroot=/isysroot"*}" ] || exit' >>
%t.dir/my_driver.sh
-# RUN: echo 'echo " $* " | grep " --sysroot /my/sysroot/path " || exit' >>
%t.dir/my_driver.sh
-# RUN: echo 'echo line to ignore >&2' >> %t.dir/my_driver.sh
-# RUN: echo 'printf "Target: arm-linux-gnueabihf\r\n" >&2' >>
%t.dir/my_driver.sh
-# RUN: echo 'printf "#include <...> search starts here:\r\n" >&2' >>
%t.dir/my_driver.sh
-# RUN: echo 'echo %t.dir/my/dir/ >&2' >> %t.dir/my_driver.sh
-# RUN: echo 'echo %t.dir/my/dir2/ >&2' >> %t.dir/my_driver.sh
-# RUN: echo 'printf "End of search list.\r\n" >&2' >> %t.dir/my_driver.sh
-# RUN: chmod +x %t.dir/my_driver.sh
+# RUN: echo '#!/bin/sh' >> %t.dir/bin/my_driver.sh
+# RUN: echo '[ "$0" = "%t.dir/bin/my_driver.sh" ] || exit' >>
%t.dir/bin/my_driver.sh
+# RUN: echo 'args="$*"' >> %t.dir/bin/my_driver.sh
+# RUN: echo '[ -z "${args##*"-nostdinc"*}" ] || exit' >>
%t.dir/bin/my_driver.sh
+# RUN: echo '[ -z "${args##*"-isysroot=/isysroot"*}" ] || exit' >>
%t.dir/bin/my_driver.sh
+# RUN: echo 'echo " $* " | grep " --sysroot /my/sysroot/path " || exit' >>
%t.dir/bin/my_driver.sh
+# RUN: echo 'echo line to ignore >&2' >> %t.dir/bin/my_d
[llvm-branch-commits] [llvm] 4e6054a - [AMDGPU] Split out new helper function macToMad in SIFoldOperands. NFC.
Author: Jay Foad
Date: 2021-01-05T11:54:48Z
New Revision: 4e6054a86c0cb0697913007c99b59f3f65c9d04b
URL:
https://github.com/llvm/llvm-project/commit/4e6054a86c0cb0697913007c99b59f3f65c9d04b
DIFF:
https://github.com/llvm/llvm-project/commit/4e6054a86c0cb0697913007c99b59f3f65c9d04b.diff
LOG: [AMDGPU] Split out new helper function macToMad in SIFoldOperands. NFC.
Differential Revision: https://reviews.llvm.org/D94009
Added:
Modified:
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
Removed:
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index d86527df5c3c..6dc01c3d3c21 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -129,6 +129,21 @@ char SIFoldOperands::ID = 0;
char &llvm::SIFoldOperandsID = SIFoldOperands::ID;
+// Map multiply-accumulate opcode to corresponding multiply-add opcode if any.
+static unsigned macToMad(unsigned Opc) {
+ switch (Opc) {
+ case AMDGPU::V_MAC_F32_e64:
+return AMDGPU::V_MAD_F32;
+ case AMDGPU::V_MAC_F16_e64:
+return AMDGPU::V_MAD_F16;
+ case AMDGPU::V_FMAC_F32_e64:
+return AMDGPU::V_FMA_F32;
+ case AMDGPU::V_FMAC_F16_e64:
+return AMDGPU::V_FMA_F16_gfx9;
+ }
+ return AMDGPU::INSTRUCTION_LIST_END;
+}
+
// Wrapper around isInlineConstant that understands special cases when
// instruction types are replaced during operand folding.
static bool isInlineConstantIfFolded(const SIInstrInfo *TII,
@@ -139,31 +154,18 @@ static bool isInlineConstantIfFolded(const SIInstrInfo
*TII,
return true;
unsigned Opc = UseMI.getOpcode();
- switch (Opc) {
- case AMDGPU::V_MAC_F32_e64:
- case AMDGPU::V_MAC_F16_e64:
- case AMDGPU::V_FMAC_F32_e64:
- case AMDGPU::V_FMAC_F16_e64: {
+ unsigned NewOpc = macToMad(Opc);
+ if (NewOpc != AMDGPU::INSTRUCTION_LIST_END) {
// Special case for mac. Since this is replaced with mad when folded into
// src2, we need to check the legality for the final instruction.
int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);
if (static_cast(OpNo) == Src2Idx) {
- bool IsFMA = Opc == AMDGPU::V_FMAC_F32_e64 ||
- Opc == AMDGPU::V_FMAC_F16_e64;
- bool IsF32 = Opc == AMDGPU::V_MAC_F32_e64 ||
- Opc == AMDGPU::V_FMAC_F32_e64;
-
- unsigned Opc = IsFMA ?
-(IsF32 ? AMDGPU::V_FMA_F32 : AMDGPU::V_FMA_F16_gfx9) :
-(IsF32 ? AMDGPU::V_MAD_F32 : AMDGPU::V_MAD_F16);
- const MCInstrDesc &MadDesc = TII->get(Opc);
+ const MCInstrDesc &MadDesc = TII->get(NewOpc);
return TII->isInlineConstant(OpToFold, MadDesc.OpInfo[OpNo].OperandType);
}
-return false;
- }
- default:
-return false;
}
+
+ return false;
}
// TODO: Add heuristic that the frame index might not fit in the addressing
mode
@@ -346,17 +348,8 @@ static bool
tryAddToFoldList(SmallVectorImpl &FoldList,
if (!TII->isOperandLegal(*MI, OpNo, OpToFold)) {
// Special case for v_mac_{f16, f32}_e64 if we are trying to fold into src2
unsigned Opc = MI->getOpcode();
-if ((Opc == AMDGPU::V_MAC_F32_e64 || Opc == AMDGPU::V_MAC_F16_e64 ||
- Opc == AMDGPU::V_FMAC_F32_e64 || Opc == AMDGPU::V_FMAC_F16_e64) &&
-(int)OpNo == AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)) {
- bool IsFMA = Opc == AMDGPU::V_FMAC_F32_e64 ||
- Opc == AMDGPU::V_FMAC_F16_e64;
- bool IsF32 = Opc == AMDGPU::V_MAC_F32_e64 ||
- Opc == AMDGPU::V_FMAC_F32_e64;
- unsigned NewOpc = IsFMA ?
-(IsF32 ? AMDGPU::V_FMA_F32 : AMDGPU::V_FMA_F16_gfx9) :
-(IsF32 ? AMDGPU::V_MAD_F32 : AMDGPU::V_MAD_F16);
-
+unsigned NewOpc = macToMad(Opc);
+if (NewOpc != AMDGPU::INSTRUCTION_LIST_END) {
// Check if changing this to a v_mad_{f16, f32} instruction will allow us
// to fold the operand.
MI->setDesc(TII->get(NewOpc));
___
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[llvm-branch-commits] [llvm] 639a50e - [AMDGPU] Precommit test case for D94010
Author: Jay Foad
Date: 2021-01-05T11:55:14Z
New Revision: 639a50e2f138ed3e647b00809a2871a1b9ae9012
URL:
https://github.com/llvm/llvm-project/commit/639a50e2f138ed3e647b00809a2871a1b9ae9012
DIFF:
https://github.com/llvm/llvm-project/commit/639a50e2f138ed3e647b00809a2871a1b9ae9012.diff
LOG: [AMDGPU] Precommit test case for D94010
Added:
Modified:
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
Removed:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
index 27ba74c3f557..8bfb81d86ace 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck
-check-prefix=GCN %s
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s |
FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1030 < %s | FileCheck
-check-prefixes=GCN,SDAG %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1030 < %s |
FileCheck -check-prefixes=GCN,GISEL %s
define float @v_fma(float %a, float %b, float %c) {
; GCN-LABEL: v_fma:
@@ -51,5 +51,98 @@ define float @v_fneg_fma(float %a, float %b, float %c) {
ret float %fma
}
+define amdgpu_ps <{ i32, i32, i32, i32, i32, float, float, float, float,
float, float, float, float, float, float, float, float, float, float, float }>
@main(<4 x i32> addrspace(6)* inreg noalias align 32
dereferenceable(18446744073709551615) %arg, <8 x i32> addrspace(6)* inreg
noalias align 32 dereferenceable(18446744073709551615) %arg1, <4 x i32>
addrspace(6)* inreg noalias align 32 dereferenceable(18446744073709551615)
%arg2, <8 x i32> addrspace(6)* inreg noalias align 32
dereferenceable(18446744073709551615) %arg3, i32 inreg %arg4, i32 inreg %arg5,
<2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32>
%arg10, <2 x i32> %arg11, <2 x i32> %arg12, <3 x float> %arg13, float %arg14,
float %arg15, float %arg16, float %arg17, i32 %arg18, i32 %arg19, float %arg20,
i32 %arg21) #0 {
+; SDAG-LABEL: main:
+; SDAG: ; %bb.0:
+; SDAG-NEXT:s_mov_b32 s16, exec_lo
+; SDAG-NEXT:v_mov_b32_e32 v14, v2
+; SDAG-NEXT:s_mov_b32 s0, s5
+; SDAG-NEXT:s_wqm_b32 exec_lo, exec_lo
+; SDAG-NEXT:s_mov_b32 s1, 0
+; SDAG-NEXT:s_mov_b32 m0, s7
+; SDAG-NEXT:s_clause 0x1
+; SDAG-NEXT:s_load_dwordx8 s[8:15], s[0:1], 0x400
+; SDAG-NEXT:s_load_dwordx4 s[0:3], s[0:1], 0x430
+; SDAG-NEXT:v_interp_p1_f32_e32 v2, v0, attr0.x
+; SDAG-NEXT:v_interp_p1_f32_e32 v3, v0, attr0.y
+; SDAG-NEXT:s_mov_b32 s4, s6
+; SDAG-NEXT:v_interp_p2_f32_e32 v2, v1, attr0.x
+; SDAG-NEXT:v_interp_p2_f32_e32 v3, v1, attr0.y
+; SDAG-NEXT:s_and_b32 exec_lo, exec_lo, s16
+; SDAG-NEXT:s_waitcnt lgkmcnt(0)
+; SDAG-NEXT:image_sample v[7:10], v[2:3], s[8:15], s[0:3] dmask:0xf
dim:SQ_RSRC_IMG_2D
+; SDAG-NEXT:v_mov_b32_e32 v4, -1.0
+; SDAG-NEXT:v_mov_b32_e32 v5, -1.0
+; SDAG-NEXT:s_waitcnt vmcnt(0)
+; SDAG-NEXT:v_fmac_legacy_f32_e64 v4, v7, 2.0
+; SDAG-NEXT:v_fmac_legacy_f32_e64 v5, v8, 2.0
+; SDAG-NEXT:v_mov_b32_e32 v2, v9
+; SDAG-NEXT:v_mov_b32_e32 v3, v10
+; SDAG-NEXT:v_mov_b32_e32 v0, v4
+; SDAG-NEXT:v_mov_b32_e32 v1, v5
+; SDAG-NEXT:; return to shader part epilog
+;
+; GISEL-LABEL: main:
+; GISEL: ; %bb.0:
+; GISEL-NEXT:s_mov_b32 s16, exec_lo
+; GISEL-NEXT:s_mov_b32 s4, s6
+; GISEL-NEXT:s_mov_b32 m0, s7
+; GISEL-NEXT:s_wqm_b32 exec_lo, exec_lo
+; GISEL-NEXT:s_add_u32 s0, s5, 0x400
+; GISEL-NEXT:s_mov_b32 s1, 0
+; GISEL-NEXT:v_interp_p1_f32_e32 v3, v0, attr0.y
+; GISEL-NEXT:s_load_dwordx8 s[8:15], s[0:1], 0x0
+; GISEL-NEXT:s_add_u32 s0, s5, 0x430
+; GISEL-NEXT:v_mov_b32_e32 v14, v2
+; GISEL-NEXT:s_load_dwordx4 s[0:3], s[0:1], 0x0
+; GISEL-NEXT:v_interp_p1_f32_e32 v2, v0, attr0.x
+; GISEL-NEXT:v_interp_p2_f32_e32 v3, v1, attr0.y
+; GISEL-NEXT:v_interp_p2_f32_e32 v2, v1, attr0.x
+; GISEL-NEXT:s_and_b32 exec_lo, exec_lo, s16
+; GISEL-NEXT:s_waitcnt lgkmcnt(0)
+; GISEL-NEXT:image_sample v[7:10], v[2:3], s[8:15], s[0:3] dmask:0xf
dim:SQ_RSRC_IMG_2D
+; GISEL-NEXT:v_mov_b32_e32 v4, -1.0
+; GISEL-NEXT:v_mov_b32_e32 v5, -1.0
+; GISEL-NEXT:s_waitcnt vmcnt(0)
+; GISEL-NEXT:v_fmac_legacy_f32_e64 v4, v7, 2.0
+; GISEL-NEXT:v_fmac_legacy_f32_e64 v5, v8, 2.0
+; GISEL-NEXT:v_mov_b32_e32 v2, v9
+; GISEL-NEXT:v_mov_b32_e32 v3, v10
+; GISEL-NEXT:v_mov_b32_e32 v0, v4
+; GISEL-NEXT:v_mov_b32_e32 v1, v5
+; GISEL-NEXT:; return to shader part epilog
+ %i = bitcast <2 x i32> %arg7 to <2 x float>
+ %i22 = extractelement <2 x float> %i, i32 0
+ %i23 = extractelement <2 x float> %i, i32 1
+ %i24 = c
[llvm-branch-commits] [llvm] 3914beb - [AMDGPU] Handle v_fmac_legacy_f32 in SIFoldOperands
Author: Jay Foad
Date: 2021-01-05T11:55:33Z
New Revision: 3914bebe91f6b557e61d6d74117762f9043593e0
URL:
https://github.com/llvm/llvm-project/commit/3914bebe91f6b557e61d6d74117762f9043593e0
DIFF:
https://github.com/llvm/llvm-project/commit/3914bebe91f6b557e61d6d74117762f9043593e0.diff
LOG: [AMDGPU] Handle v_fmac_legacy_f32 in SIFoldOperands
Convert it to v_fma_legacy_f32 if it is profitable to do so, just like
other mac instructions that are converted to their mad equivalents.
Differential Revision: https://reviews.llvm.org/D94010
Added:
Modified:
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
Removed:
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 6dc01c3d3c21..892dc1feb298 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -140,6 +140,8 @@ static unsigned macToMad(unsigned Opc) {
return AMDGPU::V_FMA_F32;
case AMDGPU::V_FMAC_F16_e64:
return AMDGPU::V_FMA_F16_gfx9;
+ case AMDGPU::V_FMAC_LEGACY_F32_e64:
+return AMDGPU::V_FMA_LEGACY_F32;
}
return AMDGPU::INSTRUCTION_LIST_END;
}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
index 8bfb81d86ace..e641d12444cc 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
@@ -70,16 +70,10 @@ define amdgpu_ps <{ i32, i32, i32, i32, i32, float, float,
float, float, float,
; SDAG-NEXT:v_interp_p2_f32_e32 v3, v1, attr0.y
; SDAG-NEXT:s_and_b32 exec_lo, exec_lo, s16
; SDAG-NEXT:s_waitcnt lgkmcnt(0)
-; SDAG-NEXT:image_sample v[7:10], v[2:3], s[8:15], s[0:3] dmask:0xf
dim:SQ_RSRC_IMG_2D
-; SDAG-NEXT:v_mov_b32_e32 v4, -1.0
-; SDAG-NEXT:v_mov_b32_e32 v5, -1.0
+; SDAG-NEXT:image_sample v[0:3], v[2:3], s[8:15], s[0:3] dmask:0xf
dim:SQ_RSRC_IMG_2D
; SDAG-NEXT:s_waitcnt vmcnt(0)
-; SDAG-NEXT:v_fmac_legacy_f32_e64 v4, v7, 2.0
-; SDAG-NEXT:v_fmac_legacy_f32_e64 v5, v8, 2.0
-; SDAG-NEXT:v_mov_b32_e32 v2, v9
-; SDAG-NEXT:v_mov_b32_e32 v3, v10
-; SDAG-NEXT:v_mov_b32_e32 v0, v4
-; SDAG-NEXT:v_mov_b32_e32 v1, v5
+; SDAG-NEXT:v_fma_legacy_f32 v0, v0, 2.0, -1.0
+; SDAG-NEXT:v_fma_legacy_f32 v1, v1, 2.0, -1.0
; SDAG-NEXT:; return to shader part epilog
;
; GISEL-LABEL: main:
@@ -100,16 +94,10 @@ define amdgpu_ps <{ i32, i32, i32, i32, i32, float, float,
float, float, float,
; GISEL-NEXT:v_interp_p2_f32_e32 v2, v1, attr0.x
; GISEL-NEXT:s_and_b32 exec_lo, exec_lo, s16
; GISEL-NEXT:s_waitcnt lgkmcnt(0)
-; GISEL-NEXT:image_sample v[7:10], v[2:3], s[8:15], s[0:3] dmask:0xf
dim:SQ_RSRC_IMG_2D
-; GISEL-NEXT:v_mov_b32_e32 v4, -1.0
-; GISEL-NEXT:v_mov_b32_e32 v5, -1.0
+; GISEL-NEXT:image_sample v[0:3], v[2:3], s[8:15], s[0:3] dmask:0xf
dim:SQ_RSRC_IMG_2D
; GISEL-NEXT:s_waitcnt vmcnt(0)
-; GISEL-NEXT:v_fmac_legacy_f32_e64 v4, v7, 2.0
-; GISEL-NEXT:v_fmac_legacy_f32_e64 v5, v8, 2.0
-; GISEL-NEXT:v_mov_b32_e32 v2, v9
-; GISEL-NEXT:v_mov_b32_e32 v3, v10
-; GISEL-NEXT:v_mov_b32_e32 v0, v4
-; GISEL-NEXT:v_mov_b32_e32 v1, v5
+; GISEL-NEXT:v_fma_legacy_f32 v0, v0, 2.0, -1.0
+; GISEL-NEXT:v_fma_legacy_f32 v1, v1, 2.0, -1.0
; GISEL-NEXT:; return to shader part epilog
%i = bitcast <2 x i32> %arg7 to <2 x float>
%i22 = extractelement <2 x float> %i, i32 0
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[llvm-branch-commits] [llvm] 9a1ac97 - [CodeGen] Format SelectionDAG::getConstant methods (NFC)
Author: Fraser Cormack
Date: 2021-01-05T12:59:46Z
New Revision: 9a1ac97d3af5efb8ddc8ae390dfeb3c7d2b9a8c5
URL:
https://github.com/llvm/llvm-project/commit/9a1ac97d3af5efb8ddc8ae390dfeb3c7d2b9a8c5
DIFF:
https://github.com/llvm/llvm-project/commit/9a1ac97d3af5efb8ddc8ae390dfeb3c7d2b9a8c5.diff
LOG: [CodeGen] Format SelectionDAG::getConstant methods (NFC)
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Removed:
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 6a3995e16822..504e62087cb1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1279,7 +1279,7 @@ SDValue SelectionDAG::getConstant(uint64_t Val, const
SDLoc &DL, EVT VT,
bool isT, bool isO) {
EVT EltVT = VT.getScalarType();
assert((EltVT.getSizeInBits() >= 64 ||
- (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) &&
+ (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) &&
"getConstant with a uint64_t value that doesn't fit in the type!");
return getConstant(APInt(EltVT.getSizeInBits(), Val), DL, VT, isT, isO);
}
@@ -1301,10 +1301,10 @@ SDValue SelectionDAG::getConstant(const ConstantInt
&Val, const SDLoc &DL,
// inserted value (the type does not need to match the vector element type).
// Any extra bits introduced will be truncated away.
if (VT.isVector() && TLI->getTypeAction(*getContext(), EltVT) ==
- TargetLowering::TypePromoteInteger) {
- EltVT = TLI->getTypeToTransformTo(*getContext(), EltVT);
- APInt NewVal = Elt->getValue().zextOrTrunc(EltVT.getSizeInBits());
- Elt = ConstantInt::get(*getContext(), NewVal);
+ TargetLowering::TypePromoteInteger) {
+EltVT = TLI->getTypeToTransformTo(*getContext(), EltVT);
+APInt NewVal = Elt->getValue().zextOrTrunc(EltVT.getSizeInBits());
+Elt = ConstantInt::get(*getContext(), NewVal);
}
// In other cases the element type is illegal and needs to be expanded, for
// example v2i64 on MIPS32. In this case, find the nearest legal type, split
@@ -1314,7 +1314,7 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val,
const SDLoc &DL,
// only legalize if the DAG tells us we must produce legal types.
else if (NewNodesMustHaveLegalTypes && VT.isVector() &&
TLI->getTypeAction(*getContext(), EltVT) ==
- TargetLowering::TypeExpandInteger) {
+ TargetLowering::TypeExpandInteger) {
const APInt &NewVal = Elt->getValue();
EVT ViaEltVT = TLI->getTypeToTransformTo(*getContext(), EltVT);
unsigned ViaEltSizeInBits = ViaEltVT.getSizeInBits();
@@ -1328,9 +1328,9 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val,
const SDLoc &DL,
SmallVector EltParts;
for (unsigned i = 0; i < ViaVecNumElts / VT.getVectorNumElements(); ++i) {
- EltParts.push_back(getConstant(NewVal.lshr(i * ViaEltSizeInBits)
- .zextOrTrunc(ViaEltSizeInBits), DL,
- ViaEltVT, isT, isO));
+ EltParts.push_back(getConstant(
+ NewVal.lshr(i * ViaEltSizeInBits).zextOrTrunc(ViaEltSizeInBits), DL,
+ ViaEltVT, isT, isO));
}
// EltParts is currently in little endian order. If we actually want
@@ -1349,7 +1349,8 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val,
const SDLoc &DL,
for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
llvm::append_range(Ops, EltParts);
-SDValue V = getNode(ISD::BITCAST, DL, VT, getBuildVector(ViaVecVT, DL,
Ops));
+SDValue V =
+getNode(ISD::BITCAST, DL, VT, getBuildVector(ViaVecVT, DL, Ops));
return V;
}
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[llvm-branch-commits] [clang] 489000d - [VE] Change clang to support SjLj Lowering
Author: Kazushi (Jam) Marukawa
Date: 2021-01-05T22:19:02+09:00
New Revision: 489000d8516da7eaf6aabaad11cce0ed7e67c61f
URL:
https://github.com/llvm/llvm-project/commit/489000d8516da7eaf6aabaad11cce0ed7e67c61f
DIFF:
https://github.com/llvm/llvm-project/commit/489000d8516da7eaf6aabaad11cce0ed7e67c61f.diff
LOG: [VE] Change clang to support SjLj Lowering
We supports SjLj exception handling in the backend, so changing
clang to allow lowering using SjLj exceptions. Update a regression
test also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D94076
Added:
Modified:
clang/lib/Basic/Targets/VE.h
clang/test/Sema/builtin-longjmp.c
Removed:
diff --git a/clang/lib/Basic/Targets/VE.h b/clang/lib/Basic/Targets/VE.h
index 2d9c74ac5247..71d6fc08d859 100644
--- a/clang/lib/Basic/Targets/VE.h
+++ b/clang/lib/Basic/Targets/VE.h
@@ -53,10 +53,7 @@ class LLVM_LIBRARY_VISIBILITY VETargetInfo : public
TargetInfo {
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override;
- bool hasSjLjLowering() const override {
-// TODO
-return false;
- }
+ bool hasSjLjLowering() const override { return true; }
ArrayRef getTargetBuiltins() const override;
diff --git a/clang/test/Sema/builtin-longjmp.c
b/clang/test/Sema/builtin-longjmp.c
index d80208f82c67..3023098a7631 100644
--- a/clang/test/Sema/builtin-longjmp.c
+++ b/clang/test/Sema/builtin-longjmp.c
@@ -4,6 +4,7 @@
// RUN: %clang_cc1 -triple powerpc-unknown-unknown -emit-llvm < %s| FileCheck
%s
// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -emit-llvm < %s|
FileCheck %s
// RUN: %clang_cc1 -triple sparc-eabi-unknown -emit-llvm < %s | FileCheck %s
+// RUN: %clang_cc1 -triple ve-unknown-unknown -emit-llvm < %s | FileCheck %s
// RUN: %clang_cc1 -triple aarch64-unknown-unknown -emit-llvm-only -verify %s
// RUN: %clang_cc1 -triple mips-unknown-unknown -emit-llvm-only -verify %s
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[llvm-branch-commits] [llvm] dc74d7e - [X86] getMemoryOpCost - use dyn_cast_or_null. NFCI.
Author: Simon Pilgrim
Date: 2021-01-05T13:23:09Z
New Revision: dc74d7ed1f651aa61d15b4eaaa32200df1f38d37
URL:
https://github.com/llvm/llvm-project/commit/dc74d7ed1f651aa61d15b4eaaa32200df1f38d37
DIFF:
https://github.com/llvm/llvm-project/commit/dc74d7ed1f651aa61d15b4eaaa32200df1f38d37.diff
LOG: [X86] getMemoryOpCost - use dyn_cast_or_null. NFCI.
Use instead of the isa_and_nonnull and use the
StoreInst::getPointerOperand wrapper instead of a hardcoded
Instruction::getOperand.
Looks cleaner and avoids a spurious clang static analyzer null dereference
warning.
Added:
Modified:
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
Removed:
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 5a342d41fb5e..71455237fb61 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -3188,11 +3188,10 @@ int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type
*Src,
const Instruction *I) {
// TODO: Handle other cost kinds.
if (CostKind != TTI::TCK_RecipThroughput) {
-if (isa_and_nonnull(I)) {
- Value *Ptr = I->getOperand(1);
+if (auto *SI = dyn_cast_or_null(I)) {
// Store instruction with index and scale costs 2 Uops.
// Check the preceding GEP to identify non-const indices.
- if (auto *GEP = dyn_cast(Ptr)) {
+ if (auto *GEP = dyn_cast(SI->getPointerOperand())) {
if (!all_of(GEP->indices(), [](Value *V) { return isa(V); }))
return TTI::TCC_Basic * 2;
}
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[llvm-branch-commits] [clang] 6f77029 - [OpenCL] Restrict pointer to member functions.
Author: Anastasia Stulova
Date: 2021-01-05T13:32:18Z
New Revision: 6f770292a39f265c985623b1550aa50566b0
URL:
https://github.com/llvm/llvm-project/commit/6f770292a39f265c985623b1550aa50566b0
DIFF:
https://github.com/llvm/llvm-project/commit/6f770292a39f265c985623b1550aa50566b0.diff
LOG: [OpenCL] Restrict pointer to member functions.
Pointers to member functions are a special case
of function pointers and therefore have to be
disallowed.
Tags: #clang
Differential Revision: https://reviews.llvm.org/D93958
Added:
clang/test/SemaOpenCLCXX/members.cl
Modified:
clang/lib/Sema/SemaDecl.cpp
Removed:
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index 949df53b40e0..73a6aea4fb7e 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -6749,8 +6749,8 @@ static bool diagnoseOpenCLTypes(Scope *S, Sema &Se,
Declarator &D,
// OpenCL v1.0 s6.8.a.3: Pointers to functions are not allowed.
QualType NR = R;
- while (NR->isPointerType()) {
-if (NR->isFunctionPointerType()) {
+ while (NR->isPointerType() || NR->isMemberFunctionPointerType()) {
+if (NR->isFunctionPointerType() || NR->isMemberFunctionPointerType()) {
Se.Diag(D.getIdentifierLoc(), diag::err_opencl_function_pointer);
D.setInvalidType();
return false;
diff --git a/clang/test/SemaOpenCLCXX/members.cl
b/clang/test/SemaOpenCLCXX/members.cl
new file mode 100644
index ..699619ccbe48
--- /dev/null
+++ b/clang/test/SemaOpenCLCXX/members.cl
@@ -0,0 +1,22 @@
+//RUN: %clang_cc1 %s -triple spir -cl-std=clc++ -verify -fsyntax-only
+
+// Check that pointer to member functions are diagnosed
+struct C {
+ void f(int n);
+};
+
+typedef void (C::*p_t)(int);
+
+template struct remove_reference { typedef T type; };
+template struct remove_reference { typedef T type; };
+
+template
+void templ_test() {
+ typename remove_reference::type *ptr; //expected-error{{pointers to
functions are not allowed}}
+}
+
+void test() {
+ void (C::*p)(int); //expected-error{{pointers to functions are not
allowed}}
+ p_t p1; //expected-error{{pointers to functions are not
allowed}}
+ templ_test(); //expected-note{{in instantiation of function
template specialization}}
+}
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[llvm-branch-commits] [mlir] 89ae5b5 - [mlir] Add canonicalization pattern out_tensor->linalg->dim to out_tensor->dim.
Author: Alexander Belyaev
Date: 2021-01-05T15:15:21+01:00
New Revision: 89ae5b5b6a475addb7248ca7a948a944a15f0275
URL:
https://github.com/llvm/llvm-project/commit/89ae5b5b6a475addb7248ca7a948a944a15f0275
DIFF:
https://github.com/llvm/llvm-project/commit/89ae5b5b6a475addb7248ca7a948a944a15f0275.diff
LOG: [mlir] Add canonicalization pattern out_tensor->linalg->dim to
out_tensor->dim.
Differential Revision: https://reviews.llvm.org/D94079
Added:
Modified:
mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
mlir/test/Dialect/Linalg/canonicalize.mlir
Removed:
diff --git a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
index bcbd6d9036121..529ba35a0b87d 100644
--- a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
+++ b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
@@ -1958,14 +1958,33 @@ struct DeduplicateInputs : public RewritePattern {
return success();
}
};
+
+/// Canonicalize a `linalgOp` -> `dim` pattern by replacing the `dim` arg
+/// with the corresponding output tensor argument of the linalg op.
+struct ReplaceDimOfLinalgResult : public OpRewritePattern {
+ using OpRewritePattern::OpRewritePattern;
+
+ LogicalResult matchAndRewrite(DimOp dimOp,
+PatternRewriter &rewriter) const override {
+Value dimOpArg = dimOp.memrefOrTensor();
+auto linalgOp = dimOpArg.getDefiningOp();
+if (!linalgOp)
+ return failure();
+
+auto results = linalgOp.getOperation()->getResults();
+int64_t id = std::distance(results.begin(), llvm::find(results, dimOpArg));
+auto outputTensors = linalgOp.getOutputTensors();
+rewriter.replaceOpWithNewOp(dimOp, outputTensors[id],
dimOp.index());
+return success();
+ }
+};
} // namespace
#define CANONICALIZERS_AND_FOLDERS(XXX)
\
void XXX::getCanonicalizationPatterns(OwningRewritePatternList &results,
\
MLIRContext *context) {
\
-results.insert();
\
-results.insert();
\
-results.insert();
\
+results.insert();
\
+results.insert(context);
\
}
\
\
LogicalResult XXX::fold(ArrayRef,
\
diff --git a/mlir/test/Dialect/Linalg/canonicalize.mlir
b/mlir/test/Dialect/Linalg/canonicalize.mlir
index f015d5fd64fd9..faac64c0d91a9 100644
--- a/mlir/test/Dialect/Linalg/canonicalize.mlir
+++ b/mlir/test/Dialect/Linalg/canonicalize.mlir
@@ -389,3 +389,31 @@ func @init_tensor_dynamic_dim(%arg0 : index) -> (index) {
// CHECK: func @init_tensor_dynamic_dim
// CHECK-SAME: %[[ARG0:[a-zA-Z0-9_]+]]: index
// CHECK: return %[[ARG0]]
+
+// -
+
+#map = affine_map<(d0) -> (d0)>
+
+func @init_tensor_dim_of_linalg_result(%arg_0 : tensor,
+%arg_1: tensor) -> (tensor, tensor) {
+ %0, %1 = linalg.generic {
+indexing_maps = [#map, #map, #map],
+iterator_types = ["parallel"]
+ } ins(%arg_0 : tensor)
+outs(%arg_0, %arg_1 : tensor, tensor) {
+ ^bb0(%in: f32, %out_0: f32, %out_1: f32):
+linalg.yield %in, %in : f32, f32
+ } -> tensor, tensor
+
+ %c0 = constant 0 : index
+ %num_elem_0 = dim %0, %c0 : tensor
+ %result_0 = linalg.init_tensor [%num_elem_0] : tensor
+
+ %num_elem_1 = dim %1, %c0 : tensor
+ %result_1 = linalg.init_tensor [%num_elem_1] : tensor
+ return %result_0, %result_1 : tensor, tensor
+}
+// CHECK-LABEL: func @init_tensor_dim_of_linalg_result(
+// CHECK-SAME: [[ARG_0:%.*]]: tensor, [[ARG_1:%.*]]: tensor)
+// CHECK: dim [[ARG_0]]
+// CHECK: dim [[ARG_1]]
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[llvm-branch-commits] [clang] c3a21e5 - [ASTMatchers] Ensure that we can match inside lambdas
Author: Stephen Kelly
Date: 2021-01-05T14:39:46Z
New Revision: c3a21e5de3dc3f55e4d219afd55dec518159d356
URL:
https://github.com/llvm/llvm-project/commit/c3a21e5de3dc3f55e4d219afd55dec518159d356
DIFF:
https://github.com/llvm/llvm-project/commit/c3a21e5de3dc3f55e4d219afd55dec518159d356.diff
LOG: [ASTMatchers] Ensure that we can match inside lambdas
Because we don't know in ASTMatchFinder whether we're matching in AsIs
or IgnoreUnlessSpelledInSource mode, we need to traverse the lambda
twice, but store whether we're matching in nodes spelled in source or
not.
Differential Revision: https://reviews.llvm.org/D93688
Added:
Modified:
clang/include/clang/ASTMatchers/ASTMatchersInternal.h
clang/lib/ASTMatchers/ASTMatchFinder.cpp
clang/lib/ASTMatchers/ASTMatchersInternal.cpp
clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
Removed:
diff --git a/clang/include/clang/ASTMatchers/ASTMatchersInternal.h
b/clang/include/clang/ASTMatchers/ASTMatchersInternal.h
index 46de4093272d..f49728d1f50e 100644
--- a/clang/include/clang/ASTMatchers/ASTMatchersInternal.h
+++ b/clang/include/clang/ASTMatchers/ASTMatchersInternal.h
@@ -723,6 +723,8 @@ class ASTMatchFinder {
virtual bool IsMatchingInASTNodeNotSpelledInSource() const = 0;
+ virtual bool IsMatchingInASTNodeNotAsIs() const = 0;
+
bool isTraversalIgnoringImplicitNodes() const;
protected:
diff --git a/clang/lib/ASTMatchers/ASTMatchFinder.cpp
b/clang/lib/ASTMatchers/ASTMatchFinder.cpp
index 762885fa0052..af21e2283d8b 100644
--- a/clang/lib/ASTMatchers/ASTMatchFinder.cpp
+++ b/clang/lib/ASTMatchers/ASTMatchFinder.cpp
@@ -475,6 +475,55 @@ class MatchASTVisitor : public
RecursiveASTVisitor,
}
}
return true;
+} else if (auto *LE = dyn_cast(S)) {
+ for (auto I : llvm::zip(LE->captures(), LE->capture_inits())) {
+auto C = std::get<0>(I);
+ASTNodeNotSpelledInSourceScope RAII(
+this, TraversingASTNodeNotSpelledInSource || !C.isExplicit());
+TraverseLambdaCapture(LE, &C, std::get<1>(I));
+ }
+
+ {
+ASTNodeNotSpelledInSourceScope RAII(this, true);
+TraverseDecl(LE->getLambdaClass());
+ }
+ {
+ASTNodeNotAsIsSourceScope RAII(this, true);
+
+// We need to poke around to find the bits that might be explicitly
+// written.
+TypeLoc TL = LE->getCallOperator()->getTypeSourceInfo()->getTypeLoc();
+FunctionProtoTypeLoc Proto = TL.getAsAdjusted();
+
+if (auto *TPL = LE->getTemplateParameterList()) {
+ for (NamedDecl *D : *TPL) {
+TraverseDecl(D);
+ }
+ if (Expr *RequiresClause = TPL->getRequiresClause()) {
+TraverseStmt(RequiresClause);
+ }
+}
+
+if (LE->hasExplicitParameters()) {
+ // Visit parameters.
+ for (ParmVarDecl *Param : Proto.getParams())
+TraverseDecl(Param);
+}
+
+const auto *T = Proto.getTypePtr();
+for (const auto &E : T->exceptions())
+ TraverseType(E);
+
+if (Expr *NE = T->getNoexceptExpr())
+ TraverseStmt(NE, Queue);
+
+if (LE->hasExplicitResultType())
+ TraverseTypeLoc(Proto.getReturnLoc());
+TraverseStmt(LE->getTrailingRequiresClause());
+
+TraverseStmt(LE->getBody());
+ }
+ return true;
}
return RecursiveASTVisitor::dataTraverseNode(S, Queue);
}
@@ -617,6 +666,9 @@ class MatchASTVisitor : public
RecursiveASTVisitor,
bool IsMatchingInASTNodeNotSpelledInSource() const override {
return TraversingASTNodeNotSpelledInSource;
}
+ bool IsMatchingInASTNodeNotAsIs() const override {
+return TraversingASTNodeNotAsIs;
+ }
bool TraverseTemplateInstantiations(ClassTemplateDecl *D) {
ASTNodeNotSpelledInSourceScope RAII(this, true);
@@ -638,6 +690,7 @@ class MatchASTVisitor : public
RecursiveASTVisitor,
private:
bool TraversingASTNodeNotSpelledInSource = false;
+ bool TraversingASTNodeNotAsIs = false;
bool TraversingASTChildrenNotSpelledInSource = false;
struct ASTNodeNotSpelledInSourceScope {
@@ -654,6 +707,18 @@ class MatchASTVisitor : public
RecursiveASTVisitor,
bool MB;
};
+ struct ASTNodeNotAsIsSourceScope {
+ASTNodeNotAsIsSourceScope(MatchASTVisitor *V, bool B)
+: MV(V), MB(V->TraversingASTNodeNotAsIs) {
+ V->TraversingASTNodeNotAsIs = B;
+}
+~ASTNodeNotAsIsSourceScope() { MV->TraversingASTNodeNotAsIs = MB; }
+
+ private:
+MatchASTVisitor *MV;
+bool MB;
+ };
+
struct ASTChildrenNotSpelledInSource {
ASTChildrenNotSpelledInSource(MatchASTVisitor *V, bool B)
: MV(V), MB(V->TraversingASTChildrenNotSpelledInSource) {
diff --git a/clang/lib/ASTMatchers/ASTMatchersInternal.cpp
b/clang/lib/ASTMatchers/ASTMatchersInternal.cpp
index 3c19bceb079e..eb0fffcc3c37 100644
--- a/clang/lib/A
[llvm-branch-commits] [llvm] c3403dc - [ASTMatchers] Fix build when no targets are enabled
Author: Stephen Kelly
Date: 2021-01-05T14:40:35Z
New Revision: c3403dc63d73710d14844e8a8cfad7a0f52d4a54
URL:
https://github.com/llvm/llvm-project/commit/c3403dc63d73710d14844e8a8cfad7a0f52d4a54
DIFF:
https://github.com/llvm/llvm-project/commit/c3403dc63d73710d14844e8a8cfad7a0f52d4a54.diff
LOG: [ASTMatchers] Fix build when no targets are enabled
This makes sense to do when building only tools like clang-tidy for
example.
Differential Revision: https://reviews.llvm.org/D93987
Added:
Modified:
llvm/cmake/modules/LLVM-Config.cmake
Removed:
diff --git a/llvm/cmake/modules/LLVM-Config.cmake
b/llvm/cmake/modules/LLVM-Config.cmake
index ebe13e7fc31c..5d9ec79c7c56 100644
--- a/llvm/cmake/modules/LLVM-Config.cmake
+++ b/llvm/cmake/modules/LLVM-Config.cmake
@@ -28,7 +28,9 @@ function(is_llvm_target_library library return_var)
string(TOUPPER "${LLVM_TARGETS_TO_BUILD}" targets)
elseif(ARG_OMITTED_TARGETS)
set(omitted_targets ${LLVM_ALL_TARGETS})
-list(REMOVE_ITEM omitted_targets ${LLVM_TARGETS_TO_BUILD})
+if (LLVM_TARGETS_TO_BUILD)
+ list(REMOVE_ITEM omitted_targets ${LLVM_TARGETS_TO_BUILD})
+endif()
string(TOUPPER "${omitted_targets}" targets)
else()
string(TOUPPER "${LLVM_ALL_TARGETS}" targets)
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[llvm-branch-commits] [llvm] 73a44f4 - [X86][AVX] combineVectorSignBitsTruncation - use PACKSS/PACKUS in more AVX cases
Author: Simon Pilgrim
Date: 2021-01-05T15:01:45Z
New Revision: 73a44f437bf19ecf2c865e6c8b9b8a2e4a811960
URL:
https://github.com/llvm/llvm-project/commit/73a44f437bf19ecf2c865e6c8b9b8a2e4a811960
DIFF:
https://github.com/llvm/llvm-project/commit/73a44f437bf19ecf2c865e6c8b9b8a2e4a811960.diff
LOG: [X86][AVX] combineVectorSignBitsTruncation - use PACKSS/PACKUS in more AVX
cases
AVX512 has fast truncation ops, but if the truncation source is a concatenation
of subvectors then its likely that we can use PACK more efficiently.
This is only guaranteed to work for truncations to 128/256-bit vectors as the
PACK works across 128-bit sub-lanes, for now I've just disabled 512-bit
truncation cases but we need to get them working eventually for D61129.
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/vector-pack-128.ll
llvm/test/CodeGen/X86/vector-pack-256.ll
Removed:
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 4dce5283b2ab..16f1023ed5f8 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -45706,8 +45706,13 @@ static SDValue combineVectorSignBitsTruncation(SDNode
*N, const SDLoc &DL,
// there's no harm in trying pack.
if (Subtarget.hasAVX512() &&
!(!Subtarget.useAVX512Regs() && VT.is256BitVector() &&
-InVT.is512BitVector()))
-return SDValue();
+InVT.is512BitVector())) {
+// PACK should still be worth it for 128/256-bit vectors if the sources
were
+// originally concatenated from subvectors.
+SmallVector ConcatOps;
+if (VT.getSizeInBits() > 256 || !collectConcatOps(In.getNode(), ConcatOps))
+ return SDValue();
+ }
unsigned NumPackedSignBits = std::min(SVT.getSizeInBits(), 16);
unsigned NumPackedZeroBits = Subtarget.hasSSE41() ? NumPackedSignBits : 8;
diff --git a/llvm/test/CodeGen/X86/vector-pack-128.ll
b/llvm/test/CodeGen/X86/vector-pack-128.ll
index 9b0bbac0199d..a49d0f9e3605 100644
--- a/llvm/test/CodeGen/X86/vector-pack-128.ll
+++ b/llvm/test/CodeGen/X86/vector-pack-128.ll
@@ -35,9 +35,7 @@ define <8 x i16> @trunc_concat_packssdw_128(<4 x i32> %a0, <4
x i32> %a1) nounwi
; AVX512: # %bb.0:
; AVX512-NEXT:vpsrad $17, %xmm0, %xmm0
; AVX512-NEXT:vpandd {{.*}}(%rip){1to4}, %xmm1, %xmm1
-; AVX512-NEXT:vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX512-NEXT:vpmovdw %ymm0, %xmm0
-; AVX512-NEXT:vzeroupper
+; AVX512-NEXT:vpackssdw %xmm1, %xmm0, %xmm0
; AVX512-NEXT:retq
%1 = ashr <4 x i32> %a0,
%2 = and <4 x i32> %a1,
@@ -80,9 +78,7 @@ define <8 x i16> @trunc_concat_packusdw_128(<4 x i32> %a0, <4
x i32> %a1) nounwi
; AVX512: # %bb.0:
; AVX512-NEXT:vpsrld $17, %xmm0, %xmm0
; AVX512-NEXT:vpandd {{.*}}(%rip){1to4}, %xmm1, %xmm1
-; AVX512-NEXT:vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX512-NEXT:vpmovdw %ymm0, %xmm0
-; AVX512-NEXT:vzeroupper
+; AVX512-NEXT:vpackusdw %xmm1, %xmm0, %xmm0
; AVX512-NEXT:retq
%1 = lshr <4 x i32> %a0,
%2 = and <4 x i32> %a1,
@@ -99,38 +95,12 @@ define <16 x i8> @trunc_concat_packsswb_128(<8 x i16> %a0,
<8 x i16> %a1) nounwi
; SSE-NEXT:packsswb %xmm1, %xmm0
; SSE-NEXT:retq
;
-; AVX1-LABEL: trunc_concat_packsswb_128:
-; AVX1: # %bb.0:
-; AVX1-NEXT:vpsraw $15, %xmm0, %xmm0
-; AVX1-NEXT:vpand {{.*}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT:vpacksswb %xmm1, %xmm0, %xmm0
-; AVX1-NEXT:retq
-;
-; AVX2-LABEL: trunc_concat_packsswb_128:
-; AVX2: # %bb.0:
-; AVX2-NEXT:vpsraw $15, %xmm0, %xmm0
-; AVX2-NEXT:vpand {{.*}}(%rip), %xmm1, %xmm1
-; AVX2-NEXT:vpacksswb %xmm1, %xmm0, %xmm0
-; AVX2-NEXT:retq
-;
-; AVX512F-LABEL: trunc_concat_packsswb_128:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT:vpsraw $15, %xmm0, %xmm0
-; AVX512F-NEXT:vpand {{.*}}(%rip), %xmm1, %xmm1
-; AVX512F-NEXT:vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX512F-NEXT:vpmovzxwd {{.*#+}} zmm0 =
ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
-; AVX512F-NEXT:vpmovdb %zmm0, %xmm0
-; AVX512F-NEXT:vzeroupper
-; AVX512F-NEXT:retq
-;
-; AVX512BW-LABEL: trunc_concat_packsswb_128:
-; AVX512BW: # %bb.0:
-; AVX512BW-NEXT:vpsraw $15, %xmm0, %xmm0
-; AVX512BW-NEXT:vpand {{.*}}(%rip), %xmm1, %xmm1
-; AVX512BW-NEXT:vinserti128 $1, %xmm1, %ymm0, %ymm0
-; AVX512BW-NEXT:vpmovwb %ymm0, %xmm0
-; AVX512BW-NEXT:vzeroupper
-; AVX512BW-NEXT:retq
+; AVX-LABEL: trunc_concat_packsswb_128:
+; AVX: # %bb.0:
+; AVX-NEXT:vpsraw $15, %xmm0, %xmm0
+; AVX-NEXT:vpand {{.*}}(%rip), %xmm1, %xmm1
+; AVX-NEXT:vpacksswb %xmm1, %xmm0, %xmm0
+; AVX-NEXT:retq
%1 = ashr <8 x i16> %a0,
%2 = and <8
[llvm-branch-commits] [llvm] 8a47e62 - [VPlan] Re-add interleave group members to plan.
Author: Florian Hahn
Date: 2021-01-05T15:06:47Z
New Revision: 8a47e6252ad43a2eb3238f9b36394571ba13f4a9
URL:
https://github.com/llvm/llvm-project/commit/8a47e6252ad43a2eb3238f9b36394571ba13f4a9
DIFF:
https://github.com/llvm/llvm-project/commit/8a47e6252ad43a2eb3238f9b36394571ba13f4a9.diff
LOG: [VPlan] Re-add interleave group members to plan.
Creating in-loop reductions relies on IR references to map
IR values to VPValues after interleave group creation.
Make sure we re-add the updated member to the plan, so the look-ups
still work as expected
This fixes a crash reported after D90562.
Added:
Modified:
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
Removed:
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 7f89fd9a1349..2bd35cca143e 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -8520,6 +8520,7 @@ VPlanPtr
LoopVectorizationPlanner::buildVPlanWithVPRecipes(
if (!Member->getType()->isVoidTy()) {
VPValue *OriginalV = Plan->getVPValue(Member);
Plan->removeVPValueFor(Member);
+ Plan->addVPValue(Member, VPIG->getVPValue(J));
OriginalV->replaceAllUsesWith(VPIG->getVPValue(J));
J++;
}
diff --git a/llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
b/llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
index fad08b91259b..0628aa888a24 100644
--- a/llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
+++ b/llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
@@ -950,4 +950,85 @@ for.cond.cleanup: ; preds
= %for.body, %entry
ret i8 %r.0.lcssa
}
+; Make sure interleave group members feeding in-loop reductions can be handled.
+define i32 @reduction_interleave_group(i32 %n, i32* %arr) #0 {
+; CHECK-LABEL: @reduction_interleave_group(
+; CHECK-NEXT: entry:
+; CHECK-NEXT:[[GUARD:%.*]] = icmp sgt i32 [[N:%.*]], 0
+; CHECK-NEXT:br i1 [[GUARD]], label [[FOR_BODY_PREHEADER:%.*]], label
[[EXIT:%.*]]
+; CHECK: for.body.preheader:
+; CHECK-NEXT:[[TMP0:%.*]] = add i32 [[N]], -1
+; CHECK-NEXT:[[TMP1:%.*]] = lshr i32 [[TMP0]], 1
+; CHECK-NEXT:[[TMP2:%.*]] = add nuw i32 [[TMP1]], 1
+; CHECK-NEXT:[[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP0]], 6
+; CHECK-NEXT:br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label
[[VECTOR_PH:%.*]]
+; CHECK: vector.ph:
+; CHECK-NEXT:[[N_VEC:%.*]] = and i32 [[TMP2]], -4
+; CHECK-NEXT:[[IND_END:%.*]] = shl i32 [[N_VEC]], 1
+; CHECK-NEXT:br label [[VECTOR_BODY:%.*]]
+; CHECK: vector.body:
+; CHECK-NEXT:[[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [
[[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:[[VEC_PHI:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [
[[TMP10:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:[[OFFSET_IDX:%.*]] = shl i32 [[INDEX]], 1
+; CHECK-NEXT:[[TMP3:%.*]] = or i32 [[OFFSET_IDX]], 1
+; CHECK-NEXT:[[TMP4:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]],
i32 -1
+; CHECK-NEXT:[[TMP5:%.*]] = getelementptr inbounds i32, i32* [[TMP4]], i32
[[TMP3]]
+; CHECK-NEXT:[[TMP6:%.*]] = bitcast i32* [[TMP5]] to <8 x i32>*
+; CHECK-NEXT:[[WIDE_VEC:%.*]] = load <8 x i32>, <8 x i32>* [[TMP6]], align
4
+; CHECK-NEXT:[[STRIDED_VEC:%.*]] = shufflevector <8 x i32> [[WIDE_VEC]],
<8 x i32> poison, <4 x i32>
+; CHECK-NEXT:[[STRIDED_VEC1:%.*]] = shufflevector <8 x i32> [[WIDE_VEC]],
<8 x i32> poison, <4 x i32>
+; CHECK-NEXT:[[TMP7:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x
i32> [[STRIDED_VEC1]])
+; CHECK-NEXT:[[TMP8:%.*]] = add i32 [[TMP7]], [[VEC_PHI]]
+; CHECK-NEXT:[[TMP9:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x
i32> [[STRIDED_VEC]])
+; CHECK-NEXT:[[TMP10]] = add i32 [[TMP9]], [[TMP8]]
+; CHECK-NEXT:[[INDEX_NEXT]] = add i32 [[INDEX]], 4
+; CHECK-NEXT:[[TMP11:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT:br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label
[[VECTOR_BODY]], [[LOOP13:!llvm.loop !.*]]
+; CHECK: middle.block:
+; CHECK-NEXT:[[CMP_N:%.*]] = icmp eq i32 [[TMP2]], [[N_VEC]]
+; CHECK-NEXT:br i1 [[CMP_N]], label [[EXIT]], label [[SCALAR_PH]]
+; CHECK: scalar.ph:
+; CHECK-NEXT:[[BC_RESUME_VAL:%.*]] = phi i32 [ [[IND_END]],
[[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_PREHEADER]] ]
+; CHECK-NEXT:[[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP10]], [[MIDDLE_BLOCK]]
], [ 0, [[FOR_BODY_PREHEADER]] ]
+; CHECK-NEXT:br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT:[[IV:%.*]] = phi i32 [ [[IV_NEXT:%.*]], [[FOR_BODY]] ], [
[[BC_RESUME_VAL]], [[SCALAR_PH]] ]
+; CHECK-NEXT:[[RED_PHI:%.*]] = phi i32 [ [[RED_2:%.*]], [[FOR_BODY]] ], [
[[BC_MERGE_RDX]], [[SCALAR_PH]] ]
+; CHECK
[llvm-branch-commits] [llvm] c005518 - [LoopNest] Allow empty basic blocks without loops
Author: Whitney Tsang
Date: 2021-01-05T15:09:38Z
New Revision: c00551893674d6d61e9e5d68412e2b8621f617b8
URL:
https://github.com/llvm/llvm-project/commit/c00551893674d6d61e9e5d68412e2b8621f617b8
DIFF:
https://github.com/llvm/llvm-project/commit/c00551893674d6d61e9e5d68412e2b8621f617b8.diff
LOG: [LoopNest] Allow empty basic blocks without loops
Allow loop nests with empty basic blocks without loops in different
levels as perfect.
Reviewers: Meinersbur
Differential Revision: https://reviews.llvm.org/D93665
Added:
Modified:
llvm/include/llvm/Analysis/LoopNestAnalysis.h
llvm/lib/Analysis/LoopNestAnalysis.cpp
llvm/test/Analysis/LoopNestAnalysis/perfectnest.ll
Removed:
diff --git a/llvm/include/llvm/Analysis/LoopNestAnalysis.h
b/llvm/include/llvm/Analysis/LoopNestAnalysis.h
index 4d77d735819f..f65ff493574c 100644
--- a/llvm/include/llvm/Analysis/LoopNestAnalysis.h
+++ b/llvm/include/llvm/Analysis/LoopNestAnalysis.h
@@ -59,6 +59,12 @@ class LoopNest {
/// getMaxPerfectDepth(Loop_i) would return 2.
static unsigned getMaxPerfectDepth(const Loop &Root, ScalarEvolution &SE);
+ /// Recursivelly traverse all empty 'single successor' basic blocks of \p
From
+ /// (if there are any). Return the last basic block found or \p End if it was
+ /// reached during the search.
+ static const BasicBlock &skipEmptyBlockUntil(const BasicBlock *From,
+ const BasicBlock *End);
+
/// Return the outermost loop in the loop nest.
Loop &getOutermostLoop() const { return *Loops.front(); }
@@ -128,6 +134,12 @@ class LoopNest {
[](const Loop *L) { return L->isLoopSimplifyForm(); });
}
+ /// Return true if all loops in the loop nest are in rotated form.
+ bool areAllLoopsRotatedForm() const {
+return std::all_of(Loops.begin(), Loops.end(),
+ [](const Loop *L) { return L->isRotatedForm(); });
+ }
+
StringRef getName() const { return Loops.front()->getName(); }
protected:
diff --git a/llvm/lib/Analysis/LoopNestAnalysis.cpp
b/llvm/lib/Analysis/LoopNestAnalysis.cpp
index ef10b7e97461..70b9ccaa87c1 100644
--- a/llvm/lib/Analysis/LoopNestAnalysis.cpp
+++ b/llvm/lib/Analysis/LoopNestAnalysis.cpp
@@ -16,6 +16,7 @@
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/PostDominators.h"
#include "llvm/Analysis/ValueTracking.h"
+#include "llvm/Transforms/Utils/BasicBlockUtils.h"
using namespace llvm;
@@ -206,6 +207,31 @@ unsigned LoopNest::getMaxPerfectDepth(const Loop &Root,
ScalarEvolution &SE) {
return CurrentDepth;
}
+const BasicBlock &LoopNest::skipEmptyBlockUntil(const BasicBlock *From,
+const BasicBlock *End) {
+ assert(From && "Expecting valid From");
+ assert(End && "Expecting valid End");
+
+ if (From == End || !From->getSingleSuccessor())
+return *From;
+
+ auto IsEmpty = [](const BasicBlock *BB) {
+return (BB->getInstList().size() == 1);
+ };
+
+ // Visited is used to avoid running into an infinite loop.
+ SmallPtrSet Visited;
+ const BasicBlock *BB = From->getSingleSuccessor();
+ const BasicBlock *PredBB = BB;
+ while (BB && BB != End && IsEmpty(BB) && !Visited.count(BB)) {
+Visited.insert(BB);
+PredBB = BB;
+BB = BB->getSingleSuccessor();
+ }
+
+ return (BB == End) ? *End : *PredBB;
+}
+
static bool checkLoopsStructure(const Loop &OuterLoop, const Loop &InnerLoop,
ScalarEvolution &SE) {
// The inner loop must be the only outer loop's child.
@@ -253,49 +279,67 @@ static bool checkLoopsStructure(const Loop &OuterLoop,
const Loop &InnerLoop,
// Ensure the only branch that may exist between the loops is the inner loop
// guard.
if (OuterLoopHeader != InnerLoopPreHeader) {
-const BranchInst *BI =
-dyn_cast(OuterLoopHeader->getTerminator());
-
-if (!BI || BI != InnerLoop.getLoopGuardBranch())
- return false;
-
-bool InnerLoopExitContainsLCSSA = ContainsLCSSAPhi(*InnerLoopExit);
-
-// The successors of the inner loop guard should be the inner loop
-// preheader and the outer loop latch.
-for (const BasicBlock *Succ : BI->successors()) {
- if (Succ == InnerLoopPreHeader)
-continue;
- if (Succ == OuterLoopLatch)
-continue;
-
- // If `InnerLoopExit` contains LCSSA Phi instructions, additional block
- // may be inserted before the `OuterLoopLatch` to which `BI` jumps. The
- // loops are still considered perfectly nested if the extra block only
- // contains Phi instructions from InnerLoopExit and OuterLoopHeader.
- if (InnerLoopExitContainsLCSSA && IsExtraPhiBlock(*Succ) &&
- Succ->getSingleSuccessor() == OuterLoopLatch) {
-// Points to the extra block so that we can reference it later in the
-// final check. We can also conclude that the inner loo
[llvm-branch-commits] [clang] 3d5b18a - [clang][AArch64][SVE] Avoid going through memory for coerced VLST arguments
Author: Joe Ellis
Date: 2021-01-05T15:18:21Z
New Revision: 3d5b18a3fdf47ae2286642131e4a92968dd01c2a
URL:
https://github.com/llvm/llvm-project/commit/3d5b18a3fdf47ae2286642131e4a92968dd01c2a
DIFF:
https://github.com/llvm/llvm-project/commit/3d5b18a3fdf47ae2286642131e4a92968dd01c2a.diff
LOG: [clang][AArch64][SVE] Avoid going through memory for coerced VLST arguments
VLST arguments are coerced to VLATs at the function boundary for
consistency with the VLAT ABI. They are then bitcast back to VLSTs in
the function prolog. Previously, this conversion is done through memory.
With the introduction of the llvm.vector.{insert,extract} intrinsic, we
can avoid going through memory here.
Depends on D92761
Differential Revision: https://reviews.llvm.org/D92762
Added:
Modified:
clang/lib/CodeGen/CGCall.cpp
clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
clang/test/CodeGen/attr-arm-sve-vector-bits-call.c
clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c
Removed:
diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index e28736bd3d2f..f1987408165b 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -2688,6 +2688,27 @@ void CodeGenFunction::EmitFunctionProlog(const
CGFunctionInfo &FI,
break;
}
+ // VLST arguments are coerced to VLATs at the function boundary for
+ // ABI consistency. If this is a VLST that was coerced to
+ // a VLAT at the function boundary and the types match up, use
+ // llvm.experimental.vector.extract to convert back to the original
+ // VLST.
+ if (auto *VecTyTo = dyn_cast(ConvertType(Ty))) {
+auto *Coerced = Fn->getArg(FirstIRArg);
+if (auto *VecTyFrom =
+dyn_cast(Coerced->getType())) {
+ if (VecTyFrom->getElementType() == VecTyTo->getElementType()) {
+llvm::Value *Zero = llvm::Constant::getNullValue(CGM.Int64Ty);
+
+assert(NumIRArgs == 1);
+Coerced->setName(Arg->getName() + ".coerce");
+
ArgVals.push_back(ParamValue::forDirect(Builder.CreateExtractVector(
+VecTyTo, Coerced, Zero, "castFixedSve")));
+break;
+ }
+}
+ }
+
Address Alloca = CreateMemTemp(Ty, getContext().getDeclAlign(Arg),
Arg->getName());
diff --git
a/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
b/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
index 9b733d21dbbb..9d3206a75f0e 100644
--- a/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
+++ b/clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
@@ -59,14 +59,14 @@ typedef int8_t vec_int8 __attribute__((vector_size(N / 8)));
// CHECK-LABEL: define{{.*}} void @f2(
// CHECK-SAME: <[[#div(VBITS,8)]] x i8>* noalias nocapture
sret(<[[#div(VBITS,8)]] x i8>) align 16 %agg.result, <[[#div(VBITS,8)]] x i8>*
nocapture readonly %0)
-// CHECK-NEXT: entry:
-// CHECK-NEXT:[[X:%.*]] = load <[[#div(VBITS,8)]] x i8>,
<[[#div(VBITS,8)]] x i8>* [[TMP0:%.*]], align 16, [[TBAA6:!tbaa !.*]]
-// CHECK-NEXT:[[TMP1:%.*]] = call
@llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
-// CHECK-NEXT:[[CASTSCALABLESVE:%.*]] = call
@llvm.experimental.vector.insert.nxv16i8.v[[#div(VBITS,8)]]i8( undef, <[[#div(VBITS,8)]] x i8> [[X]], i64 0)
-// CHECK-NEXT:[[TMP2:%.*]] = call
@llvm.aarch64.sve.asrd.nxv16i8( [[TMP1]],
[[CASTSCALABLESVE]], i32 1)
-// CHECK-NEXT:[[CASTFIXEDSVE:%.*]] = call <[[#div(VBITS,8)]] x i8>
@llvm.experimental.vector.extract.v[[#div(VBITS,8)]]i8.nxv16i8( [[TMP2]], i64 0)
-// CHECK-NEXT:store <[[#div(VBITS,8)]] x i8> [[CASTFIXEDSVE]],
<[[#div(VBITS,8)]] x i8>* [[AGG_RESULT:%.*]], align 16, [[TBAA6]]
-// CHECK-NEXT:ret void
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[X:%.*]] = load <[[#div(VBITS,8)]] x i8>, <[[#div(VBITS,8)]]
x i8>* [[TMP0:%.*]], align 16, [[TBAA6:!tbaa !.*]]
+// CHECK-NEXT: [[TMP1:%.*]] = call
@llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
+// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = call
@llvm.experimental.vector.insert.nxv16i8.v[[#div(VBITS,8)]]i8( undef, <[[#div(VBITS,8)]] x i8> [[X]], i64 0)
+// CHECK-NEXT: [[TMP2:%.*]] = call
@llvm.aarch64.sve.asrd.nxv16i8( [[TMP1]],
[[CASTSCALABLESVE]], i32 1)
+// CHECK-NEXT: [[CASTFIXEDSVE:%.*]] = call <[[#div(VBITS,8)]] x i8>
@llvm.experimental.vector.extract.v[[#div(VBITS,8)]]i8.nxv16i8( [[TMP2]], i64 0)
+// CHECK-NEXT: store <[[#div(VBITS,8)]] x i8> [[CASTFIXEDSVE]],
<[[#div(VBITS,8)]] x i8>* [[AGG_RESULT:%.*]], align 16, [[TBAA6]]
+// CHECK-NEXT: ret void
vec_int8 f2(vec_int8 x) { return svasrd_x(svptrue_b8(), x, 1); }
#endif
@@ -78,24 +78,18 @@ void f3(vec1);
typedef svint8_t vec2 __attrib
[llvm-branch-commits] [clang] 7e4f53f - [ASTMatchers] Fix traversal matchers with explicit and defaulted methods
Author: Stephen Kelly
Date: 2021-01-05T15:22:21Z
New Revision: 7e4f53f748d3c97f0b9b852bfbcab0740aba521b
URL:
https://github.com/llvm/llvm-project/commit/7e4f53f748d3c97f0b9b852bfbcab0740aba521b
DIFF:
https://github.com/llvm/llvm-project/commit/7e4f53f748d3c97f0b9b852bfbcab0740aba521b.diff
LOG: [ASTMatchers] Fix traversal matchers with explicit and defaulted methods
Differential Revision: https://reviews.llvm.org/D94030
Added:
Modified:
clang/include/clang/ASTMatchers/ASTMatchers.h
clang/include/clang/ASTMatchers/ASTMatchersInternal.h
clang/lib/ASTMatchers/ASTMatchFinder.cpp
clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
Removed:
diff --git a/clang/include/clang/ASTMatchers/ASTMatchers.h
b/clang/include/clang/ASTMatchers/ASTMatchers.h
index ba2dd862f171..a45e08345fb3 100644
--- a/clang/include/clang/ASTMatchers/ASTMatchers.h
+++ b/clang/include/clang/ASTMatchers/ASTMatchers.h
@@ -5490,6 +5490,9 @@ AST_MATCHER(FunctionDecl, isVariadic) {
/// \endcode
AST_MATCHER_P(CXXMethodDecl, ofClass,
internal::Matcher, InnerMatcher) {
+
+ ASTChildrenNotSpelledInSourceScope RAII(Finder, false);
+
const CXXRecordDecl *Parent = Node.getParent();
return (Parent != nullptr &&
InnerMatcher.matches(*Parent, Finder, Builder));
@@ -7037,6 +7040,9 @@ AST_MATCHER_P(FunctionDecl, hasExplicitSpecifier,
internal::Matcher,
ExplicitSpecifier ES = ExplicitSpecifier::getFromDecl(&Node);
if (!ES.getExpr())
return false;
+
+ ASTChildrenNotSpelledInSourceScope RAII(Finder, false);
+
return InnerMatcher.matches(*ES.getExpr(), Finder, Builder);
}
diff --git a/clang/include/clang/ASTMatchers/ASTMatchersInternal.h
b/clang/include/clang/ASTMatchers/ASTMatchersInternal.h
index f49728d1f50e..39b3a8406a61 100644
--- a/clang/include/clang/ASTMatchers/ASTMatchersInternal.h
+++ b/clang/include/clang/ASTMatchers/ASTMatchersInternal.h
@@ -742,6 +742,24 @@ class ASTMatchFinder {
const DynTypedMatcher &Matcher,
BoundNodesTreeBuilder *Builder,
AncestorMatchMode MatchMode) = 0;
+private:
+ friend struct ASTChildrenNotSpelledInSourceScope;
+ virtual bool isMatchingChildrenNotSpelledInSource() const = 0;
+ virtual void setMatchingChildrenNotSpelledInSource(bool Set) = 0;
+};
+
+struct ASTChildrenNotSpelledInSourceScope {
+ ASTChildrenNotSpelledInSourceScope(ASTMatchFinder *V, bool B)
+ : MV(V), MB(V->isMatchingChildrenNotSpelledInSource()) {
+V->setMatchingChildrenNotSpelledInSource(B);
+ }
+ ~ASTChildrenNotSpelledInSourceScope() {
+MV->setMatchingChildrenNotSpelledInSource(MB);
+ }
+
+private:
+ ASTMatchFinder *MV;
+ bool MB;
};
/// Specialization of the conversion functions for QualType.
diff --git a/clang/lib/ASTMatchers/ASTMatchFinder.cpp
b/clang/lib/ASTMatchers/ASTMatchFinder.cpp
index af21e2283d8b..54dc874470dd 100644
--- a/clang/lib/ASTMatchers/ASTMatchFinder.cpp
+++ b/clang/lib/ASTMatchers/ASTMatchFinder.cpp
@@ -666,6 +666,13 @@ class MatchASTVisitor : public
RecursiveASTVisitor,
bool IsMatchingInASTNodeNotSpelledInSource() const override {
return TraversingASTNodeNotSpelledInSource;
}
+ bool isMatchingChildrenNotSpelledInSource() const override {
+return TraversingASTChildrenNotSpelledInSource;
+ }
+ void setMatchingChildrenNotSpelledInSource(bool Set) override {
+TraversingASTChildrenNotSpelledInSource = Set;
+ }
+
bool IsMatchingInASTNodeNotAsIs() const override {
return TraversingASTNodeNotAsIs;
}
@@ -719,20 +726,6 @@ class MatchASTVisitor : public
RecursiveASTVisitor,
bool MB;
};
- struct ASTChildrenNotSpelledInSource {
-ASTChildrenNotSpelledInSource(MatchASTVisitor *V, bool B)
-: MV(V), MB(V->TraversingASTChildrenNotSpelledInSource) {
- V->TraversingASTChildrenNotSpelledInSource = B;
-}
-~ASTChildrenNotSpelledInSource() {
- MV->TraversingASTChildrenNotSpelledInSource = MB;
-}
-
- private:
-MatchASTVisitor *MV;
-bool MB;
- };
-
class TimeBucketRegion {
public:
TimeBucketRegion() : Bucket(nullptr) {}
@@ -1168,7 +1161,7 @@ bool MatchASTVisitor::TraverseDecl(Decl *DeclNode) {
}
ASTNodeNotSpelledInSourceScope RAII1(this, ScopedTraversal);
- ASTChildrenNotSpelledInSource RAII2(this, ScopedChildren);
+ ASTChildrenNotSpelledInSourceScope RAII2(this, ScopedChildren);
match(*DeclNode);
return RecursiveASTVisitor::TraverseDecl(DeclNode);
diff --git a/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
b/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
index 1dc5179ce857..cde3e460eeb0 100644
--- a/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
+++ b/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
@@ -2706,6 +2706,52 @@ void callDefaultArg()
EXPECT_TRUE(matches(Code, traverse(TK_AsIs, M)
[llvm-branch-commits] [llvm] bf09e25 - [gn build] Port fec1a442e3b
Author: LLVM GN Syncbot
Date: 2021-01-05T15:34:25Z
New Revision: bf09e25e1e9fb27db21fdb7ed54a72504137430a
URL:
https://github.com/llvm/llvm-project/commit/bf09e25e1e9fb27db21fdb7ed54a72504137430a
DIFF:
https://github.com/llvm/llvm-project/commit/bf09e25e1e9fb27db21fdb7ed54a72504137430a.diff
LOG: [gn build] Port fec1a442e3b
Added:
Modified:
llvm/utils/gn/secondary/clang/lib/Analysis/BUILD.gn
Removed:
diff --git a/llvm/utils/gn/secondary/clang/lib/Analysis/BUILD.gn
b/llvm/utils/gn/secondary/clang/lib/Analysis/BUILD.gn
index d6d22ad5411e..49ec784224b1 100644
--- a/llvm/utils/gn/secondary/clang/lib/Analysis/BUILD.gn
+++ b/llvm/utils/gn/secondary/clang/lib/Analysis/BUILD.gn
@@ -16,6 +16,7 @@ static_library("Analysis") {
"CFGReachabilityAnalysis.cpp",
"CFGStmtMap.cpp",
"CallGraph.cpp",
+"CalledOnceCheck.cpp",
"CloneDetection.cpp",
"CocoaConventions.cpp",
"CodeInjector.cpp",
___
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llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang-tools-extra] 53c3acb - [clang-tidy] Add extra tests
Author: Stephen Kelly
Date: 2021-01-05T15:43:56Z
New Revision: 53c3acb89fcc25ba7ef1f1d76a79c241eeacb7f0
URL:
https://github.com/llvm/llvm-project/commit/53c3acb89fcc25ba7ef1f1d76a79c241eeacb7f0
DIFF:
https://github.com/llvm/llvm-project/commit/53c3acb89fcc25ba7ef1f1d76a79c241eeacb7f0.diff
LOG: [clang-tidy] Add extra tests
By default, check_clang_tidy runs tests in c++11-or-later mode.
Differential Revision: https://reviews.llvm.org/D94029
Added:
Modified:
clang-tools-extra/test/clang-tidy/checkers/bugprone-suspicious-semicolon-constexpr.cpp
clang-tools-extra/test/clang-tidy/checkers/bugprone-unused-raii.cpp
clang-tools-extra/test/clang-tidy/checkers/bugprone-use-after-move.cpp
clang-tools-extra/test/clang-tidy/checkers/modernize-raw-string-literal.cpp
clang-tools-extra/test/clang-tidy/checkers/modernize-use-nodiscard.cpp
clang-tools-extra/test/clang-tidy/checkers/performance-unnecessary-value-param-header.cpp
clang-tools-extra/test/clang-tidy/checkers/readability-avoid-const-params-in-decls.cpp
clang-tools-extra/test/clang-tidy/checkers/readability-delete-null-pointer.cpp
clang-tools-extra/test/clang-tidy/checkers/readability-redundant-string-init.cpp
Removed:
diff --git
a/clang-tools-extra/test/clang-tidy/checkers/bugprone-suspicious-semicolon-constexpr.cpp
b/clang-tools-extra/test/clang-tidy/checkers/bugprone-suspicious-semicolon-constexpr.cpp
index c18dd7bd1e93..bc82ce1c3ad7 100644
---
a/clang-tools-extra/test/clang-tidy/checkers/bugprone-suspicious-semicolon-constexpr.cpp
+++
b/clang-tools-extra/test/clang-tidy/checkers/bugprone-suspicious-semicolon-constexpr.cpp
@@ -1,4 +1,4 @@
-// RUN: %check_clang_tidy %s bugprone-suspicious-semicolon %t -- -- -std=c++17
+// RUN: %check_clang_tidy -std=c++17-or-later %s bugprone-suspicious-semicolon
%t
void fail()
{
diff --git
a/clang-tools-extra/test/clang-tidy/checkers/bugprone-unused-raii.cpp
b/clang-tools-extra/test/clang-tidy/checkers/bugprone-unused-raii.cpp
index 91ade5242ef1..d637806ba20a 100644
--- a/clang-tools-extra/test/clang-tidy/checkers/bugprone-unused-raii.cpp
+++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone-unused-raii.cpp
@@ -36,6 +36,16 @@ struct Ctor {
}
};
+template
+void templ() {
+ T();
+}
+
+template
+void neverInstantiated() {
+ T();
+}
+
void test() {
Foo(42);
// CHECK-MESSAGES: :[[@LINE-1]]:3: warning: object destroyed immediately after
creation; did you mean to name the object?
@@ -54,6 +64,9 @@ void test() {
// CHECK-MESSAGES: :[[@LINE-1]]:3: warning: object destroyed immediately after
creation; did you mean to name the object?
// CHECK-FIXES: FooBar give_me_a_name;
+ templ();
+ templ();
+
Bar();
f();
qux();
diff --git
a/clang-tools-extra/test/clang-tidy/checkers/bugprone-use-after-move.cpp
b/clang-tools-extra/test/clang-tidy/checkers/bugprone-use-after-move.cpp
index 8a69ca42a072..527c79840696 100644
--- a/clang-tools-extra/test/clang-tidy/checkers/bugprone-use-after-move.cpp
+++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone-use-after-move.cpp
@@ -1,4 +1,4 @@
-// RUN: %check_clang_tidy %s bugprone-use-after-move %t -- -- -std=c++17
-fno-delayed-template-parsing
+// RUN: %check_clang_tidy -std=c++17-or-later %s bugprone-use-after-move %t --
-- -fno-delayed-template-parsing
typedef decltype(nullptr) nullptr_t;
diff --git
a/clang-tools-extra/test/clang-tidy/checkers/modernize-raw-string-literal.cpp
b/clang-tools-extra/test/clang-tidy/checkers/modernize-raw-string-literal.cpp
index 626dcbd8972b..859d3bf819ff 100644
---
a/clang-tools-extra/test/clang-tidy/checkers/modernize-raw-string-literal.cpp
+++
b/clang-tools-extra/test/clang-tidy/checkers/modernize-raw-string-literal.cpp
@@ -1,5 +1,4 @@
-// RUN: %check_clang_tidy -std=c++11,c++14,c++17 %s
modernize-raw-string-literal %t -- -config="{CheckOptions: [{key:
modernize-raw-string-literal.ReplaceShorterLiterals, value: 1}]}"
-// FIXME: Fix the checker to work in C++20 mode.
+// RUN: %check_clang_tidy %s modernize-raw-string-literal %t --
-config="{CheckOptions: [{key:
modernize-raw-string-literal.ReplaceShorterLiterals, value: 1}]}"
char const *const BackSlash("goink\\frob");
// CHECK-MESSAGES: :[[@LINE-1]]:29: warning: escaped string literal can be
written as a raw string literal [modernize-raw-string-literal]
@@ -47,8 +46,8 @@ char const *const MultibyteSnowman("\xE2\x98\x83");
char const *const TrailingSpace("A line \\with space. \n");
char const *const TrailingNewLine("A single \\line.\n");
char const *const AlreadyRaw(R"(foobie\\bletch)");
-char const *const UTF8Literal(u8"foobie\\bletch");
-char const *const UTF8RawLiteral(u8R"(foobie\\bletch)");
+auto const *const UTF8Literal(u8"foobie\\bletch");
+auto const *const UTF8RawLiteral(u8R"(foobie\\bletch)");
// TODO: enable these tests once all supported compilers
// support char16_t and char32_t (VS201
[llvm-branch-commits] [clang] 51d5991 - [Clang] Add AArch64 VCMLA LANE variants.
Author: Florian Hahn
Date: 2021-01-05T16:14:00Z
New Revision: 51d5991f04dda76c2f07123569b5c31ed3dfcfe8
URL:
https://github.com/llvm/llvm-project/commit/51d5991f04dda76c2f07123569b5c31ed3dfcfe8
DIFF:
https://github.com/llvm/llvm-project/commit/51d5991f04dda76c2f07123569b5c31ed3dfcfe8.diff
LOG: [Clang] Add AArch64 VCMLA LANE variants.
This patch adds the LANE variants for VCMLA on AArch64 as defined in
"Arm Neon Intrinsics Reference for ACLE Q3 2020" [1]
This patch also updates `dup_typed` to accept constant type strings directly.
Based on a patch by Tim Northover.
[1] https://developer.arm.com/documentation/ihi0073/latest
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D93014
Added:
Modified:
clang/include/clang/Basic/arm_neon.td
clang/test/CodeGen/aarch64-neon-vcmla.c
clang/utils/TableGen/NeonEmitter.cpp
Removed:
diff --git a/clang/include/clang/Basic/arm_neon.td
b/clang/include/clang/Basic/arm_neon.td
index 6f1380d58c16..3b2a578f796e 100644
--- a/clang/include/clang/Basic/arm_neon.td
+++ b/clang/include/clang/Basic/arm_neon.td
@@ -1902,6 +1902,24 @@ let ArchGuard =
"defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC)" in {
multiclass VCMLA_ROTS {
foreach ROT = ["", "_rot90", "_rot180", "_rot270" ] in {
def : SInst<"vcmla" # ROT, "", type # "Q" # type>;
+
+// vcmla{ROT}_lane
+def : SOpInst<"vcmla" # ROT # "_lane", "...qI", type, Op<(call "vcmla" #
ROT, $p0, $p1,
+ (bitcast $p0, (dup_typed lanety , (call "vget_lane", (bitcast
lanety, $p2), $p3>>;
+
+// vcmlaq{ROT}_lane
+def : SOpInst<"vcmla" # ROT # "_lane", "...qI", "Q" # type, Op<(call
"vcmla" # ROT, $p0, $p1,
+ (bitcast $p0, (dup_typed laneqty , (call "vget_lane", (bitcast
lanety, $p2), $p3>>;
+
+let isLaneQ = 1 in {
+ // vcmla{ROT}_laneq
+ def : SOpInst<"vcmla" # ROT # "_laneq", "...QI", type, Op<(call "vcmla"
# ROT, $p0, $p1,
+ (bitcast $p0, (dup_typed lanety, (call "vget_lane", (bitcast
laneqty, $p2), $p3>>;
+
+ // vcmlaq{ROT}_laneq
+ def : SOpInst<"vcmla" # ROT # "_laneq", "...QI", "Q" # type, Op<(call
"vcmla" # ROT, $p0, $p1,
+ (bitcast $p0, (dup_typed laneqty , (call "vget_lane", (bitcast
laneqty, $p2), $p3>>;
+}
}
}
diff --git a/clang/test/CodeGen/aarch64-neon-vcmla.c
b/clang/test/CodeGen/aarch64-neon-vcmla.c
index 2ecc1d5fbb3d..7b7a99d35b04 100644
--- a/clang/test/CodeGen/aarch64-neon-vcmla.c
+++ b/clang/test/CodeGen/aarch64-neon-vcmla.c
@@ -144,3 +144,323 @@ float32x4_t test_vcmlaq_rot270_f32(float32x4_t acc,
float32x4_t lhs, float32x4_t
float64x2_t test_vcmlaq_rot270_f64(float64x2_t acc, float64x2_t lhs,
float64x2_t rhs) {
return vcmlaq_rot270_f64(acc, lhs, rhs);
}
+
+// CHECK-LABEL: @test_vcmla_lane_f16(
+// CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32>
+// CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> undef, <2
x i32>
+// CHECK: [[DUP_FLT:%.*]] = bitcast <2 x i32> [[DUP]] to <4 x half>
+// CHECK: [[RES:%.*]] = call <4 x half> @llvm.aarch64.neon.vcmla.rot0.v4f16(<4
x half> %acc, <4 x half> %lhs, <4 x half> [[DUP_FLT]])
+// CHECK: ret <4 x half> [[RES]]
+float16x4_t test_vcmla_lane_f16(float16x4_t acc, float16x4_t lhs, float16x4_t
rhs) {
+ return vcmla_lane_f16(acc, lhs, rhs, 1);
+}
+
+// ACLE says this exists, but it won't map to a single instruction if lane > 1.
+// CHECK-LABEL: @test_vcmla_laneq_f16(
+// CHECK: [[CPLX:%.*]] = bitcast <8 x half> %rhs to <4 x i32>
+// CHECK: [[DUP:%.*]] = shufflevector <4 x i32> [[CPLX]], <4 x i32> undef, <2
x i32>
+// CHECK: [[DUP_FLT:%.*]] = bitcast <2 x i32> [[DUP]] to <4 x half>
+// CHECK: [[RES:%.*]] = call <4 x half> @llvm.aarch64.neon.vcmla.rot0.v4f16(<4
x half> %acc, <4 x half> %lhs, <4 x half> [[DUP_FLT]])
+// CHECK: ret <4 x half> [[RES]]
+float16x4_t test_vcmla_laneq_f16(float16x4_t acc, float16x4_t lhs, float16x8_t
rhs) {
+ return vcmla_laneq_f16(acc, lhs, rhs, 3);
+}
+
+// CHECK-LABEL: @test_vcmlaq_lane_f16(
+// CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32>
+// CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> undef, <4
x i32>
+// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
+// CHECK: [[RES:%.*]] = call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8
x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]])
+// CHECK: ret <8 x half> [[RES]]
+float16x8_t test_vcmlaq_lane_f16(float16x8_t acc, float16x8_t lhs, float16x4_t
rhs) {
+ return vcmlaq_lane_f16(acc, lhs, rhs, 1);
+}
+
+// CHECK-LABEL: @test_vcmlaq_laneq_f16(
+// CHECK: [[CPLX:%.*]] = bitcast <8 x half> %rhs to <4 x i32>
+// CHECK: [[DUP:%.*]] = shufflevector <4 x i32> [[CPLX]], <4 x i32> undef, <4
x i32>
+// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
+// CHECK: [[RES:%.*]] = call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8
x half> %
[llvm-branch-commits] [llvm] f26bc0d - [RegisterClassInfo] Return non-zero for RC without allocatable reg
Author: Jinsong Ji
Date: 2021-01-05T16:18:34Z
New Revision: f26bc0ddd508edad7e3838850dfcb6b960d6e681
URL:
https://github.com/llvm/llvm-project/commit/f26bc0ddd508edad7e3838850dfcb6b960d6e681
DIFF:
https://github.com/llvm/llvm-project/commit/f26bc0ddd508edad7e3838850dfcb6b960d6e681.diff
LOG: [RegisterClassInfo] Return non-zero for RC without allocatable reg
In some case, the RC may have 0 allocatable reg.
eg: VRSAVERC in PowerPC, which has only 1 reg, but it is also reserved.
The curreent implementation will keep calling the computePSetLimit because
getRegPressureSetLimit assume computePSetLimit will return a non-zero value.
The fix simply early return the value from TableGen for such special case.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D92907
Added:
Modified:
llvm/lib/CodeGen/RegisterClassInfo.cpp
llvm/test/CodeGen/PowerPC/compute-regpressure.ll
Removed:
diff --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp
b/llvm/lib/CodeGen/RegisterClassInfo.cpp
index 1523bd4d1649..0488db3d09cb 100644
--- a/llvm/lib/CodeGen/RegisterClassInfo.cpp
+++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp
@@ -188,7 +188,14 @@ unsigned RegisterClassInfo::computePSetLimit(unsigned Idx)
const {
}
assert(RC && "Failed to find register class");
compute(RC);
- unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC);
- return TRI->getRegPressureSetLimit(*MF, Idx) -
- TRI->getRegClassWeight(RC).RegWeight * NReserved;
+ unsigned NAllocatableRegs = getNumAllocatableRegs(RC);
+ unsigned RegPressureSetLimit = TRI->getRegPressureSetLimit(*MF, Idx);
+ // If all the regs are reserved, return raw RegPressureSetLimit.
+ // One example is VRSAVERC in PowerPC.
+ // Avoid returning zero, getRegPressureSetLimit(Idx) assumes computePSetLimit
+ // return non-zero value.
+ if (NAllocatableRegs == 0)
+return RegPressureSetLimit;
+ unsigned NReserved = RC->getNumRegs() - NAllocatableRegs;
+ return RegPressureSetLimit - TRI->getRegClassWeight(RC).RegWeight *
NReserved;
}
diff --git a/llvm/test/CodeGen/PowerPC/compute-regpressure.ll
b/llvm/test/CodeGen/PowerPC/compute-regpressure.ll
index 7a15e4677267..4ef7fa289381 100644
--- a/llvm/test/CodeGen/PowerPC/compute-regpressure.ll
+++ b/llvm/test/CodeGen/PowerPC/compute-regpressure.ll
@@ -1,7 +1,7 @@
; REQUIRES: asserts
; RUN: llc -debug-only=regalloc < %s 2>&1 |FileCheck %s --check-prefix=DEBUG
-; DEBUG-COUNT-3: AllocationOrder(VRSAVERC) = [ ]
+; DEBUG-COUNT-1: AllocationOrder(VRSAVERC) = [ ]
target triple = "powerpc64le-unknown-linux-gnu"
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[llvm-branch-commits] [clang-tools-extra] 9eb2284 - [clang-tidy] Update uses of deprecated Transformer APIs in StringFindStrContainsCheck.
Author: Yitzhak Mandelbaum
Date: 2021-01-05T16:49:29Z
New Revision: 9eb2284f60391eca246f12398d247fc1555d6bf5
URL:
https://github.com/llvm/llvm-project/commit/9eb2284f60391eca246f12398d247fc1555d6bf5
DIFF:
https://github.com/llvm/llvm-project/commit/9eb2284f60391eca246f12398d247fc1555d6bf5.diff
LOG: [clang-tidy] Update uses of deprecated Transformer APIs in
StringFindStrContainsCheck.
Migrates `change` to `changeTo`; changes to new constructor API (2-arg construct
+ `setRule`); refactors use of `addInclude` to newer version.
Differential Revision: https://reviews.llvm.org/D93695
Added:
Modified:
clang-tools-extra/clang-tidy/abseil/StringFindStrContainsCheck.cpp
Removed:
diff --git
a/clang-tools-extra/clang-tidy/abseil/StringFindStrContainsCheck.cpp
b/clang-tools-extra/clang-tidy/abseil/StringFindStrContainsCheck.cpp
index 977c1919cee3..3054689c9653 100644
--- a/clang-tools-extra/clang-tidy/abseil/StringFindStrContainsCheck.cpp
+++ b/clang-tools-extra/clang-tidy/abseil/StringFindStrContainsCheck.cpp
@@ -24,9 +24,10 @@ namespace clang {
namespace tidy {
namespace abseil {
+using ::clang::transformer::addInclude;
using ::clang::transformer::applyFirst;
using ::clang::transformer::cat;
-using ::clang::transformer::change;
+using ::clang::transformer::changeTo;
using ::clang::transformer::makeRule;
using ::clang::transformer::node;
using ::clang::transformer::RewriteRule;
@@ -38,22 +39,9 @@ static const char DefaultStringLikeClasses[] =
"::std::basic_string;"
"::absl::string_view";
static const char DefaultAbseilStringsMatchHeader[] = "absl/strings/match.h";
-static llvm::Optional
-MakeRule(const LangOptions &LangOpts,
- const ClangTidyCheck::OptionsView &Options) {
- // Parse options.
- //
- // FIXME(tdl-g): These options are being parsed redundantly with the
- // constructor because TransformerClangTidyCheck forces us to provide
MakeRule
- // before "this" is fully constructed, but StoreOptions requires us to store
- // the parsed options in "this". We need to fix TransformerClangTidyCheck
and
- // then we can clean this up.
- const std::vector StringLikeClassNames =
- utils::options::parseStringList(
- Options.get("StringLikeClasses", DefaultStringLikeClasses));
- const std::string AbseilStringsMatchHeader =
- Options.get("AbseilStringsMatchHeader", DefaultAbseilStringsMatchHeader);
-
+static transformer::RewriteRule
+makeRewriteRule(const std::vector &StringLikeClassNames,
+StringRef AbseilStringsMatchHeader) {
auto StringLikeClass = cxxRecordDecl(hasAnyName(SmallVector(
StringLikeClassNames.begin(), StringLikeClassNames.end(;
auto StringType =
@@ -75,29 +63,36 @@ MakeRule(const LangOptions &LangOpts,
onImplicitObjectArgument(expr().bind("string_being_searched")));
RewriteRule rule = applyFirst(
- {makeRule(binaryOperator(hasOperatorName("=="),
- hasOperands(ignoringParenImpCasts(StringNpos),
- ignoringParenImpCasts(StringFind))),
-change(cat("!absl::StrContains(",
node("string_being_searched"),
- ", ", node("parameter_to_find"), ")")),
-cat("use !absl::StrContains instead of find() == npos")),
- makeRule(binaryOperator(hasOperatorName("!="),
- hasOperands(ignoringParenImpCasts(StringNpos),
- ignoringParenImpCasts(StringFind))),
-change(cat("absl::StrContains(", node("string_being_searched"),
- ", ", node("parameter_to_find"), ")")),
-cat("use absl::StrContains instead of find() != npos"))});
- addInclude(rule, AbseilStringsMatchHeader);
+ {makeRule(
+ binaryOperator(hasOperatorName("=="),
+ hasOperands(ignoringParenImpCasts(StringNpos),
+ ignoringParenImpCasts(StringFind))),
+ {changeTo(cat("!absl::StrContains(", node("string_being_searched"),
+ ", ", node("parameter_to_find"), ")")),
+addInclude(AbseilStringsMatchHeader)},
+ cat("use !absl::StrContains instead of find() == npos")),
+ makeRule(
+ binaryOperator(hasOperatorName("!="),
+ hasOperands(ignoringParenImpCasts(StringNpos),
+ ignoringParenImpCasts(StringFind))),
+ {changeTo(cat("absl::StrContains(", node("string_being_searched"),
+ ", ", node("parameter_to_find"), ")")),
+addInclude(AbseilStringsMatchHeader)},
+ cat("use absl::StrContains instead "
+ "of find() != npos"))});
return rule;
}
StringFindStrContainsCheck::StringFindStrContainsCheck(
[llvm-branch-commits] [llvm] 60466fa - [AMDGPU] Remove deprecated V_MUL_LO_I32 from GFX10
Author: Joe Nash
Date: 2021-01-05T11:59:57-05:00
New Revision: 60466fad2dc155329cc870ea733d4f41561bd46d
URL:
https://github.com/llvm/llvm-project/commit/60466fad2dc155329cc870ea733d4f41561bd46d
DIFF:
https://github.com/llvm/llvm-project/commit/60466fad2dc155329cc870ea733d4f41561bd46d.diff
LOG: [AMDGPU] Remove deprecated V_MUL_LO_I32 from GFX10
It was removed in GFX10 GPUs, but LLVM could
generate it.
Reviewed By: rampitec, arsenm
Differential Revision: https://reviews.llvm.org/D94020
Change-Id: Id1c716d71313edcfb768b2b175a6789ef9b01f3c
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPU.td
llvm/lib/Target/AMDGPU/VOP3Instructions.td
llvm/test/MC/AMDGPU/gfx1030_unsupported.s
llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
Removed:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td
b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 42d134de9229..0a212a41ab6a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1131,6 +1131,11 @@ def isGFX10Plus :
Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">,
AssemblerPredicate<(all_of FeatureGFX10Insts)>;
+def isGFX10Before1030 :
+ Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 &&"
+"!Subtarget->hasGFX10_3Insts()">,
+ AssemblerPredicate<(all_of FeatureGFX10Insts,(not FeatureGFX10_3Insts))>;
+
def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
AssemblerPredicate<(all_of FeatureFlatAddressSpace)>;
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 28e4a09069a8..f349a0f54fa7 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -867,6 +867,10 @@ let InOperandList = (ins SSrcOrLds_b32:$src0,
SCSrc_b32:$src1, VGPR_32:$vdst_in)
defm V_WRITELANE_B32 : VOP3_Real_gfx10<0x361>;
} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1,
VGPR_32:$vdst_in)
+let SubtargetPredicate = isGFX10Before1030 in {
+ defm V_MUL_LO_I32 : VOP3_Real_gfx10<0x16b>;
+}
+
defm V_XOR3_B32 : VOP3_Real_gfx10<0x178>;
defm V_LSHLREV_B64: VOP3_Real_gfx10<0x2ff>;
defm V_LSHRREV_B64: VOP3_Real_gfx10<0x300>;
@@ -992,6 +996,7 @@ multiclass VOP3be_Real_gfx6_gfx7_gfx10 op> :
defm V_LSHL_B64: VOP3_Real_gfx6_gfx7<0x161>;
defm V_LSHR_B64: VOP3_Real_gfx6_gfx7<0x162>;
defm V_ASHR_I64: VOP3_Real_gfx6_gfx7<0x163>;
+defm V_MUL_LO_I32 : VOP3_Real_gfx6_gfx7<0x16b>;
defm V_MAD_LEGACY_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x140>;
defm V_MAD_F32 : VOP3_Real_gfx6_gfx7_gfx10<0x141>;
@@ -1033,7 +1038,6 @@ defm V_MAX_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x167>;
defm V_LDEXP_F64 : VOP3_Real_gfx6_gfx7_gfx10<0x168>;
defm V_MUL_LO_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x169>;
defm V_MUL_HI_U32 : VOP3_Real_gfx6_gfx7_gfx10<0x16a>;
-defm V_MUL_LO_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x16b>;
defm V_MUL_HI_I32 : VOP3_Real_gfx6_gfx7_gfx10<0x16c>;
defm V_DIV_FMAS_F32: VOP3_Real_gfx6_gfx7_gfx10<0x16f>;
defm V_DIV_FMAS_F64: VOP3_Real_gfx6_gfx7_gfx10<0x170>;
diff --git a/llvm/test/MC/AMDGPU/gfx1030_unsupported.s
b/llvm/test/MC/AMDGPU/gfx1030_unsupported.s
index b3660d66f21d..57cfb2f2514c 100644
--- a/llvm/test/MC/AMDGPU/gfx1030_unsupported.s
+++ b/llvm/test/MC/AMDGPU/gfx1030_unsupported.s
@@ -1,6 +1,9 @@
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1030
-mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck
--implicit-check-not=error: %s
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1030
-mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck
--implicit-check-not=error: %s
+v_mul_lo_i32 v0, v1, v2
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
//===--===//
// Unsupported dpp variants.
//===--===//
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
b/llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
index a4f77a4bbaad..be5b3d4a7cf3 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
@@ -6685,6 +6685,30 @@ v_mul_hi_u32 v5, v1, 0.5
v_mul_hi_u32 v5, v1, -4.0
// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xef,0x01,0x00]
+v_mul_lo_i32 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_lo_i32 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x6b,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_lo_i32 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0xff,0x05,0x02,0x00]
+
+v_mul_lo_i32 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x01,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, s103, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x67,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd5,0x6a,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, vcc_hi,
[llvm-branch-commits] [clang] 55488bd - CGExpr - EmitMatrixSubscriptExpr - fix getAs<> null-dereference static analyzer warning. NFCI.
Author: Simon Pilgrim
Date: 2021-01-05T17:08:11Z
New Revision: 55488bd3cd1a468941e26ad4cf94f2bad887fc02
URL:
https://github.com/llvm/llvm-project/commit/55488bd3cd1a468941e26ad4cf94f2bad887fc02
DIFF:
https://github.com/llvm/llvm-project/commit/55488bd3cd1a468941e26ad4cf94f2bad887fc02.diff
LOG: CGExpr - EmitMatrixSubscriptExpr - fix getAs<> null-dereference static
analyzer warning. NFCI.
getAs<> can return null if the cast is invalid, which can lead to null pointer
deferences. Use castAs<> instead which will assert that the cast is valid.
Added:
Modified:
clang/lib/CodeGen/CGExpr.cpp
Removed:
diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp
index 3013fffcbf6d..a3f90449bb4c 100644
--- a/clang/lib/CodeGen/CGExpr.cpp
+++ b/clang/lib/CodeGen/CGExpr.cpp
@@ -3858,7 +3858,7 @@ LValue CodeGenFunction::EmitMatrixSubscriptExpr(const
MatrixSubscriptExpr *E) {
llvm::Value *ColIdx = EmitScalarExpr(E->getColumnIdx());
llvm::Value *NumRows = Builder.getIntN(
RowIdx->getType()->getScalarSizeInBits(),
- E->getBase()->getType()->getAs()->getNumRows());
+ E->getBase()->getType()->castAs()->getNumRows());
llvm::Value *FinalIdx =
Builder.CreateAdd(Builder.CreateMul(ColIdx, NumRows), RowIdx);
return LValue::MakeMatrixElt(
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[llvm-branch-commits] [llvm] 0c59a4d - [ARM][AArch64] Some extra test to show anyextend lowering. NFC
Author: David Green
Date: 2021-01-05T17:34:23Z
New Revision: 0c59a4da59a42f04ba932fdab806fc4473d4e0b5
URL:
https://github.com/llvm/llvm-project/commit/0c59a4da59a42f04ba932fdab806fc4473d4e0b5
DIFF:
https://github.com/llvm/llvm-project/commit/0c59a4da59a42f04ba932fdab806fc4473d4e0b5.diff
LOG: [ARM][AArch64] Some extra test to show anyextend lowering. NFC
Added:
llvm/test/CodeGen/AArch64/lowerMUL-newload.ll
Modified:
llvm/test/CodeGen/ARM/lowerMUL-newload.ll
Removed:
diff --git a/llvm/test/CodeGen/AArch64/lowerMUL-newload.ll
b/llvm/test/CodeGen/AArch64/lowerMUL-newload.ll
new file mode 100644
index ..530aeed7f34c
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/lowerMUL-newload.ll
@@ -0,0 +1,439 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
+
+define <4 x i16> @mlai16_trunc(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16>
%vec2) {
+; CHECK-LABEL: mlai16_trunc:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT:smull v0.4s, v1.4h, v0.4h
+; CHECK-NEXT:saddw v0.4s, v0.4s, v2.4h
+; CHECK-NEXT:xtn v0.4h, v0.4s
+; CHECK-NEXT:ret
+entry:
+ %v0 = sext <4 x i16> %vec0 to <4 x i32>
+ %v1 = sext <4 x i16> %vec1 to <4 x i32>
+ %v2 = sext <4 x i16> %vec2 to <4 x i32>
+ %v3 = mul <4 x i32> %v1, %v0
+ %v4 = add <4 x i32> %v3, %v2
+ %v5 = trunc <4 x i32> %v4 to <4 x i16>
+ ret <4 x i16> %v5
+}
+
+define <4 x i32> @mlai16_and(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16>
%vec2) {
+; CHECK-LABEL: mlai16_and:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT:ushll v0.4s, v0.4h, #0
+; CHECK-NEXT:ushll v1.4s, v1.4h, #0
+; CHECK-NEXT:ushll v2.4s, v2.4h, #0
+; CHECK-NEXT:mla v2.4s, v1.4s, v0.4s
+; CHECK-NEXT:movi v0.2d, #0x00
+; CHECK-NEXT:and v0.16b, v2.16b, v0.16b
+; CHECK-NEXT:ret
+entry:
+ %v0 = sext <4 x i16> %vec0 to <4 x i32>
+ %v1 = sext <4 x i16> %vec1 to <4 x i32>
+ %v2 = sext <4 x i16> %vec2 to <4 x i32>
+ %v3 = mul <4 x i32> %v1, %v0
+ %v4 = add <4 x i32> %v3, %v2
+ %v5 = and <4 x i32> %v4,
+ ret <4 x i32> %v5
+}
+
+define void @mlai16_loadstore(i16* %a, i16* %b, i16* %c) {
+; CHECK-LABEL: mlai16_loadstore:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT:ldr d0, [x0, #16]
+; CHECK-NEXT:ldr d1, [x1, #16]
+; CHECK-NEXT:ldr d2, [x2, #16]
+; CHECK-NEXT:smull v0.4s, v1.4h, v0.4h
+; CHECK-NEXT:saddw v0.4s, v0.4s, v2.4h
+; CHECK-NEXT:xtn v0.4h, v0.4s
+; CHECK-NEXT:str d0, [x0, #16]
+; CHECK-NEXT:ret
+entry:
+ %scevgep0 = getelementptr i16, i16* %a, i32 8
+ %vector_ptr0 = bitcast i16* %scevgep0 to <4 x i16>*
+ %vec0 = load <4 x i16>, <4 x i16>* %vector_ptr0, align 8
+ %v0 = sext <4 x i16> %vec0 to <4 x i32>
+ %scevgep1 = getelementptr i16, i16* %b, i32 8
+ %vector_ptr1 = bitcast i16* %scevgep1 to <4 x i16>*
+ %vec1 = load <4 x i16>, <4 x i16>* %vector_ptr1, align 8
+ %v1 = sext <4 x i16> %vec1 to <4 x i32>
+ %scevgep2 = getelementptr i16, i16* %c, i32 8
+ %vector_ptr2 = bitcast i16* %scevgep2 to <4 x i16>*
+ %vec2 = load <4 x i16>, <4 x i16>* %vector_ptr2, align 8
+ %v2 = sext <4 x i16> %vec2 to <4 x i32>
+ %v3 = mul <4 x i32> %v1, %v0
+ %v4 = add <4 x i32> %v3, %v2
+ %v5 = trunc <4 x i32> %v4 to <4 x i16>
+ %scevgep3 = getelementptr i16, i16* %a, i32 8
+ %vector_ptr3 = bitcast i16* %scevgep3 to <4 x i16>*
+ store <4 x i16> %v5, <4 x i16>* %vector_ptr3, align 8
+ ret void
+}
+
+define <4 x i16> @addmuli16_trunc(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16>
%vec2) {
+; CHECK-LABEL: addmuli16_trunc:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT:smull v1.4s, v1.4h, v2.4h
+; CHECK-NEXT:smlal v1.4s, v0.4h, v2.4h
+; CHECK-NEXT:xtn v0.4h, v1.4s
+; CHECK-NEXT:ret
+entry:
+ %v0 = sext <4 x i16> %vec0 to <4 x i32>
+ %v1 = sext <4 x i16> %vec1 to <4 x i32>
+ %v2 = sext <4 x i16> %vec2 to <4 x i32>
+ %v3 = add <4 x i32> %v1, %v0
+ %v4 = mul <4 x i32> %v3, %v2
+ %v5 = trunc <4 x i32> %v4 to <4 x i16>
+ ret <4 x i16> %v5
+}
+
+define <4 x i32> @addmuli16_and(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16>
%vec2) {
+; CHECK-LABEL: addmuli16_and:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT:ushll v0.4s, v0.4h, #0
+; CHECK-NEXT:ushll v1.4s, v1.4h, #0
+; CHECK-NEXT:ushll v2.4s, v2.4h, #0
+; CHECK-NEXT:add v0.4s, v1.4s, v0.4s
+; CHECK-NEXT:mul v0.4s, v0.4s, v2.4s
+; CHECK-NEXT:movi v1.2d, #0x00
+; CHECK-NEXT:and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:ret
+entry:
+ %v0 = sext <4 x i16> %vec0 to <4 x i32>
+ %v1 = sext <4 x i16> %vec1 to <4 x i32>
+ %v2 = sext <4 x i16> %vec2 to <4 x i32>
+ %v3 = add <4 x i32> %v1, %v0
+ %v4 = mul <4 x i32> %v3, %v2
+ %v5 = and <4 x i32> %v4,
+ ret <4 x i32> %v5
+}
+
+define void @addmuli16_loadstore(i16* %a, i16* %b, i16* %c) {
+; CHECK-LABEL: addmuli16_loadstore:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT
[llvm-branch-commits] [clang] f22c0f4 - [ASTMatchers] Omit methods from explicit template instantations
Author: Stephen Kelly
Date: 2021-01-05T17:42:33Z
New Revision: f22c0f40b5d657c0293fc9332274c18d3c4f836c
URL:
https://github.com/llvm/llvm-project/commit/f22c0f40b5d657c0293fc9332274c18d3c4f836c
DIFF:
https://github.com/llvm/llvm-project/commit/f22c0f40b5d657c0293fc9332274c18d3c4f836c.diff
LOG: [ASTMatchers] Omit methods from explicit template instantations
Differential Revision: https://reviews.llvm.org/D94032
Added:
Modified:
clang/lib/ASTMatchers/ASTMatchFinder.cpp
clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
Removed:
diff --git a/clang/lib/ASTMatchers/ASTMatchFinder.cpp
b/clang/lib/ASTMatchers/ASTMatchFinder.cpp
index 54dc874470dd..99d95838af61 100644
--- a/clang/lib/ASTMatchers/ASTMatchFinder.cpp
+++ b/clang/lib/ASTMatchers/ASTMatchFinder.cpp
@@ -1158,6 +1158,8 @@ bool MatchASTVisitor::TraverseDecl(Decl *DeclNode) {
} else if (const auto *FD = dyn_cast(DeclNode)) {
if (FD->isDefaulted())
ScopedChildren = true;
+if (FD->isTemplateInstantiation())
+ ScopedTraversal = true;
}
ASTNodeNotSpelledInSourceScope RAII1(this, ScopedTraversal);
diff --git a/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
b/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
index cde3e460eeb0..e706ea4b2a54 100644
--- a/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
+++ b/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
@@ -2201,10 +2201,18 @@ struct TemplStruct {
TemplStruct() {}
~TemplStruct() {}
+ void outOfLine(T);
+
private:
T m_t;
};
+template
+void TemplStruct::outOfLine(T)
+{
+
+}
+
template
T timesTwo(T input)
{
@@ -2277,7 +2285,7 @@ template<> bool timesTwo(bool){
hasTemplateArgument(0, refersToType(asString("float";
EXPECT_TRUE(matches(Code, traverse(TK_AsIs, MTempl)));
// TODO: If we could match on explicit instantiations of function
templates,
-// this would be EXPECT_TRUE.
+// this would be EXPECT_TRUE. See Sema::ActOnExplicitInstantiation.
EXPECT_FALSE(
matches(Code, traverse(TK_IgnoreUnlessSpelledInSource, MTempl)));
}
@@ -2324,6 +2332,14 @@ template<> bool timesTwo(bool){
EXPECT_TRUE(matches(Code, traverse(TK_AsIs, M)));
EXPECT_FALSE(matches(Code, traverse(TK_IgnoreUnlessSpelledInSource, M)));
}
+ {
+// Instantiated, out-of-line methods are not matchable.
+auto M =
+cxxMethodDecl(hasName("outOfLine"), isDefinition(),
+ hasParameter(0,
parmVarDecl(hasType(asString("float");
+EXPECT_TRUE(matches(Code, traverse(TK_AsIs, M)));
+EXPECT_FALSE(matches(Code, traverse(TK_IgnoreUnlessSpelledInSource, M)));
+ }
{
// Explicit specialization is written in source and it matches:
auto M = classTemplateSpecializationDecl(
___
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[llvm-branch-commits] [mlir] 30dcbb2 - [mlir][Linalg] Add a test case that consumer has "reduction" loops.
Author: Hanhan Wang
Date: 2021-01-05T09:47:07-08:00
New Revision: 30dcbb2a83018da90bac9e52fdbf1b0770e941c2
URL:
https://github.com/llvm/llvm-project/commit/30dcbb2a83018da90bac9e52fdbf1b0770e941c2
DIFF:
https://github.com/llvm/llvm-project/commit/30dcbb2a83018da90bac9e52fdbf1b0770e941c2.diff
LOG: [mlir][Linalg] Add a test case that consumer has "reduction" loops.
In the past, this was a missing test case and the fusion was not supported. It's
supported after the revisit of init_tensor in Linalg.
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D94093
Added:
Modified:
mlir/test/Dialect/Linalg/fusion-tensor.mlir
Removed:
diff --git a/mlir/test/Dialect/Linalg/fusion-tensor.mlir
b/mlir/test/Dialect/Linalg/fusion-tensor.mlir
index df7e59d59dde..6a67b5dff10e 100644
--- a/mlir/test/Dialect/Linalg/fusion-tensor.mlir
+++ b/mlir/test/Dialect/Linalg/fusion-tensor.mlir
@@ -536,3 +536,45 @@ func @constant_fusion(%arg0 : tensor<4xf32>) ->
(tensor<4xf32>) {
// CHECK: %[[T2:.+]] = addf %[[ARG1]], %[[CST]]
// CHECK: linalg.yield %[[T2]]
// CHECK: return %[[T1]]
+
+// -
+
+#map0 = affine_map<(d0, d1) -> (d0, d1)>
+#map1 = affine_map<(d0) -> (0, d0)>
+#map2 = affine_map<(d0) -> (0)>
+func @consumer_with_reduction(%arg0: tensor<1x10xf32>,
+ %arg1: tensor<1x10xf32>,
+ %arg2: tensor<1xf32>) -> tensor<1xf32> {
+ %init = linalg.init_tensor [1, 10] : tensor<1x10xf32>
+ %0 = linalg.generic
+{indexing_maps = [#map0, #map0, #map0],
+ iterator_types = ["parallel", "parallel"]}
+ins(%arg0, %arg1 : tensor<1x10xf32>, tensor<1x10xf32>)
+outs(%init : tensor<1x10xf32>) {
+ ^bb0(%arg3: f32, %arg4: f32, %arg5: f32): // no predecessors
+%2 = addf %arg3, %arg4 : f32
+linalg.yield %2 : f32
+ } -> tensor<1x10xf32>
+ %1 = linalg.generic
+{indexing_maps = [#map1, #map2],
+ iterator_types = ["reduction"]}
+ins(%0 : tensor<1x10xf32>)
+outs(%arg2 : tensor<1xf32>) {
+ ^bb0(%arg3: f32, %arg4: f32): // no predecessors
+%2 = addf %arg3, %arg4 : f32
+linalg.yield %2 : f32
+ } -> tensor<1xf32>
+ return %1 : tensor<1xf32>
+}
+// CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0) -> (0, d0)>
+// CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0) -> (0)>
+// CHECK: func @consumer_with_reduction(%[[ARG0:.+]]: tensor<1x10xf32>,
%[[ARG1:.+]]: tensor<1x10xf32>, %[[ARG2:.+]]: tensor<1xf32>)
+// CHECK: %[[RES:.+]] = linalg.generic
+// CHECK-SAME: indexing_maps = [#[[MAP0]], #[[MAP0]], #[[MAP1]]]
+// CHECK-SAME: iterator_types = ["reduction"]
+// CHECK-SAME: ins(%[[ARG0]], %[[ARG1]] : tensor<1x10xf32>,
tensor<1x10xf32>)
+// CHECK: ^{{.+}}(%[[T0:.+]]: f32, %[[T1:.+]]: f32, %[[T2:.+]]: f32)
+// CHECK: %[[T3:.+]] = addf %[[T0]], %[[T1]] : f32
+// CHECK: %[[T4:.+]] = addf %[[T3]], %[[T2]] : f32
+// CHECK: linalg.yield %[[T4]]
+// CHECK: return %[[RES]]
___
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[llvm-branch-commits] [lldb] c82beab - [lldb] Add timers to Reproducer::Keep and Reproducer::Discard
Author: Jonas Devlieghere
Date: 2021-01-05T09:54:31-08:00
New Revision: c82beaba319657d93a62523a65f8969aad9ecab1
URL:
https://github.com/llvm/llvm-project/commit/c82beaba319657d93a62523a65f8969aad9ecab1
DIFF:
https://github.com/llvm/llvm-project/commit/c82beaba319657d93a62523a65f8969aad9ecab1.diff
LOG: [lldb] Add timers to Reproducer::Keep and Reproducer::Discard
Added:
Modified:
lldb/source/Utility/Reproducer.cpp
Removed:
diff --git a/lldb/source/Utility/Reproducer.cpp
b/lldb/source/Utility/Reproducer.cpp
index f238a2fabc39..f302cce4436f 100644
--- a/lldb/source/Utility/Reproducer.cpp
+++ b/lldb/source/Utility/Reproducer.cpp
@@ -9,6 +9,7 @@
#include "lldb/Utility/Reproducer.h"
#include "lldb/Utility/LLDBAssert.h"
#include "lldb/Utility/ReproducerProvider.h"
+#include "lldb/Utility/Timer.h"
#include "llvm/Support/FileSystem.h"
#include "llvm/Support/Threading.h"
@@ -194,6 +195,7 @@ ProviderBase
*Generator::Register(std::unique_ptr provider) {
}
void Generator::Keep() {
+ LLDB_SCOPED_TIMER();
assert(!m_done);
m_done = true;
@@ -204,6 +206,7 @@ void Generator::Keep() {
}
void Generator::Discard() {
+ LLDB_SCOPED_TIMER();
assert(!m_done);
m_done = true;
___
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[llvm-branch-commits] [clang] 675a297 - [libTooling] Add support for smart pointers to relevant Transformer `Stencil`s.
Author: Yitzhak Mandelbaum
Date: 2021-01-05T17:57:41Z
New Revision: 675a2973ee7745d1859e3b72be40a803dd349e55
URL:
https://github.com/llvm/llvm-project/commit/675a2973ee7745d1859e3b72be40a803dd349e55
DIFF:
https://github.com/llvm/llvm-project/commit/675a2973ee7745d1859e3b72be40a803dd349e55.diff
LOG: [libTooling] Add support for smart pointers to relevant Transformer
`Stencil`s.
Stencils `maybeDeref` and `maybeAddressOf` are designed to handle nodes that may
be pointers. Currently, they only handle native pointers. This patch extends the
support to recognize smart pointers and handle them as well.
Differential Revision: https://reviews.llvm.org/D93637
Added:
Modified:
clang/include/clang/Tooling/Transformer/Stencil.h
clang/lib/Tooling/Transformer/Stencil.cpp
clang/unittests/Tooling/StencilTest.cpp
Removed:
diff --git a/clang/include/clang/Tooling/Transformer/Stencil.h
b/clang/include/clang/Tooling/Transformer/Stencil.h
index b729c826c808..1b7495eb0262 100644
--- a/clang/include/clang/Tooling/Transformer/Stencil.h
+++ b/clang/include/clang/Tooling/Transformer/Stencil.h
@@ -82,7 +82,6 @@ Stencil deref(llvm::StringRef ExprId);
/// If \p ExprId is of pointer type, constructs an idiomatic dereferencing of
/// the expression bound to \p ExprId, including wrapping it in parentheses, if
/// needed. Otherwise, generates the original expression source.
-/// FIXME: Identify smart-pointers as pointer types.
Stencil maybeDeref(llvm::StringRef ExprId);
/// Constructs an expression that idiomatically takes the address of the
@@ -94,7 +93,6 @@ Stencil addressOf(llvm::StringRef ExprId);
/// idiomatically takes the address of the expression bound to \p ExprId,
/// including wrapping \p ExprId in parentheses, if needed. Otherwise,
generates
/// the original expression source.
-/// FIXME: Identify smart-pointers as pointer types.
Stencil maybeAddressOf(llvm::StringRef ExprId);
/// Constructs a `MemberExpr` that accesses the named member (\p Member) of the
diff --git a/clang/lib/Tooling/Transformer/Stencil.cpp
b/clang/lib/Tooling/Transformer/Stencil.cpp
index 56f145393691..d46087e4b04b 100644
--- a/clang/lib/Tooling/Transformer/Stencil.cpp
+++ b/clang/lib/Tooling/Transformer/Stencil.cpp
@@ -195,6 +195,24 @@ Error evalData(const DebugPrintNodeData &Data,
return printNode(Data.Id, Match, Result);
}
+// FIXME: Consider memoizing this function using the `ASTContext`.
+static bool isSmartPointerType(QualType Ty, ASTContext &Context) {
+ using namespace ::clang::ast_matchers;
+
+ // Optimization: hard-code common smart-pointer types. This can/should be
+ // removed if we start caching the results of this function.
+ auto KnownSmartPointer =
+ cxxRecordDecl(hasAnyName("::std::unique_ptr", "::std::shared_ptr"));
+ const auto QuacksLikeASmartPointer = cxxRecordDecl(
+ hasMethod(cxxMethodDecl(hasOverloadedOperatorName("->"),
+ returns(qualType(pointsTo(type()),
+ hasMethod(cxxMethodDecl(hasOverloadedOperatorName("*"),
+ returns(qualType(references(type()));
+ const auto SmartPointer = qualType(hasDeclaration(
+ cxxRecordDecl(anyOf(KnownSmartPointer, QuacksLikeASmartPointer;
+ return match(SmartPointer, Ty, Context).size() > 0;
+}
+
Error evalData(const UnaryOperationData &Data,
const MatchFinder::MatchResult &Match, std::string *Result) {
// The `Describe` operation can be applied to any node, not just expressions,
@@ -215,17 +233,37 @@ Error evalData(const UnaryOperationData &Data,
Source = tooling::buildDereference(*E, *Match.Context);
break;
case UnaryNodeOperator::MaybeDeref:
-if (!E->getType()->isAnyPointerType()) {
- *Result += tooling::getText(*E, *Match.Context);
- return Error::success();
+if (E->getType()->isAnyPointerType() ||
+isSmartPointerType(E->getType(), *Match.Context)) {
+ // Strip off any operator->. This can only occur inside an actual arrow
+ // member access, so we treat it as equivalent to an actual object
+ // expression.
+ if (const auto *OpCall = dyn_cast(E)) {
+if (OpCall->getOperator() == clang::OO_Arrow &&
+OpCall->getNumArgs() == 1) {
+ E = OpCall->getArg(0);
+}
+ }
+ Source = tooling::buildDereference(*E, *Match.Context);
+ break;
}
-Source = tooling::buildDereference(*E, *Match.Context);
-break;
+*Result += tooling::getText(*E, *Match.Context);
+return Error::success();
case UnaryNodeOperator::AddressOf:
Source = tooling::buildAddressOf(*E, *Match.Context);
break;
case UnaryNodeOperator::MaybeAddressOf:
-if (E->getType()->isAnyPointerType()) {
+if (E->getType()->isAnyPointerType() ||
+isSmartPointerType(E->getType(), *Match.Context)) {
+ // Strip off any operator->. This can only occ
[llvm-branch-commits] [llvm] a427f15 - GlobalISel: Add isKnownToBeAPowerOfTwo helper function
Author: Matt Arsenault
Date: 2021-01-05T12:59:08-05:00
New Revision: a427f15d6070fd50457c553a097e031139b40886
URL:
https://github.com/llvm/llvm-project/commit/a427f15d6070fd50457c553a097e031139b40886
DIFF:
https://github.com/llvm/llvm-project/commit/a427f15d6070fd50457c553a097e031139b40886.diff
LOG: GlobalISel: Add isKnownToBeAPowerOfTwo helper function
Added:
Modified:
llvm/include/llvm/CodeGen/GlobalISel/Utils.h
llvm/lib/CodeGen/GlobalISel/Utils.cpp
llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
Removed:
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
index 446aaf8c3551..9bd5180f7222 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
@@ -23,6 +23,7 @@
namespace llvm {
class AnalysisUsage;
+class GISelKnownBits;
class MachineFunction;
class MachineInstr;
class MachineOperand;
@@ -194,6 +195,12 @@ Optional ConstantFoldBinOp(unsigned Opcode, const
Register Op1,
Optional ConstantFoldExtOp(unsigned Opcode, const Register Op1,
uint64_t Imm, const MachineRegisterInfo
&MRI);
+/// Test if the given value is known to have exactly one bit set. This
diff ers
+/// from computeKnownBits in that it doesn't necessarily determine which bit is
+/// set.
+bool isKnownToBeAPowerOfTwo(Register Val, const MachineRegisterInfo &MRI,
+GISelKnownBits *KnownBits = nullptr);
+
/// Returns true if \p Val can be assumed to never be a NaN. If \p SNaN is
true,
/// this returns if \p Val can be assumed to never be a signaling NaN.
bool isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index c19ee2e3860f..aeacd4fb797d 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -14,6 +14,7 @@
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/Optional.h"
#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
+#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
@@ -551,6 +552,58 @@ Optional llvm::ConstantFoldExtOp(unsigned Opcode,
const Register Op1,
return None;
}
+bool llvm::isKnownToBeAPowerOfTwo(Register Reg, const MachineRegisterInfo &MRI,
+ GISelKnownBits *KB) {
+ Optional DefSrcReg =
+ getDefSrcRegIgnoringCopies(Reg, MRI);
+ if (!DefSrcReg)
+return false;
+
+ const MachineInstr &MI = *DefSrcReg->MI;
+ const LLT Ty = MRI.getType(Reg);
+
+ switch (MI.getOpcode()) {
+ case TargetOpcode::G_CONSTANT: {
+unsigned BitWidth = Ty.getScalarSizeInBits();
+const ConstantInt *CI = MI.getOperand(1).getCImm();
+return CI->getValue().zextOrTrunc(BitWidth).isPowerOf2();
+ }
+ case TargetOpcode::G_SHL: {
+// A left-shift of a constant one will have exactly one bit set because
+// shifting the bit off the end is undefined.
+
+// TODO: Constant splat
+if (auto ConstLHS = getConstantVRegVal(MI.getOperand(1).getReg(), MRI)) {
+ if (*ConstLHS == 1)
+return true;
+}
+
+break;
+ }
+ case TargetOpcode::G_LSHR: {
+if (auto ConstLHS = getConstantVRegVal(MI.getOperand(1).getReg(), MRI)) {
+ if (ConstLHS->isSignMask())
+return true;
+}
+
+break;
+ }
+ default:
+break;
+ }
+
+ // TODO: Are all operands of a build vector constant powers of two?
+ if (!KB)
+return false;
+
+ // More could be done here, though the above checks are enough
+ // to handle some common cases.
+
+ // Fall back to computeKnownBits to catch other known cases.
+ KnownBits Known = KB->getKnownBits(Reg);
+ return (Known.countMaxPopulation() == 1) && (Known.countMinPopulation() ==
1);
+}
+
void llvm::getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU) {
AU.addPreserved();
}
diff --git a/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
b/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
index 7888f461957e..b1e0548cdced 100644
--- a/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
@@ -528,6 +528,87 @@ TEST_F(AMDGPUGISelMITest, TestTargetKnownAlign) {
EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyImplicitBufferPtr));
}
+TEST_F(AMDGPUGISelMITest, TestIsKnownToBeAPowerOfTwo) {
+
+ StringRef MIRString = R"MIR(
+ %zero:_(s32) = G_CONSTANT i32 0
+ %one:_(s32) = G_CONSTANT i32 1
+ %two:_(s32) = G_CONSTANT i32 2
+ %three:_(s32) = G_CONSTANT i32 3
+ %five:_(s32) = G_CONSTANT i32 5
+ %copy_zero:_(s32) = COPY %zero
+ %copy_one:_(s32) = COPY %one
+ %copy_two:_(s32) = COPY %two
+ %copy_three:_(s32) = COPY %three
+
+ %trunc_two:_(s1) = G_TRUNC %two
+ %trunc_three
[llvm-branch-commits] [llvm] 761aca1 - [llvm-link] fix linker behavior when linking archives with --only-needed option
Author: Sergey Dmitriev
Date: 2021-01-05T10:02:51-08:00
New Revision: 761aca1e2e393da62ddaf7c42b61196be2466571
URL:
https://github.com/llvm/llvm-project/commit/761aca1e2e393da62ddaf7c42b61196be2466571
DIFF:
https://github.com/llvm/llvm-project/commit/761aca1e2e393da62ddaf7c42b61196be2466571.diff
LOG: [llvm-link] fix linker behavior when linking archives with --only-needed
option
This patch fixes linker behavior when archive is linked with other inputs
as a library (i.e. when --only-needed option is specified). In this case library
is expected to be normally linked first into a separate module and only after
that linker should import required symbols from the linked library module.
Reviewed By: tra
Differential Revision: https://reviews.llvm.org/D92535
Added:
llvm/test/tools/llvm-link/Inputs/i.ll
llvm/test/tools/llvm-link/archive-only-needed.ll
Modified:
llvm/tools/llvm-link/llvm-link.cpp
Removed:
diff --git a/llvm/test/tools/llvm-link/Inputs/i.ll
b/llvm/test/tools/llvm-link/Inputs/i.ll
new file mode 100644
index ..d23df3792a60
--- /dev/null
+++ b/llvm/test/tools/llvm-link/Inputs/i.ll
@@ -0,0 +1,8 @@
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+define void @i() {
+ call void @f()
+ ret void
+}
+
+declare void @f()
diff --git a/llvm/test/tools/llvm-link/archive-only-needed.ll
b/llvm/test/tools/llvm-link/archive-only-needed.ll
new file mode 100644
index ..d997e6c71b9c
--- /dev/null
+++ b/llvm/test/tools/llvm-link/archive-only-needed.ll
@@ -0,0 +1,15 @@
+; RUN: llvm-as %S/Inputs/f.ll -o %t.f.bc
+; RUN: llvm-as %S/Inputs/g.ll -o %t.g.bc
+; RUN: llvm-as %S/Inputs/i.ll -o %t.i.bc
+; RUN: rm -f %t.lib
+; RUN: llvm-ar cr %t.lib %t.f.bc %t.g.bc %t.i.bc
+; RUN: llvm-link %s %t.lib -o %t.linked.bc --only-needed
+; RUN: llvm-nm %t.linked.bc | FileCheck %s
+
+; CHECK: T f
+; CHECK: T i
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+@i = external global i8*
+@llvm.used = appending global [1 x i8*] [i8* bitcast (i8** @i to i8*)],
section "llvm.metadata"
diff --git a/llvm/tools/llvm-link/llvm-link.cpp
b/llvm/tools/llvm-link/llvm-link.cpp
index 6996c5bfbe76..61d0c1561054 100644
--- a/llvm/tools/llvm-link/llvm-link.cpp
+++ b/llvm/tools/llvm-link/llvm-link.cpp
@@ -142,9 +142,9 @@ static std::unique_ptr loadFile(const char *argv0,
return Result;
}
-static std::unique_ptr
-loadArFile(const char *Argv0, std::unique_ptr Buffer,
- LLVMContext &Context, unsigned OrigFlags, unsigned ApplicableFlags)
{
+static std::unique_ptr loadArFile(const char *Argv0,
+ std::unique_ptr Buffer,
+ LLVMContext &Context) {
std::unique_ptr Result(new Module("ArchiveModule", Context));
StringRef ArchiveName = Buffer->getBufferIdentifier();
if (Verbose)
@@ -197,9 +197,8 @@ loadArFile(const char *Argv0, std::unique_ptr
Buffer,
}
if (Verbose)
errs() << "Linking member '" << ChildName << "' of archive library.\n";
-if (Linker::linkModules(*Result, std::move(M), ApplicableFlags))
+if (Linker::linkModules(*Result, std::move(M)))
return nullptr;
-ApplicableFlags = OrigFlags;
} // end for each child
ExitOnErr(std::move(Err));
return Result;
@@ -354,8 +353,7 @@ static bool linkFiles(const char *argv0, LLVMContext
&Context, Linker &L,
std::unique_ptr M =
identify_magic(Buffer->getBuffer()) == file_magic::archive
-? loadArFile(argv0, std::move(Buffer), Context, Flags,
- ApplicableFlags)
+? loadArFile(argv0, std::move(Buffer), Context)
: loadFile(argv0, std::move(Buffer), Context);
if (!M.get()) {
errs() << argv0 << ": ";
___
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llvm-branch-commits@lists.llvm.org
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[llvm-branch-commits] [llvm] c707716 - [RISCV] Match vmslt(u).vx intrinsics with a small immediate to vmsle(u).vx.
Author: Craig Topper
Date: 2021-01-05T10:20:21-08:00
New Revision: c707716c049cd46bd89da102cf962487b490
URL:
https://github.com/llvm/llvm-project/commit/c707716c049cd46bd89da102cf962487b490
DIFF:
https://github.com/llvm/llvm-project/commit/c707716c049cd46bd89da102cf962487b490.diff
LOG: [RISCV] Match vmslt(u).vx intrinsics with a small immediate to vmsle(u).vx.
There are vmsle(u).vx and vmsle(u).vi instructions, but there is
only vmslt(u).vx and no vmslt(u).vi. vmslt(u).vi can be emulated
for some immediates by decrementing the immediate and using vmsle(u).vi.
To avoid the user needing to know about this, this patch does this
conversion.
The assembler does the same thing for vmslt(u).vi and vmsge(u).vi
pseudoinstructions. There is no vmsge(u).vx intrinsic or
instruction so this patch is limited to vmslt(u).
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D94070
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 87c4ca7c1253..d10c2a2c70ab 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -35,6 +35,11 @@ def NoX0 : SDNodeXForm;
+def DecImm : SDNodeXFormgetTargetConstant(N->getSExtValue() - 1, SDLoc(N),
+ N->getValueType(0));
+}]>;
+
//===--===//
// Utilities.
//===--===//
@@ -3080,6 +3085,71 @@ defm "" : VPatBinaryM_VV_VX_VI<"int_riscv_vmsle",
"PseudoVMSLE", AllIntegerVecto
defm "" : VPatBinaryM_VX_VI<"int_riscv_vmsgtu", "PseudoVMSGTU",
AllIntegerVectors>;
defm "" : VPatBinaryM_VX_VI<"int_riscv_vmsgt", "PseudoVMSGT",
AllIntegerVectors>;
+// Match vmslt(u).vx intrinsics to vmsle(u).vi if the scalar is -15 to 16. This
+// avoids the user needing to know that there is no vmslt(u).vi instruction.
+// This is limited to vmslt(u).vx as there is no vmsge().vx intrinsic or
+// instruction.
+foreach vti = AllIntegerVectors in {
+ def : Pat<(vti.Mask (int_riscv_vmslt (vti.Vector vti.RegClass:$rs1),
+ (vti.Scalar simm5_plus1:$rs2),
GPR:$vl)),
+(!cast("PseudoVMSLE_VI_"#vti.LMul.MX)
vti.RegClass:$rs1,
+ (DecImm
simm5_plus1:$rs2),
+ (NoX0 GPR:$vl),
+ vti.SEW)>;
+ def : Pat<(vti.Mask (int_riscv_vmslt_mask (vti.Mask V0),
+(vti.Vector vti.RegClass:$rs1),
+(vti.Scalar simm5_plus1:$rs2),
+(vti.Mask VR:$merge),
+GPR:$vl)),
+(!cast("PseudoVMSLE_VI_"#vti.LMul.MX#"_MASK")
+ VR:$merge,
+ vti.RegClass:$rs1,
+ (DecImm
simm5_plus1:$rs2),
+ (vti.Mask V0),
+ (NoX0 GPR:$vl),
+ vti.SEW)>;
+
+ def : Pat<(vti.Mask (int_riscv_vmsltu (vti.Vector vti.RegClass:$rs1),
+(vti.Scalar simm5_plus1:$rs2),
GPR:$vl)),
+(!cast("PseudoVMSLEU_VI_"#vti.LMul.MX)
vti.RegClass:$rs1,
+(DecImm
simm5_plus1:$rs2),
+(NoX0 GPR:$vl),
+vti.SEW)>;
+ def : Pat<(vti.Mask (int_riscv_vmsltu_mask (vti.Mask V0),
+ (vti.Vector vti.RegClass:$rs1),
+ (vti.Scalar simm5_plus1:$rs2),
+ (vti.Mask VR:$merge),
+ GPR:$vl)),
+(!cast("PseudoVMSLEU_VI_"#vti.LMul.MX#"_MASK")
+ VR:$merge,
+ vti.RegClass:$rs1,
+ (DecImm
simm5_plus1:$rs2),
+ (vti.Mask V0),
+
[llvm-branch-commits] [llvm] 3b8b2c7 - [SLP] delete unused pairwise reduction option
Author: Sanjay Patel
Date: 2021-01-05T13:23:07-05:00
New Revision: 3b8b2c7da2efb88d9f13e911e383af430ab463ef
URL:
https://github.com/llvm/llvm-project/commit/3b8b2c7da2efb88d9f13e911e383af430ab463ef
DIFF:
https://github.com/llvm/llvm-project/commit/3b8b2c7da2efb88d9f13e911e383af430ab463ef.diff
LOG: [SLP] delete unused pairwise reduction option
SLP tries to model 2 forms of vector reductions: pairwise and splitting.
>From the cost model code comments, those are defined using an example as:
/// Pairwise:
/// (v0, v1, v2, v3)
/// ((v0+v1), (v2+v3), undef, undef)
/// Split:
/// (v0, v1, v2, v3)
/// ((v0+v2), (v1+v3), undef, undef)
I don't know the full history of this functionality, but it was partly
added back in D29402. There are apparently no users at this point (no
regression tests change). X86 might have managed to work-around the need
for this through cost model and codegen improvements.
Removing this code makes it easier to continue the work that was started
in D87416 / D88193. The alternative -- if there is some target that is
silently using this option -- is to move this logic into LoopUtils. We
have related/duplicate functionality there via llvm::createTargetReduction().
Differential Revision: https://reviews.llvm.org/D93860
Added:
Modified:
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Removed:
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index a655d3dd91bd..8965a44ffd2b 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -6382,35 +6382,6 @@ bool SLPVectorizerPass::tryToVectorize(Instruction *I,
BoUpSLP &R) {
return false;
}
-/// Generate a shuffle mask to be used in a reduction tree.
-///
-/// \param VecLen The length of the vector to be reduced.
-/// \param NumEltsToRdx The number of elements that should be reduced in the
-///vector.
-/// \param IsPairwise Whether the reduction is a pairwise or splitting
-///reduction. A pairwise reduction will generate a mask of
-///<0,2,...> or <1,3,..> while a splitting reduction will generate
-///<2,3, undef,undef> for a vector of 4 and NumElts = 2.
-/// \param IsLeft True will generate a mask of even elements, odd otherwise.
-static SmallVector createRdxShuffleMask(unsigned VecLen,
- unsigned NumEltsToRdx,
- bool IsPairwise, bool IsLeft)
{
- assert((IsPairwise || !IsLeft) && "Don't support a <0,1,undef,...> mask");
-
- SmallVector ShuffleMask(VecLen, -1);
-
- if (IsPairwise)
-// Build a mask of 0, 2, ... (left) or 1, 3, ... (right).
-for (unsigned i = 0; i != NumEltsToRdx; ++i)
- ShuffleMask[i] = 2 * i + !IsLeft;
- else
-// Move the upper half of the vector to the lower half.
-for (unsigned i = 0; i != NumEltsToRdx; ++i)
- ShuffleMask[i] = NumEltsToRdx + i;
-
- return ShuffleMask;
-}
-
namespace {
/// Model horizontal reductions.
@@ -6730,10 +6701,6 @@ class HorizontalReduction {
/// The operation data for the leaf values that we perform a reduction on.
OperationData RdxLeafVal;
- /// Should we model this reduction as a pairwise reduction tree or a tree
that
- /// splits the vector in halves and adds those halves.
- bool IsPairwiseReduction = false;
-
/// Checks if the ParentStackElem.first should be marked as a reduction
/// operation with an extra argument or as extra argument itself.
void markExtraArg(std::pair &ParentStackElem,
@@ -7170,7 +7137,6 @@ class HorizontalReduction {
Type *ScalarTy = FirstReducedVal->getType();
auto *VecTy = FixedVectorType::get(ScalarTy, ReduxWidth);
-int PairwiseRdxCost;
int SplittingRdxCost;
switch (RdxTreeInst.getKind()) {
case RecurKind::Add:
@@ -7180,9 +7146,6 @@ class HorizontalReduction {
case RecurKind::Xor:
case RecurKind::FAdd:
case RecurKind::FMul:
- PairwiseRdxCost =
- TTI->getArithmeticReductionCost(RdxTreeInst.getOpcode(), VecTy,
- /*IsPairwiseForm=*/true);
SplittingRdxCost =
TTI->getArithmeticReductionCost(RdxTreeInst.getOpcode(), VecTy,
/*IsPairwiseForm=*/false);
@@ -7194,9 +7157,6 @@ class HorizontalReduction {
auto *VecCondTy = cast(CmpInst::makeCmpResultType(VecTy));
RecurKind Kind = RdxTreeInst.getKind();
bool IsUnsigned = Kind == RecurKind::UMax || Kind == RecurKind::UMin;
- PairwiseRdxCost =
- TTI->getMinMaxReductionCost(VecTy, VecCondTy,
- /*IsPairwiseForm=*/true, IsUnsigned);
SplittingRdxCost =
TTI->getMinMaxReductionCost(VecTy, VecCondTy,
/*IsPairwiseForm=*/false, IsUnsi
[llvm-branch-commits] [llvm] 249d7de - [RISCV] Don't print zext.b alias.
Author: Craig Topper
Date: 2021-01-05T10:41:08-08:00
New Revision: 249d7de1190f50178181d2477aa661cd252e294c
URL:
https://github.com/llvm/llvm-project/commit/249d7de1190f50178181d2477aa661cd252e294c
DIFF:
https://github.com/llvm/llvm-project/commit/249d7de1190f50178181d2477aa661cd252e294c.diff
LOG: [RISCV] Don't print zext.b alias.
This alias for andi x, 255 was recently added to the spec. If we
print it, code we output can't be compiled with -fno-integrated-as
unless the GNU assembler is also a version that supports alias.
Reviewed By: lenary
Differential Revision: https://reviews.llvm.org/D93826
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/alu8.ll
llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
llvm/test/CodeGen/RISCV/atomic-rmw.ll
llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll
llvm/test/CodeGen/RISCV/rv32Zbbp.ll
llvm/test/CodeGen/RISCV/rv64Zbbp.ll
llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
llvm/test/MC/RISCV/rv32b-aliases-valid.s
llvm/test/MC/RISCV/rv32i-aliases-valid.s
llvm/test/MC/RISCV/rv64b-aliases-valid.s
llvm/test/MC/RISCV/rv64i-aliases-valid.s
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index e31cbd37877d..98f8935d8a05 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -809,7 +809,10 @@ def : MnemonicAlias<"move", "mv">;
def : MnemonicAlias<"scall", "ecall">;
def : MnemonicAlias<"sbreak", "ebreak">;
-def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF)>;
+// This alias was added to the spec in December 2020. Don't print it by default
+// to allow assembly we print to be compatible with versions of GNU assembler
+// that don't support this alias.
+def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF), 0>;
//===--===//
// Pseudo-instructions and codegen patterns
diff --git a/llvm/test/CodeGen/RISCV/alu8.ll b/llvm/test/CodeGen/RISCV/alu8.ll
index 1462b1b70eb5..ed09174745b8 100644
--- a/llvm/test/CodeGen/RISCV/alu8.ll
+++ b/llvm/test/CodeGen/RISCV/alu8.ll
@@ -44,13 +44,13 @@ define i8 @slti(i8 %a) nounwind {
define i8 @sltiu(i8 %a) nounwind {
; RV32I-LABEL: sltiu:
; RV32I: # %bb.0:
-; RV32I-NEXT:zext.b a0, a0
+; RV32I-NEXT:andi a0, a0, 255
; RV32I-NEXT:sltiu a0, a0, 3
; RV32I-NEXT:ret
;
; RV64I-LABEL: sltiu:
; RV64I: # %bb.0:
-; RV64I-NEXT:zext.b a0, a0
+; RV64I-NEXT:andi a0, a0, 255
; RV64I-NEXT:sltiu a0, a0, 3
; RV64I-NEXT:ret
%1 = icmp ult i8 %a, 3
@@ -215,15 +215,15 @@ define i8 @slt(i8 %a, i8 %b) nounwind {
define i8 @sltu(i8 %a, i8 %b) nounwind {
; RV32I-LABEL: sltu:
; RV32I: # %bb.0:
-; RV32I-NEXT:zext.b a1, a1
-; RV32I-NEXT:zext.b a0, a0
+; RV32I-NEXT:andi a1, a1, 255
+; RV32I-NEXT:andi a0, a0, 255
; RV32I-NEXT:sltu a0, a0, a1
; RV32I-NEXT:ret
;
; RV64I-LABEL: sltu:
; RV64I: # %bb.0:
-; RV64I-NEXT:zext.b a1, a1
-; RV64I-NEXT:zext.b a0, a0
+; RV64I-NEXT:andi a1, a1, 255
+; RV64I-NEXT:andi a0, a0, 255
; RV64I-NEXT:sltu a0, a0, a1
; RV64I-NEXT:ret
%1 = icmp ult i8 %a, %b
@@ -248,13 +248,13 @@ define i8 @xor(i8 %a, i8 %b) nounwind {
define i8 @srl(i8 %a, i8 %b) nounwind {
; RV32I-LABEL: srl:
; RV32I: # %bb.0:
-; RV32I-NEXT:zext.b a0, a0
+; RV32I-NEXT:andi a0, a0, 255
; RV32I-NEXT:srl a0, a0, a1
; RV32I-NEXT:ret
;
; RV64I-LABEL: srl:
; RV64I: # %bb.0:
-; RV64I-NEXT:zext.b a0, a0
+; RV64I-NEXT:andi a0, a0, 255
; RV64I-NEXT:srl a0, a0, a1
; RV64I-NEXT:ret
%1 = lshr i8 %a, %b
diff --git a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
index 272af5604550..6656e3d964d6 100644
--- a/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
@@ -29,9 +29,9 @@ define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8
%cmp, i8 %val) nounwind
; RV32IA-NEXT:andi a0, a0, 24
; RV32IA-NEXT:addi a4, zero, 255
; RV32IA-NEXT:sll a4, a4, a0
-; RV32IA-NEXT:zext.b a1, a1
+; RV32IA-NEXT:andi a1, a1, 255
; RV32IA-NEXT:sll a1, a1, a0
-; RV32IA-NEXT:zext.b a2, a2
+; RV32IA-NEXT:andi a2, a2, 255
; RV32IA-NEXT:sll a0, a2, a0
; RV32IA-NEXT: .LBB0_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT:lr.w a2, (a3)
@@ -66,9 +66,9 @@ define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8
%cmp, i8 %val) nounwind
; RV64IA-NEXT:andi a0, a0, 24
; RV64IA-NEXT:addi a4, zero, 255
; RV64IA-NEXT:sllw a4, a4, a0
-; RV64IA-NEXT:zext
[llvm-branch-commits] [mlir] 7afd5cf - [NFC] Fix -Wrange-loop-analysis warnings.
Author: Dan Zheng
Date: 2021-01-05T18:44:17Z
New Revision: 7afd5cfbc757b004cba99d234df4e76b06956b2d
URL:
https://github.com/llvm/llvm-project/commit/7afd5cfbc757b004cba99d234df4e76b06956b2d
DIFF:
https://github.com/llvm/llvm-project/commit/7afd5cfbc757b004cba99d234df4e76b06956b2d.diff
LOG: [NFC] Fix -Wrange-loop-analysis warnings.
Remove unnecessary `&` from loop variables.
Fix warnings: "loop variable is always a copy because the range does not
return a reference".
```
[240/2862] Building CXX object
tools/mlir/tools/mlir-tblgen/CMakeFiles/mlir-tblgen.dir/TypeDefGen.cpp.o
llvm-project/mlir/tools/mlir-tblgen/TypeDefGen.cpp:50:25: warning: loop
variable 'typeDef' is always a copy because the range of type
'llvm::iterator_range, (lambda at llvm-project/mlir/tools/mlir-tblgen/TypeDefGen.cpp:40:16),
mlir::tblgen::TypeDef> >' does not return a reference [-Wrange-loop-analysis]
for (const TypeDef &typeDef : defs)
^
llvm-project/mlir/tools/mlir-tblgen/TypeDefGen.cpp:50:10: note: use
non-reference type 'mlir::tblgen::TypeDef'
for (const TypeDef &typeDef : defs)
^~~~
llvm-project/mlir/tools/mlir-tblgen/TypeDefGen.cpp:64:23: warning: loop
variable 'typeDef' is always a copy because the range of type
'llvm::iterator_range, (lambda at llvm-project/mlir/tools/mlir-tblgen/TypeDefGen.cpp:40:16),
mlir::tblgen::TypeDef> >' does not return a reference [-Wrange-loop-analysis]
for (const TypeDef &typeDef : defs)
^
llvm-project/mlir/tools/mlir-tblgen/TypeDefGen.cpp:64:8: note: use
non-reference type 'mlir::tblgen::TypeDef'
for (const TypeDef &typeDef : defs)
^~~~
2 warnings generated.
[1934/2862] Building CXX object tools...Files/toyc-ch4.dir/mlir/MLIRGen.cpp.o
llvm-project/mlir/examples/toy/Ch4/mlir/MLIRGen.cpp:139:22: warning: loop
variable 'name_value' is always a copy because the range of type
'detail::zippy > > &, MutableArrayRef >' does
not return a reference [-Wrange-loop-analysis]
for (const auto &name_value :
^
llvm-project/mlir/examples/toy/Ch4/mlir/MLIRGen.cpp:139:10: note: use
non-reference type 'std::__1::tuple > &, mlir::BlockArgument &>'
for (const auto &name_value :
^~~~
1 warning generated.
[1940/2862] Building CXX object tools...Files/toyc-ch5.dir/mlir/MLIRGen.cpp.o
llvm-project/mlir/examples/toy/Ch5/mlir/MLIRGen.cpp:139:22: warning: loop
variable 'name_value' is always a copy because the range of type
'detail::zippy > > &, MutableArrayRef >' does
not return a reference [-Wrange-loop-analysis]
for (const auto &name_value :
^
llvm-project/mlir/examples/toy/Ch5/mlir/MLIRGen.cpp:139:10: note: use
non-reference type 'std::__1::tuple > &, mlir::BlockArgument &>'
for (const auto &name_value :
^~~~
1 warning generated.
```
Reviewed By: jpienaar
Differential Revision: https://reviews.llvm.org/D94003
Added:
Modified:
mlir/examples/toy/Ch2/mlir/MLIRGen.cpp
mlir/examples/toy/Ch3/mlir/MLIRGen.cpp
mlir/examples/toy/Ch4/mlir/MLIRGen.cpp
mlir/examples/toy/Ch5/mlir/MLIRGen.cpp
mlir/examples/toy/Ch6/mlir/MLIRGen.cpp
mlir/examples/toy/Ch7/mlir/Dialect.cpp
mlir/examples/toy/Ch7/mlir/MLIRGen.cpp
mlir/tools/mlir-tblgen/TypeDefGen.cpp
Removed:
diff --git a/mlir/examples/toy/Ch2/mlir/MLIRGen.cpp
b/mlir/examples/toy/Ch2/mlir/MLIRGen.cpp
index 282a1bc76815..8b9f9dbdf190 100644
--- a/mlir/examples/toy/Ch2/mlir/MLIRGen.cpp
+++ b/mlir/examples/toy/Ch2/mlir/MLIRGen.cpp
@@ -136,10 +136,10 @@ class MLIRGenImpl {
auto protoArgs = funcAST.getProto()->getArgs();
// Declare all the function arguments in the symbol table.
-for (const auto &name_value :
+for (const auto nameValue :
llvm::zip(protoArgs, entryBlock.getArguments())) {
- if (failed(declare(std::get<0>(name_value)->getName(),
- std::get<1>(name_value
+ if (failed(declare(std::get<0>(nameValue)->getName(),
+ std::get<1>(nameValue
return nullptr;
}
diff --git a/mlir/examples/toy/Ch3/mlir/MLIRGen.cpp
b/mlir/examples/toy/Ch3/mlir/MLIRGen.cpp
index 282a1bc76815..8b9f9dbdf190 100644
--- a/mlir/examples/toy/Ch3/mlir/MLIRGen.cpp
+++ b/mlir/examples/toy/Ch3/mlir/MLIRGen.cpp
@@ -136,10 +136,10 @@ class MLIRGenImpl {
auto protoArgs = funcAST.getProto()->getArgs();
// Declare all the function arguments in the symbol table.
-for (const auto &name_value :
+for (const auto nameValue :
llvm::zip(protoArgs, entryBlock.getArguments())) {
- if (failed(declare(std::get<0>(name_value)->getName(),
- std::get<1>(name_value
+ if (failed(declare(std::get<0>(nameValue)->getName(),
+ std::get<1>(nameValue
retur
[llvm-branch-commits] [llvm] 601636d - [LoopNest] Allow empty basic blocks without loops
Author: Whitney Tsang
Date: 2021-01-05T18:44:43Z
New Revision: 601636de98061b53242b598fc2354905c8efbfb8
URL:
https://github.com/llvm/llvm-project/commit/601636de98061b53242b598fc2354905c8efbfb8
DIFF:
https://github.com/llvm/llvm-project/commit/601636de98061b53242b598fc2354905c8efbfb8.diff
LOG: [LoopNest] Allow empty basic blocks without loops
Addressed Florian's post commit review comments:
1. included STLExtras.h
2. changed std::all_of to llvm::all_of
Differential Revision: https://reviews.llvm.org/D93665
Added:
Modified:
llvm/include/llvm/Analysis/LoopNestAnalysis.h
Removed:
diff --git a/llvm/include/llvm/Analysis/LoopNestAnalysis.h
b/llvm/include/llvm/Analysis/LoopNestAnalysis.h
index f65ff493574c4..9c4fb4dbc29b4 100644
--- a/llvm/include/llvm/Analysis/LoopNestAnalysis.h
+++ b/llvm/include/llvm/Analysis/LoopNestAnalysis.h
@@ -14,6 +14,7 @@
#ifndef LLVM_ANALYSIS_LOOPNESTANALYSIS_H
#define LLVM_ANALYSIS_LOOPNESTANALYSIS_H
+#include "llvm/ADT/STLExtras.h"
#include "llvm/Analysis/LoopAnalysisManager.h"
#include "llvm/Analysis/LoopInfo.h"
@@ -130,14 +131,12 @@ class LoopNest {
/// Return true if all loops in the loop nest are in simplify form.
bool areAllLoopsSimplifyForm() const {
-return llvm::all_of(Loops,
-[](const Loop *L) { return L->isLoopSimplifyForm(); });
+return all_of(Loops, [](const Loop *L) { return L->isLoopSimplifyForm();
});
}
/// Return true if all loops in the loop nest are in rotated form.
bool areAllLoopsRotatedForm() const {
-return std::all_of(Loops.begin(), Loops.end(),
- [](const Loop *L) { return L->isRotatedForm(); });
+return all_of(Loops, [](const Loop *L) { return L->isRotatedForm(); });
}
StringRef getName() const { return Loops.front()->getName(); }
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[llvm-branch-commits] [mlir] 86d68e2 - [mlir] Gen removeAttr methods with tablegen
Author: Felipe de Azevedo Piovezan
Date: 2021-01-05T18:48:09Z
New Revision: 86d68e288585964546d6382ecf71dcce10d018b7
URL:
https://github.com/llvm/llvm-project/commit/86d68e288585964546d6382ecf71dcce10d018b7
DIFF:
https://github.com/llvm/llvm-project/commit/86d68e288585964546d6382ecf71dcce10d018b7.diff
LOG: [mlir] Gen removeAttr methods with tablegen
If an operation defines an optional attribute (OptionalAttr or
UnitAttr), transformations may wish to remove these attributes while
maintaining invariants established by the operation. Currently, the only
way to do this is by calling `Operation::removeAttr("attrName")`, which
requires developers to know the exact name of the attribute used by
table-gen. Furthermore, if the attribute name changes, this won't be
detected at compile time. Instead, `removeAttr` would return an empty
attribute and no errors would be raised, unless the caller checks for
the returned value.
This patch adds table gen support for generating `removeAttr`
methods for OptionalAttributes defined by operations.
Implementation choice: to preserve camelCase for the method's name, the
first character of an attribute called `myAttr` is changed to upper case
in order to preserve the coding style, so the final method would be
called `removeMyAttr`.
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D93903
Added:
Modified:
mlir/test/mlir-tblgen/op-attribute.td
mlir/test/mlir-tblgen/op-decl.td
mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
Removed:
diff --git a/mlir/test/mlir-tblgen/op-attribute.td
b/mlir/test/mlir-tblgen/op-attribute.td
index 833f90dd28a2..b4c193c30c51 100644
--- a/mlir/test/mlir-tblgen/op-attribute.td
+++ b/mlir/test/mlir-tblgen/op-attribute.td
@@ -77,6 +77,12 @@ def AOp : NS_Op<"a_op", []> {
// DEF: void AOp::cAttrAttr(some-attr-kind attr) {
// DEF-NEXT: (*this)->setAttr("cAttr", attr);
+// Test remove methods
+// ---
+
+// DEF: Attribute AOp::removeCAttrAttr() {
+// DEF-NEXT: return (*this)->removeAttr("cAttr");
+
// Test build methods
// ---
@@ -265,6 +271,9 @@ def UnitAttrOp : NS_Op<"unit_attr_op", []> {
// DEF: bool UnitAttrOp::attr() {
// DEF: return {{.*}} != nullptr
+// DEF: Attribute UnitAttrOp::removeAttrAttr() {
+// DEF-NEXT: (*this)->removeAttr("attr");
+
// DEF: build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState,
/*optional*/::mlir::UnitAttr attr)
diff --git a/mlir/test/mlir-tblgen/op-decl.td
b/mlir/test/mlir-tblgen/op-decl.td
index 13daca67c475..d4d1a8b012c6 100644
--- a/mlir/test/mlir-tblgen/op-decl.td
+++ b/mlir/test/mlir-tblgen/op-decl.td
@@ -81,6 +81,7 @@ def NS_AOp : NS_Op<"a_op", [IsolatedFromAbove,
IsolatedFromAbove]> {
// CHECK: uint32_t attr1();
// CHECK: ::mlir::FloatAttr attr2Attr()
// CHECK: ::llvm::Optional< ::llvm::APFloat > attr2();
+// CHECK: Attribute removeAttr2Attr();
// CHECK: static void build(::mlir::OpBuilder &odsBuilder,
::mlir::OperationState &odsState, Value val);
// CHECK: static void build(::mlir::OpBuilder &odsBuilder,
::mlir::OperationState &odsState, int integer = 0);
// CHECK: static void build(::mlir::OpBuilder &odsBuilder,
::mlir::OperationState &odsState, ::mlir::Type r, ::mlir::TypeRange s,
::mlir::Value a, ::mlir::ValueRange b, ::mlir::IntegerAttr attr1,
/*optional*/::mlir::FloatAttr attr2, unsigned someRegionsCount)
diff --git a/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
b/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
index 995b4cd05cd5..468fd7848d82 100644
--- a/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
+++ b/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
@@ -328,6 +328,9 @@ class OpEmitter {
// Generates setter for the attributes.
void genAttrSetters();
+ // Generates removers for optional attributes.
+ void genOptionalAttrRemovers();
+
// Generates getters for named operands.
void genNamedOperandGetters();
@@ -600,6 +603,7 @@ OpEmitter::OpEmitter(const Operator &op,
genNamedSuccessorGetters();
genAttrGetters();
genAttrSetters();
+ genOptionalAttrRemovers();
genBuilder();
genParser();
genPrinter();
@@ -777,6 +781,28 @@ void OpEmitter::genAttrSetters() {
}
}
+void OpEmitter::genOptionalAttrRemovers() {
+ // Generate methods for removing optional attributes, instead of having to
+ // use the string interface. Enables better compile time verification.
+ auto emitRemoveAttr = [&](StringRef name) {
+auto upperInitial = name.take_front().upper();
+auto suffix = name.drop_front();
+auto *method = opClass.addMethodAndPrune(
+"Attribute", ("remove" + upperInitial + suffix + "Attr").str());
+if (!method)
+ return;
+auto &body = method->body();
+body << " return (*this)->removeAttr(\"" << name << "\");";
+ };
+
+ for (const auto &namedAttr : op.getAttributes()) {
+const auto &name = namedAttr.name;
+const auto &attr = namedAttr.at
[llvm-branch-commits] [llvm] 210bc3d - [RISCV] Don't parse 'vmsltu.vi v0, v1, 0' as 'vmsleu.vi v0, v1, -1'
Author: Craig Topper
Date: 2021-01-05T10:59:30-08:00
New Revision: 210bc3dc0eb3550fd99158e5747619ad9e91c548
URL:
https://github.com/llvm/llvm-project/commit/210bc3dc0eb3550fd99158e5747619ad9e91c548
DIFF:
https://github.com/llvm/llvm-project/commit/210bc3dc0eb3550fd99158e5747619ad9e91c548.diff
LOG: [RISCV] Don't parse 'vmsltu.vi v0, v1, 0' as 'vmsleu.vi v0, v1, -1'
vmsltu.vi v0, v1, 0 is always false there is no unsigned number
less than 0. vmsleu.vi v0, v1, -1 on the other hand is always true
since -1 will be considered unsigned max and all numbers are <=
unsigned max.
A similar problem exists for vmsgeu.vi v0, v1, 0 which is always true,
but becomes vmsgtu.vi v0, v1, -1 which is always false.
To match the GNU assembler we'll emit vmsne.vv and vmseq.vv with
the same register for these cases instead.
I'm using AsmParserOnly pseudo instructions here because we can't
match an explicit immediate in an InstAlias. And we can't use a
AsmOperand for the zero because the output we want doesn't use an
immediate so there's nowhere to name the AsmOperand we want to use.
To keep the implementations similar I'm also handling signed with
pseudo instructions even though they don't have this issue. This
way we can avoid the special renderMethod that decremented by 1 so
the immediate we see for the pseudo instruction in processInstruction
is 0 and not -1. Another option might have been to have a different
simm5_plus1 operand for the unsigned case or just live with the
immediate being pre-decremented. I felt this way was clearer, but I'm
open to other opinions.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D94035
Added:
Modified:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/test/MC/RISCV/rvv/compare.s
Removed:
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index d31bb8f02dab..975945c9a5e5 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -832,16 +832,6 @@ struct RISCVOperand : public MCParsedAsmOperand {
addExpr(Inst, getImm());
}
- void addSImm5Plus1Operands(MCInst &Inst, unsigned N) const {
-assert(N == 1 && "Invalid number of operands!");
-int64_t Imm = 0;
-RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
-bool IsConstant = evaluateConstantImm(getImm(), Imm, VK);
-assert(IsConstant && "Expect constant value!");
-(void)IsConstant;
-Inst.addOperand(MCOperand::createImm(Imm - 1));
- }
-
void addFenceArgOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
// isFenceArg has validated the operand, meaning this cast is safe
@@ -2488,6 +2478,50 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst,
SMLoc IDLoc,
case RISCV::PseudoVMSGE_VX_M_T:
emitVMSGE(Inst, RISCV::VMSLT_VX, IDLoc, Out);
return false;
+ case RISCV::PseudoVMSGE_VI:
+ case RISCV::PseudoVMSLT_VI: {
+// These instructions are signed and so is immediate so we can subtract one
+// and change the opcode.
+int64_t Imm = Inst.getOperand(2).getImm();
+unsigned Opc = Inst.getOpcode() == RISCV::PseudoVMSGE_VI ? RISCV::VMSGT_VI
+ : RISCV::VMSLE_VI;
+emitToStreamer(Out, MCInstBuilder(Opc)
+.addOperand(Inst.getOperand(0))
+.addOperand(Inst.getOperand(1))
+.addImm(Imm - 1)
+.addOperand(Inst.getOperand(3)));
+return false;
+ }
+ case RISCV::PseudoVMSGEU_VI:
+ case RISCV::PseudoVMSLTU_VI: {
+int64_t Imm = Inst.getOperand(2).getImm();
+// Unsigned comparisons are tricky because the immediate is signed. If the
+// immediate is 0 we can't just subtract one. vmsltu.vi v0, v1, 0 is always
+// false, but vmsle.vi v0, v1, -1 is always true. Instead we use
+// vmsne v0, v1, v1 which is always false.
+if (Imm == 0) {
+ unsigned Opc = Inst.getOpcode() == RISCV::PseudoVMSGEU_VI
+ ? RISCV::VMSEQ_VV
+ : RISCV::VMSNE_VV;
+ emitToStreamer(Out, MCInstBuilder(Opc)
+ .addOperand(Inst.getOperand(0))
+ .addOperand(Inst.getOperand(1))
+ .addOperand(Inst.getOperand(1))
+ .addOperand(Inst.getOperand(3)));
+} else {
+ // Other immediate values can subtract one like signed.
+ unsigned Opc = Inst.getOpcode() == RISCV::PseudoVMSGEU_VI
+ ? RISCV::VMSGTU_VI
+ : RISCV::VMSLEU_VI;
+ emitToStreamer(Out, MCInstBuilder(Opc)
+ .addOperand(Inst.getOperand(0))
+
[llvm-branch-commits] [llvm] 28a326e - [NFC] Rename registerAliasAnalyses -> registerDefaultAliasAnalyses
Author: Arthur Eubanks
Date: 2021-01-05T11:07:58-08:00
New Revision: 28a326eba0a9c367ab6a2d23ca0ae4fb8ab2b536
URL:
https://github.com/llvm/llvm-project/commit/28a326eba0a9c367ab6a2d23ca0ae4fb8ab2b536
DIFF:
https://github.com/llvm/llvm-project/commit/28a326eba0a9c367ab6a2d23ca0ae4fb8ab2b536.diff
LOG: [NFC] Rename registerAliasAnalyses -> registerDefaultAliasAnalyses
To clarify that this only affects the "default" AA.
Reviewed By: ychen
Differential Revision: https://reviews.llvm.org/D93980
Added:
Modified:
llvm/include/llvm/Passes/PassBuilder.h
llvm/include/llvm/Target/TargetMachine.h
llvm/lib/Passes/PassBuilder.cpp
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
Removed:
diff --git a/llvm/include/llvm/Passes/PassBuilder.h
b/llvm/include/llvm/Passes/PassBuilder.h
index fdd4474a8ff0..fd7f6a2ba3b0 100644
--- a/llvm/include/llvm/Passes/PassBuilder.h
+++ b/llvm/include/llvm/Passes/PassBuilder.h
@@ -465,7 +465,7 @@ class PassBuilder {
/// registered.
///
/// This also adds target-specific alias analyses registered via
- /// TargetMachine::registerAliasAnalyses().
+ /// TargetMachine::registerDefaultAliasAnalyses().
AAManager buildDefaultAAPipeline();
/// Parse a textual pass pipeline description into a \c
diff --git a/llvm/include/llvm/Target/TargetMachine.h
b/llvm/include/llvm/Target/TargetMachine.h
index 3908bcadf51f..e1fb53dcd9bb 100644
--- a/llvm/include/llvm/Target/TargetMachine.h
+++ b/llvm/include/llvm/Target/TargetMachine.h
@@ -335,7 +335,7 @@ class TargetMachine {
/// Allow the target to register alias analyses with the AAManager for use
/// with the new pass manager. Only affects the "default" AAManager.
- virtual void registerAliasAnalyses(AAManager &) {}
+ virtual void registerDefaultAliasAnalyses(AAManager &) {}
/// Add passes to the specified pass manager to get the specified file
/// emitted. Typically this will involve several steps of code generation.
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 7cebb5985614..8f6a96dcf4ad 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -1897,7 +1897,7 @@ AAManager PassBuilder::buildDefaultAAPipeline() {
// Add target-specific alias analyses.
if (TM)
-TM->registerAliasAnalyses(AA);
+TM->registerDefaultAliasAnalyses(AA);
return AA;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index be7d86d02fb0..daed6f750c57 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -489,7 +489,7 @@ void
AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
});
}
-void AMDGPUTargetMachine::registerAliasAnalyses(AAManager &AAM) {
+void AMDGPUTargetMachine::registerDefaultAliasAnalyses(AAManager &AAM) {
AAM.registerFunctionAnalysis();
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
index abcc38ff73ba..9799548eccd2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
@@ -58,7 +58,7 @@ class AMDGPUTargetMachine : public LLVMTargetMachine {
void registerPassBuilderCallbacks(PassBuilder &PB,
bool DebugPassManager) override;
- void registerAliasAnalyses(AAManager &) override;
+ void registerDefaultAliasAnalyses(AAManager &) override;
/// Get the integer value of a null pointer in the given address space.
static int64_t getNullPointerValue(unsigned AddrSpace) {
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[llvm-branch-commits] [clang] f111cf9 - [clang][cli] Specify correct integer width for -fbuild-session-timestamp
Author: Jan Svoboda
Date: 2021-01-05T20:10:07+01:00
New Revision: f111cf992df4ec00acfdd026eac12b36c3831999
URL:
https://github.com/llvm/llvm-project/commit/f111cf992df4ec00acfdd026eac12b36c3831999
DIFF:
https://github.com/llvm/llvm-project/commit/f111cf992df4ec00acfdd026eac12b36c3831999.diff
LOG: [clang][cli] Specify correct integer width for -fbuild-session-timestamp
This fixes an issue where large integer values were rejected as invalid.
Reviewed By: arphaman
Differential Revision: https://reviews.llvm.org/D94101
Added:
Modified:
clang/include/clang/Driver/Options.td
clang/unittests/Frontend/CompilerInvocationTest.cpp
Removed:
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 9a851f63a663..c7da888968a8 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -1767,7 +1767,7 @@ def fmodules_search_all : Flag <["-"],
"fmodules-search-all">, Group,
def fbuild_session_timestamp : Joined<["-"], "fbuild-session-timestamp=">,
Group, Flags<[CC1Option]>, MetaVarName<"">,
HelpText<"Time when the current build session started">,
- MarshallingInfoStringInt<"HeaderSearchOpts->BuildSessionTimestamp">;
+ MarshallingInfoStringInt<"HeaderSearchOpts->BuildSessionTimestamp", "0",
"uint64_t">;
def fbuild_session_file : Joined<["-"], "fbuild-session-file=">,
Group, MetaVarName<"">,
HelpText<"Use the last modification time of as the build session
timestamp">;
diff --git a/clang/unittests/Frontend/CompilerInvocationTest.cpp
b/clang/unittests/Frontend/CompilerInvocationTest.cpp
index 51b7ba8c147f..83ae169f9929 100644
--- a/clang/unittests/Frontend/CompilerInvocationTest.cpp
+++ b/clang/unittests/Frontend/CompilerInvocationTest.cpp
@@ -368,6 +368,18 @@ TEST_F(CommandLineTest,
CanGenerateCC1COmmandLineSeparateEnumDefault) {
ASSERT_THAT(GeneratedArgs, Not(Contains(StrEq("pic";
}
+// Wide integer option.
+
+TEST_F(CommandLineTest, WideIntegerHighValue) {
+ const char *Args[] = {"-fbuild-session-timestamp=1609827494445723662"};
+
+ CompilerInvocation::CreateFromArgs(Invocation, Args, *Diags);
+
+ ASSERT_FALSE(Diags->hasErrorOccurred());
+ ASSERT_EQ(Invocation.getHeaderSearchOpts().BuildSessionTimestamp,
+1609827494445723662ull);
+}
+
// Tree of boolean options that can be (directly or transitively) implied by
// their parent:
//
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[llvm-branch-commits] [clang] 497026c - [WebAssembly] Prototype prefetch instructions
Author: Thomas Lively
Date: 2021-01-05T11:32:03-08:00
New Revision: 497026c90233e82ffd3ce2438c5f9567be6dabe7
URL:
https://github.com/llvm/llvm-project/commit/497026c90233e82ffd3ce2438c5f9567be6dabe7
DIFF:
https://github.com/llvm/llvm-project/commit/497026c90233e82ffd3ce2438c5f9567be6dabe7.diff
LOG: [WebAssembly] Prototype prefetch instructions
As proposed in https://github.com/WebAssembly/simd/pull/352 and using the
opcodes used in the V8 prototype:
https://chromium-review.googlesource.com/c/v8/v8/+/2543167. These instructions
are only usable via intrinsics and clang builtins to make them opt-in while they
are being benchmarked.
Differential Revision: https://reviews.llvm.org/D93883
Added:
llvm/test/CodeGen/WebAssembly/simd-prefetch-offset.ll
Modified:
clang/include/clang/Basic/BuiltinsWebAssembly.def
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-wasm.c
llvm/include/llvm/IR/IntrinsicsWebAssembly.td
llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
llvm/test/MC/WebAssembly/simd-encodings.s
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsWebAssembly.def
b/clang/include/clang/Basic/BuiltinsWebAssembly.def
index d6860e0b13be..84482082095e 100644
--- a/clang/include/clang/Basic/BuiltinsWebAssembly.def
+++ b/clang/include/clang/Basic/BuiltinsWebAssembly.def
@@ -220,5 +220,8 @@ TARGET_BUILTIN(__builtin_wasm_store64_lane, "vLLi*V2LLiIi",
"n", "simd128")
TARGET_BUILTIN(__builtin_wasm_eq_i64x2, "V2LLiV2LLiV2LLi", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_prefetch_t, "vv*", "n", "simd128")
+TARGET_BUILTIN(__builtin_wasm_prefetch_nt, "vv*", "n", "simd128")
+
#undef BUILTIN
#undef TARGET_BUILTIN
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 6e98af407a9a..1e0337ca7ac3 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -17171,6 +17171,16 @@ Value
*CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_shuffle);
return Builder.CreateCall(Callee, Ops);
}
+ case WebAssembly::BI__builtin_wasm_prefetch_t: {
+Value *Ptr = EmitScalarExpr(E->getArg(0));
+Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_prefetch_t);
+return Builder.CreateCall(Callee, Ptr);
+ }
+ case WebAssembly::BI__builtin_wasm_prefetch_nt: {
+Value *Ptr = EmitScalarExpr(E->getArg(0));
+Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_prefetch_nt);
+return Builder.CreateCall(Callee, Ptr);
+ }
default:
return nullptr;
}
diff --git a/clang/test/CodeGen/builtins-wasm.c
b/clang/test/CodeGen/builtins-wasm.c
index a07c278c33af..83924b48542e 100644
--- a/clang/test/CodeGen/builtins-wasm.c
+++ b/clang/test/CodeGen/builtins-wasm.c
@@ -1002,3 +1002,13 @@ i8x16 shuffle(i8x16 x, i8x16 y) {
// WEBASSEMBLY-SAME: i32 15
// WEBASSEMBLY-NEXT: ret
}
+
+void prefetch_t(void *p) {
+ return __builtin_wasm_prefetch_t(p);
+ // WEBASSEMBLY: call void @llvm.wasm.prefetch.t(i8* %p)
+}
+
+void prefetch_nt(void *p) {
+ return __builtin_wasm_prefetch_nt(p);
+ // WEBASSEMBLY: call void @llvm.wasm.prefetch.nt(i8* %p)
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsWebAssembly.td
b/llvm/include/llvm/IR/IntrinsicsWebAssembly.td
index d9a6aa78fdcd..e87700ab0fcb 100644
--- a/llvm/include/llvm/IR/IntrinsicsWebAssembly.td
+++ b/llvm/include/llvm/IR/IntrinsicsWebAssembly.td
@@ -311,6 +311,20 @@ def int_wasm_eq :
[llvm_v2i64_ty, llvm_v2i64_ty],
[IntrNoMem, IntrSpeculatable]>;
+// TODO: Remove this after experiments have been run. Use the target-agnostic
+// int_prefetch if this becomes specified at some point.
+def int_wasm_prefetch_t :
+ Intrinsic<[], [llvm_ptr_ty],
+[IntrInaccessibleMemOrArgMemOnly, IntrWillReturn,
+ ReadOnly>, NoCapture>],
+"", [SDNPMemOperand]>;
+
+def int_wasm_prefetch_nt :
+ Intrinsic<[], [llvm_ptr_ty],
+[IntrInaccessibleMemOrArgMemOnly, IntrWillReturn,
+ ReadOnly>, NoCapture>],
+"", [SDNPMemOperand]>;
+
//===--===//
// Thread-local storage intrinsics
//===--===//
diff --git a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
index 18d7b642e044..cd07a142147c 100644
--- a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
+++ b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
@@ -427,7 +427,8 @@ class WebAssemblyAsmParser final : public MCTargetAsmParser
{
bool c
[llvm-branch-commits] [clang] 16f3401 - [Coverage] Fix test failures from commit rG9f2967bcfe2f
Author: Alan Phipps
Date: 2021-01-05T13:35:52-06:00
New Revision: 16f3401eae4310c95163269c41d9b45261f0c7c3
URL:
https://github.com/llvm/llvm-project/commit/16f3401eae4310c95163269c41d9b45261f0c7c3
DIFF:
https://github.com/llvm/llvm-project/commit/16f3401eae4310c95163269c41d9b45261f0c7c3.diff
LOG: [Coverage] Fix test failures from commit rG9f2967bcfe2f
Fix test failures with Branch Coverage tests from commit rG9f2967bcfe2f
that failed build on builder clang-x64-windows-msvc while building llvm:
http://lab.llvm.org:8011/#builders/123/builds/2155
Added:
Modified:
clang/test/CoverageMapping/branch-constfolded.cpp
clang/test/CoverageMapping/branch-macros.cpp
clang/test/CoverageMapping/branch-mincounters.cpp
clang/test/CoverageMapping/branch-templates.cpp
clang/test/Profile/branch-logical-mixed.cpp
clang/test/Profile/branch-profdup.cpp
Removed:
diff --git a/clang/test/CoverageMapping/branch-constfolded.cpp
b/clang/test/CoverageMapping/branch-constfolded.cpp
index bb7c675e3ef7..5173286addbb 100644
--- a/clang/test/CoverageMapping/branch-constfolded.cpp
+++ b/clang/test/CoverageMapping/branch-constfolded.cpp
@@ -1,6 +1,6 @@
// Test that branch regions are not generated for constant-folded conditions.
-// RUN: %clang_cc1 -fprofile-instrument=clang -fcoverage-mapping
-dump-coverage-mapping -emit-llvm-only -main-file-name branch-constfolded.cpp
%s | FileCheck %s
+// RUN: %clang_cc1 -triple %itanium_abi_triple -std=c++11
-fprofile-instrument=clang -fcoverage-mapping -dump-coverage-mapping
-emit-llvm-only -main-file-name branch-constfolded.cpp %s | FileCheck %s
// CHECK-LABEL: _Z6fand_0b:
bool fand_0(bool a) {
diff --git a/clang/test/CoverageMapping/branch-macros.cpp
b/clang/test/CoverageMapping/branch-macros.cpp
index d5bc47fbef76..0f9ae791a355 100644
--- a/clang/test/CoverageMapping/branch-macros.cpp
+++ b/clang/test/CoverageMapping/branch-macros.cpp
@@ -1,7 +1,7 @@
// Test that branch regions are generated for conditions in nested macro
// expansions.
-// RUN: %clang_cc1 -fprofile-instrument=clang -fcoverage-mapping
-dump-coverage-mapping -emit-llvm-only -main-file-name branch-macros.cpp %s |
FileCheck %s
+// RUN: %clang_cc1 -triple %itanium_abi_triple -std=c++11
-fprofile-instrument=clang -fcoverage-mapping -dump-coverage-mapping
-emit-llvm-only -main-file-name branch-macros.cpp %s | FileCheck %s
#define COND1 (a == b)
#define COND2 (a != b)
diff --git a/clang/test/CoverageMapping/branch-mincounters.cpp
b/clang/test/CoverageMapping/branch-mincounters.cpp
index 68e691684970..6d4341cbeafd 100644
--- a/clang/test/CoverageMapping/branch-mincounters.cpp
+++ b/clang/test/CoverageMapping/branch-mincounters.cpp
@@ -1,7 +1,7 @@
// Test to ensure right number of counters are allocated and used for nested
// logical operators on branch conditions for branch coverage.
-// RUN: %clang_cc1 -fprofile-instrument=clang -fcoverage-mapping
-dump-coverage-mapping -emit-llvm-only -main-file-name branch-logical-mixed.cpp
%s | FileCheck %s
+// RUN: %clang_cc1 -triple %itanium_abi_triple -std=c++11
-fprofile-instrument=clang -fcoverage-mapping -dump-coverage-mapping
-emit-llvm-only -main-file-name branch-logical-mixed.cpp %s | FileCheck %s
// CHECK-LABEL: _Z5func1ii:
diff --git a/clang/test/CoverageMapping/branch-templates.cpp
b/clang/test/CoverageMapping/branch-templates.cpp
index 9e312df9b2de..1fd01218c903 100644
--- a/clang/test/CoverageMapping/branch-templates.cpp
+++ b/clang/test/CoverageMapping/branch-templates.cpp
@@ -1,7 +1,7 @@
// Test that branch regions are generated for conditions in function template
// instantiations.
-// RUN: %clang_cc1 -fprofile-instrument=clang -fcoverage-mapping
-dump-coverage-mapping -emit-llvm-only -main-file-name branch-templates.cpp %s
| FileCheck %s
+// RUN: %clang_cc1 -triple %itanium_abi_triple -std=c++11
-fprofile-instrument=clang -fcoverage-mapping -dump-coverage-mapping
-emit-llvm-only -main-file-name branch-templates.cpp %s | FileCheck %s
template
void unused(T x) {
diff --git a/clang/test/Profile/branch-logical-mixed.cpp
b/clang/test/Profile/branch-logical-mixed.cpp
index e6f546d3ac4b..cbfcf061f152 100644
--- a/clang/test/Profile/branch-logical-mixed.cpp
+++ b/clang/test/Profile/branch-logical-mixed.cpp
@@ -1,7 +1,7 @@
// Test to ensure instrumentation of logical operator RHS True/False counters
// are being instrumented for branch coverage
-// RUN: %clang_cc1 -main-file-name branch-logical-mixed.cpp %s -o - -emit-llvm
-fprofile-instrument=clang | FileCheck -allow-deprecated-dag-overlap %s
+// RUN: %clang_cc1 -triple %itanium_abi_triple -std=c++11 -main-file-name
branch-logical-mixed.cpp %s -o - -emit-llvm -fprofile-instrument=clang |
FileCheck -allow-deprecated-dag-overlap %s
// CHECK: @[[FUNC:__profc__Z4funcv]] = private global [61 x i64]
zeroinitializer
diff --git a/clang/test/Profil
[llvm-branch-commits] [llvm] 7b5a0e2 - [RISCV] Move shift ComplexPatterns and custom isel to PatFrags with predicates
Author: Craig Topper
Date: 2021-01-05T11:37:48-08:00
New Revision: 7b5a0e2f88eedc1123f4027552940bdf1ab6c03e
URL:
https://github.com/llvm/llvm-project/commit/7b5a0e2f88eedc1123f4027552940bdf1ab6c03e
DIFF:
https://github.com/llvm/llvm-project/commit/7b5a0e2f88eedc1123f4027552940bdf1ab6c03e.diff
LOG: [RISCV] Move shift ComplexPatterns and custom isel to PatFrags with
predicates
ComplexPatterns are kind of weird, they don't call any of the predicates on
their operands. And their "complexity" used for tablegen ordering purposes in
the matcher table is hand specified.
This started as an attempt to just use sext_inreg + SLOIPat to implement SLOIW
just to have one less Select function. The matching for the or+shl is the same
as long as you know the immediate is less than 32 for SLOIW. But that didn't
work out because using uimm5 with SLOIPat didn't do anything if it was a
ComplexPattern.
I realized I could just use a PatFrag with the opcodes I wanted to match and an
immediate predicate would then evaluate correctly. This also computes the
complexity just like any other pattern does. Then I just needed to check the
constraints on the immediates in the predicate. Conveniently the predicate is
evaluated after the fragment has been matched. So the structure has already
been checked, we just need to find the constants.
I'll note that this is unusual, I didn't find any other targets looking through
operands in PatFrag predicate. There is a PredicateCodeUsesOperands feature
that can be used to collect the operands into an array that is used by
AMDGPU/VOP3Instructions.td. I believe that feature exists to handle commuted
matching, but since the nodes here use constants, they aren't ever commuted
Differential Revision: https://reviews.llvm.org/D91901
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 2a815863a81c..e332a3c90b42 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -49,17 +49,6 @@ static SDNode *selectImm(SelectionDAG *CurDAG, const SDLoc
&DL, int64_t Imm,
return Result;
}
-// Returns true if the Node is an ISD::AND with a constant argument. If so,
-// set Mask to that constant value.
-static bool isConstantMask(SDNode *Node, uint64_t &Mask) {
- if (Node->getOpcode() == ISD::AND &&
- Node->getOperand(1).getOpcode() == ISD::Constant) {
-Mask = cast(Node->getOperand(1))->getZExtValue();
-return true;
- }
- return false;
-}
-
void RISCVDAGToDAGISel::Select(SDNode *Node) {
// If we have a custom node, we have already selected.
if (Node->isMachineOpcode()) {
@@ -121,27 +110,6 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ADDI, DL, VT, TFI, Imm));
return;
}
- case ISD::SRL: {
-if (!Subtarget->is64Bit())
- break;
-SDNode *Op0 = Node->getOperand(0).getNode();
-uint64_t Mask;
-// Match (srl (and val, mask), imm) where the result would be a
-// zero-extended 32-bit integer. i.e. the mask is 0x or the result
-// is equivalent to this (SimplifyDemandedBits may have removed lower bits
-// from the mask that aren't necessary due to the right-shifting).
-if (isa(Node->getOperand(1)) && isConstantMask(Op0, Mask))
{
- uint64_t ShAmt = Node->getConstantOperandVal(1);
-
- if ((Mask | maskTrailingOnes(ShAmt)) == 0x) {
-SDValue ShAmtVal = CurDAG->getTargetConstant(ShAmt, DL, XLenVT);
-CurDAG->SelectNodeTo(Node, RISCV::SRLIW, XLenVT, Op0->getOperand(0),
- ShAmtVal);
-return;
- }
-}
-break;
- }
case ISD::INTRINSIC_W_CHAIN: {
unsigned IntNo = cast(Node->getOperand(1))->getZExtValue();
switch (IntNo) {
@@ -238,198 +206,147 @@ bool RISCVDAGToDAGISel::SelectAddrFI(SDValue Addr,
SDValue &Base) {
return false;
}
-// Check that it is a SLOI (Shift Left Ones Immediate). We first check that
-// it is the right node tree:
+// Match (srl (and val, mask), imm) where the result would be a
+// zero-extended 32-bit integer. i.e. the mask is 0x or the result
+// is equivalent to this (SimplifyDemandedBits may have removed lower bits
+// from the mask that aren't necessary due to the right-shifting).
+bool RISCVDAGToDAGISel::MatchSRLIW(SDNode *N) const {
+ assert(N->getOpcode() == ISD::SRL);
+ assert(N->getOperand(0).getOpcode() == ISD::AND);
+ assert(isa(N->getOperand(1)));
+ assert(isa(N->getOperand(0).getOperand(1)));
+
+ // The IsRV64 predicate is checked after PatFrag predicates so we can get
+ // here even on RV32.
+ if (!Subtarget->is64Bit())
+
[llvm-branch-commits] [clang] f88a797 - [LoopDeletion] Allows deletion of possibly infinite side-effect free loops
Author: Atmn Patel
Date: 2021-01-05T09:56:16-05:00
New Revision: f88a7975210fc995197af4b393e3bb5030e97a5c
URL:
https://github.com/llvm/llvm-project/commit/f88a7975210fc995197af4b393e3bb5030e97a5c
DIFF:
https://github.com/llvm/llvm-project/commit/f88a7975210fc995197af4b393e3bb5030e97a5c.diff
LOG: [LoopDeletion] Allows deletion of possibly infinite side-effect free loops
>From C11 and C++11 onwards, a forward-progress requirement has been
introduced for both languages. In the case of C, loops with non-constant
conditionals that do not have any observable side-effects (as defined by
6.8.5p6) can be assumed by the implementation to terminate, and in the
case of C++, this assumption extends to all functions. The clang
frontend will emit the `mustprogress` function attribute for C++
functions (D86233, D85393, D86841) and emit the loop metadata
`llvm.loop.mustprogress` for every loop in C11 or later that has a
non-constant conditional.
This patch modifies LoopDeletion so that only loops with
the `llvm.loop.mustprogress` metadata or loops contained in functions
that are required to make progress (`mustprogress` or `willreturn`) are
checked for observable side-effects. If these loops do not have an
observable side-effect, then we delete them.
Loops without observable side-effects that do not satisfy the above
conditions will not be deleted.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D86844
Added:
llvm/test/Transforms/LoopDeletion/mustprogress.ll
Modified:
clang/test/Misc/loop-opt-setup.c
llvm/include/llvm/Transforms/Utils/LoopUtils.h
llvm/lib/Transforms/Scalar/LoopDeletion.cpp
llvm/lib/Transforms/Utils/LoopUtils.cpp
llvm/test/Transforms/LoopDeletion/no-exit-blocks.ll
Removed:
diff --git a/clang/test/Misc/loop-opt-setup.c
b/clang/test/Misc/loop-opt-setup.c
index 9cea02a8bcb3..e9a9c1e8ae2d 100644
--- a/clang/test/Misc/loop-opt-setup.c
+++ b/clang/test/Misc/loop-opt-setup.c
@@ -1,5 +1,6 @@
-// This relies on %clang_cc1, %clang does not emit the block names in Release
mode.
+// This tests loop unrolling and loop deletion (enabled under -O1)
// RUN: %clang_cc1 -O1 -fno-unroll-loops -S -o - %s -emit-llvm | FileCheck %s
+// RUN: %clang_cc1 -std=c99 -O1 -fno-unroll-loops -S -o - %s -emit-llvm |
FileCheck %s --check-prefix C99
extern int a[16];
int b = 0;
@@ -25,7 +26,12 @@ void Helper() {
}
// Check br i1 to make sure the loop is gone, there will still be a label
branch for the infinite loop.
+// In C99, there was no forward progress requirement, so we expect the
infinite loop to still exist,
+// but for C11 and onwards, the infinite loop can be deleted.
// CHECK-LABEL: Helper
-// CHECK: br label
-// CHECK-NOT: br i1
-// CHECK: br label
+// C99: br label
+// C99-NOT: br i1
+// C99: br label
+// CHECK: entry:
+// CHECK-NOT: br i1
+// CHECK-NEXT: ret void
diff --git a/llvm/include/llvm/Transforms/Utils/LoopUtils.h
b/llvm/include/llvm/Transforms/Utils/LoopUtils.h
index d606fa954f95..80c6b09d9cf0 100644
--- a/llvm/include/llvm/Transforms/Utils/LoopUtils.h
+++ b/llvm/include/llvm/Transforms/Utils/LoopUtils.h
@@ -255,6 +255,9 @@ bool hasDisableAllTransformsHint(const Loop *L);
/// Look for the loop attribute that disables the LICM transformation
heuristics.
bool hasDisableLICMTransformsHint(const Loop *L);
+/// Look for the loop attribute that requires progress within the loop.
+bool hasMustProgress(const Loop *L);
+
/// The mode sets how eager a transformation should be applied.
enum TransformationMode {
/// The pass can use heuristics to determine whether a transformation should
diff --git a/llvm/lib/Transforms/Scalar/LoopDeletion.cpp
b/llvm/lib/Transforms/Scalar/LoopDeletion.cpp
index 065db647561e..814cfc7ac6a9 100644
--- a/llvm/lib/Transforms/Scalar/LoopDeletion.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopDeletion.cpp
@@ -128,10 +128,11 @@ static bool isLoopNeverExecuted(Loop *L) {
/// Remove a loop if it is dead.
///
-/// A loop is considered dead if it does not impact the observable behavior of
-/// the program other than finite running time. This never removes a loop that
-/// might be infinite (unless it is never executed), as doing so could change
-/// the halting/non-halting nature of a program.
+/// A loop is considered dead either if it does not impact the observable
+/// behavior of the program other than finite running time, or if it is
+/// required to make progress by an attribute such as 'mustprogress' or
+/// 'llvm.loop.mustprogress' and does not make any. This may remove
+/// infinite loops that have been required to make progress.
///
/// This entire process relies pretty heavily on LoopSimplify form and LCSSA in
/// order to make various safety checks work.
@@ -207,11 +208,13 @@ static LoopDeletionResult deleteLoopIfDead(Loop *L,
DominatorTree &DT,
: LoopDeletionResult::Unmodifie
[llvm-branch-commits] [llvm] 314ccc0 - [LoopNest] Remove unused include.
Author: Whitney Tsang Date: 2021-01-05T20:05:31Z New Revision: 314ccc00139a7f382db7b598dcd94883b366b7de URL: https://github.com/llvm/llvm-project/commit/314ccc00139a7f382db7b598dcd94883b366b7de DIFF: https://github.com/llvm/llvm-project/commit/314ccc00139a7f382db7b598dcd94883b366b7de.diff LOG: [LoopNest] Remove unused include. Differential Revision: https://reviews.llvm.org/D93665 Added: Modified: llvm/lib/Analysis/LoopNestAnalysis.cpp Removed: diff --git a/llvm/lib/Analysis/LoopNestAnalysis.cpp b/llvm/lib/Analysis/LoopNestAnalysis.cpp index 70b9ccaa87c1..f3aa0d76742f 100644 --- a/llvm/lib/Analysis/LoopNestAnalysis.cpp +++ b/llvm/lib/Analysis/LoopNestAnalysis.cpp @@ -16,7 +16,6 @@ #include "llvm/ADT/Statistic.h" #include "llvm/Analysis/PostDominators.h" #include "llvm/Analysis/ValueTracking.h" -#include "llvm/Transforms/Utils/BasicBlockUtils.h" using namespace llvm; ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] ee11bf3 - [Hexagon] Silence unused function warning with gcc10, NFC
Author: Krzysztof Parzyszek
Date: 2021-01-05T14:11:45-06:00
New Revision: ee11bf316f6be9dba29026b332fcde1dc3be4f9d
URL:
https://github.com/llvm/llvm-project/commit/ee11bf316f6be9dba29026b332fcde1dc3be4f9d
DIFF:
https://github.com/llvm/llvm-project/commit/ee11bf316f6be9dba29026b332fcde1dc3be4f9d.diff
LOG: [Hexagon] Silence unused function warning with gcc10, NFC
Added:
Modified:
llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
Removed:
diff --git a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
index 056a5a83a0a6..05269d37f812 100644
--- a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp
@@ -118,7 +118,7 @@ class HexagonVectorCombine {
private:
bool isByteVecTy(Type *Ty) const;
- bool isSectorTy(Type *Ty) const;
+ bool isSectorTy(Type *Ty) const LLVM_ATTRIBUTE_UNUSED;
Value *getElementRange(IRBuilder<> &Builder, Value *Lo, Value *Hi, int Start,
int Length) const;
};
___
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[llvm-branch-commits] [llvm] d4a999b - [SLP] reduce code duplication; NFC
Author: Sanjay Patel
Date: 2021-01-05T15:12:40-05:00
New Revision: d4a999b453a4d3cfeee02f00f4900327fc7fcede
URL:
https://github.com/llvm/llvm-project/commit/d4a999b453a4d3cfeee02f00f4900327fc7fcede
DIFF:
https://github.com/llvm/llvm-project/commit/d4a999b453a4d3cfeee02f00f4900327fc7fcede.diff
LOG: [SLP] reduce code duplication; NFC
Added:
Modified:
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Removed:
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 8965a44ffd2b..390b71e7a46b 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -7137,8 +7137,9 @@ class HorizontalReduction {
Type *ScalarTy = FirstReducedVal->getType();
auto *VecTy = FixedVectorType::get(ScalarTy, ReduxWidth);
+RecurKind Kind = RdxTreeInst.getKind();
int SplittingRdxCost;
-switch (RdxTreeInst.getKind()) {
+switch (Kind) {
case RecurKind::Add:
case RecurKind::Mul:
case RecurKind::Or:
@@ -7155,7 +7156,6 @@ class HorizontalReduction {
case RecurKind::UMax:
case RecurKind::UMin: {
auto *VecCondTy = cast(CmpInst::makeCmpResultType(VecTy));
- RecurKind Kind = RdxTreeInst.getKind();
bool IsUnsigned = Kind == RecurKind::UMax || Kind == RecurKind::UMin;
SplittingRdxCost =
TTI->getMinMaxReductionCost(VecTy, VecCondTy,
@@ -7167,7 +7167,7 @@ class HorizontalReduction {
}
int ScalarReduxCost = 0;
-switch (RdxTreeInst.getKind()) {
+switch (Kind) {
case RecurKind::Add:
case RecurKind::Mul:
case RecurKind::Or:
___
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[llvm-branch-commits] [llvm] 5a1d31a - [SLP] use reduction kind's opcode for cost model queries; NFC
Author: Sanjay Patel
Date: 2021-01-05T15:12:40-05:00
New Revision: 5a1d31a28490e85de440b55e2e257b61d32e85b9
URL:
https://github.com/llvm/llvm-project/commit/5a1d31a28490e85de440b55e2e257b61d32e85b9
DIFF:
https://github.com/llvm/llvm-project/commit/5a1d31a28490e85de440b55e2e257b61d32e85b9.diff
LOG: [SLP] use reduction kind's opcode for cost model queries; NFC
This should be no-functional-change because the reduction kind
opcodes are 1-for-1 mappings to the instructions we are matching
as reductions. But we want to remove the need for the
`OperationData` opcode field because that does not work when
we start matching intrinsics (eg, maxnum) as reduction candidates.
Added:
Modified:
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Removed:
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 390b71e7a46b..48f2a2d2886f 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -7138,6 +7138,7 @@ class HorizontalReduction {
auto *VecTy = FixedVectorType::get(ScalarTy, ReduxWidth);
RecurKind Kind = RdxTreeInst.getKind();
+unsigned RdxOpcode = RecurrenceDescriptor::getOpcode(Kind);
int SplittingRdxCost;
switch (Kind) {
case RecurKind::Add:
@@ -7147,9 +7148,8 @@ class HorizontalReduction {
case RecurKind::Xor:
case RecurKind::FAdd:
case RecurKind::FMul:
- SplittingRdxCost =
- TTI->getArithmeticReductionCost(RdxTreeInst.getOpcode(), VecTy,
- /*IsPairwiseForm=*/false);
+ SplittingRdxCost = TTI->getArithmeticReductionCost(
+ RdxOpcode, VecTy, /*IsPairwiseForm=*/false);
break;
case RecurKind::SMax:
case RecurKind::SMin:
@@ -7175,15 +7175,14 @@ class HorizontalReduction {
case RecurKind::Xor:
case RecurKind::FAdd:
case RecurKind::FMul:
- ScalarReduxCost =
- TTI->getArithmeticInstrCost(RdxTreeInst.getOpcode(), ScalarTy);
+ ScalarReduxCost = TTI->getArithmeticInstrCost(RdxOpcode, ScalarTy);
break;
case RecurKind::SMax:
case RecurKind::SMin:
case RecurKind::UMax:
case RecurKind::UMin:
ScalarReduxCost =
- TTI->getCmpSelInstrCost(RdxTreeInst.getOpcode(), ScalarTy) +
+ TTI->getCmpSelInstrCost(RdxOpcode, ScalarTy) +
TTI->getCmpSelInstrCost(Instruction::Select, ScalarTy,
CmpInst::makeCmpResultType(ScalarTy));
break;
___
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[llvm-branch-commits] [llvm] 4ef91f5 - [DAGCombiner] Don't speculatively create an all ones constant in visitREM that might not be used.
Author: Craig Topper
Date: 2021-01-05T12:45:57-08:00
New Revision: 4ef91f5871a3c38bb2324f89b47a2a845e8a33fd
URL:
https://github.com/llvm/llvm-project/commit/4ef91f5871a3c38bb2324f89b47a2a845e8a33fd
DIFF:
https://github.com/llvm/llvm-project/commit/4ef91f5871a3c38bb2324f89b47a2a845e8a33fd.diff
LOG: [DAGCombiner] Don't speculatively create an all ones constant in visitREM
that might not be used.
This looks to have been done to save some duplicated code under
two different if statements, but it ends up being harmful to D94073.
This speculative constant can be called on a scalable vector type
with i64 element size when i64 scalars aren't legal. The code tries
and fails to find a vector type with i32 elements that it can use.
So only create the node when we know it will be used.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Removed:
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 6b1bd721a993..09c8f7219390 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4274,9 +4274,9 @@ SDValue DAGCombiner::visitREM(SDNode *N) {
if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
return DAG.getNode(ISD::UREM, DL, VT, N0, N1);
} else {
-SDValue NegOne = DAG.getAllOnesConstant(DL, VT);
if (DAG.isKnownToBeAPowerOfTwo(N1)) {
// fold (urem x, pow2) -> (and x, pow2-1)
+ SDValue NegOne = DAG.getAllOnesConstant(DL, VT);
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne);
AddToWorklist(Add.getNode());
return DAG.getNode(ISD::AND, DL, VT, N0, Add);
@@ -4284,6 +4284,7 @@ SDValue DAGCombiner::visitREM(SDNode *N) {
if (N1.getOpcode() == ISD::SHL &&
DAG.isKnownToBeAPowerOfTwo(N1.getOperand(0))) {
// fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
+ SDValue NegOne = DAG.getAllOnesConstant(DL, VT);
SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne);
AddToWorklist(Add.getNode());
return DAG.getNode(ISD::AND, DL, VT, N0, Add);
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[llvm-branch-commits] [llvm] 65cd3cb - [Inliner] Compute the full cost for the cost benefit analsysis
Author: Kazu Hirata
Date: 2021-01-05T12:48:49-08:00
New Revision: 65cd3cbb3fc9ee440234a5adbfea6cbe4834f3d3
URL:
https://github.com/llvm/llvm-project/commit/65cd3cbb3fc9ee440234a5adbfea6cbe4834f3d3
DIFF:
https://github.com/llvm/llvm-project/commit/65cd3cbb3fc9ee440234a5adbfea6cbe4834f3d3.diff
LOG: [Inliner] Compute the full cost for the cost benefit analsysis
This patch teaches the inliner to compute the full cost for a call
site where the newly introduced cost benefit analysis is enabled.
Note that the cost benefit analysis requires the full cost to be
computed. However, without this patch or the -inline-cost-full
option, the early termination logic would kick in when the cost
exceeds the threshold, so we don't get to perform the cost benefit
analysis. For this reason, we would need to specify four clang
options:
-mllvm -inline-cost-full
-mllvm -inline-enable-cost-benefit-analysis
This patch eliminates the need to specify -inline-cost-full.
Differential Revision: https://reviews.llvm.org/D93658
Added:
Modified:
llvm/lib/Analysis/InlineCost.cpp
Removed:
diff --git a/llvm/lib/Analysis/InlineCost.cpp
b/llvm/lib/Analysis/InlineCost.cpp
index bf8d9c98aa0e..ff589b86bb50 100644
--- a/llvm/lib/Analysis/InlineCost.cpp
+++ b/llvm/lib/Analysis/InlineCost.cpp
@@ -901,7 +901,8 @@ class InlineCostCallAnalyzer final : public CallAnalyzer {
bool IgnoreThreshold = false)
: CallAnalyzer(Callee, Call, TTI, GetAssumptionCache, GetBFI, PSI, ORE),
ComputeFullInlineCost(OptComputeFullInlineCost ||
- Params.ComputeFullInlineCost || ORE),
+ Params.ComputeFullInlineCost || ORE ||
+ isCostBenefitAnalysisEnabled()),
Params(Params), Threshold(Params.DefaultThreshold),
BoostIndirectCalls(BoostIndirect), IgnoreThreshold(IgnoreThreshold),
CostBenefitAnalysisEnabled(isCostBenefitAnalysisEnabled()),
___
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[llvm-branch-commits] [clang] 2168942 - [Coverage] Fix Profile test failures from commit rG9f2967bcfe2f
Author: Alan Phipps
Date: 2021-01-05T14:53:07-06:00
New Revision: 216894211713bbb1e8beb249f2b008c11a9d8c2c
URL:
https://github.com/llvm/llvm-project/commit/216894211713bbb1e8beb249f2b008c11a9d8c2c
DIFF:
https://github.com/llvm/llvm-project/commit/216894211713bbb1e8beb249f2b008c11a9d8c2c.diff
LOG: [Coverage] Fix Profile test failures from commit rG9f2967bcfe2f
Fix test failures with Branch Coverage tests from commit rG9f2967bcfe2f
that failed build on builder clang-x64-windows-msvc while building llvm:
http://lab.llvm.org:8011/#/builders/123/builds/2162
Added:
Modified:
clang/test/Profile/branch-logical-mixed.cpp
Removed:
diff --git a/clang/test/Profile/branch-logical-mixed.cpp
b/clang/test/Profile/branch-logical-mixed.cpp
index cbfcf061f152..04b51d81d13b 100644
--- a/clang/test/Profile/branch-logical-mixed.cpp
+++ b/clang/test/Profile/branch-logical-mixed.cpp
@@ -4,7 +4,7 @@
// RUN: %clang_cc1 -triple %itanium_abi_triple -std=c++11 -main-file-name
branch-logical-mixed.cpp %s -o - -emit-llvm -fprofile-instrument=clang |
FileCheck -allow-deprecated-dag-overlap %s
-// CHECK: @[[FUNC:__profc__Z4funcv]] = private global [61 x i64]
zeroinitializer
+// CHECK: @[[FUNC:__profc__Z4funcv]] = {{.*}} global [61 x i64] zeroinitializer
// CHECK-LABEL: @_Z4funcv()
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[llvm-branch-commits] [compiler-rt] 1f8031c - [android] Fix some tests for AOSP-master devices.
Author: Mitch Phillips
Date: 2021-01-05T12:54:09-08:00
New Revision: 1f8031cd74887025a5de1e7129718186369db769
URL:
https://github.com/llvm/llvm-project/commit/1f8031cd74887025a5de1e7129718186369db769
DIFF:
https://github.com/llvm/llvm-project/commit/1f8031cd74887025a5de1e7129718186369db769.diff
LOG: [android] Fix some tests for AOSP-master devices.
Some tests are broken at API level 30 on AOSP-master devices. When we
change the buildbuit to API level 30, the following tests get enabled.
They're currently broken due to various issues, and so fix up those
issues.
Reviewed By: oontvoo, eugenis
Differential Revision: https://reviews.llvm.org/D94100
Added:
Modified:
compiler-rt/test/cfi/cross-dso/target_out_of_bounds.cpp
compiler-rt/test/lsan/TestCases/Linux/use_tls_dynamic.cpp
compiler-rt/test/lsan/TestCases/stale_stack_leak.cpp
Removed:
diff --git a/compiler-rt/test/cfi/cross-dso/target_out_of_bounds.cpp
b/compiler-rt/test/cfi/cross-dso/target_out_of_bounds.cpp
index 6353f030a6ac..80b736e2c91c 100644
--- a/compiler-rt/test/cfi/cross-dso/target_out_of_bounds.cpp
+++ b/compiler-rt/test/cfi/cross-dso/target_out_of_bounds.cpp
@@ -10,6 +10,12 @@
// REQUIRES: cxxabi
+// These checks are unsupported on newer versions of Android due to the
+// following patch that makes it harder to defeat ASLR by not mapping unused
+// shadow regions:
+// https://android-review.googlesource.com/c/platform/bionic/+/1333960
+// UNSUPPORTED: android
+
#include
#include
#include
diff --git a/compiler-rt/test/lsan/TestCases/Linux/use_tls_dynamic.cpp
b/compiler-rt/test/lsan/TestCases/Linux/use_tls_dynamic.cpp
index be1cdc943c6a..63a7c87f66da 100644
--- a/compiler-rt/test/lsan/TestCases/Linux/use_tls_dynamic.cpp
+++ b/compiler-rt/test/lsan/TestCases/Linux/use_tls_dynamic.cpp
@@ -23,6 +23,11 @@
int main(int argc, char *argv[]) {
std::string path = std::string(argv[0]) + "-so.so";
+ // Clear any previous errors. On Android, the dynamic loader can have some
+ // left over dlerror() messages due to a missing symbol resolution for a
+ // deprecated malloc function.
+ dlerror();
+
void *handle = dlopen(path.c_str(), RTLD_LAZY);
assert(handle != 0);
typedef void **(* store_t)(void *p);
@@ -31,10 +36,10 @@ int main(int argc, char *argv[]) {
// Sometimes dlerror() occurs when we broke the interceptors.
// Add the message here to make the error more obvious.
const char *dlerror_msg = dlerror();
- assert(dlerror_msg == nullptr);
if (dlerror_msg != nullptr) {
fprintf(stderr, "DLERROR: %s\n", dlerror_msg);
fflush(stderr);
+abort();
}
void *p = malloc(1337);
// If we don't know about dynamic TLS, we will return a false leak above.
diff --git a/compiler-rt/test/lsan/TestCases/stale_stack_leak.cpp
b/compiler-rt/test/lsan/TestCases/stale_stack_leak.cpp
index 72aee5f56fd9..fa644c6cb451 100644
--- a/compiler-rt/test/lsan/TestCases/stale_stack_leak.cpp
+++ b/compiler-rt/test/lsan/TestCases/stale_stack_leak.cpp
@@ -1,6 +1,15 @@
// Test that out-of-scope local variables are ignored by LSan.
// RUN: LSAN_BASE="report_objects=1:use_registers=0:use_stacks=1"
-// RUN: %clangxx_lsan %s -o %t
+
+// LSan-in-ASan fails at -O0 on aarch64, because the stack use-after-return
+// instrumentation stashes the argument to `PutPointerOnStaleStack` on the
stack
+// in order to conditionally call __asan_stack_malloc. This subverts our
+// expectations for this test, where we assume the pointer is never stashed
+// except at the bottom of the dead frame. Building at -O1 or greater solves
+// this problem, because the compiler is smart enough to stash the argument in
a
+// callee-saved register for rematerialization instead.
+// RUN: %clangxx_lsan -O1 %s -o %t
+
// RUN: %env_lsan_opts=$LSAN_BASE not %run %t 2>&1 | FileCheck %s
// RUN: %env_lsan_opts=$LSAN_BASE":exitcode=0" %run %t 2>&1 | FileCheck
--check-prefix=CHECK-sanity %s
//
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[llvm-branch-commits] [llvm] a954346 - [NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel
Author: Mircea Trofin Date: 2021-01-05T12:57:17-08:00 New Revision: a9543469d54e3dfa1c6b4e9d498b55bca947d51e URL: https://github.com/llvm/llvm-project/commit/a9543469d54e3dfa1c6b4e9d498b55bca947d51e DIFF: https://github.com/llvm/llvm-project/commit/a9543469d54e3dfa1c6b4e9d498b55bca947d51e.diff LOG: [NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel Differential Revision: https://reviews.llvm.org/D94099 Added: Modified: llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fixed-function-abi-vgpr-args.ll llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-non-entry-func.ll llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.gws.sema.br.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.gws.sema.release.all.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.gws.sema.v.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot8.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll Removed: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll index de316692c70a..2a2037247375 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/dynamic-alloca-uniform.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10 %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX9 %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s @gv = external addrspace(4) constant i32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll index 7823cba3b250..eaec12a8d3e7 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s -; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI -check-prefix=GFX89 %s -; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX89 %s +; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s +; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=VI %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s
[llvm-branch-commits] [compiler-rt] 90b8fd6 - scudo: Fix compilation for non-Linux aarch64
Author: Roland McGrath
Date: 2021-01-05T13:21:52-08:00
New Revision: 90b8fd6136078127f5b792ec64745e5ae54a12a4
URL:
https://github.com/llvm/llvm-project/commit/90b8fd6136078127f5b792ec64745e5ae54a12a4
DIFF:
https://github.com/llvm/llvm-project/commit/90b8fd6136078127f5b792ec64745e5ae54a12a4.diff
LOG: scudo: Fix compilation for non-Linux aarch64
Linux-specific aarch64 code was deconditionalized in commit
dfa40840e0e2fa094c5d3f441affe0785cdc8d09. This broke builds for
non-Linux aarch64 platforms.
Reviewed By: cryptoad
Differential Revision: https://reviews.llvm.org/D94108
Added:
Modified:
compiler-rt/lib/scudo/standalone/memtag.h
Removed:
diff --git a/compiler-rt/lib/scudo/standalone/memtag.h
b/compiler-rt/lib/scudo/standalone/memtag.h
index d848e3a0b6c9..b1b62065ed72 100644
--- a/compiler-rt/lib/scudo/standalone/memtag.h
+++ b/compiler-rt/lib/scudo/standalone/memtag.h
@@ -52,6 +52,8 @@ inline uint8_t extractTag(uptr Ptr) {
#if defined(__aarch64__)
+#if SCUDO_LINUX
+
inline bool systemSupportsMemoryTagging() {
#ifndef HWCAP2_MTE
#define HWCAP2_MTE (1 << 18)
@@ -77,6 +79,14 @@ inline bool systemDetectsMemoryTagFaultsTestOnly() {
PR_MTE_TCF_MASK) != PR_MTE_TCF_NONE;
}
+#else // !SCUDO_LINUX
+
+inline bool systemSupportsMemoryTagging() { return false; }
+
+inline bool systemDetectsMemoryTagFaultsTestOnly() { return false; }
+
+#endif // SCUDO_LINUX
+
inline void disableMemoryTagChecksTestOnly() {
__asm__ __volatile__(".arch_extension mte; msr tco, #1");
}
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[llvm-branch-commits] [llvm] 8cf1cc5 - [FuncAttrs] Infer noreturn
Author: Arthur Eubanks
Date: 2021-01-05T13:25:42-08:00
New Revision: 8cf1cc578d3288f5b9cfe1584e524f8b1517dc97
URL:
https://github.com/llvm/llvm-project/commit/8cf1cc578d3288f5b9cfe1584e524f8b1517dc97
DIFF:
https://github.com/llvm/llvm-project/commit/8cf1cc578d3288f5b9cfe1584e524f8b1517dc97.diff
LOG: [FuncAttrs] Infer noreturn
A function is noreturn if all blocks terminating with a ReturnInst
contain a call to a noreturn function. Skip looking at naked functions
since there may be asm that returns.
This can be further refined in the future by checking unreachable blocks
and taking into account recursion. It looks like the attributor pass
does this, but that is not yet enabled by default.
This seems to help with code size under the new PM since PruneEH does
not run under the new PM, missing opportunities to mark some functions
noreturn, which in turn doesn't allow simplifycfg to clean up dead code.
https://bugs.llvm.org/show_bug.cgi?id=46858.
Reviewed By: rnk
Differential Revision: https://reviews.llvm.org/D93946
Added:
llvm/test/Transforms/FunctionAttrs/noreturn.ll
Modified:
llvm/lib/Transforms/IPO/FunctionAttrs.cpp
llvm/test/Transforms/PruneEH/simplenoreturntest.ll
Removed:
diff --git a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
index 0d25d5d319e7..62e3e5ad0a52 100644
--- a/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
+++ b/llvm/lib/Transforms/IPO/FunctionAttrs.cpp
@@ -1388,6 +1388,42 @@ static bool addNoRecurseAttrs(const SCCNodeSet
&SCCNodes) {
return true;
}
+static bool instructionDoesNotReturn(Instruction &I) {
+ if (auto *CB = dyn_cast(&I)) {
+Function *Callee = CB->getCalledFunction();
+return Callee && Callee->doesNotReturn();
+ }
+ return false;
+}
+
+// A basic block can only return if it terminates with a ReturnInst and does
not
+// contain calls to noreturn functions.
+static bool basicBlockCanReturn(BasicBlock &BB) {
+ if (!isa(BB.getTerminator()))
+return false;
+ return none_of(BB, instructionDoesNotReturn);
+}
+
+// Set the noreturn function attribute if possible.
+static bool addNoReturnAttrs(const SCCNodeSet &SCCNodes) {
+ bool Changed = false;
+
+ for (Function *F : SCCNodes) {
+if (!F || !F->hasExactDefinition() || F->hasFnAttribute(Attribute::Naked)
||
+F->doesNotReturn())
+ continue;
+
+// The function can return if any basic blocks can return.
+// FIXME: this doesn't handle recursion or unreachable blocks.
+if (none_of(*F, basicBlockCanReturn)) {
+ F->setDoesNotReturn();
+ Changed = true;
+}
+ }
+
+ return Changed;
+}
+
static SCCNodesResult createSCCNodeSet(ArrayRef Functions) {
SCCNodesResult Res;
Res.HasUnknownCall = false;
@@ -1431,6 +1467,7 @@ static bool deriveAttrsInPostOrder(ArrayRef
Functions,
Changed |= addReadAttrs(Nodes.SCCNodes, AARGetter);
Changed |= addArgumentAttrs(Nodes.SCCNodes);
Changed |= inferConvergent(Nodes.SCCNodes);
+ Changed |= addNoReturnAttrs(Nodes.SCCNodes);
// If we have no external nodes participating in the SCC, we can deduce some
// more precise attributes as well.
diff --git a/llvm/test/Transforms/FunctionAttrs/noreturn.ll
b/llvm/test/Transforms/FunctionAttrs/noreturn.ll
new file mode 100644
index ..acc538d3ccee
--- /dev/null
+++ b/llvm/test/Transforms/FunctionAttrs/noreturn.ll
@@ -0,0 +1,66 @@
+; RUN: opt < %s -passes='function-attrs' -S | FileCheck %s
+
+declare i32 @f()
+
+; CHECK: Function Attrs: noreturn
+; CHECK-NEXT: @noreturn()
+declare i32 @noreturn() noreturn
+
+; CHECK: Function Attrs: noreturn
+; CHECK-NEXT: @caller()
+define i32 @caller() {
+ %c = call i32 @noreturn()
+ ret i32 %c
+}
+
+; CHECK: Function Attrs: noreturn
+; CHECK-NEXT: @caller2()
+define i32 @caller2() {
+ %c = call i32 @caller()
+ ret i32 %c
+}
+
+; CHECK: Function Attrs: noreturn
+; CHECK-NEXT: @caller3()
+define i32 @caller3() {
+entry:
+ br label %end
+end:
+ %c = call i32 @noreturn()
+ ret i32 %c
+}
+
+; CHECK-NOT: Function Attrs: {{.*}}noreturn
+; CHECK: define i32 @caller4()
+define i32 @caller4() {
+entry:
+ br label %end
+end:
+ %c = call i32 @f()
+ ret i32 %c
+}
+
+; CHECK-NOT: Function Attrs: {{.*}}noreturn
+; CHECK: @caller5()
+; We currently don't handle unreachable blocks.
+define i32 @caller5() {
+entry:
+ %c = call i32 @noreturn()
+ ret i32 %c
+unreach:
+ %d = call i32 @f()
+ ret i32 %d
+}
+
+; CHECK-NOT: Function Attrs: {{.*}}noreturn
+; CHECK: @caller6()
+define i32 @caller6() naked {
+ %c = call i32 @noreturn()
+ ret i32 %c
+}
+
+; CHECK: Function Attrs: {{.*}}noreturn
+; CHECK-NEXT: @alreadynoreturn()
+define i32 @alreadynoreturn() noreturn {
+ unreachable
+}
diff --git a/llvm/test/Transforms/PruneEH/simplenoreturntest.ll
b/llvm/test/Transforms/PruneEH/simplenoreturntest.ll
index 814f8b4a686f..ccb9f5eb6f59 100644
--- a/llvm/test/Transforms/PruneEH/simplenoreturntest
[llvm-branch-commits] [clang] 16c6e9c - [ASTMatchers] Fix child traversal over range-for loops
Author: Stephen Kelly
Date: 2021-01-05T21:29:37Z
New Revision: 16c6e9c58e9ae50a775945e6b407f1891f353d2f
URL:
https://github.com/llvm/llvm-project/commit/16c6e9c58e9ae50a775945e6b407f1891f353d2f
DIFF:
https://github.com/llvm/llvm-project/commit/16c6e9c58e9ae50a775945e6b407f1891f353d2f.diff
LOG: [ASTMatchers] Fix child traversal over range-for loops
Differential Revision: https://reviews.llvm.org/D94031
Added:
Modified:
clang/lib/ASTMatchers/ASTMatchFinder.cpp
clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
Removed:
diff --git a/clang/lib/ASTMatchers/ASTMatchFinder.cpp
b/clang/lib/ASTMatchers/ASTMatchFinder.cpp
index 99d95838af61..39bdb94e62c6 100644
--- a/clang/lib/ASTMatchers/ASTMatchFinder.cpp
+++ b/clang/lib/ASTMatchers/ASTMatchFinder.cpp
@@ -236,6 +236,20 @@ class MatchChildASTVisitor
ScopedIncrement ScopedDepth(&CurrentDepth);
return traverse(TAL);
}
+ bool TraverseCXXForRangeStmt(CXXForRangeStmt *Node) {
+if (!Finder->isTraversalIgnoringImplicitNodes())
+ return VisitorBase::TraverseCXXForRangeStmt(Node);
+if (!Node)
+ return true;
+ScopedIncrement ScopedDepth(&CurrentDepth);
+if (auto *Init = Node->getInit())
+ if (!match(*Init))
+return false;
+if (!match(*Node->getLoopVariable()) || !match(*Node->getRangeInit()) ||
+!match(*Node->getBody()))
+ return false;
+return VisitorBase::TraverseStmt(Node->getBody());
+ }
bool TraverseLambdaExpr(LambdaExpr *Node) {
if (!Finder->isTraversalIgnoringImplicitNodes())
return VisitorBase::TraverseLambdaExpr(Node);
@@ -575,8 +589,6 @@ class MatchASTVisitor : public
RecursiveASTVisitor,
if (isTraversalIgnoringImplicitNodes()) {
IgnoreImplicitChildren = true;
- if (Node.get())
-ScopedTraversal = true;
}
ASTNodeNotSpelledInSourceScope RAII(this, ScopedTraversal);
diff --git a/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
b/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
index e706ea4b2a54..19ab6187d960 100644
--- a/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
+++ b/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
@@ -2553,7 +2553,9 @@ struct CtorInitsNonTrivial : NonTrivial
int arr[2];
for (auto i : arr)
{
-
+ if (true)
+ {
+ }
}
}
)cpp";
@@ -2596,6 +2598,33 @@ struct CtorInitsNonTrivial : NonTrivial
EXPECT_TRUE(matches(Code, traverse(TK_AsIs, M)));
EXPECT_TRUE(matches(Code, traverse(TK_IgnoreUnlessSpelledInSource, M)));
}
+ {
+auto M = cxxForRangeStmt(hasDescendant(ifStmt()));
+EXPECT_TRUE(matches(Code, traverse(TK_AsIs, M)));
+EXPECT_TRUE(matches(Code, traverse(TK_IgnoreUnlessSpelledInSource, M)));
+ }
+ {
+EXPECT_TRUE(matches(
+Code, traverse(TK_AsIs, cxxForRangeStmt(has(declStmt(
+hasSingleDecl(varDecl(hasName("i");
+EXPECT_TRUE(
+matches(Code, traverse(TK_IgnoreUnlessSpelledInSource,
+ cxxForRangeStmt(has(varDecl(hasName("i")));
+ }
+ {
+EXPECT_TRUE(matches(
+Code, traverse(TK_AsIs, cxxForRangeStmt(has(declStmt(hasSingleDecl(
+varDecl(hasInitializer(declRefExpr(
+to(varDecl(hasName("arr");
+EXPECT_TRUE(matches(Code, traverse(TK_IgnoreUnlessSpelledInSource,
+ cxxForRangeStmt(has(declRefExpr(
+ to(varDecl(hasName("arr");
+ }
+ {
+auto M = cxxForRangeStmt(has(compoundStmt()));
+EXPECT_TRUE(matches(Code, traverse(TK_AsIs, M)));
+EXPECT_TRUE(matches(Code, traverse(TK_IgnoreUnlessSpelledInSource, M)));
+ }
{
auto M = binaryOperator(hasOperatorName("!="));
EXPECT_TRUE(matches(Code, traverse(TK_AsIs, M)));
@@ -2659,7 +2688,8 @@ struct CtorInitsNonTrivial : NonTrivial
true, {"-std=c++20"}));
}
{
-auto M = cxxForRangeStmt(has(declStmt()));
+auto M =
+cxxForRangeStmt(has(declStmt(hasSingleDecl(varDecl(hasName("i"));
EXPECT_TRUE(
matchesConditionally(Code, traverse(TK_AsIs, M), true,
{"-std=c++20"}));
EXPECT_FALSE(
@@ -2679,6 +2709,19 @@ struct CtorInitsNonTrivial : NonTrivial
matchesConditionally(Code, traverse(TK_IgnoreUnlessSpelledInSource, M),
true, {"-std=c++20"}));
}
+ {
+auto M = cxxForRangeStmt(
+has(declStmt(hasSingleDecl(varDecl(
+hasName("a"),
+hasInitializer(declRefExpr(to(varDecl(hasName("arr"),
+hasLoopVariable(varDecl(hasName("i"))),
+hasRangeInit(declRefExpr(to(varDecl(hasName("a"));
+EXPECT_TRUE(
+matchesConditionally(Code, traverse(TK_AsIs, M), true,
{"-std=c++20"}));
+EXPECT_TRUE(
+
[llvm-branch-commits] [llvm] bec987e - [NFC] Removed unused prefixes in CodeGen/AMDGPU
Author: Mircea Trofin Date: 2021-01-05T14:10:03-08:00 New Revision: bec987ea6727f18e1512636804367c3695f51b6f URL: https://github.com/llvm/llvm-project/commit/bec987ea6727f18e1512636804367c3695f51b6f DIFF: https://github.com/llvm/llvm-project/commit/bec987ea6727f18e1512636804367c3695f51b6f.diff LOG: [NFC] Removed unused prefixes in CodeGen/AMDGPU This is part of the pertinent tests, more to follow in subsequent patches. Differential Revision: https://reviews.llvm.org/D94114 Added: Modified: llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll llvm/test/CodeGen/AMDGPU/amdpal-cs.ll llvm/test/CodeGen/AMDGPU/amdpal-es.ll llvm/test/CodeGen/AMDGPU/amdpal-gs.ll llvm/test/CodeGen/AMDGPU/amdpal-hs.ll llvm/test/CodeGen/AMDGPU/amdpal-ls.ll llvm/test/CodeGen/AMDGPU/amdpal-msgpack-cs.ll llvm/test/CodeGen/AMDGPU/amdpal-msgpack-default.ll llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp.ll llvm/test/CodeGen/AMDGPU/amdpal-msgpack-es.ll llvm/test/CodeGen/AMDGPU/amdpal-msgpack-gs.ll llvm/test/CodeGen/AMDGPU/amdpal-msgpack-hs.ll llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ls.ll llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ps.ll llvm/test/CodeGen/AMDGPU/amdpal-msgpack-psenable.ll llvm/test/CodeGen/AMDGPU/amdpal-msgpack-vs.ll llvm/test/CodeGen/AMDGPU/amdpal-ps.ll llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll llvm/test/CodeGen/AMDGPU/amdpal-vs.ll llvm/test/CodeGen/AMDGPU/andorn2.ll llvm/test/CodeGen/AMDGPU/anyext.ll llvm/test/CodeGen/AMDGPU/atomic_cmp_swap_local.ll llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll Removed: diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll index d38452a3a22a..bbbec113e78c 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgcn.private-memory.ll @@ -1,9 +1,9 @@ -; RUN: llc -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-PROMOTE %s -; RUN: llc -mattr=+promote-alloca,-flat-for-global -verify-machineinstrs -mtriple=amdgcn--amdhsa -mcpu=kaveri < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-PROMOTE -check-prefix=HSA %s -; RUN: llc -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-ALLOCA %s -; RUN: llc -mattr=-promote-alloca,-flat-for-global -verify-machineinstrs -mtriple=amdgcn-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-ALLOCA -check-prefix=HSA %s -; RUN: llc -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-PROMOTE %s -; RUN: llc -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-ALLOCA %s +; RUN: llc -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn < %s | FileCheck --check-prefixes=GCN,GCN-PROMOTE %s +; RUN: llc -mattr=+promote-alloca,-flat-for-global -verify-machineinstrs -mtriple=amdgcn--amdhsa -mcpu=kaveri < %s | FileCheck --check-prefixes=GCN,GCN-PROMOTE %s +; RUN: llc -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn < %s | FileCheck --check-prefixes=GCN,GCN-ALLOCA %s +; RUN: llc -mattr=-promote-alloca,-flat-for-global -verify-machineinstrs -mtriple=amdgcn-amdhsa -mcpu=kaveri < %s | FileCheck --check-prefixes=GCN,GCN-ALLOCA %s +; RUN: llc -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCN,GCN-PROMOTE %s +; RUN: llc -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCN,GCN-ALLOCA %s declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll b/llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll index b11f17ba0882..d00e66b7adbb 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SI-NOHSA -check-prefix=GCN-NOHSA -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOHSA -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=amd
[llvm-branch-commits] [llvm] 1ebe86a - [NFC] Removed unused prefixes in test/CodeGen/AMDGPU
Author: Mircea Trofin
Date: 2021-01-05T14:16:52-08:00
New Revision: 1ebe86adf52cbddc03f535554b16585b2947b32c
URL:
https://github.com/llvm/llvm-project/commit/1ebe86adf52cbddc03f535554b16585b2947b32c
DIFF:
https://github.com/llvm/llvm-project/commit/1ebe86adf52cbddc03f535554b16585b2947b32c.diff
LOG: [NFC] Removed unused prefixes in test/CodeGen/AMDGPU
More patches to follow.
Differential Revision: https://reviews.llvm.org/D94121
Added:
Modified:
llvm/test/CodeGen/AMDGPU/bfm.ll
llvm/test/CodeGen/AMDGPU/bitreverse.ll
llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir
llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
llvm/test/CodeGen/AMDGPU/bswap.ll
llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll
llvm/test/CodeGen/AMDGPU/call-encoding.ll
llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll
llvm/test/CodeGen/AMDGPU/clamp.ll
llvm/test/CodeGen/AMDGPU/code-object-v3.ll
llvm/test/CodeGen/AMDGPU/commute-compares.ll
llvm/test/CodeGen/AMDGPU/commute-shifts.ll
llvm/test/CodeGen/AMDGPU/concat_vectors.ll
llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
llvm/test/CodeGen/AMDGPU/ctlz.ll
llvm/test/CodeGen/AMDGPU/cube.ll
llvm/test/CodeGen/AMDGPU/debug.ll
llvm/test/CodeGen/AMDGPU/diverge-extra-formal-args.ll
llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll
llvm/test/CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll
llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
llvm/test/CodeGen/AMDGPU/ds_read2.ll
llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll
llvm/test/CodeGen/AMDGPU/ds_write2.ll
Removed:
diff --git a/llvm/test/CodeGen/AMDGPU/bfm.ll b/llvm/test/CodeGen/AMDGPU/bfm.ll
index 5673995588da..06e03c0a934a 100644
--- a/llvm/test/CodeGen/AMDGPU/bfm.ll
+++ b/llvm/test/CodeGen/AMDGPU/bfm.ll
@@ -1,6 +1,6 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck
-check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global
-verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck
-check-prefix=EG -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck
--check-prefixes=SI,FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global
-verify-machineinstrs < %s | FileCheck --check-prefixes=SI,FUNC %s
+; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck
-check-prefix=FUNC %s
; FUNC-LABEL: {{^}}bfm_pattern:
; SI: s_bfm_b32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
diff --git a/llvm/test/CodeGen/AMDGPU/bitreverse.ll
b/llvm/test/CodeGen/AMDGPU/bitreverse.ll
index 55ae15218a44..d6dc59a60dbf 100644
--- a/llvm/test/CodeGen/AMDGPU/bitreverse.ll
+++ b/llvm/test/CodeGen/AMDGPU/bitreverse.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tahiti -verify-machineinstrs |
FileCheck %s --check-prefixes=FUNC,SI
-; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global
-verify-machineinstrs | FileCheck %s --check-prefixes=FUNC,FLAT,TONGA
-; RUN: llc < %s -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global
-verify-machineinstrs | FileCheck %s --check-prefixes=FUNC,FLAT,VI
+; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tahiti -verify-machineinstrs |
FileCheck %s --check-prefix=SI
+; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global
-verify-machineinstrs | FileCheck %s --check-prefix=FLAT
+; RUN: llc < %s -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global
-verify-machineinstrs | FileCheck %s --check-prefix=FLAT
declare i32 @llvm.amdgcn.workitem.id.x() #1
diff --git a/llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir
b/llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir
index fa482532338e..bc172a33d512 100644
--- a/llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir
+++ b/llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir
@@ -1,5 +1,5 @@
# RUN: llc -march=amdgcn -mcpu=carrizo -verify-machineinstrs -run-pass
post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,XNACK %s
-# RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass
post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,NOXNACK %s
+# RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass
post-RA-hazard-rec %s -o - | FileCheck --check-prefix=GCN %s
---
# Trivial clause at beginning of program
diff --git a/llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
b/llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
index 39afa4c4515f..a4b71ed2fee6 100644
--- a/llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
+++ b/llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
@@ -2,7 +2,7 @@
# Make sure the default assumption is xnack enabled with no cpu
# RUN: llc -march
[llvm-branch-commits] [llvm] 6a03f8a - [SLP] reduce code for finding reduction costs; NFC
Author: Sanjay Patel
Date: 2021-01-05T17:35:54-05:00
New Revision: 6a03f8ab629b34a2425764caaa46dbfcf3d8e1ef
URL:
https://github.com/llvm/llvm-project/commit/6a03f8ab629b34a2425764caaa46dbfcf3d8e1ef
DIFF:
https://github.com/llvm/llvm-project/commit/6a03f8ab629b34a2425764caaa46dbfcf3d8e1ef.diff
LOG: [SLP] reduce code for finding reduction costs; NFC
We can get both (vector/scalar) costs in a single switch
instead of sequentially.
Added:
Modified:
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Removed:
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 48f2a2d2886f..92e3ae7bea8b 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -7140,6 +7140,7 @@ class HorizontalReduction {
RecurKind Kind = RdxTreeInst.getKind();
unsigned RdxOpcode = RecurrenceDescriptor::getOpcode(Kind);
int SplittingRdxCost;
+int ScalarReduxCost;
switch (Kind) {
case RecurKind::Add:
case RecurKind::Mul:
@@ -7150,6 +7151,7 @@ class HorizontalReduction {
case RecurKind::FMul:
SplittingRdxCost = TTI->getArithmeticReductionCost(
RdxOpcode, VecTy, /*IsPairwiseForm=*/false);
+ ScalarReduxCost = TTI->getArithmeticInstrCost(RdxOpcode, ScalarTy);
break;
case RecurKind::SMax:
case RecurKind::SMin:
@@ -7160,42 +7162,21 @@ class HorizontalReduction {
SplittingRdxCost =
TTI->getMinMaxReductionCost(VecTy, VecCondTy,
/*IsPairwiseForm=*/false, IsUnsigned);
- break;
-}
-default:
- llvm_unreachable("Expected arithmetic or min/max reduction operation");
-}
-
-int ScalarReduxCost = 0;
-switch (Kind) {
-case RecurKind::Add:
-case RecurKind::Mul:
-case RecurKind::Or:
-case RecurKind::And:
-case RecurKind::Xor:
-case RecurKind::FAdd:
-case RecurKind::FMul:
- ScalarReduxCost = TTI->getArithmeticInstrCost(RdxOpcode, ScalarTy);
- break;
-case RecurKind::SMax:
-case RecurKind::SMin:
-case RecurKind::UMax:
-case RecurKind::UMin:
ScalarReduxCost =
TTI->getCmpSelInstrCost(RdxOpcode, ScalarTy) +
TTI->getCmpSelInstrCost(Instruction::Select, ScalarTy,
CmpInst::makeCmpResultType(ScalarTy));
break;
+}
default:
llvm_unreachable("Expected arithmetic or min/max reduction operation");
}
-ScalarReduxCost *= (ReduxWidth - 1);
+ScalarReduxCost *= (ReduxWidth - 1);
LLVM_DEBUG(dbgs() << "SLP: Adding cost "
<< SplittingRdxCost - ScalarReduxCost
<< " for reduction that starts with " << *FirstReducedVal
<< " (It is a splitting reduction)\n");
-
return SplittingRdxCost - ScalarReduxCost;
}
___
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[llvm-branch-commits] [llvm] cb5b52a - AMDGPU: Annotate amdgpu.noclobber for global loads only
Author: Changpeng Fang
Date: 2021-01-05T14:47:19-08:00
New Revision: cb5b52a06eeb7cc868944bb08f71fffe13f33412
URL:
https://github.com/llvm/llvm-project/commit/cb5b52a06eeb7cc868944bb08f71fffe13f33412
DIFF:
https://github.com/llvm/llvm-project/commit/cb5b52a06eeb7cc868944bb08f71fffe13f33412.diff
LOG: AMDGPU: Annotate amdgpu.noclobber for global loads only
Summary:
This is to avoid unnecessary analysis since amdgpu.noclobber is only used for
globals.
Reviewers:
arsenm
Fixes:
SWDEV-239161
Differential Revision:
https://reviews.llvm.org/D94107
Added:
llvm/test/CodeGen/AMDGPU/annotate-noclobber.ll
Modified:
llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
llvm/test/CodeGen/AMDGPU/store-clobbers-load.ll
Removed:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
index f23c4c17ab794..0123450b18bf4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
@@ -142,10 +142,11 @@ void AMDGPUAnnotateUniformValues::visitLoadInst(LoadInst
&I) {
}
bool NotClobbered = false;
+ bool GlobalLoad = isGlobalLoad(I);
if (PtrI)
-NotClobbered = !isClobberedInFunction(&I);
+NotClobbered = GlobalLoad && !isClobberedInFunction(&I);
else if (isa(Ptr) || isa(Ptr)) {
-if (isGlobalLoad(I) && !isClobberedInFunction(&I)) {
+if (GlobalLoad && !isClobberedInFunction(&I)) {
NotClobbered = true;
// Lookup for the existing GEP
if (noClobberClones.count(Ptr)) {
diff --git a/llvm/test/CodeGen/AMDGPU/annotate-noclobber.ll
b/llvm/test/CodeGen/AMDGPU/annotate-noclobber.ll
new file mode 100644
index 0..580ea202addd6
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/annotate-noclobber.ll
@@ -0,0 +1,47 @@
+; RUN: opt -S --amdgpu-annotate-uniform < %s | FileCheck -check-prefix=OPT %s
+target datalayout = "A5"
+
+
+; OPT-LABEL: @amdgpu_noclobber_global(
+; OPT: %addr = getelementptr i32, i32 addrspace(1)* %in, i64 0,
!amdgpu.uniform !0, !amdgpu.noclobber !0
+; OPT-NEXT: %load = load i32, i32 addrspace(1)* %addr, align 4
+define amdgpu_kernel void @amdgpu_noclobber_global( i32 addrspace(1)* %in,
i32 addrspace(1)* %out) {
+entry:
+ %addr = getelementptr i32, i32 addrspace(1)* %in, i64 0
+ %load = load i32, i32 addrspace(1)* %addr, align 4
+ store i32 %load, i32 addrspace(1)* %out, align 4
+ ret void
+}
+
+; OPT-LABEL: @amdgpu_noclobber_local(
+; OPT: %addr = getelementptr i32, i32 addrspace(3)* %in, i64 0,
!amdgpu.uniform !0
+; OPT-NEXT: %load = load i32, i32 addrspace(3)* %addr, align 4
+define amdgpu_kernel void @amdgpu_noclobber_local( i32 addrspace(3)* %in, i32
addrspace(1)* %out) {
+entry:
+ %addr = getelementptr i32, i32 addrspace(3)* %in, i64 0
+ %load = load i32, i32 addrspace(3)* %addr, align 4
+ store i32 %load, i32 addrspace(1)* %out, align 4
+ ret void
+}
+
+; OPT-LABEL: @amdgpu_noclobber_private(
+; OPT: %addr = getelementptr i32, i32 addrspace(5)* %in, i64 0,
!amdgpu.uniform !0
+; OPT-NEXT: %load = load i32, i32 addrspace(5)* %addr, align 4
+define amdgpu_kernel void @amdgpu_noclobber_private( i32 addrspace(5)* %in,
i32 addrspace(1)* %out) {
+entry:
+ %addr = getelementptr i32, i32 addrspace(5)* %in, i64 0
+ %load = load i32, i32 addrspace(5)* %addr, align 4
+ store i32 %load, i32 addrspace(1)* %out, align 4
+ ret void
+}
+
+; OPT-LABEL: @amdgpu_noclobber_flat(
+; OPT: %addr = getelementptr i32, i32 addrspace(4)* %in, i64 0,
!amdgpu.uniform !0
+; OPT-NEXT: %load = load i32, i32 addrspace(4)* %addr, align 4
+define amdgpu_kernel void @amdgpu_noclobber_flat( i32 addrspace(4)* %in, i32
addrspace(1)* %out) {
+entry:
+ %addr = getelementptr i32, i32 addrspace(4)* %in, i64 0
+ %load = load i32, i32 addrspace(4)* %addr, align 4
+ store i32 %load, i32 addrspace(1)* %out, align 4
+ ret void
+}
diff --git a/llvm/test/CodeGen/AMDGPU/store-clobbers-load.ll
b/llvm/test/CodeGen/AMDGPU/store-clobbers-load.ll
index 88cfffed47c59..fbf6990a5629d 100644
--- a/llvm/test/CodeGen/AMDGPU/store-clobbers-load.ll
+++ b/llvm/test/CodeGen/AMDGPU/store-clobbers-load.ll
@@ -4,24 +4,24 @@ target datalayout = "A5"
; "load vaddr" depends on the store, so we should not mark vaddr as
amdgpu.noclobber.
; OPT-LABEL: @store_clobbers_load(
-; OPT: %vaddr = bitcast [4 x i32] addrspace(5)* %alloca to <4 x i32>
addrspace(5)*, !amdgpu.uniform !0
-; OPT-NEXT: %zero = load <4 x i32>, <4 x i32> addrspace(5)* %vaddr, align 16
-define amdgpu_kernel void @store_clobbers_load(i32 addrspace(1)* %out, i32
%index) {
+; OPT: %vaddr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %input,
i64 0, !amdgpu.uniform !0
+; OPT-NEXT: %zero = load <4 x i32>, <4 x i32> addrspace(1)* %vaddr, align 16
+define amdgpu_kernel void @store_clobbers_load( < 4 x i32> addrspace(1)*
%input, i32 addrspace(1)*
[llvm-branch-commits] [llvm] f985356 - [SimplifyCFG] simplifyUnreachable(): switch to non-permissive DomTree updates
Author: Roman Lebedev
Date: 2021-01-06T01:52:36+03:00
New Revision: f98535686e3c1fa76986337639df1636282692c9
URL:
https://github.com/llvm/llvm-project/commit/f98535686e3c1fa76986337639df1636282692c9
DIFF:
https://github.com/llvm/llvm-project/commit/f98535686e3c1fa76986337639df1636282692c9.diff
LOG: [SimplifyCFG] simplifyUnreachable(): switch to non-permissive DomTree
updates
... which requires not removing a DomTree edge if the switch's default
still points at that destination, because it can't be removed;
... and not processing the same predecessor more than once.
Added:
Modified:
llvm/lib/Transforms/Utils/SimplifyCFG.cpp
Removed:
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 9f808278d899..d01d9512212c 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -4616,7 +4616,6 @@ bool SimplifyCFGOpt::simplifyReturn(ReturnInst *RI,
IRBuilder<> &Builder) {
return false;
}
-// FIXME: switch to non-permissive DomTreeUpdater::applyUpdates().
bool SimplifyCFGOpt::simplifyUnreachable(UnreachableInst *UI) {
BasicBlock *BB = UI->getParent();
@@ -4678,7 +4677,7 @@ bool SimplifyCFGOpt::simplifyUnreachable(UnreachableInst
*UI) {
std::vector Updates;
- SmallVector Preds(predecessors(BB));
+ SmallSetVector Preds(pred_begin(BB), pred_end(BB));
for (unsigned i = 0, e = Preds.size(); i != e; ++i) {
auto *Predecessor = Preds[i];
Instruction *TI = Predecessor->getTerminator();
@@ -4718,7 +4717,9 @@ bool SimplifyCFGOpt::simplifyUnreachable(UnreachableInst
*UI) {
e = SU->case_end();
Changed = true;
}
- Updates.push_back({DominatorTree::Delete, Predecessor, BB});
+ // Note that the default destination can't be removed!
+ if (SI->getDefaultDest() != BB)
+Updates.push_back({DominatorTree::Delete, Predecessor, BB});
} else if (auto *II = dyn_cast(TI)) {
if (II->getUnwindDest() == BB) {
if (DTU)
@@ -4785,7 +4786,7 @@ bool SimplifyCFGOpt::simplifyUnreachable(UnreachableInst
*UI) {
}
if (DTU)
-DTU->applyUpdatesPermissive(Updates);
+DTU->applyUpdates(Updates);
// If this block is now dead, remove it.
if (pred_empty(BB) && BB != &BB->getParent()->getEntryBlock()) {
___
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[llvm-branch-commits] [llvm] 3460719 - [NFC][SimplifyCFG] Add a test with same-destination condidional branch
Author: Roman Lebedev
Date: 2021-01-06T01:52:36+03:00
New Revision: 3460719f583583e6990ec5c1b2a718cc01797bf7
URL:
https://github.com/llvm/llvm-project/commit/3460719f583583e6990ec5c1b2a718cc01797bf7
DIFF:
https://github.com/llvm/llvm-project/commit/3460719f583583e6990ec5c1b2a718cc01797bf7.diff
LOG: [NFC][SimplifyCFG] Add a test with same-destination condidional branch
Reported by Mikael Holmén as post-commit feedback on
https://reviews.llvm.org/rG2d07414ee5f74a09fb89723b4a9bb0818bdc2e18#968162
Added:
llvm/test/Transforms/SimplifyCFG/simplifyUnreachable-degenerate-conditional-branch-with-matching-destinations.ll
Modified:
llvm/lib/Transforms/Utils/SimplifyCFG.cpp
Removed:
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index d01d9512212c..cf4854d27f4a 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -4690,9 +4690,9 @@ bool SimplifyCFGOpt::simplifyUnreachable(UnreachableInst
*UI) {
Changed = true;
} else {
Value* Cond = BI->getCondition();
-assert(BI->getSuccessor(0) != BI->getSuccessor(1) &&
- "Same-destination conditional branch instruction was "
- "already canonicalized into an unconditional branch.");
+//assert(BI->getSuccessor(0) != BI->getSuccessor(1) &&
+// "Same-destination conditional branch instruction was "
+// "already canonicalized into an unconditional
branch.");
if (BI->getSuccessor(0) == BB) {
Builder.CreateAssumption(Builder.CreateNot(Cond));
Builder.CreateBr(BI->getSuccessor(1));
diff --git
a/llvm/test/Transforms/SimplifyCFG/simplifyUnreachable-degenerate-conditional-branch-with-matching-destinations.ll
b/llvm/test/Transforms/SimplifyCFG/simplifyUnreachable-degenerate-conditional-branch-with-matching-destinations.ll
new file mode 100644
index ..b56d9d435925
--- /dev/null
+++
b/llvm/test/Transforms/SimplifyCFG/simplifyUnreachable-degenerate-conditional-branch-with-matching-destinations.ll
@@ -0,0 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=0 < %s |
FileCheck %s
+
+@global = external global i16, align 1
+@global.1 = external global i16, align 1
+@global.2 = external global i16, align 1
+
+define void @widget() {
+; CHECK-LABEL: @widget(
+; CHECK-NEXT: bb:
+; CHECK-NEXT:[[I:%.*]] = load i16, i16* @global, align 1
+; CHECK-NEXT:[[I13:%.*]] = icmp ne i16 [[I]], 0
+; CHECK-NEXT:call void @llvm.assume(i1 [[I13]])
+; CHECK-NEXT:[[I17:%.*]] = load i16, i16* @global, align 1
+; CHECK-NEXT:[[I18:%.*]] = sdiv i16 2, [[I17]]
+; CHECK-NEXT:[[I19:%.*]] = icmp ne i16 [[I18]], 0
+; CHECK-NEXT:[[I20:%.*]] = zext i1 [[I19]] to i16
+; CHECK-NEXT:[[I21:%.*]] = load i16, i16* @global.1, align 1
+; CHECK-NEXT:[[SPEC_SELECT:%.*]] = select i1 [[I19]], i16 [[I20]], i16
[[I21]]
+; CHECK-NEXT:[[TMP0:%.*]] = xor i1 [[I19]], true
+; CHECK-NEXT:call void @llvm.assume(i1 [[TMP0]])
+; CHECK-NEXT:unreachable
+;
+bb:
+ %i = load i16, i16* @global, align 1
+ %i13 = icmp ne i16 %i, 0
+ br i1 %i13, label %bb16, label %bb14
+
+bb14: ; preds = %bb
+ %i15 = load i16, i16* @global.1, align 1
+ br label %bb23
+
+bb16: ; preds = %bb
+ %i17 = load i16, i16* @global, align 1
+ %i18 = sdiv i16 2, %i17
+ %i19 = icmp ne i16 %i18, 0
+ %i20 = zext i1 %i19 to i16
+ %i21 = load i16, i16* @global.1, align 1
+ br i1 %i19, label %bb22, label %bb23
+
+bb22: ; preds = %bb16
+ br label %bb23
+
+bb23: ; preds = %bb22, %bb16, %bb14
+ %i24 = phi i16 [ %i20, %bb22 ], [ %i21, %bb16 ], [ %i15, %bb14 ]
+ store i16 %i24, i16* @global.2, align 1
+ unreachable
+}
___
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[llvm-branch-commits] [llvm] 29ca7d5 - [SimplifyCFG] simplifyUnreachable(): fix handling of degenerate same-destination conditional branch
Author: Roman Lebedev
Date: 2021-01-06T01:52:36+03:00
New Revision: 29ca7d5a1ad968c371124b8d82edd8d91eee7b4f
URL:
https://github.com/llvm/llvm-project/commit/29ca7d5a1ad968c371124b8d82edd8d91eee7b4f
DIFF:
https://github.com/llvm/llvm-project/commit/29ca7d5a1ad968c371124b8d82edd8d91eee7b4f.diff
LOG: [SimplifyCFG] simplifyUnreachable(): fix handling of degenerate
same-destination conditional branch
One would hope that it would have been already canonicalized into an
unconditional branch, but that isn't really guaranteed to happen
with SimplifyCFG's visitation order.
Added:
Modified:
llvm/lib/Transforms/Utils/SimplifyCFG.cpp
llvm/test/Transforms/SimplifyCFG/simplifyUnreachable-degenerate-conditional-branch-with-matching-destinations.ll
Removed:
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index cf4854d27f4a..7921a7462e2d 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -4683,16 +4683,18 @@ bool
SimplifyCFGOpt::simplifyUnreachable(UnreachableInst *UI) {
Instruction *TI = Predecessor->getTerminator();
IRBuilder<> Builder(TI);
if (auto *BI = dyn_cast(TI)) {
- if (BI->isUnconditional()) {
-assert(BI->getSuccessor(0) == BB && "Incorrect CFG");
+ // We could either have a proper unconditional branch,
+ // or a degenerate conditional branch with matching destinations.
+ if (all_of(BI->successors(),
+ [BB](auto *Successor) { return Successor == BB; })) {
new UnreachableInst(TI->getContext(), TI);
TI->eraseFromParent();
Changed = true;
} else {
+assert(BI->isConditional() && "Can't get here with an uncond branch.");
Value* Cond = BI->getCondition();
-//assert(BI->getSuccessor(0) != BI->getSuccessor(1) &&
-// "Same-destination conditional branch instruction was "
-// "already canonicalized into an unconditional
branch.");
+assert(BI->getSuccessor(0) != BI->getSuccessor(1) &&
+ "The destinations are guaranteed to be
diff erent here.");
if (BI->getSuccessor(0) == BB) {
Builder.CreateAssumption(Builder.CreateNot(Cond));
Builder.CreateBr(BI->getSuccessor(1));
diff --git
a/llvm/test/Transforms/SimplifyCFG/simplifyUnreachable-degenerate-conditional-branch-with-matching-destinations.ll
b/llvm/test/Transforms/SimplifyCFG/simplifyUnreachable-degenerate-conditional-branch-with-matching-destinations.ll
index b56d9d435925..66218a10521b 100644
---
a/llvm/test/Transforms/SimplifyCFG/simplifyUnreachable-degenerate-conditional-branch-with-matching-destinations.ll
+++
b/llvm/test/Transforms/SimplifyCFG/simplifyUnreachable-degenerate-conditional-branch-with-matching-destinations.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=0 < %s |
FileCheck %s
+; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s |
FileCheck %s
@global = external global i16, align 1
@global.1 = external global i16, align 1
@@ -11,14 +11,6 @@ define void @widget() {
; CHECK-NEXT:[[I:%.*]] = load i16, i16* @global, align 1
; CHECK-NEXT:[[I13:%.*]] = icmp ne i16 [[I]], 0
; CHECK-NEXT:call void @llvm.assume(i1 [[I13]])
-; CHECK-NEXT:[[I17:%.*]] = load i16, i16* @global, align 1
-; CHECK-NEXT:[[I18:%.*]] = sdiv i16 2, [[I17]]
-; CHECK-NEXT:[[I19:%.*]] = icmp ne i16 [[I18]], 0
-; CHECK-NEXT:[[I20:%.*]] = zext i1 [[I19]] to i16
-; CHECK-NEXT:[[I21:%.*]] = load i16, i16* @global.1, align 1
-; CHECK-NEXT:[[SPEC_SELECT:%.*]] = select i1 [[I19]], i16 [[I20]], i16
[[I21]]
-; CHECK-NEXT:[[TMP0:%.*]] = xor i1 [[I19]], true
-; CHECK-NEXT:call void @llvm.assume(i1 [[TMP0]])
; CHECK-NEXT:unreachable
;
bb:
___
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[llvm-branch-commits] [llvm] fc96cb2 - [SimplifyCFG] FoldValueComparisonIntoPredecessors(): switch to non-permissive DomTree updates
Author: Roman Lebedev
Date: 2021-01-06T01:52:37+03:00
New Revision: fc96cb2dad6b8293124f12d00fb55ff75c2ebe71
URL:
https://github.com/llvm/llvm-project/commit/fc96cb2dad6b8293124f12d00fb55ff75c2ebe71
DIFF:
https://github.com/llvm/llvm-project/commit/fc96cb2dad6b8293124f12d00fb55ff75c2ebe71.diff
LOG: [SimplifyCFG] FoldValueComparisonIntoPredecessors(): switch to
non-permissive DomTree updates
... which requires not adding a DomTree edge that we just added.
Added:
Modified:
llvm/lib/Transforms/Utils/SimplifyCFG.cpp
Removed:
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 7921a7462e2d..08005c198298 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -17,6 +17,7 @@
#include "llvm/ADT/Optional.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/ScopeExit.h"
+#include "llvm/ADT/Sequence.h"
#include "llvm/ADT/SetOperations.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallPtrSet.h"
@@ -1085,7 +1086,6 @@ static void FitWeights(MutableArrayRef Weights)
{
/// (either a switch or a branch on "X == c").
/// See if any of the predecessors of the terminator block are value
comparisons
/// on the same value. If so, and if safe to do so, fold them together.
-// FIXME: switch to non-permissive DomTreeUpdater::applyUpdates().
bool SimplifyCFGOpt::FoldValueComparisonIntoPredecessors(Instruction *TI,
IRBuilder<> &Builder)
{
BasicBlock *BB = TI->getParent();
@@ -1129,7 +1129,7 @@ bool
SimplifyCFGOpt::FoldValueComparisonIntoPredecessors(Instruction *TI,
// Based on whether the default edge from PTI goes to BB or not, fill in
// PredCases and PredDefault with the new switch cases we would like to
// build.
- SmallVector NewSuccessors;
+ SmallMapVector NewSuccessors;
// Update the branch weight metadata along the way
SmallVector Weights;
@@ -1185,7 +1185,7 @@ bool
SimplifyCFGOpt::FoldValueComparisonIntoPredecessors(Instruction *TI,
if (PredDefault != BB)
Updates.push_back({DominatorTree::Delete, Pred, PredDefault});
PredDefault = BBDefault;
- NewSuccessors.push_back(BBDefault);
+ ++NewSuccessors[BBDefault];
}
unsigned CasesFromPred = Weights.size();
@@ -1194,7 +1194,7 @@ bool
SimplifyCFGOpt::FoldValueComparisonIntoPredecessors(Instruction *TI,
if (!PTIHandled.count(BBCases[i].Value) &&
BBCases[i].Dest != BBDefault) {
PredCases.push_back(BBCases[i]);
-NewSuccessors.push_back(BBCases[i].Dest);
+++NewSuccessors[BBCases[i].Dest];
if (SuccHasWeights || PredHasWeights) {
// The default weight is at index 0, so weight for the ith case
// should be at index i+1. Scale the cases from successor by
@@ -1242,7 +1242,7 @@ bool
SimplifyCFGOpt::FoldValueComparisonIntoPredecessors(Instruction *TI,
if (PredHasWeights || SuccHasWeights)
Weights.push_back(WeightsForHandled[BBCases[i].Value]);
PredCases.push_back(BBCases[i]);
-NewSuccessors.push_back(BBCases[i].Dest);
+++NewSuccessors[BBCases[i].Dest];
PTIHandled.erase(
BBCases[i].Value); // This constant is taken care of
}
@@ -1253,16 +1253,20 @@ bool
SimplifyCFGOpt::FoldValueComparisonIntoPredecessors(Instruction *TI,
if (PredHasWeights || SuccHasWeights)
Weights.push_back(WeightsForHandled[I]);
PredCases.push_back(ValueEqualityComparisonCase(I, BBDefault));
- NewSuccessors.push_back(BBDefault);
+ ++NewSuccessors[BBDefault];
}
}
// Okay, at this point, we know which new successor Pred will get. Make
// sure we update the number of entries in the PHI nodes for these
// successors.
- for (BasicBlock *NewSuccessor : NewSuccessors) {
-AddPredecessorToBlock(NewSuccessor, Pred, BB);
-Updates.push_back({DominatorTree::Insert, Pred, NewSuccessor});
+ for (const std::pair &NewSuccessor :
+ NewSuccessors) {
+for (auto I : seq(0, NewSuccessor.second)) {
+ (void)I;
+ AddPredecessorToBlock(NewSuccessor.first, Pred, BB);
+}
+Updates.push_back({DominatorTree::Insert, Pred, NewSuccessor.first});
}
Builder.SetInsertPoint(PTI);
@@ -1314,7 +1318,7 @@ bool
SimplifyCFGOpt::FoldValueComparisonIntoPredecessors(Instruction *TI,
Updates.push_back({DominatorTree::Delete, Pred, BB});
if (DTU)
-DTU->applyUpdatesPermissive(Updates);
+DTU->applyUpdates(Updates);
Changed = true;
}
___
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[llvm-branch-commits] [llvm] d15d81c - [SimplifyCFG] FoldValueComparisonIntoPredecessors(): deal with each predecessor only once
Author: Roman Lebedev
Date: 2021-01-06T01:52:37+03:00
New Revision: d15d81ce15e086208f30d99ce2257a75401dc12c
URL:
https://github.com/llvm/llvm-project/commit/d15d81ce15e086208f30d99ce2257a75401dc12c
DIFF:
https://github.com/llvm/llvm-project/commit/d15d81ce15e086208f30d99ce2257a75401dc12c.diff
LOG: [SimplifyCFG] FoldValueComparisonIntoPredecessors(): deal with each
predecessor only once
If the predecessor is a switch, and BB is not the default destination,
multiple cases could have the same destination. and it doesn't
make sense to re-process the predecessor, because we won't make any changes,
once is enough.
I'm not sure this can be really tested, other than via the assertion
being added here, which fires without the fix.
Added:
Modified:
llvm/lib/Transforms/Utils/SimplifyCFG.cpp
Removed:
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 08005c198298..6d5a68214e7c 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -1099,7 +1099,7 @@ bool
SimplifyCFGOpt::FoldValueComparisonIntoPredecessors(Instruction *TI,
++NumFoldValueComparisonIntoPredecessors;
});
- SmallVector Preds(predecessors(BB));
+ SmallSetVector Preds(pred_begin(BB), pred_end(BB));
while (!Preds.empty()) {
BasicBlock *Pred = Preds.pop_back_val();
@@ -1260,6 +1260,7 @@ bool
SimplifyCFGOpt::FoldValueComparisonIntoPredecessors(Instruction *TI,
// Okay, at this point, we know which new successor Pred will get. Make
// sure we update the number of entries in the PHI nodes for these
// successors.
+ assert(!NewSuccessors.empty() && "Should be adding some new
successors.");
for (const std::pair &NewSuccessor :
NewSuccessors) {
for (auto I : seq(0, NewSuccessor.second)) {
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[llvm-branch-commits] [llvm] fa5447a - [NFC][SimplifyCFG] SwitchToLookupTable(): pull out SI->getParent() into a variable
Author: Roman Lebedev
Date: 2021-01-06T01:52:38+03:00
New Revision: fa5447aa3fec313bfd8ec31b7c66d390a5589b94
URL:
https://github.com/llvm/llvm-project/commit/fa5447aa3fec313bfd8ec31b7c66d390a5589b94
DIFF:
https://github.com/llvm/llvm-project/commit/fa5447aa3fec313bfd8ec31b7c66d390a5589b94.diff
LOG: [NFC][SimplifyCFG] SwitchToLookupTable(): pull out SI->getParent() into a
variable
Added:
Modified:
llvm/lib/Transforms/Utils/SimplifyCFG.cpp
Removed:
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 6d5a68214e7c..dc931557ebb6 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -5833,7 +5833,8 @@ static bool SwitchToLookupTable(SwitchInst *SI,
IRBuilder<> &Builder,
const TargetTransformInfo &TTI) {
assert(SI->getNumCases() > 1 && "Degenerate switch?");
- Function *Fn = SI->getParent()->getParent();
+ BasicBlock *BB = SI->getParent();
+ Function *Fn = BB->getParent();
// Only build lookup table when we have a target that supports it or the
// attribute is not set.
if (!TTI.shouldBuildLookupTables() ||
@@ -5961,7 +5962,7 @@ static bool SwitchToLookupTable(SwitchInst *SI,
IRBuilder<> &Builder,
if (!DefaultIsReachable || GeneratingCoveredLookupTable) {
Builder.CreateBr(LookupBB);
-Updates.push_back({DominatorTree::Insert, SI->getParent(), LookupBB});
+Updates.push_back({DominatorTree::Insert, BB, LookupBB});
// Note: We call removeProdecessor later since we need to be able to get
the
// PHI value for the default case in case we're using a bit mask.
} else {
@@ -5969,9 +5970,8 @@ static bool SwitchToLookupTable(SwitchInst *SI,
IRBuilder<> &Builder,
TableIndex, ConstantInt::get(MinCaseVal->getType(), TableSize));
RangeCheckBranch =
Builder.CreateCondBr(Cmp, LookupBB, SI->getDefaultDest());
-Updates.push_back({DominatorTree::Insert, SI->getParent(), LookupBB});
-Updates.push_back(
-{DominatorTree::Insert, SI->getParent(), SI->getDefaultDest()});
+Updates.push_back({DominatorTree::Insert, BB, LookupBB});
+Updates.push_back({DominatorTree::Insert, BB, SI->getDefaultDest()});
}
// Populate the BB that does the lookups.
@@ -6012,16 +6012,15 @@ static bool SwitchToLookupTable(SwitchInst *SI,
IRBuilder<> &Builder,
Updates.push_back({DominatorTree::Insert, MaskBB, LookupBB});
Updates.push_back({DominatorTree::Insert, MaskBB, SI->getDefaultDest()});
Builder.SetInsertPoint(LookupBB);
-AddPredecessorToBlock(SI->getDefaultDest(), MaskBB, SI->getParent());
+AddPredecessorToBlock(SI->getDefaultDest(), MaskBB, BB);
}
if (!DefaultIsReachable || GeneratingCoveredLookupTable) {
// We cached PHINodes in PHIs. To avoid accessing deleted PHINodes later,
// do not delete PHINodes here.
-SI->getDefaultDest()->removePredecessor(SI->getParent(),
+SI->getDefaultDest()->removePredecessor(BB,
/*KeepOneInputPHIs=*/true);
-Updates.push_back(
-{DominatorTree::Delete, SI->getParent(), SI->getDefaultDest()});
+Updates.push_back({DominatorTree::Delete, BB, SI->getDefaultDest()});
}
bool ReturnedEarly = false;
@@ -6069,8 +6068,8 @@ static bool SwitchToLookupTable(SwitchInst *SI,
IRBuilder<> &Builder,
if (Succ == SI->getDefaultDest())
continue;
-Succ->removePredecessor(SI->getParent());
-Updates.push_back({DominatorTree::Delete, SI->getParent(), Succ});
+Succ->removePredecessor(BB);
+Updates.push_back({DominatorTree::Delete, BB, Succ});
}
SI->eraseFromParent();
if (DTU)
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[llvm-branch-commits] [llvm] 2b437fc - [SimplifyCFG] SwitchToLookupTable(): switch to non-permissive DomTree updates
Author: Roman Lebedev
Date: 2021-01-06T01:52:38+03:00
New Revision: 2b437fcd479befb96bd61e71c4de8143bd861a48
URL:
https://github.com/llvm/llvm-project/commit/2b437fcd479befb96bd61e71c4de8143bd861a48
DIFF:
https://github.com/llvm/llvm-project/commit/2b437fcd479befb96bd61e71c4de8143bd861a48.diff
LOG: [SimplifyCFG] SwitchToLookupTable(): switch to non-permissive DomTree
updates
... which requires not deleting a DomTree edge that we just deleted.
Added:
Modified:
llvm/lib/Transforms/Utils/SimplifyCFG.cpp
Removed:
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index dc931557ebb6..a433d04f2422 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -5827,7 +5827,6 @@ static void reuseTableCompare(
/// If the switch is only used to initialize one or more phi nodes in a common
/// successor block with
diff erent constant values, replace the switch with
/// lookup tables.
-// FIXME: switch to non-permissive DomTreeUpdater::applyUpdates().
static bool SwitchToLookupTable(SwitchInst *SI, IRBuilder<> &Builder,
DomTreeUpdater *DTU, const DataLayout &DL,
const TargetTransformInfo &TTI) {
@@ -6063,17 +6062,22 @@ static bool SwitchToLookupTable(SwitchInst *SI,
IRBuilder<> &Builder,
}
// Remove the switch.
+ SmallSetVector RemovedSuccessors;
for (unsigned i = 0, e = SI->getNumSuccessors(); i < e; ++i) {
BasicBlock *Succ = SI->getSuccessor(i);
if (Succ == SI->getDefaultDest())
continue;
Succ->removePredecessor(BB);
-Updates.push_back({DominatorTree::Delete, BB, Succ});
+RemovedSuccessors.insert(Succ);
}
SI->eraseFromParent();
- if (DTU)
-DTU->applyUpdatesPermissive(Updates);
+
+ if (DTU) {
+for (BasicBlock *RemovedSuccessor : RemovedSuccessors)
+ Updates.push_back({DominatorTree::Delete, BB, RemovedSuccessor});
+DTU->applyUpdates(Updates);
+ }
++NumLookupTables;
if (NeedMask)
___
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[llvm-branch-commits] [llvm] 0a87e53 - [NFC][SimplifyCFG] Add a test where SimplifyEqualityComparisonWithOnlyPredecessor() deletes existing edge
Author: Roman Lebedev
Date: 2021-01-06T01:52:39+03:00
New Revision: 0a87e53fc40ffd644139cdd210e7c382dbe329c8
URL:
https://github.com/llvm/llvm-project/commit/0a87e53fc40ffd644139cdd210e7c382dbe329c8
DIFF:
https://github.com/llvm/llvm-project/commit/0a87e53fc40ffd644139cdd210e7c382dbe329c8.diff
LOG: [NFC][SimplifyCFG] Add a test where
SimplifyEqualityComparisonWithOnlyPredecessor() deletes existing edge
Added:
llvm/test/Transforms/SimplifyCFG/SimplifyEqualityComparisonWithOnlyPredecessor-domtree-preservation-edgecase.ll
Modified:
Removed:
diff --git
a/llvm/test/Transforms/SimplifyCFG/SimplifyEqualityComparisonWithOnlyPredecessor-domtree-preservation-edgecase.ll
b/llvm/test/Transforms/SimplifyCFG/SimplifyEqualityComparisonWithOnlyPredecessor-domtree-preservation-edgecase.ll
new file mode 100644
index ..d6b9ea7f52c7
--- /dev/null
+++
b/llvm/test/Transforms/SimplifyCFG/SimplifyEqualityComparisonWithOnlyPredecessor-domtree-preservation-edgecase.ll
@@ -0,0 +1,51 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=0 < %s |
FileCheck %s
+
+declare void @zzz()
+
+define i32 @lex(i1 %c0, i1 %c1, i32 %r0, i32 %r1, i32 %v) {
+; CHECK-LABEL: @lex(
+; CHECK-NEXT: entry:
+; CHECK-NEXT:[[C0_NOT:%.*]] = xor i1 [[C0:%.*]], true
+; CHECK-NEXT:[[C1_NOT:%.*]] = xor i1 [[C1:%.*]], true
+; CHECK-NEXT:[[BRMERGE:%.*]] = or i1 [[C0_NOT]], [[C1_NOT]]
+; CHECK-NEXT:[[R0_MUX:%.*]] = select i1 [[C0_NOT]], i32 [[R0:%.*]], i32
[[R1:%.*]]
+; CHECK-NEXT:br i1 [[BRMERGE]], label [[IF_THEN:%.*]], label
[[DO_BODY:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT:[[MERGE:%.*]] = phi i32 [ [[R0_MUX]], [[ENTRY:%.*]] ], [
[[R1]], [[DO_BODY]] ]
+; CHECK-NEXT:ret i32 [[MERGE]]
+; CHECK: do.body:
+; CHECK-NEXT:call void @zzz()
+; CHECK-NEXT:switch i32 [[V:%.*]], label [[IF_THEN]] [
+; CHECK-NEXT:i32 10, label [[DO_BODY]]
+; CHECK-NEXT:i32 32, label [[DO_BODY]]
+; CHECK-NEXT:i32 9, label [[DO_BODY]]
+; CHECK-NEXT:]
+;
+entry:
+ br i1 %c0, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ ret i32 %r0
+
+if.end: ; preds = %entry
+ br i1 %c1, label %do.body, label %do.end
+
+do.body: ; preds = %if.then193,
%if.then193, %if.then193, %do.body, %do.body, %if.end
+ call void @zzz()
+ switch i32 %v, label %do.end [
+ i32 10, label %if.then193
+ i32 32, label %do.body
+ i32 9, label %do.body
+ ]
+
+if.then193: ; preds = %do.body
+ switch i32 %v, label %do.end [
+ i32 32, label %do.body
+ i32 10, label %do.body
+ i32 9, label %do.body
+ ]
+
+do.end: ; preds = %if.then193,
%do.body, %if.end
+ ret i32 %r1
+}
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[llvm-branch-commits] [llvm] a14945c - [SimplifyCFG] SimplifyEqualityComparisonWithOnlyPredecessor(): really don't delete DomTree edges multiple times
Author: Roman Lebedev
Date: 2021-01-06T01:52:39+03:00
New Revision: a14945c1db614261a6f8d5d199e246d78f51e977
URL:
https://github.com/llvm/llvm-project/commit/a14945c1db614261a6f8d5d199e246d78f51e977
DIFF:
https://github.com/llvm/llvm-project/commit/a14945c1db614261a6f8d5d199e246d78f51e977.diff
LOG: [SimplifyCFG] SimplifyEqualityComparisonWithOnlyPredecessor(): really
don't delete DomTree edges multiple times
Added:
Modified:
llvm/lib/Transforms/Utils/SimplifyCFG.cpp
llvm/test/Transforms/SimplifyCFG/SimplifyEqualityComparisonWithOnlyPredecessor-domtree-preservation-edgecase.ll
Removed:
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index a433d04f2422..3fbc22a85be4 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -994,7 +994,8 @@ bool
SimplifyCFGOpt::SimplifyEqualityComparisonWithOnlyPredecessor(
BasicBlock *CheckEdge = TheRealDest;
for (BasicBlock *Succ : successors(TIBB))
if (Succ != CheckEdge) {
- RemovedSuccs.insert(Succ);
+ if (Succ != TheRealDest)
+RemovedSuccs.insert(Succ);
Succ->removePredecessor(TIBB);
} else
CheckEdge = nullptr;
diff --git
a/llvm/test/Transforms/SimplifyCFG/SimplifyEqualityComparisonWithOnlyPredecessor-domtree-preservation-edgecase.ll
b/llvm/test/Transforms/SimplifyCFG/SimplifyEqualityComparisonWithOnlyPredecessor-domtree-preservation-edgecase.ll
index d6b9ea7f52c7..617cd062652e 100644
---
a/llvm/test/Transforms/SimplifyCFG/SimplifyEqualityComparisonWithOnlyPredecessor-domtree-preservation-edgecase.ll
+++
b/llvm/test/Transforms/SimplifyCFG/SimplifyEqualityComparisonWithOnlyPredecessor-domtree-preservation-edgecase.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=0 < %s |
FileCheck %s
+; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s |
FileCheck %s
declare void @zzz()
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[llvm-branch-commits] [mlir] 8b124c1 - [mlir][sparse] adjust output shape inference to new tensor abstraction
Author: Aart Bik
Date: 2021-01-05T15:31:39-08:00
New Revision: 8b124c19f52cb8ed0236b602df56787553e1e1b6
URL:
https://github.com/llvm/llvm-project/commit/8b124c19f52cb8ed0236b602df56787553e1e1b6
DIFF:
https://github.com/llvm/llvm-project/commit/8b124c19f52cb8ed0236b602df56787553e1e1b6.diff
LOG: [mlir][sparse] adjust output shape inference to new tensor abstraction
Nicolas changed the tensor abstraction so that every output has
its own shape definition. This simplifies the "inference" that
was used in the sparse compiler.
Reviewed By: penpornk
Differential Revision: https://reviews.llvm.org/D94119
Added:
Modified:
mlir/lib/Dialect/Linalg/Transforms/Sparsification.cpp
mlir/test/Dialect/Linalg/sparse_2d.mlir
Removed:
diff --git a/mlir/lib/Dialect/Linalg/Transforms/Sparsification.cpp
b/mlir/lib/Dialect/Linalg/Transforms/Sparsification.cpp
index a6b7277e47e3..ed81d5e24805 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/Sparsification.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/Sparsification.cpp
@@ -538,15 +538,8 @@ static void genBuffers(Merger &merger, CodeGen &codegen,
// Find lower and upper bound in current dimension.
Value up;
if (shape[d] == TensorType::kDynamicSize) {
-// For the output tensor, we may need to infer the upper bound.
-// For all others, we look at the incoming argument.
-if (t == numInputs && !op.getNumInitTensors()) {
- up = codegen.sizes[i];
- assert(up); // TODO: what else?
-} else {
- Value arg = t < numInputs ? op.getInput(t) : op.getInitTensors()[0];
- up = rewriter.create(loc, arg, d);
-}
+Value arg = t < numInputs ? op.getInput(t) : op.getOutput(0);
+up = rewriter.create(loc, arg, d);
args.push_back(up);
} else {
up = rewriter.create(loc, shape[d]);
diff --git a/mlir/test/Dialect/Linalg/sparse_2d.mlir
b/mlir/test/Dialect/Linalg/sparse_2d.mlir
index 6612a723f23d..9bb68ca91089 100644
--- a/mlir/test/Dialect/Linalg/sparse_2d.mlir
+++ b/mlir/test/Dialect/Linalg/sparse_2d.mlir
@@ -1139,19 +1139,19 @@ func @sum_reduction(%arga: tensor<10x20xf32>, %argx:
tensor) -> tensor
// CHECK: %[[VAL_2:.*]] = constant 999 : index
// CHECK: %[[VAL_3:.*]] = constant 0 : index
// CHECK: %[[VAL_4:.*]] = constant 1 : index
-// CHECK: %[[VAL_5:.*]] = dim %[[VAL_0]], %[[VAL_3]] :
tensor
+// CHECK: %[[VAL_5:.*]] = alloca(%[[VAL_2]]) : memref
// CHECK: %[[VAL_6:.*]] = alloca(%[[VAL_2]]) : memref
-// CHECK: %[[VAL_7:.*]] = alloca(%[[VAL_2]]) : memref
-// CHECK: %[[VAL_8:.*]] = dim %[[VAL_0]], %[[VAL_4]] :
tensor
-// CHECK: %[[VAL_9:.*]] = alloca(%[[VAL_2]]) : memref
-// CHECK: %[[VAL_10:.*]] = alloca(%[[VAL_5]], %[[VAL_8]]) :
memref
-// CHECK: scf.for %[[VAL_11:.*]] = %[[VAL_3]] to %[[VAL_5]] step
%[[VAL_4]] {
-// CHECK: %[[VAL_12:.*]] = load %[[VAL_6]]{{\[}}%[[VAL_11]]] :
memref
+// CHECK: %[[VAL_7:.*]] = alloca(%[[VAL_2]]) : memref
+// CHECK: %[[VAL_8:.*]] = dim %[[VAL_0]], %[[VAL_3]] :
tensor
+// CHECK: %[[VAL_9:.*]] = dim %[[VAL_0]], %[[VAL_4]] :
tensor
+// CHECK: %[[VAL_10:.*]] = alloca(%[[VAL_8]], %[[VAL_9]]) :
memref
+// CHECK: scf.for %[[VAL_11:.*]] = %[[VAL_3]] to %[[VAL_8]] step
%[[VAL_4]] {
+// CHECK: %[[VAL_12:.*]] = load %[[VAL_5]]{{\[}}%[[VAL_11]]] :
memref
// CHECK: %[[VAL_13:.*]] = addi %[[VAL_11]], %[[VAL_4]] : index
-// CHECK: %[[VAL_14:.*]] = load %[[VAL_6]]{{\[}}%[[VAL_13]]] :
memref
+// CHECK: %[[VAL_14:.*]] = load %[[VAL_5]]{{\[}}%[[VAL_13]]] :
memref
// CHECK: scf.for %[[VAL_15:.*]] = %[[VAL_12]] to %[[VAL_14]] step
%[[VAL_4]] {
-// CHECK: %[[VAL_16:.*]] = load %[[VAL_7]]{{\[}}%[[VAL_15]]] :
memref
-// CHECK: %[[VAL_17:.*]] = load %[[VAL_9]]{{\[}}%[[VAL_15]]] :
memref
+// CHECK: %[[VAL_16:.*]] = load %[[VAL_6]]{{\[}}%[[VAL_15]]] :
memref
+// CHECK: %[[VAL_17:.*]] = load %[[VAL_7]]{{\[}}%[[VAL_15]]] :
memref
// CHECK: %[[VAL_18:.*]] = mulf %[[VAL_17]], %[[VAL_1]] : f64
// CHECK: store %[[VAL_18]], %[[VAL_10]]{{\[}}%[[VAL_11]],
%[[VAL_16]]] : memref
// CHECK: }
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[llvm-branch-commits] [clang] b12e473 - Allow dependent alias template specializations in the preferred_name
Author: Richard Smith
Date: 2021-01-05T15:33:51-08:00
New Revision: b12e4735317ec96e1b35deee68b90d62a23a9353
URL:
https://github.com/llvm/llvm-project/commit/b12e4735317ec96e1b35deee68b90d62a23a9353
DIFF:
https://github.com/llvm/llvm-project/commit/b12e4735317ec96e1b35deee68b90d62a23a9353.diff
LOG: Allow dependent alias template specializations in the preferred_name
attribute.
This was intended to work, but didn't match the checks because these
types are modeled as TemplateSpecializationTypes not TypedefTypes.
Added:
Modified:
clang/include/clang/AST/Type.h
clang/lib/AST/TypePrinter.cpp
clang/lib/Sema/SemaDeclAttr.cpp
clang/test/SemaTemplate/attributes.cpp
Removed:
diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index 684005c4876d..143a05cba6ad 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -2093,6 +2093,7 @@ class alignas(8) Type : public ExtQualsTypeCommonBase {
bool isAtomicType() const;// C11 _Atomic()
bool isUndeducedAutoType() const; // C++11 auto or
// C++14 decltype(auto)
+ bool isTypedefNameType() const; // typedef or alias template
#define IMAGE_TYPE(ImgType, Id, SingletonId, Access, Suffix) \
bool is##Id##Type() const;
@@ -7066,6 +7067,15 @@ inline bool Type::isOverloadableType() const {
return isDependentType() || isRecordType() || isEnumeralType();
}
+/// Determines whether this type is written as a typedef-name.
+inline bool Type::isTypedefNameType() const {
+ if (getAs())
+return true;
+ if (auto *TST = getAs())
+return TST->isTypeAlias();
+ return false;
+}
+
/// Determines whether this type can decay to a pointer type.
inline bool Type::canDecayToPointerType() const {
return isFunctionType() || isArrayType();
diff --git a/clang/lib/AST/TypePrinter.cpp b/clang/lib/AST/TypePrinter.cpp
index 54c451291a07..d1882ac1a3b3 100644
--- a/clang/lib/AST/TypePrinter.cpp
+++ b/clang/lib/AST/TypePrinter.cpp
@@ -116,6 +116,8 @@ namespace {
static bool canPrefixQualifiers(const Type *T, bool
&NeedARCStrongQualifier);
void spaceBeforePlaceHolder(raw_ostream &OS);
void printTypeSpec(NamedDecl *D, raw_ostream &OS);
+void printTemplateId(const TemplateSpecializationType *T, raw_ostream &OS,
+ bool FullyQualify);
void printBefore(QualType T, raw_ostream &OS);
void printAfter(QualType T, raw_ostream &OS);
@@ -1352,9 +1354,17 @@ void TypePrinter::printRecordBefore(const RecordType *T,
raw_ostream &OS) {
// Print the preferred name if we have one for this type.
for (const auto *PNA : T->getDecl()->specific_attrs()) {
if (declaresSameEntity(PNA->getTypedefType()->getAsCXXRecordDecl(),
- T->getDecl()))
- return printTypeSpec(
- PNA->getTypedefType()->castAs()->getDecl(), OS);
+ T->getDecl())) {
+ // Find the outermost typedef or alias template.
+ QualType T = PNA->getTypedefType();
+ while (true) {
+if (auto *TT = dyn_cast(T))
+ return printTypeSpec(TT->getDecl(), OS);
+if (auto *TST = dyn_cast(T))
+ return printTemplateId(TST, OS, /*FullyQualify=*/true);
+T = T->getLocallyUnqualifiedSingleStepDesugaredType();
+ }
+}
}
printTag(T->getDecl(), OS);
@@ -1416,20 +1426,32 @@ void TypePrinter::printSubstTemplateTypeParmPackAfter(
printTemplateTypeParmAfter(T->getReplacedParameter(), OS);
}
-void TypePrinter::printTemplateSpecializationBefore(
-const TemplateSpecializationType
*T,
-raw_ostream &OS) {
+void TypePrinter::printTemplateId(const TemplateSpecializationType *T,
+ raw_ostream &OS, bool FullyQualify) {
IncludeStrongLifetimeRAII Strong(Policy);
- T->getTemplateName().print(OS, Policy);
- const TemplateParameterList *TPL = nullptr;
- if (TemplateDecl *TD = T->getTemplateName().getAsTemplateDecl())
-TPL = TD->getTemplateParameters();
+ TemplateDecl *TD = T->getTemplateName().getAsTemplateDecl();
+ if (FullyQualify && TD) {
+if (!Policy.SuppressScope)
+ AppendScope(TD->getDeclContext(), OS, TD->getDeclName());
+
+IdentifierInfo *II = TD->getIdentifier();
+OS << II->getName();
+ } else {
+T->getTemplateName().print(OS, Policy);
+ }
+ const TemplateParameterList *TPL = TD ? TD->getTemplateParameters() :
nullptr;
printTemplateArgumentList(OS, T->template_arguments(), Policy, TPL);
spaceBeforePlaceHolder(OS);
}
+void TypePrinter::printTemplateSpecializationBefore(
+const TemplateSpecializationType
*T,
+raw_ostream &OS) {
+ printTemplateId(T,
[llvm-branch-commits] [mlir] cbda2cb - [mlir] Fully specify removeAttr return type
Author: Tres Popp
Date: 2021-01-06T00:52:35+01:00
New Revision: cbda2cba4f8e4d236d56158cecfb008e03341a70
URL:
https://github.com/llvm/llvm-project/commit/cbda2cba4f8e4d236d56158cecfb008e03341a70
DIFF:
https://github.com/llvm/llvm-project/commit/cbda2cba4f8e4d236d56158cecfb008e03341a70.diff
LOG: [mlir] Fully specify removeAttr return type
This was added without full specification like other generated methods.
This then leads to other downstream dialects failing to compile the
generated code when they are not in the mlir namespace.
Differential Revision: https://reviews.llvm.org/D94132
Added:
Modified:
mlir/test/mlir-tblgen/op-attribute.td
mlir/test/mlir-tblgen/op-decl.td
mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
Removed:
diff --git a/mlir/test/mlir-tblgen/op-attribute.td
b/mlir/test/mlir-tblgen/op-attribute.td
index b4c193c30c51..2f1d44016b62 100644
--- a/mlir/test/mlir-tblgen/op-attribute.td
+++ b/mlir/test/mlir-tblgen/op-attribute.td
@@ -80,7 +80,7 @@ def AOp : NS_Op<"a_op", []> {
// Test remove methods
// ---
-// DEF: Attribute AOp::removeCAttrAttr() {
+// DEF: ::mlir::Attribute AOp::removeCAttrAttr() {
// DEF-NEXT: return (*this)->removeAttr("cAttr");
// Test build methods
@@ -271,7 +271,7 @@ def UnitAttrOp : NS_Op<"unit_attr_op", []> {
// DEF: bool UnitAttrOp::attr() {
// DEF: return {{.*}} != nullptr
-// DEF: Attribute UnitAttrOp::removeAttrAttr() {
+// DEF: ::mlir::Attribute UnitAttrOp::removeAttrAttr() {
// DEF-NEXT: (*this)->removeAttr("attr");
// DEF: build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState,
/*optional*/::mlir::UnitAttr attr)
@@ -288,7 +288,7 @@ def SomeTypedArrayAttr : TypedArrayAttrBase;
def Test_Dialect_2 : Dialect {
let name = "dialect_2";
}
-def MyStruct : StructAttr<"MyStruct", Test_Dialect_2,
+def MyStruct : StructAttr<"MyStruct", Test_Dialect_2,
[StructFieldAttr<"potatoes", I64ElementsAttr>]> {
let description = "A structure describing a number of potatoes.";
}
diff --git a/mlir/test/mlir-tblgen/op-decl.td
b/mlir/test/mlir-tblgen/op-decl.td
index d4d1a8b012c6..3d4d46ceb42f 100644
--- a/mlir/test/mlir-tblgen/op-decl.td
+++ b/mlir/test/mlir-tblgen/op-decl.td
@@ -81,7 +81,7 @@ def NS_AOp : NS_Op<"a_op", [IsolatedFromAbove,
IsolatedFromAbove]> {
// CHECK: uint32_t attr1();
// CHECK: ::mlir::FloatAttr attr2Attr()
// CHECK: ::llvm::Optional< ::llvm::APFloat > attr2();
-// CHECK: Attribute removeAttr2Attr();
+// CHECK: ::mlir::Attribute removeAttr2Attr();
// CHECK: static void build(::mlir::OpBuilder &odsBuilder,
::mlir::OperationState &odsState, Value val);
// CHECK: static void build(::mlir::OpBuilder &odsBuilder,
::mlir::OperationState &odsState, int integer = 0);
// CHECK: static void build(::mlir::OpBuilder &odsBuilder,
::mlir::OperationState &odsState, ::mlir::Type r, ::mlir::TypeRange s,
::mlir::Value a, ::mlir::ValueRange b, ::mlir::IntegerAttr attr1,
/*optional*/::mlir::FloatAttr attr2, unsigned someRegionsCount)
diff --git a/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
b/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
index 468fd7848d82..b1c86522c6b5 100644
--- a/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
+++ b/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
@@ -788,7 +788,7 @@ void OpEmitter::genOptionalAttrRemovers() {
auto upperInitial = name.take_front().upper();
auto suffix = name.drop_front();
auto *method = opClass.addMethodAndPrune(
-"Attribute", ("remove" + upperInitial + suffix + "Attr").str());
+"::mlir::Attribute", ("remove" + upperInitial + suffix +
"Attr").str());
if (!method)
return;
auto &body = method->body();
___
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[llvm-branch-commits] [openmp] dec0290 - [libomptarget] Allow calls to omp_target_memcpy with 0 size.
Author: George Rokos
Date: 2021-01-05T16:03:53-08:00
New Revision: dec02904d2675a14cd9c7b5a306d3f4f85c2abca
URL:
https://github.com/llvm/llvm-project/commit/dec02904d2675a14cd9c7b5a306d3f4f85c2abca
DIFF:
https://github.com/llvm/llvm-project/commit/dec02904d2675a14cd9c7b5a306d3f4f85c2abca.diff
LOG: [libomptarget] Allow calls to omp_target_memcpy with 0 size.
Differential Revision: https://reviews.llvm.org/D94095
Added:
Modified:
openmp/libomptarget/src/api.cpp
Removed:
diff --git a/openmp/libomptarget/src/api.cpp b/openmp/libomptarget/src/api.cpp
index 58f7cec2fdd6..2d376109308b 100644
--- a/openmp/libomptarget/src/api.cpp
+++ b/openmp/libomptarget/src/api.cpp
@@ -137,6 +137,11 @@ EXTERN int omp_target_memcpy(void *dst, void *src, size_t
length,
DPxPTR(src), dst_offset, src_offset, length);
if (!dst || !src || length <= 0) {
+if (length == 0) {
+ DP("Call to omp_target_memcpy with zero length, nothing to do\n");
+ return OFFLOAD_SUCCESS;
+}
+
REPORT("Call to omp_target_memcpy with invalid arguments\n");
return OFFLOAD_FAIL;
}
___
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[llvm-branch-commits] [compiler-rt] b7718b6 - Reland D93848 "[sanitizer] Define SANITIZER_GLIBC to refine SANITIZER_LINUX feature detection and support musl""
Author: Fangrui Song Date: 2021-01-05T16:18:43-08:00 New Revision: b7718b617557aa9827f994a16267537236634095 URL: https://github.com/llvm/llvm-project/commit/b7718b617557aa9827f994a16267537236634095 DIFF: https://github.com/llvm/llvm-project/commit/b7718b617557aa9827f994a16267537236634095.diff LOG: Reland D93848 "[sanitizer] Define SANITIZER_GLIBC to refine SANITIZER_LINUX feature detection and support musl"" Several `#if SANITIZER_LINUX && !SANITIZER_ANDROID` guards are replaced with the more appropriate `#if SANITIZER_GLIBC` (the headers are glibc extensions, not specific to Linux (i.e. if we ever support GNU/kFreeBSD or Hurd, the guards may automatically work)). Several `#if SANITIZER_LINUX && !SANITIZER_ANDROID` guards are refined with `#if SANITIZER_GLIBC` (the definitions are available on Linux glibc, but may not be available on other libc (e.g. musl) implementations). This patch makes `ninja asan cfi msan stats tsan ubsan xray` build on a musl based Linux distribution (apk install musl-libintl) Notes about disabled interceptors for musl: * `SANITIZER_INTERCEPT_GLOB`: musl does not implement `GLOB_ALTDIRFUNC` (GNU extension) * Some ioctl structs and functions operating on them. * `SANITIZER_INTERCEPT___PRINTF_CHK`: `_FORTIFY_SOURCE` functions are GNU extension * `SANITIZER_INTERCEPT___STRNDUP`: `dlsym(RTLD_NEXT, "__strndup")` errors so a diagnostic is formed. The diagnostic uses `write` which hasn't been intercepted => SIGSEGV * `SANITIZER_INTERCEPT_*64`: the `_LARGEFILE64_SOURCE` functions are glibc specific. musl does something like `#define pread64 pread` * Disabled `msg_iovlen msg_controllen cmsg_len` checks: musl is conforming while many implementations (Linux/FreeBSD/NetBSD/Solaris) are non-conforming. Since we pick the glibc definition, exclude the checks for musl (incompatible sizes but compatible offsets) Pass through LIBCXX_HAS_MUSL_LIBC to make check-msan/check-tsan able to build libc++ (https://bugs.llvm.org/show_bug.cgi?id=48618). Many sanitizer features are available now. ``` % ninja check-asan (known issues: * ASAN_OPTIONS=fast_unwind_on_malloc=0 odr-violations hangs ) ... Testing Time: 53.69s Unsupported : 185 Passed : 512 Expectedly Failed: 1 Failed : 12 % ninja check-ubsan check-ubsan-minimal check-memprof # all passed % ninja check-cfi ( all cross-dso/) ... Testing Time: 8.68s Unsupported : 264 Passed : 80 Expectedly Failed: 8 Failed : 32 % ninja check-lsan (With GetTls (D93972), 10 failures) Testing Time: 4.09s Unsupported: 7 Passed : 65 Failed : 22 % ninja check-msan (Many are due to functions not marked unsupported.) Testing Time: 23.09s Unsupported : 6 Passed : 764 Expectedly Failed: 2 Failed : 58 % ninja check-tsan Testing Time: 23.21s Unsupported : 86 Passed : 295 Expectedly Failed: 1 Failed : 25 ``` Used `ASAN_OPTIONS=verbosity=2` to verify there is no unneeded interceptor. Partly based on Jari Ronkainen's https://reviews.llvm.org/D63785#1921014 Reviewed By: vitalybuka Differential Revision: https://reviews.llvm.org/D93848 Added: Modified: compiler-rt/cmake/Modules/AddCompilerRT.cmake compiler-rt/lib/asan/asan_interceptors.h compiler-rt/lib/asan/tests/asan_test.cpp compiler-rt/lib/interception/interception_linux.cpp compiler-rt/lib/interception/interception_linux.h compiler-rt/lib/msan/tests/msan_test.cpp compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors_ioctl.inc compiler-rt/lib/sanitizer_common/sanitizer_linux_libcdep.cpp compiler-rt/lib/sanitizer_common/sanitizer_platform.h compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.cpp compiler-rt/lib/sanitizer_common/sanitizer_platform_limits_posix.h compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp Removed: diff --git a/compiler-rt/cmake/Modules/AddCompilerRT.cmake b/compiler-rt/cmake/Modules/AddCompilerRT.cmake index 0b8db6a868a1..361538a58e47 100644 --- a/compiler-rt/cmake/Modules/AddCompilerRT.cmake +++ b/compiler-rt/cmake/Modules/AddCompilerRT.cmake @@ -583,6 +583,7 @@ macro(add_custom_libcxx name prefix) CMAKE_OBJDUMP CMAKE_STRIP CMAKE_SYSROOT +LIBCXX_HAS_MUSL_LIBC PYTHON_EXECUTABLE Python3_EXECUTABLE Python2_EXECUTABLE diff --git a/compiler-rt/lib/asan/asan_interceptors.h b/compiler-rt/lib/asan/asan_interceptors.h index 4266a31cecb9..45cdb80b1b64 100644 --- a/compiler-rt/lib/asan/asan_interceptors.h +++ b/compiler-rt/lib/asan/asan_interceptors.h @@ -60,7 +60,7 @@ void InitializePlatformInterceptors(); # define ASAN_USE_ALIAS_ATTRIBUTE_FOR_INDEX 0 #endif -#if (SANITIZER_LINUX && !SANITIZER_ANDROID) || SANITIZER_SOLARIS +#if SANITIZER_GLIBC || SANI
[llvm-branch-commits] [llvm] ad18b07 - DebugInfo: Add support for always using ranges (rather than low/high pc) in DWARFv5
Author: David Blaikie
Date: 2021-01-05T16:36:22-08:00
New Revision: ad18b075fd63935148b460f9c6b4dce130c56b15
URL:
https://github.com/llvm/llvm-project/commit/ad18b075fd63935148b460f9c6b4dce130c56b15
DIFF:
https://github.com/llvm/llvm-project/commit/ad18b075fd63935148b460f9c6b4dce130c56b15.diff
LOG: DebugInfo: Add support for always using ranges (rather than low/high pc)
in DWARFv5
Given the ability provided by DWARFv5 rnglists to reuse addresses in the
address pool, it can be advantageous to object file size to use range
encodings even when the range could be described by a direct low/high
pc.
Add a flag to allow enabling this in DWARFv5 for the purpose of
experimentation/data gathering.
It might be that it makes sense to enable this functionality by default
for DWARFv5 + Split DWARF at least, where the tradeoff/desire to
optimize for .o file size is more explicit and .o bytes are higher
priority than .dwo bytes.
Added:
llvm/test/DebugInfo/X86/ranges_always.ll
Modified:
llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
Removed:
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
index 7cf2b566ede8..02791f2280d2 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
@@ -558,7 +558,12 @@ void DwarfCompileUnit::addScopeRangeList(DIE &ScopeDIE,
void DwarfCompileUnit::attachRangesOrLowHighPC(
DIE &Die, SmallVector Ranges) {
- if (Ranges.size() == 1 || !DD->useRangesSection()) {
+ assert(!Ranges.empty());
+ if (!DD->useRangesSection() ||
+ (Ranges.size() == 1 &&
+ (!DD->alwaysUseRanges() ||
+DD->getSectionLabel(&Ranges.front().Begin->getSection()) ==
+Ranges.front().Begin))) {
const RangeSpan &Front = Ranges.front();
const RangeSpan &Back = Ranges.back();
attachLowHighPC(Die, Front.Begin, Back.End);
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
index b790434576cb..fa5d55071e17 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
@@ -151,6 +151,14 @@ static cl::opt
"Abstract subprograms")),
cl::init(DefaultLinkageNames));
+static cl::opt AlwaysUseRangesInV5(
+"always-use-ranges-in-v5", cl::Hidden,
+cl::desc("Always use DW_AT_ranges in DWARFv5 whenever it could allow more "
+ "address pool entry sharing to reduce relocations/object size"),
+cl::values(clEnumVal(Default, "Default for platform"),
+ clEnumVal(Enable, "Enabled"), clEnumVal(Disable, "Disabled")),
+cl::init(Default));
+
static constexpr unsigned ULEB128PadSize = 4;
void DebugLocDwarfExpression::emitOp(uint8_t Op, const char *Comment) {
@@ -422,6 +430,19 @@ DwarfDebug::DwarfDebug(AsmPrinter *A)
else
EnableOpConvert = (DwarfOpConvert == Enable);
+ // Split DWARF would benefit object size significantly by trading reductions
+ // in address pool usage for slightly increased range list encodings.
+ if (DwarfVersion >= 5) {
+if (AlwaysUseRangesInV5 == Default) {
+ // FIXME: In the future, enable this by default for Split DWARF where the
+ // tradeoff is more pronounced due to being able to offload the range
+ // lists to the dwo file and shrink object files/reduce relocations
there.
+ AlwaysUseRanges = false;
+} else {
+ AlwaysUseRanges = AlwaysUseRangesInV5 == Enable;
+}
+ }
+
Asm->OutStreamer->getContext().setDwarfVersion(DwarfVersion);
Asm->OutStreamer->getContext().setDwarfFormat(Dwarf64 ? dwarf::DWARF64
: dwarf::DWARF32);
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
index 502aef481a3a..b3b8e62fb5d9 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
@@ -378,6 +378,9 @@ class DwarfDebug : public DebugHandlerBase {
/// Avoid using DW_OP_convert due to consumer incompatibilities.
bool EnableOpConvert;
+ /// Force the use of DW_AT_ranges even for single-entry range lists.
+ bool AlwaysUseRanges = false;
+
/// DWARF5 Experimental Options
/// @{
AccelTableKind TheAccelTableKind;
@@ -689,6 +692,10 @@ class DwarfDebug : public DebugHandlerBase {
/// Returns whether ranges section should be emitted.
bool useRangesSection() const { return UseRangesSection; }
+ /// Returns whether range encodings should be used for single entry range
+ /// lists.
+ bool alwaysUseRanges() const { return AlwaysUseRanges; }
+
/// Returns whether to use sections as labels rather than temp symbols.
bool useSectionsAsReferences() const {
[llvm-branch-commits] [lldb] a39b198 - Make DWARFUnit use the dwo_id from the DWARF5 CU header.
Author: Jorge Gorbe Moya
Date: 2021-01-05T16:40:37-08:00
New Revision: a39b19821b6b8c6b4ae853f6b6a88128275ea2c7
URL:
https://github.com/llvm/llvm-project/commit/a39b19821b6b8c6b4ae853f6b6a88128275ea2c7
DIFF:
https://github.com/llvm/llvm-project/commit/a39b19821b6b8c6b4ae853f6b6a88128275ea2c7.diff
LOG: Make DWARFUnit use the dwo_id from the DWARF5 CU header.
In split DWARF v5 files, the DWO id is no longer in the DW_AT_GNU_dwo_id
attribute. It's in the CU header instead. This change makes lldb look in
both places.
Differential Revision: https://reviews.llvm.org/D93444
Added:
lldb/test/Shell/SymbolFile/DWARF/dwarf5-split.s
Modified:
lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp
Removed:
diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
b/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
index d0cfb5fca82f..a761dd3daac4 100644
--- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
+++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
@@ -34,7 +34,8 @@ DWARFUnit::DWARFUnit(SymbolFileDWARF &dwarf, lldb::user_id_t
uid,
const DWARFAbbreviationDeclarationSet &abbrevs,
DIERef::Section section, bool is_dwo)
: UserID(uid), m_dwarf(dwarf), m_header(header), m_abbrevs(&abbrevs),
- m_cancel_scopes(false), m_section(section), m_is_dwo(is_dwo) {}
+ m_cancel_scopes(false), m_section(section), m_is_dwo(is_dwo),
+ m_dwo_id(header.GetDWOId()) {}
DWARFUnit::~DWARFUnit() = default;
@@ -284,6 +285,11 @@ void DWARFUnit::SetDwoStrOffsetsBase() {
SetStrOffsetsBase(baseOffset);
}
+uint64_t DWARFUnit::GetDWOId() {
+ ExtractUnitDIEIfNeeded();
+ return m_dwo_id;
+}
+
// m_die_array_mutex must be already held as read/write.
void DWARFUnit::AddUnitDIE(const DWARFDebugInfoEntry &cu_die) {
llvm::Optional addr_base, gnu_addr_base, ranges_base,
@@ -337,6 +343,9 @@ void DWARFUnit::AddUnitDIE(const DWARFDebugInfoEntry
&cu_die) {
case DW_AT_GNU_ranges_base:
gnu_ranges_base = form_value.Unsigned();
break;
+case DW_AT_GNU_dwo_id:
+ m_dwo_id = form_value.Unsigned();
+ break;
}
}
@@ -350,9 +359,8 @@ void DWARFUnit::AddUnitDIE(const DWARFDebugInfoEntry
&cu_die) {
if (!dwo_symbol_file)
return;
- uint64_t main_dwo_id =
- cu_die.GetAttributeValueAsUnsigned(this, DW_AT_GNU_dwo_id, 0);
- DWARFUnit *dwo_cu = dwo_symbol_file->GetDWOCompileUnitForHash(main_dwo_id);
+ DWARFUnit *dwo_cu = dwo_symbol_file->GetDWOCompileUnitForHash(m_dwo_id);
+
if (!dwo_cu)
return; // Can't fetch the compile unit from the dwo file.
dwo_cu->SetUserData(this);
@@ -788,7 +796,8 @@ DWARFUnitHeader::extract(const DWARFDataExtractor &data,
header.m_unit_type = data.GetU8(offset_ptr);
header.m_addr_size = data.GetU8(offset_ptr);
header.m_abbr_offset = data.GetDWARFOffset(offset_ptr);
-if (header.m_unit_type == llvm::dwarf::DW_UT_skeleton)
+if (header.m_unit_type == llvm::dwarf::DW_UT_skeleton ||
+header.m_unit_type == llvm::dwarf::DW_UT_split_compile)
header.m_dwo_id = data.GetU64(offset_ptr);
} else {
header.m_abbr_offset = data.GetDWARFOffset(offset_ptr);
diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
b/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
index d6009518da12..5739c36bbacb 100644
--- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
+++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
@@ -65,6 +65,7 @@ class DWARFUnitHeader {
}
uint64_t GetTypeHash() const { return m_type_hash; }
dw_offset_t GetTypeOffset() const { return m_type_offset; }
+ uint64_t GetDWOId() const { return m_dwo_id; }
bool IsTypeUnit() const {
return m_unit_type == DW_UT_type || m_unit_type == DW_UT_split_type;
}
@@ -88,6 +89,7 @@ class DWARFUnit : public lldb_private::UserID {
virtual ~DWARFUnit();
bool IsDWOUnit() { return m_is_dwo; }
+ uint64_t GetDWOId();
void ExtractUnitDIEIfNeeded();
void ExtractDIEsIfNeeded();
@@ -333,6 +335,8 @@ class DWARFUnit : public lldb_private::UserID {
const DIERef::Section m_section;
bool m_is_dwo;
+ /// Value of DW_AT_GNU_dwo_id (v4) or dwo_id from CU header (v5).
+ uint64_t m_dwo_id;
private:
void ParseProducerInfo();
diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp
b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp
index 3aaa7d330b84..fcb51dfa0e7a 100644
--- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp
+++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp
@@ -49,8 +49,7 @@ DWARFCompileUnit
*SymbolFileDWARFDwo::GetDWOCompileUnitForHash(uint64_t hash) {
DWARFCompileUnit *cu = FindSingleCompileUnit();
if (!cu)
return nullptr;
- if (hash !=
- cu->GetUnitDIEOnly().GetA
[llvm-branch-commits] [compiler-rt] 8b0bd54 - [sanitizer][Darwin] Suppress -Wno-non-virtual-dtor warning
Author: Julian Lettner
Date: 2021-01-05T17:09:18-08:00
New Revision: 8b0bd54d0ec968df28ccc58bbb537a7b7c074ef2
URL:
https://github.com/llvm/llvm-project/commit/8b0bd54d0ec968df28ccc58bbb537a7b7c074ef2
DIFF:
https://github.com/llvm/llvm-project/commit/8b0bd54d0ec968df28ccc58bbb537a7b7c074ef2.diff
LOG: [sanitizer][Darwin] Suppress -Wno-non-virtual-dtor warning
Suppress the warning:
```
'fake_shared_weak_count' has virtual functions but non-virtual destructor
[-Wnon-virtual-dtor]
```
The warning has been recently enabled [1], but the associated cleanup
missed this instance in Darwin code [2].
[1] 9c31e12609e1935eb84a2497ac08a49e3139859a
[2] d48f2d7c02743571075bb7812bb4c9e634e51ed1
Differential Revision: https://reviews.llvm.org/D94139
Added:
Modified:
compiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp
Removed:
diff --git a/compiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp
b/compiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp
index aa29536d8616..ed10fccc980a 100644
--- a/compiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp
+++ b/compiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp
@@ -438,6 +438,7 @@ struct fake_shared_weak_count {
virtual void on_zero_shared() = 0;
virtual void _unused_0x18() = 0;
virtual void on_zero_shared_weak() = 0;
+ virtual ~fake_shared_weak_count() = 0; // suppress -Wnon-virtual-dtor
};
} // namespace
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[llvm-branch-commits] [llvm] f4bcbdf - Suppress GCC Wdangling-else warning on gtest macros
Author: Reid Kleckner
Date: 2021-01-05T17:32:56-08:00
New Revision: f4bcbdf9cea16bf91ba342268f681de45e15733c
URL:
https://github.com/llvm/llvm-project/commit/f4bcbdf9cea16bf91ba342268f681de45e15733c
DIFF:
https://github.com/llvm/llvm-project/commit/f4bcbdf9cea16bf91ba342268f681de45e15733c.diff
LOG: Suppress GCC Wdangling-else warning on gtest macros
See https://github.com/google/googletest/issues/1119
Added:
Modified:
llvm/unittests/Support/CrashRecoveryTest.cpp
Removed:
diff --git a/llvm/unittests/Support/CrashRecoveryTest.cpp
b/llvm/unittests/Support/CrashRecoveryTest.cpp
index 864b852cf2d2..c38fa0b4cb25 100644
--- a/llvm/unittests/Support/CrashRecoveryTest.cpp
+++ b/llvm/unittests/Support/CrashRecoveryTest.cpp
@@ -109,8 +109,9 @@ TEST(CrashRecoveryTest, LimitedStackTrace) {
std::string Str = RawStream.str();
// FIXME: Handle "Depth" parameter in PrintStackTrace() function
// to print stack trace upto a specified Depth.
- if (!Triple(sys::getProcessTriple()).isOSWindows())
+ if (!Triple(sys::getProcessTriple()).isOSWindows()) {
EXPECT_EQ(std::string::npos, Str.find("#1"));
+ }
}
#ifdef _WIN32
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[llvm-branch-commits] [clang] 74f93bc - [Sema] Fix deleted function problem in implicitly movable test
Author: Yang Fan
Date: 2021-01-06T10:05:40+08:00
New Revision: 74f93bc373d089e757bb65cf8b30b63a4eae8b69
URL:
https://github.com/llvm/llvm-project/commit/74f93bc373d089e757bb65cf8b30b63a4eae8b69
DIFF:
https://github.com/llvm/llvm-project/commit/74f93bc373d089e757bb65cf8b30b63a4eae8b69.diff
LOG: [Sema] Fix deleted function problem in implicitly movable test
In implicitly movable test, a two-stage overload resolution is performed.
If the first overload resolution selects a deleted function, Clang directly
performs the second overload resolution, without checking whether the
deleted function matches the additional criteria.
This patch fixes the above problem.
Reviewed By: Quuxplusone
Differential Revision: https://reviews.llvm.org/D92936
Added:
clang/test/CXX/class/class.init/class.copy.elision/p3.cpp
Modified:
clang/lib/Sema/SemaInit.cpp
clang/lib/Sema/SemaStmt.cpp
clang/test/SemaCXX/warn-return-std-move.cpp
Removed:
diff --git a/clang/lib/Sema/SemaInit.cpp b/clang/lib/Sema/SemaInit.cpp
index 6d2e6094e79c..b5f31bf403d4 100644
--- a/clang/lib/Sema/SemaInit.cpp
+++ b/clang/lib/Sema/SemaInit.cpp
@@ -4115,11 +4115,13 @@ static void TryConstructorInitialization(Sema &S,
IsListInit);
}
if (Result) {
-Sequence.SetOverloadFailure(IsListInit ?
- InitializationSequence::FK_ListConstructorOverloadFailed
:
- InitializationSequence::FK_ConstructorOverloadFailed,
-Result);
-return;
+Sequence.SetOverloadFailure(
+IsListInit ? InitializationSequence::FK_ListConstructorOverloadFailed
+ : InitializationSequence::FK_ConstructorOverloadFailed,
+Result);
+
+if (Result != OR_Deleted)
+ return;
}
bool HadMultipleCandidates = (CandidateSet.size() > 1);
@@ -4140,31 +4142,45 @@ static void TryConstructorInitialization(Sema &S,
return;
}
- // C++11 [dcl.init]p6:
- // If a program calls for the default initialization of an object
- // of a const-qualified type T, T shall be a class type with a
- // user-provided default constructor.
- // C++ core issue 253 proposal:
- // If the implicit default constructor initializes all subobjects, no
- // initializer should be required.
- // The 253 proposal is for example needed to process libstdc++ headers in
5.x.
CXXConstructorDecl *CtorDecl = cast(Best->Function);
- if (Kind.getKind() == InitializationKind::IK_Default &&
- Entity.getType().isConstQualified()) {
-if (!CtorDecl->getParent()->allowConstDefaultInit()) {
- if (!maybeRecoverWithZeroInitialization(S, Sequence, Entity))
-Sequence.SetFailed(InitializationSequence::FK_DefaultInitOfConst);
+ if (Result != OR_Deleted) {
+// C++11 [dcl.init]p6:
+// If a program calls for the default initialization of an object
+// of a const-qualified type T, T shall be a class type with a
+// user-provided default constructor.
+// C++ core issue 253 proposal:
+// If the implicit default constructor initializes all subobjects, no
+// initializer should be required.
+// The 253 proposal is for example needed to process libstdc++ headers
+// in 5.x.
+if (Kind.getKind() == InitializationKind::IK_Default &&
+Entity.getType().isConstQualified()) {
+ if (!CtorDecl->getParent()->allowConstDefaultInit()) {
+if (!maybeRecoverWithZeroInitialization(S, Sequence, Entity))
+ Sequence.SetFailed(InitializationSequence::FK_DefaultInitOfConst);
+return;
+ }
+}
+
+// C++11 [over.match.list]p1:
+// In copy-list-initialization, if an explicit constructor is chosen, the
+// initializer is ill-formed.
+if (IsListInit && !Kind.AllowExplicit() && CtorDecl->isExplicit()) {
+ Sequence.SetFailed(InitializationSequence::FK_ExplicitConstructor);
return;
}
}
- // C++11 [over.match.list]p1:
- // In copy-list-initialization, if an explicit constructor is chosen, the
- // initializer is ill-formed.
- if (IsListInit && !Kind.AllowExplicit() && CtorDecl->isExplicit()) {
-Sequence.SetFailed(InitializationSequence::FK_ExplicitConstructor);
+ // [class.copy.elision]p3:
+ // In some copy-initialization contexts, a two-stage overload resolution
+ // is performed.
+ // If the first overload resolution selects a deleted function, we also
+ // need the initialization sequence to decide whether to perform the second
+ // overload resolution.
+ // For deleted functions in other contexts, there is no need to get the
+ // initialization sequence.
+ if (Result == OR_Deleted && Kind.getKind() != InitializationKind::IK_Copy)
return;
- }
// Add the constructor initialization step. Any cv-qualification conversion
is
// subsumed by the initialization.
@@ -5258,9 +5274,17 @@ static void
[llvm-branch-commits] [mlir] 4ae7952 - [mlir] Fix MathJax rendering in Affine doc
Author: lewuathe
Date: 2021-01-06T02:11:36Z
New Revision: 4ae7952e2b3566d373c55c8e9740051ca37ed738
URL:
https://github.com/llvm/llvm-project/commit/4ae7952e2b3566d373c55c8e9740051ca37ed738
DIFF:
https://github.com/llvm/llvm-project/commit/4ae7952e2b3566d373c55c8e9740051ca37ed738.diff
LOG: [mlir] Fix MathJax rendering in Affine doc
MathJax is not properly imported in Affine doc. It causes the invalid rendering
of math formulas in the Affine doc page.
https://mlir.llvm.org/docs/Dialects/Affine/#affine-expressions
Importing MathJax code from CDN resolved the rendering issue as follows.
{F14942131}
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D94004
Added:
Modified:
mlir/docs/Dialects/Affine.md
Removed:
diff --git a/mlir/docs/Dialects/Affine.md b/mlir/docs/Dialects/Affine.md
index cedbb0106c30..1ce535a0c9b7 100644
--- a/mlir/docs/Dialects/Affine.md
+++ b/mlir/docs/Dialects/Affine.md
@@ -124,19 +124,19 @@ one-dimensional affine expressions, with the entire list
enclosed in
parentheses.
**Context:** An affine function, informally, is a linear function plus a
-constant. More formally, a function f defined on a vector $$\vec{v} \in
-\mathbb{Z}^n$$ is a multidimensional affine function of $$\vec{v}$$ if
-$$f(\vec{v})$$ can be expressed in the form $$M \vec{v} + \vec{c}$$ where $$M$$
-is a constant matrix from $$\mathbb{Z}^{m \times n}$$ and $$\vec{c}$$ is a
-constant vector from $$\mathbb{Z}$$. $$m$$ is the dimensionality of such an
+constant. More formally, a function f defined on a vector $\vec{v} \in
+\mathbb{Z}^n$ is a multidimensional affine function of $\vec{v}$ if
+$f(\vec{v})$ can be expressed in the form $M \vec{v} + \vec{c}$ where $M$
+is a constant matrix from $\mathbb{Z}^{m \times n}$ and $\vec{c}$ is a
+constant vector from $\mathbb{Z}$. $m$ is the dimensionality of such an
affine function. MLIR further extends the definition of an affine function to
allow 'floordiv', 'ceildiv', and 'mod' with respect to positive integer
constants. Such extensions to affine functions have often been referred to as
quasi-affine functions by the polyhedral compiler community. MLIR uses the term
'affine map' to refer to these multidimensional quasi-affine functions. As
-examples, $$(i+j+1, j)$$, $$(i \mod 2, j+i)$$, $$(j, i/4, i \mod 4)$$, $$(2i+1,
-j)$$ are two-dimensional affine functions of $$(i, j)$$, but $$(i \cdot j,
-i^2)$$, $$(i \mod j, i/j)$$ are not affine functions of $$(i, j)$$.
+examples, $(i+j+1, j)$, $(i \mod 2, j+i)$, $(j, i/4, i \mod 4)$, $(2i+1,
+j)$ are two-dimensional affine functions of $(i, j)$, but $(i \cdot j,
+i^2)$, $(i \mod j, i/j)$ are not affine functions of $(i, j)$.
### Affine Maps
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[llvm-branch-commits] [llvm] 29f8628 - [Constant] Add containsPoisonElement
Author: Juneyoung Lee
Date: 2021-01-06T12:10:33+09:00
New Revision: 29f8628d1fc8d96670e13562c4d92fc916bd0ce1
URL:
https://github.com/llvm/llvm-project/commit/29f8628d1fc8d96670e13562c4d92fc916bd0ce1
DIFF:
https://github.com/llvm/llvm-project/commit/29f8628d1fc8d96670e13562c4d92fc916bd0ce1.diff
LOG: [Constant] Add containsPoisonElement
This patch
- Adds containsPoisonElement that checks existence of poison in constant vector
elements,
- Renames containsUndefElement to containsUndefOrPoisonElement to clarify its
behavior & updates its uses properly
With this patch, isGuaranteedNotToBeUndefOrPoison's tests w.r.t constant
vectors are added because its analysis is improved.
Thanks!
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D94053
Added:
Modified:
llvm/include/llvm/IR/Constant.h
llvm/lib/Analysis/ValueTracking.cpp
llvm/lib/IR/ConstantFold.cpp
llvm/lib/IR/Constants.cpp
llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
llvm/unittests/Analysis/ValueTrackingTest.cpp
llvm/unittests/IR/ConstantsTest.cpp
Removed:
diff --git a/llvm/include/llvm/IR/Constant.h b/llvm/include/llvm/IR/Constant.h
index 97650c2051ca..0190aca27b72 100644
--- a/llvm/include/llvm/IR/Constant.h
+++ b/llvm/include/llvm/IR/Constant.h
@@ -101,11 +101,15 @@ class Constant : public User {
/// lane, the constants still match.
bool isElementWiseEqual(Value *Y) const;
- /// Return true if this is a vector constant that includes any undefined
- /// elements. Since it is impossible to inspect a scalable vector element-
- /// wise at compile time, this function returns true only if the entire
- /// vector is undef
- bool containsUndefElement() const;
+ /// Return true if this is a vector constant that includes any undef or
+ /// poison elements. Since it is impossible to inspect a scalable vector
+ /// element- wise at compile time, this function returns true only if the
+ /// entire vector is undef or poison.
+ bool containsUndefOrPoisonElement() const;
+
+ /// Return true if this is a vector constant that includes any poison
+ /// elements.
+ bool containsPoisonElement() const;
/// Return true if this is a fixed width vector constant that includes
/// any constant expressions.
diff --git a/llvm/lib/Analysis/ValueTracking.cpp
b/llvm/lib/Analysis/ValueTracking.cpp
index e15d4f0e4b07..1c75c5fbd0db 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -4895,7 +4895,8 @@ static bool isGuaranteedNotToBeUndefOrPoison(const Value
*V,
return true;
if (C->getType()->isVectorTy() && !isa(C))
- return (PoisonOnly || !C->containsUndefElement()) &&
+ return (PoisonOnly ? !C->containsPoisonElement()
+ : !C->containsUndefOrPoisonElement()) &&
!C->containsConstantExpression();
}
@@ -5636,10 +5637,10 @@ static SelectPatternResult
matchSelectPattern(CmpInst::Predicate Pred,
// elements because those can not be back-propagated for analysis.
Value *OutputZeroVal = nullptr;
if (match(TrueVal, m_AnyZeroFP()) && !match(FalseVal, m_AnyZeroFP()) &&
-!cast(TrueVal)->containsUndefElement())
+!cast(TrueVal)->containsUndefOrPoisonElement())
OutputZeroVal = TrueVal;
else if (match(FalseVal, m_AnyZeroFP()) && !match(TrueVal, m_AnyZeroFP())
&&
- !cast(FalseVal)->containsUndefElement())
+ !cast(FalseVal)->containsUndefOrPoisonElement())
OutputZeroVal = FalseVal;
if (OutputZeroVal) {
diff --git a/llvm/lib/IR/ConstantFold.cpp b/llvm/lib/IR/ConstantFold.cpp
index 47745689ba2d..03cb108cc485 100644
--- a/llvm/lib/IR/ConstantFold.cpp
+++ b/llvm/lib/IR/ConstantFold.cpp
@@ -811,7 +811,7 @@ Constant *llvm::ConstantFoldSelectInstruction(Constant
*Cond,
return true;
if (C->getType()->isVectorTy())
- return !C->containsUndefElement() && !C->containsConstantExpression();
+ return !C->containsPoisonElement() && !C->containsConstantExpression();
// TODO: Recursively analyze aggregates or other constants.
return false;
diff --git a/llvm/lib/IR/Constants.cpp b/llvm/lib/IR/Constants.cpp
index a38302d17937..5aa819dda2b3 100644
--- a/llvm/lib/IR/Constants.cpp
+++ b/llvm/lib/IR/Constants.cpp
@@ -304,31 +304,42 @@ bool Constant::isElementWiseEqual(Value *Y) const {
return isa(CmpEq) || match(CmpEq, m_One());
}
-bool Constant::containsUndefElement() const {
- if (auto *VTy = dyn_cast(getType())) {
-if (isa(this))
+static bool
+containsUndefinedElement(const Constant *C,
+ function_ref HasFn) {
+ if (auto *VTy = dyn_cast(C->getType())) {
+if (HasFn(C))
return true;
-if (isa(this))
+if (isa(C))
return false;
-if (isa(getType()))
+if (isa(C->getType()))
[llvm-branch-commits] [mlir] 91f17ba - [mlir] Print the correct tool name in mlirTranslateMain
Author: Andrew Young Date: 2021-01-05T19:17:01-08:00 New Revision: 91f17ba24e86bfdd6e794e564f1e562b1d25e156 URL: https://github.com/llvm/llvm-project/commit/91f17ba24e86bfdd6e794e564f1e562b1d25e156 DIFF: https://github.com/llvm/llvm-project/commit/91f17ba24e86bfdd6e794e564f1e562b1d25e156.diff LOG: [mlir] Print the correct tool name in mlirTranslateMain The passed in tool name is not used, causing the wrong tool name to be printed by the help text. Reviewed By: mehdi_amini Differential Revision: https://reviews.llvm.org/D94120 Added: mlir/test/mlir-translate/commandline.mlir Modified: mlir/lib/Translation/Translation.cpp Removed: diff --git a/mlir/lib/Translation/Translation.cpp b/mlir/lib/Translation/Translation.cpp index 5c5ecb7e46c4..3c17ea237085 100644 --- a/mlir/lib/Translation/Translation.cpp +++ b/mlir/lib/Translation/Translation.cpp @@ -157,7 +157,7 @@ LogicalResult mlir::mlirTranslateMain(int argc, char **argv, llvm::cl::Required); registerAsmPrinterCLOptions(); registerMLIRContextCLOptions(); - llvm::cl::ParseCommandLineOptions(argc, argv, "MLIR translation driver\n"); + llvm::cl::ParseCommandLineOptions(argc, argv, toolName); std::string errorMessage; auto input = openInputFile(inputFilename, &errorMessage); diff --git a/mlir/test/mlir-translate/commandline.mlir b/mlir/test/mlir-translate/commandline.mlir new file mode 100644 index ..e55e7346cf48 --- /dev/null +++ b/mlir/test/mlir-translate/commandline.mlir @@ -0,0 +1,2 @@ +// RUN: mlir-translate --help | FileCheck %s +// CHECK: OVERVIEW: MLIR Translation Testing Tool \ No newline at end of file ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] cdfd4c5 - [NFC] Removed unused prefixes in test/CodeGen/AMDGPU
Author: Mircea Trofin Date: 2021-01-05T19:18:30-08:00 New Revision: cdfd4c5c1a9740b881eccb622b3bea474a26f1f9 URL: https://github.com/llvm/llvm-project/commit/cdfd4c5c1a9740b881eccb622b3bea474a26f1f9 DIFF: https://github.com/llvm/llvm-project/commit/cdfd4c5c1a9740b881eccb622b3bea474a26f1f9.diff LOG: [NFC] Removed unused prefixes in test/CodeGen/AMDGPU More patches to follow. This covers the pertinent tests starting with e, f, and g. Differential Revision: https://reviews.llvm.org/D94124 Added: Modified: llvm/test/CodeGen/AMDGPU/elf-notes.ll llvm/test/CodeGen/AMDGPU/extload-align.ll llvm/test/CodeGen/AMDGPU/extload.ll llvm/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll llvm/test/CodeGen/AMDGPU/fast-regalloc-bundles.mir llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll llvm/test/CodeGen/AMDGPU/flat-address-space.ll llvm/test/CodeGen/AMDGPU/flat-scratch.ll llvm/test/CodeGen/AMDGPU/fmad-formation-fmul-distribute-denormal-mode.ll llvm/test/CodeGen/AMDGPU/fmax_legacy.ll llvm/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll llvm/test/CodeGen/AMDGPU/fmin_legacy.ll llvm/test/CodeGen/AMDGPU/fminnum.f64.ll llvm/test/CodeGen/AMDGPU/fmuladd.f16.ll llvm/test/CodeGen/AMDGPU/fmuladd.f32.ll llvm/test/CodeGen/AMDGPU/fmuladd.v2f16.ll llvm/test/CodeGen/AMDGPU/fneg-combines.ll llvm/test/CodeGen/AMDGPU/fneg-combines.si.ll llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll llvm/test/CodeGen/AMDGPU/fneg-fabs.ll llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address.ll llvm/test/CodeGen/AMDGPU/fp_to_sint.ll llvm/test/CodeGen/AMDGPU/fpext-free.ll llvm/test/CodeGen/AMDGPU/fpext.f16.ll llvm/test/CodeGen/AMDGPU/fract.f64.ll llvm/test/CodeGen/AMDGPU/fract.ll llvm/test/CodeGen/AMDGPU/frem.ll llvm/test/CodeGen/AMDGPU/fshl.ll llvm/test/CodeGen/AMDGPU/fshr.ll llvm/test/CodeGen/AMDGPU/fsub.f16.ll llvm/test/CodeGen/AMDGPU/function-args.ll llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll llvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx1030.ll llvm/test/CodeGen/AMDGPU/global-saddr-atomics.gfx908.ll llvm/test/CodeGen/AMDGPU/gv-const-addrspace.ll Removed: diff --git a/llvm/test/CodeGen/AMDGPU/elf-notes.ll b/llvm/test/CodeGen/AMDGPU/elf-notes.ll index fa262752fbc7..05ac3c92f4ba 100644 --- a/llvm/test/CodeGen/AMDGPU/elf-notes.ll +++ b/llvm/test/CodeGen/AMDGPU/elf-notes.ll @@ -1,12 +1,12 @@ -; RUN: llc -mtriple=amdgcn-amd-unknown -mcpu=gfx802 --amdhsa-code-object-version=2 < %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK --check-prefix=GFX802 %s -; RUN: llc -mtriple=amdgcn-amd-unknown -mcpu=iceland --amdhsa-code-object-version=2 < %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK --check-prefix=GFX802 %s -; RUN: llc -mtriple=amdgcn-amd-unknown -mcpu=gfx802 -filetype=obj --amdhsa-code-object-version=2 < %s | llvm-readelf --notes - | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK-ELF --check-prefix=GFX802 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 --amdhsa-code-object-version=2 < %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA --check-prefix=GFX802 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=iceland --amdhsa-code-object-version=2 < %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA --check-prefix=GFX802 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 -filetype=obj --amdhsa-code-object-version=2 < %s | llvm-readelf --notes - | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA-ELF --check-prefix=GFX802 %s -; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx802 --amdhsa-code-object-version=2 < %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-PAL --check-prefix=GFX802 %s -; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=iceland --amdhsa-code-object-version=2 < %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-PAL --check-prefix=GFX802 %s -; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx802 -filetype=obj --amdhsa-code-object-version=2 < %s | llvm-readelf --notes - | FileCheck --check-prefix=GCN --check-prefix=OSABI-PAL-ELF --check-prefix=GFX802 %s +; RUN: llc -mtriple=amdgcn-amd-unknown -mcpu=gfx802 --amdhsa-code-object-version=2 < %s | FileCheck --check-prefix=OSABI-UNK %s +; RUN: llc -mtriple=amdgcn-amd-unknown -mcpu=iceland --amdhsa-code-object-version=2 < %s | FileCheck --check-prefix=OSABI-UNK %s +; RUN: llc -mtriple=amdgcn-amd-unknown -mcpu=gfx802 -filetype=obj --amdhsa-code-object-version=2 < %s | llvm-readelf --notes - | FileCheck --check-prefix=OSABI-UNK-ELF %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 --amdhsa-code-object-version=2 < %s | FileCheck --check-prefix=OSABI-HSA %s +; RUN: llc -mtriple=amdgcn-a
[llvm-branch-commits] [lld] aed8454 - ELF: Teach the linker about the 'B' augmentation string character.
Author: Peter Collingbourne
Date: 2021-01-05T19:51:11-08:00
New Revision: aed84542d5a05b415a9a7f54494107aea8bd7e89
URL:
https://github.com/llvm/llvm-project/commit/aed84542d5a05b415a9a7f54494107aea8bd7e89
DIFF:
https://github.com/llvm/llvm-project/commit/aed84542d5a05b415a9a7f54494107aea8bd7e89.diff
LOG: ELF: Teach the linker about the 'B' augmentation string character.
This character indicates that when return pointer authentication is
being used, the function signs the return address using the B key.
Differential Revision: https://reviews.llvm.org/D93954
Added:
lld/test/ELF/eh-frame-cfi-b-key.s
Modified:
lld/ELF/EhFrame.cpp
Removed:
diff --git a/lld/ELF/EhFrame.cpp b/lld/ELF/EhFrame.cpp
index 13f0484ff9e4..578c640f0214 100644
--- a/lld/ELF/EhFrame.cpp
+++ b/lld/ELF/EhFrame.cpp
@@ -194,7 +194,7 @@ uint8_t EhReader::getFdeEncoding() {
readByte();
else if (c == 'P')
skipAugP();
-else if (c != 'S')
+else if (c != 'B' && c != 'S')
failOn(aug.data(), "unknown .eh_frame augmentation string: " + aug);
}
return DW_EH_PE_absptr;
@@ -211,7 +211,7 @@ bool EhReader::hasLSDA() {
skipAugP();
else if (c == 'R')
readByte();
-else if (c != 'S')
+else if (c != 'B' && c != 'S')
failOn(aug.data(), "unknown .eh_frame augmentation string: " + aug);
}
return false;
diff --git a/lld/test/ELF/eh-frame-cfi-b-key.s
b/lld/test/ELF/eh-frame-cfi-b-key.s
new file mode 100644
index ..406674e8b5c8
--- /dev/null
+++ b/lld/test/ELF/eh-frame-cfi-b-key.s
@@ -0,0 +1,9 @@
+// REQUIRES: aarch64
+// RUN: llvm-mc -filetype=obj -triple aarch64-arm-none-eabi %s -o %t.o
+// RUN: ld.lld %t.o -o %t --icf=all --eh-frame-hdr
+
+.globl _start
+_start:
+.cfi_startproc
+.cfi_b_key_frame
+.cfi_endproc
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[llvm-branch-commits] [compiler-rt] 6dc3c11 - scudo: Update a comment to match the Linux kernel behavior. NFCI.
Author: Peter Collingbourne Date: 2021-01-05T19:51:47-08:00 New Revision: 6dc3c117a30744f3fcff5297ef702c1773d9328e URL: https://github.com/llvm/llvm-project/commit/6dc3c117a30744f3fcff5297ef702c1773d9328e DIFF: https://github.com/llvm/llvm-project/commit/6dc3c117a30744f3fcff5297ef702c1773d9328e.diff LOG: scudo: Update a comment to match the Linux kernel behavior. NFCI. Added: Modified: compiler-rt/lib/scudo/standalone/include/scudo/interface.h Removed: diff --git a/compiler-rt/lib/scudo/standalone/include/scudo/interface.h b/compiler-rt/lib/scudo/standalone/include/scudo/interface.h index 0736af1f2dc2..68029e4857a3 100644 --- a/compiler-rt/lib/scudo/standalone/include/scudo/interface.h +++ b/compiler-rt/lib/scudo/standalone/include/scudo/interface.h @@ -40,10 +40,11 @@ typedef void (*iterate_callback)(uintptr_t base, size_t size, void *arg); // the version in the process that analyzes the crash. // // fault_addr is the fault address. On aarch64 this is available in the system -// register FAR_ELx, or far_context.far in an upcoming release of the Linux -// kernel. This address must include the pointer tag; note that the kernel -// strips the tag from the fields siginfo.si_addr and sigcontext.fault_address, -// so these addresses are not suitable to be passed as fault_addr. +// register FAR_ELx, or siginfo.si_addr in Linux 5.11 or above. This address +// must include the pointer tag; this is available if SA_EXPOSE_TAGBITS was set +// in sigaction.sa_flags when the signal handler was registered. Note that the +// kernel strips the tag from the field sigcontext.fault_address, so this +// address is not suitable to be passed as fault_addr. // // stack_depot is a pointer to the stack depot data structure, which may be // obtained by calling the function __scudo_get_stack_depot_addr() in the ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
