[llvm-branch-commits] [llvm] 808fcfe - Revert "[DebugInfo] Improve dbg preservation in LSR."

[Markus Lavin via llvm-branch-commits]

Author: Markus Lavin
Date: 2020-11-27T08:52:32+01:00
New Revision: 808fcfe5944755f08ae88722070302fcf9135e58

URL: 
https://github.com/llvm/llvm-project/commit/808fcfe5944755f08ae88722070302fcf9135e58
DIFF: 
https://github.com/llvm/llvm-project/commit/808fcfe5944755f08ae88722070302fcf9135e58.diff

LOG: Revert "[DebugInfo] Improve dbg preservation in LSR."

This reverts commit 06758c6a6135f59deec8e73d4fcb69946ab47f54.

Bug: https://bugs.llvm.org/show_bug.cgi?id=48166
Additional discussion in: https://reviews.llvm.org/D91711

Added: 


Modified: 
llvm/include/llvm/Analysis/ScalarEvolution.h
llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
llvm/test/DebugInfo/COFF/fpo-shrink-wrap.ll

Removed: 
llvm/test/Transforms/LoopStrengthReduce/dbg-preserve-0.ll



diff  --git a/llvm/include/llvm/Analysis/ScalarEvolution.h 
b/llvm/include/llvm/Analysis/ScalarEvolution.h
index a7a24f086fbe..35e569710cab 100644
--- a/llvm/include/llvm/Analysis/ScalarEvolution.h
+++ b/llvm/include/llvm/Analysis/ScalarEvolution.h
@@ -1163,15 +1163,6 @@ class ScalarEvolution {
   const SCEV *S, const Loop *L,
   SmallPtrSetImpl &Preds);
 
-  /// Compute \p LHS - \p RHS and returns the result as an APInt if it is a
-  /// constant, and None if it isn't.
-  ///
-  /// This is intended to be a cheaper version of getMinusSCEV.  We can be
-  /// frugal here since we just bail out of actually constructing and
-  /// canonicalizing an expression in the cases where the result isn't going
-  /// to be a constant.
-  Optional computeConstantDifference(const SCEV *LHS, const SCEV *RHS);
-
   /// Update no-wrap flags of an AddRec. This may drop the cached info about
   /// this AddRec (such as range info) in case if new flags may potentially
   /// sharpen it.
@@ -1893,6 +1884,15 @@ class ScalarEvolution {
   bool splitBinaryAdd(const SCEV *Expr, const SCEV *&L, const SCEV *&R,
   SCEV::NoWrapFlags &Flags);
 
+  /// Compute \p LHS - \p RHS and returns the result as an APInt if it is a
+  /// constant, and None if it isn't.
+  ///
+  /// This is intended to be a cheaper version of getMinusSCEV.  We can be
+  /// frugal here since we just bail out of actually constructing and
+  /// canonicalizing an expression in the cases where the result isn't going
+  /// to be a constant.
+  Optional computeConstantDifference(const SCEV *LHS, const SCEV *RHS);
+
   /// Drop memoized information computed for S.
   void forgetMemoizedResults(const SCEV *S);
 

diff  --git a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp 
b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
index 2713fa61ba31..a1d182931d0f 100644
--- a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
@@ -59,7 +59,6 @@
 #include "llvm/ADT/Hashing.h"
 #include "llvm/ADT/PointerIntPair.h"
 #include "llvm/ADT/STLExtras.h"
-#include "llvm/ADT/SetOperations.h"
 #include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallBitVector.h"
 #include "llvm/ADT/SmallPtrSet.h"
@@ -81,7 +80,6 @@
 #include "llvm/IR/BasicBlock.h"
 #include "llvm/IR/Constant.h"
 #include "llvm/IR/Constants.h"
-#include "llvm/IR/DebugInfoMetadata.h"
 #include "llvm/IR/DerivedTypes.h"
 #include "llvm/IR/Dominators.h"
 #include "llvm/IR/GlobalValue.h"
@@ -5788,27 +5786,6 @@ static bool ReduceLoopStrength(Loop *L, IVUsers &IU, 
ScalarEvolution &SE,
   if (MSSA)
 MSSAU = std::make_unique(MSSA);
 
-  // Debug preservation - record all llvm.dbg.value from the loop as well as
-  // the SCEV of their variable location. Since salvageDebugInfo may change the
-  // DIExpression we need to store the original here as well (i.e. it needs to
-  // be in sync with the SCEV).
-  SmallVector<
-  std::tuple,
-  32>
-  DbgValues;
-  for (auto &B : L->getBlocks()) {
-for (auto &I : *B) {
-  if (DbgValueInst *D = dyn_cast(&I)) {
-auto V = D->getVariableLocation();
-if (!V || !SE.isSCEVable(V->getType()))
-  continue;
-auto DS = SE.getSCEV(V);
-DbgValues.push_back(
-std::make_tuple(D, V->getType(), DS, D->getExpression()));
-  }
-}
-  }
-
   // Run the main LSR transformation.
   Changed |=
   LSRInstance(L, IU, SE, DT, LI, TTI, AC, TLI, MSSAU.get()).getChanged();
@@ -5830,40 +5807,6 @@ static bool ReduceLoopStrength(Loop *L, IVUsers &IU, 
ScalarEvolution &SE,
   DeleteDeadPHIs(L->getHeader(), &TLI, MSSAU.get());
 }
   }
-  // Debug preservation - go through all recorded llvm.dbg.value and for those
-  // that now have an undef variable location use the recorded SCEV to try and
-  // update it. Compare with SCEV of Phi-nodes of loop header to find a
-  // suitable update candidate. SCEV match with constant offset is allowed and
-  // will be compensated for in the DIExpression.
-  if (Changed) {
-for (auto &D : DbgValues) {
-  auto DbgValue = std::get(D);
-  auto DbgValueType 

[llvm-branch-commits] [libc] a513be4 - [libc][Obvious] Fix typo in strnlen_test.cpp.

[Cheng Wang via llvm-branch-commits]

Author: Cheng Wang
Date: 2020-11-27T15:56:19+08:00
New Revision: a513be490080ce7b974c5411a9de38e118c25991

URL: 
https://github.com/llvm/llvm-project/commit/a513be490080ce7b974c5411a9de38e118c25991
DIFF: 
https://github.com/llvm/llvm-project/commit/a513be490080ce7b974c5411a9de38e118c25991.diff

LOG: [libc][Obvious] Fix typo in strnlen_test.cpp.

Added: 


Modified: 
libc/test/src/string/strnlen_test.cpp

Removed: 




diff  --git a/libc/test/src/string/strnlen_test.cpp 
b/libc/test/src/string/strnlen_test.cpp
index 9d8616bc8bd7..b15ec2f8cef2 100644
--- a/libc/test/src/string/strnlen_test.cpp
+++ b/libc/test/src/string/strnlen_test.cpp
@@ -1,4 +1,4 @@
-//===-- Unittests for 
strnlen--===//
+//===-- Unittests for strnlen 
-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.



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[llvm-branch-commits] [mlir] 5dd5a08 - [mlir] Let ModuleTranslate propagate LLVM triple

[Nicolas Vasilache via llvm-branch-commits]

Author: Nicolas Vasilache
Date: 2020-11-27T08:01:44Z
New Revision: 5dd5a083630c797c958b02acd381b9de2bf02c86

URL: 
https://github.com/llvm/llvm-project/commit/5dd5a083630c797c958b02acd381b9de2bf02c86
DIFF: 
https://github.com/llvm/llvm-project/commit/5dd5a083630c797c958b02acd381b9de2bf02c86.diff

LOG: [mlir] Let ModuleTranslate propagate LLVM triple

This adds LLVM triple propagation and updates the test that did not check it 
properly.

Differential Revision: https://reviews.llvm.org/D92182

Added: 


Modified: 
mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
mlir/test/Target/llvmir.mlir

Removed: 




diff  --git a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp 
b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
index d333c2ff8390..4f21eac5965f 100644
--- a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
+++ b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
@@ -946,6 +946,9 @@ std::unique_ptr 
ModuleTranslation::prepareLLVMModule(
   if (auto dataLayoutAttr =
   m->getAttr(LLVM::LLVMDialect::getDataLayoutAttrName()))
 llvmModule->setDataLayout(dataLayoutAttr.cast().getValue());
+  if (auto targetTripleAttr =
+  m->getAttr(LLVM::LLVMDialect::getTargetTripleAttrName()))
+
llvmModule->setTargetTriple(targetTripleAttr.cast().getValue());
 
   // Inject declarations for `malloc` and `free` functions that can be used in
   // memref allocation/deallocation coming from standard ops lowering.

diff  --git a/mlir/test/Target/llvmir.mlir b/mlir/test/Target/llvmir.mlir
index 8491e67fdfb5..9dc2fbfda028 100644
--- a/mlir/test/Target/llvmir.mlir
+++ b/mlir/test/Target/llvmir.mlir
@@ -1319,6 +1319,7 @@ module attributes {llvm.target_triple = 
"x86_64-pc-windows-msvc"} {}
 // -
 
 // CHECK-NOT: "CodeView", i32 1
+// CHECK: aarch64-linux-android
 module attributes {llvm.target_triple = "aarch64-linux-android"} {}
 
 // -



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[llvm-branch-commits] [llvm] 8dcf8d1 - [msan] Fix bugs when instrument x86.avx512*_cvt* intrinsics.

[via llvm-branch-commits]

Author: Wang, Pengfei
Date: 2020-11-27T16:33:14+08:00
New Revision: 8dcf8d1da5630d1beecafe6cb1247df3f6a47022

URL: 
https://github.com/llvm/llvm-project/commit/8dcf8d1da5630d1beecafe6cb1247df3f6a47022
DIFF: 
https://github.com/llvm/llvm-project/commit/8dcf8d1da5630d1beecafe6cb1247df3f6a47022.diff

LOG: [msan] Fix bugs when instrument x86.avx512*_cvt* intrinsics.

Scalar intrinsics x86.avx512*_cvt* have an extra rounding mode operand.
We can directly ignore it to reuse the SSE/AVX math.
This fix the bug https://bugs.llvm.org/show_bug.cgi?id=48298.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D92206

Added: 


Modified: 
llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
llvm/test/Instrumentation/MemorySanitizer/vector_cvt.ll

Removed: 




diff  --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp 
b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
index d4f481f7c327..1d4f279aeff4 100644
--- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
@@ -2734,14 +2734,16 @@ struct MemorySanitizerVisitor : public 
InstVisitor {
   // We copy the shadow of \p CopyOp[NumUsedElements:] to \p
   // Out[NumUsedElements:]. This means that intrinsics without \p CopyOp always
   // return a fully initialized value.
-  void handleVectorConvertIntrinsic(IntrinsicInst &I, int NumUsedElements) {
+  void handleVectorConvertIntrinsic(IntrinsicInst &I, int NumUsedElements,
+bool HasRoundingMode = false) {
 IRBuilder<> IRB(&I);
 Value *CopyOp, *ConvertOp;
 
-switch (I.getNumArgOperands()) {
-case 3:
-  assert(isa(I.getArgOperand(2)) && "Invalid rounding mode");
-  LLVM_FALLTHROUGH;
+assert((!HasRoundingMode ||
+isa(I.getArgOperand(I.getNumArgOperands() - 1))) &&
+   "Invalid rounding mode");
+
+switch (I.getNumArgOperands() - HasRoundingMode) {
 case 2:
   CopyOp = I.getArgOperand(0);
   ConvertOp = I.getArgOperand(1);
@@ -3294,6 +3296,8 @@ struct MemorySanitizerVisitor : public 
InstVisitor {
 case Intrinsic::x86_avx512_cvtusi2ss:
 case Intrinsic::x86_avx512_cvtusi642sd:
 case Intrinsic::x86_avx512_cvtusi642ss:
+  handleVectorConvertIntrinsic(I, 1, true);
+  break;
 case Intrinsic::x86_sse2_cvtsd2si64:
 case Intrinsic::x86_sse2_cvtsd2si:
 case Intrinsic::x86_sse2_cvtsd2ss:

diff  --git a/llvm/test/Instrumentation/MemorySanitizer/vector_cvt.ll 
b/llvm/test/Instrumentation/MemorySanitizer/vector_cvt.ll
index bb60145709b5..096b1011e55f 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/vector_cvt.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/vector_cvt.ll
@@ -9,6 +9,7 @@ target triple = "x86_64-unknown-linux-gnu"
 declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>) nounwind readnone
 declare <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double>, i32) nounwind 
readnone
 declare x86_mmx @llvm.x86.sse.cvtps2pi(<4 x float>) nounwind readnone
+declare i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float>, i32) nounwind readnone
 
 ; Single argument vector conversion.
 
@@ -45,3 +46,20 @@ entry:
 ; CHECK: call x86_mmx @llvm.x86.sse.cvtps2pi
 ; CHECK: store i64 0, {{.*}} @__msan_retval_tls
 ; CHECK: ret x86_mmx
+
+; avx512 rounding conversion.
+
+define i32 @pr48298(<4 x float> %value) sanitize_memory {
+entry:
+  %0 = tail call i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float> %value, i32 11)
+  ret i32 %0
+}
+
+; CHECK-LABEL: @pr48298
+; CHECK: extractelement <4 x i32> {{.*}}, i32 0
+; CHECK: icmp ne i32 {{.*}}, 0
+; CHECK: br
+; CHECK: call void @__msan_warning_with_origin_noreturn
+; CHECK: call i32 @llvm.x86.avx512.vcvtss2usi32
+; CHECK: store i32 0, {{.*}} @__msan_retval_tls
+; CHECK: ret i32



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[llvm-branch-commits] [mlir] 5535696 - [mlir] Add gpu.allocate, gpu.deallocate ops with LLVM lowering to runtime function calls.

[Christian Sigg via llvm-branch-commits]

Author: Christian Sigg
Date: 2020-11-27T09:40:59+01:00
New Revision: 5535696c386ba89b66c1b5a72a2aa98783571cc9

URL: 
https://github.com/llvm/llvm-project/commit/5535696c386ba89b66c1b5a72a2aa98783571cc9
DIFF: 
https://github.com/llvm/llvm-project/commit/5535696c386ba89b66c1b5a72a2aa98783571cc9.diff

LOG: [mlir] Add gpu.allocate, gpu.deallocate ops with LLVM lowering to runtime 
function calls.

The ops are very similar to the std variants, but support async GPU execution.

gpu.alloc does not currently support an alignment attribute, and the new ops do 
not have
canonicalizers/folders like their std siblings do.

Reviewed By: herhut

Differential Revision: https://reviews.llvm.org/D91698

Added: 
mlir/test/Conversion/GPUCommon/lower-alloc-to-gpu-runtime-calls.mlir

Modified: 
mlir/include/mlir/Dialect/GPU/GPUDialect.h
mlir/include/mlir/Dialect/GPU/GPUOps.td
mlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp
mlir/test/Dialect/GPU/ops.mlir
mlir/tools/mlir-cuda-runner/cuda-runtime-wrappers.cpp
mlir/tools/mlir-rocm-runner/rocm-runtime-wrappers.cpp

Removed: 




diff  --git a/mlir/include/mlir/Dialect/GPU/GPUDialect.h 
b/mlir/include/mlir/Dialect/GPU/GPUDialect.h
index 9828af7a31b0..99f388b4db51 100644
--- a/mlir/include/mlir/Dialect/GPU/GPUDialect.h
+++ b/mlir/include/mlir/Dialect/GPU/GPUDialect.h
@@ -19,6 +19,7 @@
 #include "mlir/IR/FunctionSupport.h"
 #include "mlir/IR/OpDefinition.h"
 #include "mlir/IR/OpImplementation.h"
+#include "mlir/IR/StandardTypes.h"
 #include "mlir/IR/SymbolTable.h"
 #include "mlir/Interfaces/SideEffectInterfaces.h"
 

diff  --git a/mlir/include/mlir/Dialect/GPU/GPUOps.td 
b/mlir/include/mlir/Dialect/GPU/GPUOps.td
index 593b735f01c9..33c00ca9b22c 100644
--- a/mlir/include/mlir/Dialect/GPU/GPUOps.td
+++ b/mlir/include/mlir/Dialect/GPU/GPUOps.td
@@ -804,4 +804,79 @@ def GPU_WaitOp : GPU_Op<"wait", [GPU_AsyncOpInterface]> {
   }];
 }
 
+def GPU_AllocOp : GPU_Op<"alloc", [
+GPU_AsyncOpInterface,
+AttrSizedOperandSegments,
+MemoryEffects<[MemAlloc]>
+  ]> {
+
+  let summary = "GPU memory allocation operation.";
+  let description = [{
+The `gpu.alloc` operation allocates a region of memory on the GPU. It is
+similar to the `std.alloc` op, but supports asynchronous GPU execution.
+
+The op does not execute before all async dependencies have finished
+executing.
+
+If the `async` keyword is present, the op is executed asynchronously (i.e.
+it does not block until the execution has finished on the device). In
+that case, it also returns a !gpu.async.token.
+
+Example:
+
+```mlir
+%memref, %token = gpu.alloc async [%dep] (%width) : memref<64x?xf32, 1>
+```
+  }];
+
+  let arguments = (ins Variadic:$asyncDependencies,
+   Variadic:$dynamicSizes, 
Variadic:$symbolOperands);
+  let results = (outs Res]>:$memref,
+ Optional:$asyncToken);
+
+  let extraClassDeclaration = [{
+MemRefType getType() { return memref().getType().cast(); }
+  }];
+
+  let assemblyFormat = [{
+custom(type($asyncToken), $asyncDependencies) ` `
+`(` $dynamicSizes `)` (`` `[` $symbolOperands^ `]`)? attr-dict `:` 
type($memref)
+  }];
+}
+
+def GPU_DeallocOp : GPU_Op<"dealloc", [
+GPU_AsyncOpInterface, MemoryEffects<[MemFree]>
+  ]> {
+
+  let summary = "GPU memory deallocation operation";
+
+  let description = [{
+The `gpu.dealloc` operation frees the region of memory referenced by a
+memref which was originally created by the `gpu.alloc` operation. It is
+similar to the `std.dealloc` op, but supports asynchronous GPU execution.
+
+The op does not execute before all async dependencies have finished
+executing.
+
+If the `async` keyword is present, the op is executed asynchronously (i.e.
+it does not block until the execution has finished on the device). In
+that case, it returns a !gpu.async.token.
+
+Example:
+
+```mlir
+%token = gpu.dealloc async [%dep] %memref : memref<8x64xf32, 1>
+```
+  }];
+
+  let arguments = (ins Variadic:$asyncDependencies,
+   Arg:$memref);
+  let results = (outs Optional:$asyncToken);
+
+  let assemblyFormat = [{
+custom(type($asyncToken), $asyncDependencies)
+$memref attr-dict `:` type($memref)
+  }];
+}
+
 #endif // GPU_OPS

diff  --git a/mlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp 
b/mlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp
index a046bb068d12..d625db95e976 100644
--- a/mlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp
+++ b/mlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp
@@ -142,6 +142,15 @@ class ConvertOpToGpuRuntimeCallPattern : public 
ConvertOpToLLVMPattern {
   {llvmIntPtrType /* intptr_t rank */,
llvmPointerType /* void *memrefDesc */,
llvmIntPtrType /* intptr_t elementSizeBytes */}};
+  

[llvm-branch-commits] [mlir] 6484567 - [MLIR][SCF] Find all innermost loops for parallel loop tiling

[Frederik Gossen via llvm-branch-commits]

Author: Frederik Gossen
Date: 2020-11-27T10:08:56+01:00
New Revision: 6484567f14881003a7c46d1587dbb0cf8082282a

URL: 
https://github.com/llvm/llvm-project/commit/6484567f14881003a7c46d1587dbb0cf8082282a
DIFF: 
https://github.com/llvm/llvm-project/commit/6484567f14881003a7c46d1587dbb0cf8082282a.diff

LOG: [MLIR][SCF] Find all innermost loops for parallel loop tiling

Overcome the assumption that parallel loops are only nested in other parallel
loops.

Differential Revision: https://reviews.llvm.org/D92188

Added: 


Modified: 
mlir/lib/Dialect/SCF/Transforms/ParallelLoopTiling.cpp
mlir/test/Dialect/SCF/parallel-loop-tiling.mlir

Removed: 




diff  --git a/mlir/lib/Dialect/SCF/Transforms/ParallelLoopTiling.cpp 
b/mlir/lib/Dialect/SCF/Transforms/ParallelLoopTiling.cpp
index 7bcc989a5b28..7bd589214f4c 100644
--- a/mlir/lib/Dialect/SCF/Transforms/ParallelLoopTiling.cpp
+++ b/mlir/lib/Dialect/SCF/Transforms/ParallelLoopTiling.cpp
@@ -22,15 +22,15 @@ using namespace mlir::scf;
 
 /// Tile a parallel loop of the form
 ///   scf.parallel (%i0, %i1) = (%arg0, %arg1) to (%arg2, %arg3)
-/// step (%arg4, %arg5)
+///step (%arg4, %arg5)
 ///
 /// into
 ///   scf.parallel (%i0, %i1) = (%arg0, %arg1) to (%arg2, %arg3)
-/// step (%arg4*tileSize[0],
-///   %arg5*tileSize[1])
+///step (%arg4*tileSize[0],
+///  %arg5*tileSize[1])
 /// scf.parallel (%j0, %j1) = (0, 0) to (min(%arg4*tileSize[0], %arg2-%i0)
-///   min(%arg5*tileSize[1], 
%arg3-%i1))
-///step (%arg4, %arg5)
+///  min(%arg5*tileSize[1], %arg3-%i1))
+///  step (%arg4, %arg5)
 ///
 /// where the uses of %i0 and %i1 in the loop body are replaced by
 /// %i0 + j0 and %i1 + %j1.
@@ -126,17 +126,27 @@ void mlir::scf::tileParallelLoop(ParallelOp op, 
ArrayRef tileSizes) {
   op.erase();
 }
 
-/// Get a list of most nested parallel loops. Assumes that ParallelOps are
-/// only directly nested.
-static bool getInnermostNestedLoops(Block *block,
-SmallVectorImpl &loops) {
-  bool hasInnerLoop = false;
-  for (auto parallelOp : block->getOps()) {
-hasInnerLoop = true;
-if (!getInnermostNestedLoops(parallelOp.getBody(), loops))
-  loops.push_back(parallelOp);
+/// Get a list of most nested parallel loops.
+static bool getInnermostPloops(Operation *rootOp,
+   SmallVectorImpl &result) {
+  assert(rootOp != nullptr && "Root operation must not be a nullptr.");
+  bool rootEnclosesPloops = false;
+  for (Region ®ion : rootOp->getRegions()) {
+for (Block &block : region.getBlocks()) {
+  for (Operation &op : block) {
+bool enclosesPloops = getInnermostPloops(&op, result);
+rootEnclosesPloops |= enclosesPloops;
+if (auto ploop = dyn_cast(op)) {
+  rootEnclosesPloops = true;
+
+  // Collect ploop if it is an innermost one.
+  if (!enclosesPloops)
+result.push_back(ploop);
+}
+  }
+}
   }
-  return hasInnerLoop;
+  return rootEnclosesPloops;
 }
 
 namespace {
@@ -148,14 +158,12 @@ struct ParallelLoopTiling
   }
 
   void runOnFunction() override {
-SmallVector mostNestedParallelOps;
-for (Block &block : getFunction()) {
-  getInnermostNestedLoops(&block, mostNestedParallelOps);
-}
-for (ParallelOp pLoop : mostNestedParallelOps) {
+SmallVector innermostPloops;
+getInnermostPloops(getFunction().getOperation(), innermostPloops);
+for (ParallelOp ploop : innermostPloops) {
   // FIXME: Add reduction support.
-  if (pLoop.getNumReductions() == 0)
-tileParallelLoop(pLoop, tileSizes);
+  if (ploop.getNumReductions() == 0)
+tileParallelLoop(ploop, tileSizes);
 }
   }
 };

diff  --git a/mlir/test/Dialect/SCF/parallel-loop-tiling.mlir 
b/mlir/test/Dialect/SCF/parallel-loop-tiling.mlir
index e0dc8344f14d..5d3a676f58ab 100644
--- a/mlir/test/Dialect/SCF/parallel-loop-tiling.mlir
+++ b/mlir/test/Dialect/SCF/parallel-loop-tiling.mlir
@@ -112,3 +112,29 @@ func @tile_nested_innermost() {
 // CHECK:   }
 // CHECK:   return
 // CHECK: }
+
+// -
+
+func @tile_nested_in_non_ploop() {
+  %c0 = constant 0 : index
+  %c1 = constant 1 : index
+  %c2 = constant 2 : index
+  scf.for %i = %c0 to %c2 step %c1 {
+scf.for %j = %c0 to %c2 step %c1 {
+  scf.parallel (%k, %l) = (%c0, %c0) to (%c2, %c2) step (%c1, %c1) {
+  }
+}
+  }
+  return
+}
+
+// CHECK-LABEL: func @tile_nested_in_non_ploop
+// CHECK: scf.for
+// CHECK:   

[llvm-branch-commits] [llvm] 4018806 - [NFC][SimplifyCFG] FoldBranchToCommonDest: add one more test with PHI

[Roman Lebedev via llvm-branch-commits]

Author: Roman Lebedev
Date: 2020-11-27T12:47:14+03:00
New Revision: 40188063296f3a55f7816b20f518fa99977145bb

URL: 
https://github.com/llvm/llvm-project/commit/40188063296f3a55f7816b20f518fa99977145bb
DIFF: 
https://github.com/llvm/llvm-project/commit/40188063296f3a55f7816b20f518fa99977145bb.diff

LOG: [NFC][SimplifyCFG] FoldBranchToCommonDest: add one more test with PHI

This is the problematic pattern i didn't think of,
that lead to revert of 2245fb8aaa1c1f85f53f7b19a1ee3ac69b1a1dfe
in f3abd54958ab90ba7c100d3fa936a3ce0dd2ad04.

Added: 


Modified: 
llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll

Removed: 




diff  --git a/llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll 
b/llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll
index 1a6f7955fd80..6f83a20c72da 100644
--- a/llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll
+++ b/llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll
@@ -3,6 +3,7 @@
 
 declare void @sideeffect0()
 declare void @sideeffect1()
+declare void @sideeffect2()
 declare void @use8(i8)
 
 ; Basic cases, blocks have nothing other than the comparison itself.
@@ -304,6 +305,55 @@ final_right:
   ret void
 }
 
+define void @one_pred_with_extra_op_liveout_distant_phi(i8 %v0, i8 %v1) {
+; CHECK-LABEL: @one_pred_with_extra_op_liveout_distant_phi(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:[[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0
+; CHECK-NEXT:br i1 [[C0]], label [[PRED:%.*]], label [[LEFT_END:%.*]]
+; CHECK:   pred:
+; CHECK-NEXT:[[C1:%.*]] = icmp eq i8 [[V1:%.*]], 0
+; CHECK-NEXT:br i1 [[C1]], label [[DISPATCH:%.*]], label 
[[FINAL_RIGHT:%.*]]
+; CHECK:   dispatch:
+; CHECK-NEXT:[[V2_ADJ:%.*]] = add i8 [[V0]], [[V1]]
+; CHECK-NEXT:[[C2:%.*]] = icmp eq i8 [[V2_ADJ]], 0
+; CHECK-NEXT:br i1 [[C2]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT]]
+; CHECK:   final_left:
+; CHECK-NEXT:call void @sideeffect0()
+; CHECK-NEXT:call void @use8(i8 [[V2_ADJ]])
+; CHECK-NEXT:br label [[LEFT_END]]
+; CHECK:   left_end:
+; CHECK-NEXT:[[MERGE_LEFT:%.*]] = phi i8 [ [[V2_ADJ]], [[FINAL_LEFT]] ], [ 
0, [[ENTRY:%.*]] ]
+; CHECK-NEXT:call void @sideeffect1()
+; CHECK-NEXT:call void @use8(i8 [[MERGE_LEFT]])
+; CHECK-NEXT:ret void
+; CHECK:   final_right:
+; CHECK-NEXT:call void @sideeffect2()
+; CHECK-NEXT:ret void
+;
+entry:
+  %c0 = icmp eq i8 %v0, 0
+  br i1 %c0, label %pred, label %left_end
+pred:
+  %c1 = icmp eq i8 %v1, 0
+  br i1 %c1, label %dispatch, label %final_right
+dispatch:
+  %v2_adj = add i8 %v0, %v1
+  %c2 = icmp eq i8 %v2_adj, 0
+  br i1 %c2, label %final_left, label %final_right
+final_left:
+  call void @sideeffect0()
+  call void @use8(i8 %v2_adj)
+  br label %left_end
+left_end:
+  %merge_left = phi i8 [ %v2_adj, %final_left ], [ 0, %entry ]
+  call void @sideeffect1()
+  call void @use8(i8 %merge_left)
+  ret void
+final_right:
+  call void @sideeffect2()
+  ret void
+}
+
 define void @two_preds_with_extra_op_liveout(i8 %v0, i8 %v1, i8 %v2, i8 %v3) {
 ; CHECK-LABEL: @two_preds_with_extra_op_liveout(
 ; CHECK-NEXT:  entry:



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[llvm-branch-commits] [llvm] b33fbba - Reland [SimplifyCFG] FoldBranchToCommonDest: lift use-restriction on bonus instructions

[Roman Lebedev via llvm-branch-commits]

Author: Roman Lebedev
Date: 2020-11-27T12:47:15+03:00
New Revision: b33fbbaa34f0fe9fb16789afc72ae424c1825b69

URL: 
https://github.com/llvm/llvm-project/commit/b33fbbaa34f0fe9fb16789afc72ae424c1825b69
DIFF: 
https://github.com/llvm/llvm-project/commit/b33fbbaa34f0fe9fb16789afc72ae424c1825b69.diff

LOG: Reland [SimplifyCFG] FoldBranchToCommonDest: lift use-restriction on bonus 
instructions

This was orginally committed in 2245fb8aaa1c1f85f53f7b19a1ee3ac69b1a1dfe.
but was immediately reverted in f3abd54958ab90ba7c100d3fa936a3ce0dd2ad04
because of a PHI handling issue.

Original commit message:

1. It doesn't make sense to enforce that the bonus instruction
   is only used once in it's basic block. What matters is
   whether those user instructions fit within our budget, sure,
   but that is another question.
2. It doesn't make sense to enforce that said bonus instructions
   are only used within their basic block. Perhaps the branch
   condition isn't using the value computed by said bonus instruction,
   and said bonus instruction is simply being calculated
   to be used in successors?

So iff we can clone bonus instructions, to lift these restrictions,
we just need to carefully update their external uses
to use the new cloned instructions.

Notably, this transform (even without this change) appears to be
poison-unsafe as per alive2, but is otherwise (including the patch) legal.

We don't introduce any new PHI nodes, but only "move" the instructions
around, i'm not really seeing much potential for extra cost modelling
for the transform, especially since now we allow at most one such
bonus instruction by default.

This causes the fold to fire +11.4% more (13216 -> 14725)
as of vanilla llvm test-suite + RawSpeed.

The motivational pattern is IEEE-754-2008 Binary16->Binary32
extension code:
https://github.com/darktable-org/rawspeed/blob/ca57d77fb2ba81f21fc712cfac26e54f46406473/src/librawspeed/common/FloatingPoint.h#L115-L120
^ that should be a switch, but it is not now: https://godbolt.org/z/bvja5v
That being said, even thought this seemed like this would fix it: 
https://godbolt.org/z/xGq3TM
apparently that fold is happening somewhere else afterall,
so something else also has a similar 'artificial' restriction.

Added: 


Modified: 
llvm/lib/Transforms/Utils/SimplifyCFG.cpp
llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
llvm/test/Transforms/LoopUnroll/peel-loop-inner.ll
llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll

Removed: 




diff  --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp 
b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 0f4c1b4038e5..55ce05987bfd 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -2779,15 +2779,9 @@ bool llvm::FoldBranchToCommonDest(BranchInst *BI, 
MemorySSAUpdater *MSSAU,
 // Ignore dbg intrinsics.
 if (isa(I))
   continue;
-if (!I->hasOneUse() || !isSafeToSpeculativelyExecute(&*I))
+// I must be safe to execute unconditionally.
+if (!isSafeToSpeculativelyExecute(&*I))
   return Changed;
-// I has only one use and can be executed unconditionally.
-Instruction *User = dyn_cast(I->user_back());
-if (User == nullptr || User->getParent() != BB)
-  return Changed;
-// I is used in the same BB. Since BI uses Cond and doesn't have more slots
-// to use any other instruction, User must be an instruction between 
next(I)
-// and Cond.
 
 // Account for the cost of duplicating this instruction into each
 // predecessor.
@@ -2883,6 +2877,13 @@ bool llvm::FoldBranchToCommonDest(BranchInst *BI, 
MemorySSAUpdater *MSSAU,
   PBI->swapSuccessors();
 }
 
+// Before cloning instructions, notify the successor basic block that it
+// is about to have a new predecessor. This will update PHI nodes,
+// which will allow us to update live-out uses of bonus instructions.
+if (BI->isConditional())
+  AddPredecessorToBlock(PBI->getSuccessor(0) == BB ? TrueDest : FalseDest,
+PredBlock, BB, MSSAU);
+
 // If we have bonus instructions, clone them into the predecessor block.
 // Note that there may be multiple predecessor blocks, so we cannot move
 // bonus instructions to a predecessor block.
@@ -2914,6 +2915,18 @@ bool llvm::FoldBranchToCommonDest(BranchInst *BI, 
MemorySSAUpdater *MSSAU,
   PredBlock->getInstList().insert(PBI->getIterator(), NewBonusInst);
   NewBonusInst->takeName(&*BonusInst);
   BonusInst->setName(BonusInst->getName() + ".old");
+  BonusInst->replaceUsesWithIf(NewBonusInst, [BB](Use &U) {
+auto *User = cast(U.getUser());
+// Ignore uses in the same block as the bonus instruction itself.
+if (User->getParent() == BB)
+  return false;

[llvm-branch-commits] [llvm] 7b8d50b - [InstSimplify] Clarify use of FixedVectorType in SimplifySelectInst

[Cullen Rhodes via llvm-branch-commits]

Author: Cullen Rhodes
Date: 2020-11-27T09:55:29Z
New Revision: 7b8d50b141bbf223eab33a75f468be4ee92ad052

URL: 
https://github.com/llvm/llvm-project/commit/7b8d50b141bbf223eab33a75f468be4ee92ad052
DIFF: 
https://github.com/llvm/llvm-project/commit/7b8d50b141bbf223eab33a75f468be4ee92ad052.diff

LOG: [InstSimplify] Clarify use of FixedVectorType in SimplifySelectInst

Folding a select of vector constants that include undef elements only
applies to fixed vectors, but there's no earlier check the type is not
scalable so it crashes for scalable vectors. This adds a check so this
optimization is only attempted for fixed vectors.

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D92046

Added: 


Modified: 
llvm/lib/Analysis/InstructionSimplify.cpp
llvm/test/Transforms/InstSimplify/select.ll

Removed: 




diff  --git a/llvm/lib/Analysis/InstructionSimplify.cpp 
b/llvm/lib/Analysis/InstructionSimplify.cpp
index 813fb6c89863..6b116eb0ed00 100644
--- a/llvm/lib/Analysis/InstructionSimplify.cpp
+++ b/llvm/lib/Analysis/InstructionSimplify.cpp
@@ -4136,7 +4136,8 @@ static Value *SimplifySelectInst(Value *Cond, Value 
*TrueVal, Value *FalseVal,
 
   // Deal with partial undef vector constants: select ?, VecC, VecC' --> VecC''
   Constant *TrueC, *FalseC;
-  if (TrueVal->getType()->isVectorTy() && match(TrueVal, m_Constant(TrueC)) &&
+  if (isa(TrueVal->getType()) &&
+  match(TrueVal, m_Constant(TrueC)) &&
   match(FalseVal, m_Constant(FalseC))) {
 unsigned NumElts =
 cast(TrueC->getType())->getNumElements();

diff  --git a/llvm/test/Transforms/InstSimplify/select.ll 
b/llvm/test/Transforms/InstSimplify/select.ll
index 2dcd29753788..4cbc5832d234 100644
--- a/llvm/test/Transforms/InstSimplify/select.ll
+++ b/llvm/test/Transforms/InstSimplify/select.ll
@@ -957,3 +957,14 @@ define i32 @pr47322_more_poisonous_replacement(i32 %arg) {
   ret i32 %r1.sroa.0.1
 }
 declare i32 @llvm.cttz.i32(i32, i1 immarg)
+
+; Partial undef scalable vectors should be ignored.
+define  @ignore_scalable_undef( %cond) {
+; CHECK-LABEL: @ignore_scalable_undef(
+; CHECK-NEXT:[[S:%.*]] = select  [[COND:%.*]],  undef,  insertelement ( undef, i1 
true, i32 0)
+; CHECK-NEXT:ret  [[S]]
+;
+  %vec = insertelement  undef, i1 true, i32 0
+  %s = select  %cond,  undef,  %vec
+  ret  %s
+}



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[llvm-branch-commits] [clang] a2d561f - [SVE] Add a couple of extra sizeless type tests

[Richard Sandiford via llvm-branch-commits]

Author: Richard Sandiford
Date: 2020-11-27T10:33:47Z
New Revision: a2d561f1a33694a44451b5e0fe2d534522a4ee1d

URL: 
https://github.com/llvm/llvm-project/commit/a2d561f1a33694a44451b5e0fe2d534522a4ee1d
DIFF: 
https://github.com/llvm/llvm-project/commit/a2d561f1a33694a44451b5e0fe2d534522a4ee1d.diff

LOG: [SVE] Add a couple of extra sizeless type tests

This patch adds tests for things that happened to be fixed by previous
patches, but that should continue working if we do decide to treat
sizeless types as incomplete types.

Differential Revision: https://reviews.llvm.org/D79584

Added: 


Modified: 
clang/test/Sema/sizeless-1.c
clang/test/SemaCXX/sizeless-1.cpp

Removed: 




diff  --git a/clang/test/Sema/sizeless-1.c b/clang/test/Sema/sizeless-1.c
index dd6492c44b62..e1d926544894 100644
--- a/clang/test/Sema/sizeless-1.c
+++ b/clang/test/Sema/sizeless-1.c
@@ -290,4 +290,10 @@ void test_generic(void) {
   int a3[_Generic(0, svint8_t : 1, svint16_t : 2, default : 3) == 3 ? 1 : -1];
   (void)_Generic(0, svint8_t : 1, svint8_t : 2, default : 3); // 
expected-error {{type 'svint8_t' (aka '__SVInt8_t') in generic association 
compatible with previously specified type 'svint8_t'}} expected-note 
{{compatible type}}
 }
+
+void test_compound_literal(void) {
+  svint8_t local_int8;
+
+  (void)(svint8_t){local_int8};
+}
 #endif

diff  --git a/clang/test/SemaCXX/sizeless-1.cpp 
b/clang/test/SemaCXX/sizeless-1.cpp
index 46a183f7ad0c..96a3ce7542a7 100644
--- a/clang/test/SemaCXX/sizeless-1.cpp
+++ b/clang/test/SemaCXX/sizeless-1.cpp
@@ -379,6 +379,8 @@ extern array_alias *array_alias_int_ptr;
 extern array_alias *array_alias_int8_ptr; // expected-note {{in 
instantiation of template type alias 'array_alias' requested here}}
 #endif
 
+extern "C" svint8_t c_return_int8();
+
 void cxx_only(int sel) {
   svint8_t local_int8;
   svint16_t local_int16;



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[llvm-branch-commits] [clang] 89c1a7a - [ASTImporter] Import the default argument of NonTypeTemplateParmDecl

[Raphael Isemann via llvm-branch-commits]

Author: Raphael Isemann
Date: 2020-11-27T11:40:07+01:00
New Revision: 89c1a7a67d6947f56dc2db189d3872626f5a8609

URL: 
https://github.com/llvm/llvm-project/commit/89c1a7a67d6947f56dc2db189d3872626f5a8609
DIFF: 
https://github.com/llvm/llvm-project/commit/89c1a7a67d6947f56dc2db189d3872626f5a8609.diff

LOG: [ASTImporter] Import the default argument of NonTypeTemplateParmDecl

The test case isn't using the AST matchers for all checks as there doesn't seem 
to be support for
matching NonTypeTemplateParmDecl default arguments. Otherwise this is simply 
importing the
default arguments.

Reviewed By: martong

Differential Revision: https://reviews.llvm.org/D92106

Added: 


Modified: 
clang/lib/AST/ASTImporter.cpp
clang/unittests/AST/ASTImporterTest.cpp

Removed: 




diff  --git a/clang/lib/AST/ASTImporter.cpp b/clang/lib/AST/ASTImporter.cpp
index 5159682da85f..01ee8d275af1 100644
--- a/clang/lib/AST/ASTImporter.cpp
+++ b/clang/lib/AST/ASTImporter.cpp
@@ -5227,15 +5227,22 @@ 
ASTNodeImporter::VisitNonTypeTemplateParmDecl(NonTypeTemplateParmDecl *D) {
   if (Err)
 return std::move(Err);
 
-  // FIXME: Import default argument.
-
   NonTypeTemplateParmDecl *ToD = nullptr;
-  (void)GetImportedOrCreateDecl(
-  ToD, D, Importer.getToContext(),
-  Importer.getToContext().getTranslationUnitDecl(),
-  ToInnerLocStart, ToLocation, D->getDepth(),
-  D->getPosition(), ToDeclName.getAsIdentifierInfo(), ToType,
-  D->isParameterPack(), ToTypeSourceInfo);
+  if (GetImportedOrCreateDecl(ToD, D, Importer.getToContext(),
+  Importer.getToContext().getTranslationUnitDecl(),
+  ToInnerLocStart, ToLocation, D->getDepth(),
+  D->getPosition(),
+  ToDeclName.getAsIdentifierInfo(), ToType,
+  D->isParameterPack(), ToTypeSourceInfo))
+return ToD;
+
+  if (D->hasDefaultArgument()) {
+ExpectedExpr ToDefaultArgOrErr = import(D->getDefaultArgument());
+if (!ToDefaultArgOrErr)
+  return ToDefaultArgOrErr.takeError();
+ToD->setDefaultArgument(*ToDefaultArgOrErr);
+  }
+
   return ToD;
 }
 

diff  --git a/clang/unittests/AST/ASTImporterTest.cpp 
b/clang/unittests/AST/ASTImporterTest.cpp
index 5a93a7348e7a..81a92a10f48d 100644
--- a/clang/unittests/AST/ASTImporterTest.cpp
+++ b/clang/unittests/AST/ASTImporterTest.cpp
@@ -953,6 +953,27 @@ TEST_P(ASTImporterOptionSpecificTestBase, 
TemplateTemplateParmDeclDefaultArg) {
   ASSERT_EQ(ToTemplate, ToExpectedDecl);
 }
 
+TEST_P(ASTImporterOptionSpecificTestBase, NonTypeTemplateParmDeclNoDefaultArg) 
{
+  Decl *FromTU = getTuDecl("template struct X {};", Lang_CXX03);
+  auto From = FirstDeclMatcher().match(
+  FromTU, nonTypeTemplateParmDecl(hasName("N")));
+  NonTypeTemplateParmDecl *To = Import(From, Lang_CXX03);
+  ASSERT_FALSE(To->hasDefaultArgument());
+}
+
+TEST_P(ASTImporterOptionSpecificTestBase, NonTypeTemplateParmDeclDefaultArg) {
+  Decl *FromTU = getTuDecl("template struct X {};", Lang_CXX03);
+  auto From = FirstDeclMatcher().match(
+  FromTU, nonTypeTemplateParmDecl(hasName("S")));
+  NonTypeTemplateParmDecl *To = Import(From, Lang_CXX03);
+  ASSERT_TRUE(To->hasDefaultArgument());
+  Stmt *ToArg = To->getDefaultArgument();
+  ASSERT_TRUE(isa(ToArg));
+  ToArg = *ToArg->child_begin();
+  ASSERT_TRUE(isa(ToArg));
+  ASSERT_EQ(cast(ToArg)->getValue().getLimitedValue(), 1U);
+}
+
 TEST_P(ASTImporterOptionSpecificTestBase,
ImportOfTemplatedDeclOfClassTemplateDecl) {
   Decl *FromTU = getTuDecl("template struct S{};", Lang_CXX03);



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[llvm-branch-commits] [llvm] 0d9166f - [LegacyPM] Remove unused undocumented parameter. NFC.

[Jay Foad via llvm-branch-commits]

Author: Jay Foad
Date: 2020-11-27T10:41:38Z
New Revision: 0d9166ff79578c7e98cef8c554e1342ece8efee6

URL: 
https://github.com/llvm/llvm-project/commit/0d9166ff79578c7e98cef8c554e1342ece8efee6
DIFF: 
https://github.com/llvm/llvm-project/commit/0d9166ff79578c7e98cef8c554e1342ece8efee6.diff

LOG: [LegacyPM] Remove unused undocumented parameter. NFC.

The Direction parameter to AnalysisResolver::getAnalysisIfAvailable has
never been documented or used for anything.

Added: 


Modified: 
llvm/include/llvm/PassAnalysisSupport.h
llvm/lib/IR/LegacyPassManager.cpp
llvm/lib/IR/Pass.cpp

Removed: 




diff  --git a/llvm/include/llvm/PassAnalysisSupport.h 
b/llvm/include/llvm/PassAnalysisSupport.h
index 84df171d38d8..4e28466c4968 100644
--- a/llvm/include/llvm/PassAnalysisSupport.h
+++ b/llvm/include/llvm/PassAnalysisSupport.h
@@ -183,7 +183,7 @@ class AnalysisResolver {
   }
 
   /// Return analysis result or null if it doesn't exist.
-  Pass *getAnalysisIfAvailable(AnalysisID ID, bool Direction) const;
+  Pass *getAnalysisIfAvailable(AnalysisID ID) const;
 
 private:
   /// This keeps track of which passes implements the interfaces that are
@@ -207,7 +207,7 @@ AnalysisType *Pass::getAnalysisIfAvailable() const {
 
   const void *PI = &AnalysisType::ID;
 
-  Pass *ResultPass = Resolver->getAnalysisIfAvailable(PI, true);
+  Pass *ResultPass = Resolver->getAnalysisIfAvailable(PI);
   if (!ResultPass) return nullptr;
 
   // Because the AnalysisType may not be a subclass of pass (for

diff  --git a/llvm/lib/IR/LegacyPassManager.cpp 
b/llvm/lib/IR/LegacyPassManager.cpp
index 7f94d42d6ecd..bb2661d36b56 100644
--- a/llvm/lib/IR/LegacyPassManager.cpp
+++ b/llvm/lib/IR/LegacyPassManager.cpp
@@ -1392,8 +1392,8 @@ PMDataManager::~PMDataManager() {
 
//===--===//
 // NOTE: Is this the right place to define this method ?
 // getAnalysisIfAvailable - Return analysis result or null if it doesn't exist.
-Pass *AnalysisResolver::getAnalysisIfAvailable(AnalysisID ID, bool dir) const {
-  return PM.findAnalysisPass(ID, dir);
+Pass *AnalysisResolver::getAnalysisIfAvailable(AnalysisID ID) const {
+  return PM.findAnalysisPass(ID, true);
 }
 
 std::tuple

diff  --git a/llvm/lib/IR/Pass.cpp b/llvm/lib/IR/Pass.cpp
index a815da2bdc51..0750501a92c4 100644
--- a/llvm/lib/IR/Pass.cpp
+++ b/llvm/lib/IR/Pass.cpp
@@ -62,7 +62,7 @@ bool ModulePass::skipModule(Module &M) const {
 }
 
 bool Pass::mustPreserveAnalysisID(char &AID) const {
-  return Resolver->getAnalysisIfAvailable(&AID, true) != nullptr;
+  return Resolver->getAnalysisIfAvailable(&AID) != nullptr;
 }
 
 // dumpPassStructure - Implement the -debug-pass=Structure option



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[llvm-branch-commits] [llvm] 68ed644 - [LegacyPM] Avoid a redundant map lookup in setLastUser. NFC.

[Jay Foad via llvm-branch-commits]

Author: Jay Foad
Date: 2020-11-27T10:42:01Z
New Revision: 68ed6447855632b954b55f63807481eaa44705df

URL: 
https://github.com/llvm/llvm-project/commit/68ed6447855632b954b55f63807481eaa44705df
DIFF: 
https://github.com/llvm/llvm-project/commit/68ed6447855632b954b55f63807481eaa44705df.diff

LOG: [LegacyPM] Avoid a redundant map lookup in setLastUser. NFC.

As a bonus this makes it (IMO) obvious that the iterator is not
invalidated, so remove the comment explaining that.

Added: 


Modified: 
llvm/lib/IR/LegacyPassManager.cpp

Removed: 




diff  --git a/llvm/lib/IR/LegacyPassManager.cpp 
b/llvm/lib/IR/LegacyPassManager.cpp
index bb2661d36b56..8fd35ef975e2 100644
--- a/llvm/lib/IR/LegacyPassManager.cpp
+++ b/llvm/lib/IR/LegacyPassManager.cpp
@@ -675,11 +675,9 @@ PMTopLevelManager::setLastUser(ArrayRef 
AnalysisPasses, Pass *P) {
 
 // If AP is the last user of other passes then make P last user of
 // such passes.
-for (auto LU : LastUser) {
+for (auto &LU : LastUser) {
   if (LU.second == AP)
-// DenseMap iterator is not invalidated here because
-// this is just updating existing entries.
-LastUser[LU.first] = P;
+LU.second = P;
 }
   }
 }



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[llvm-branch-commits] [libc] a8beb4a - [libc] Fix typo in buildbot README.txt.

[Cheng Wang via llvm-branch-commits]

Author: Cheng Wang
Date: 2020-11-27T19:01:21+08:00
New Revision: a8beb4ada4bd01980e9effc8a2671d4c6454a7ba

URL: 
https://github.com/llvm/llvm-project/commit/a8beb4ada4bd01980e9effc8a2671d4c6454a7ba
DIFF: 
https://github.com/llvm/llvm-project/commit/a8beb4ada4bd01980e9effc8a2671d4c6454a7ba.diff

LOG: [libc] Fix typo in buildbot README.txt.

Reviewed By: sivachandra

Differential Revision: https://reviews.llvm.org/D90381

Added: 


Modified: 
libc/utils/buildbot/README.txt

Removed: 




diff  --git a/libc/utils/buildbot/README.txt b/libc/utils/buildbot/README.txt
index 3edec0e416c3..40c2cb5b8776 100644
--- a/libc/utils/buildbot/README.txt
+++ b/libc/utils/buildbot/README.txt
@@ -1,5 +1,5 @@
 This folder contains resources needed to create a docker container for
-llvm-libc builbot worker.
+llvm-libc buildbot worker.
 
 Dockerfile: Sets up the docker image with all pre-requisites.
 



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[llvm-branch-commits] [llvm] 4b9c2bb - [X86] Regenerate extract-store.ll tests

[Simon Pilgrim via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2020-11-27T11:18:57Z
New Revision: 4b9c2bbdb67139e69b689cbfc490632391324f02

URL: 
https://github.com/llvm/llvm-project/commit/4b9c2bbdb67139e69b689cbfc490632391324f02
DIFF: 
https://github.com/llvm/llvm-project/commit/4b9c2bbdb67139e69b689cbfc490632391324f02.diff

LOG: [X86] Regenerate extract-store.ll tests

Rename prefix from X32 to X86 as we typically use X32 for gnux32 triples

Added: 


Modified: 
llvm/test/CodeGen/X86/extract-store.ll

Removed: 




diff  --git a/llvm/test/CodeGen/X86/extract-store.ll 
b/llvm/test/CodeGen/X86/extract-store.ll
index 1160c6e5d21a..77a98028b37b 100644
--- a/llvm/test/CodeGen/X86/extract-store.ll
+++ b/llvm/test/CodeGen/X86/extract-store.ll
@@ -1,20 +1,20 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s 
--check-prefix=X32 --check-prefix=SSE-X32 --check-prefix=SSE2-X32
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2   | FileCheck %s 
--check-prefix=X64 --check-prefix=SSE-X64 --check-prefix=SSE2-X64
-; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.1   | FileCheck %s 
--check-prefix=X32 --check-prefix=SSE-X32 --check-prefix=SSE41-X32
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s 
--check-prefix=X64 --check-prefix=SSE-X64 --check-prefix=SSE41-X64
-; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx  | FileCheck %s 
--check-prefix=X32 --check-prefix=AVX-X32
-; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx| FileCheck %s 
--check-prefix=X64 --check-prefix=AVX-X64
-; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+sse 
-enable-legalize-types-checking | FileCheck %s --check-prefix=X64 
--check-prefix=SSE-X64 --check-prefix=SSE2-X64
-; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+sse 
-enable-legalize-types-checking | FileCheck %s --check-prefix=X64 
--check-prefix=SSE-X64 --check-prefix=SSE2-X64
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s 
--check-prefixes=X86,SSE-X86,SSE2-X86
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2   | FileCheck %s 
--check-prefixes=X64,SSE-X64,SSE2-X64
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.1   | FileCheck %s 
--check-prefixes=X86,SSE-X86,SSE41-X86
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s 
--check-prefixes=X64,SSE-X64,SSE41-X64
+; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx  | FileCheck %s 
--check-prefixes=X86,AVX-X86
+; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx| FileCheck %s 
--check-prefixes=X64,AVX-X64
+; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+sse 
-enable-legalize-types-checking | FileCheck %s 
--check-prefixes=X64,SSE-X64,SSE2-X64
+; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+sse 
-enable-legalize-types-checking | FileCheck %s 
--check-prefixes=X64,SSE-X64,SSE2-X64
 
 define void @extract_i8_0(i8* nocapture %dst, <16 x i8> %foo) nounwind {
-; SSE2-X32-LABEL: extract_i8_0:
-; SSE2-X32:   # %bb.0:
-; SSE2-X32-NEXT:movl {{[0-9]+}}(%esp), %eax
-; SSE2-X32-NEXT:movd %xmm0, %ecx
-; SSE2-X32-NEXT:movb %cl, (%eax)
-; SSE2-X32-NEXT:retl
+; SSE2-X86-LABEL: extract_i8_0:
+; SSE2-X86:   # %bb.0:
+; SSE2-X86-NEXT:movl {{[0-9]+}}(%esp), %eax
+; SSE2-X86-NEXT:movd %xmm0, %ecx
+; SSE2-X86-NEXT:movb %cl, (%eax)
+; SSE2-X86-NEXT:retl
 ;
 ; SSE2-X64-LABEL: extract_i8_0:
 ; SSE2-X64:   # %bb.0:
@@ -22,22 +22,22 @@ define void @extract_i8_0(i8* nocapture %dst, <16 x i8> 
%foo) nounwind {
 ; SSE2-X64-NEXT:movb %al, (%rdi)
 ; SSE2-X64-NEXT:retq
 ;
-; SSE41-X32-LABEL: extract_i8_0:
-; SSE41-X32:   # %bb.0:
-; SSE41-X32-NEXT:movl {{[0-9]+}}(%esp), %eax
-; SSE41-X32-NEXT:pextrb $0, %xmm0, (%eax)
-; SSE41-X32-NEXT:retl
+; SSE41-X86-LABEL: extract_i8_0:
+; SSE41-X86:   # %bb.0:
+; SSE41-X86-NEXT:movl {{[0-9]+}}(%esp), %eax
+; SSE41-X86-NEXT:pextrb $0, %xmm0, (%eax)
+; SSE41-X86-NEXT:retl
 ;
 ; SSE41-X64-LABEL: extract_i8_0:
 ; SSE41-X64:   # %bb.0:
 ; SSE41-X64-NEXT:pextrb $0, %xmm0, (%rdi)
 ; SSE41-X64-NEXT:retq
 ;
-; AVX-X32-LABEL: extract_i8_0:
-; AVX-X32:   # %bb.0:
-; AVX-X32-NEXT:movl {{[0-9]+}}(%esp), %eax
-; AVX-X32-NEXT:vpextrb $0, %xmm0, (%eax)
-; AVX-X32-NEXT:retl
+; AVX-X86-LABEL: extract_i8_0:
+; AVX-X86:   # %bb.0:
+; AVX-X86-NEXT:movl {{[0-9]+}}(%esp), %eax
+; AVX-X86-NEXT:vpextrb $0, %xmm0, (%eax)
+; AVX-X86-NEXT:retl
 ;
 ; AVX-X64-LABEL: extract_i8_0:
 ; AVX-X64:   # %bb.0:
@@ -49,13 +49,13 @@ define void @extract_i8_0(i8* nocapture %dst, <16 x i8> 
%foo) nounwind {
 }
 
 define void @extract_i8_3(i8* nocapture %dst, <16 x i8> %foo) nounwind {
-; SSE2-X32-LABEL: extract_i8_3:
-; SSE2-X32:   # %bb.0:
-; SSE2-X32-NEXT:movl {{[0-9]+}}(%esp), %eax
-; SSE2-X32-NEXT:movd %xmm0, %ecx
-; SSE2-X32-NEXT:shrl $24, %ecx
-; S

[llvm-branch-commits] [llvm] 969918e - [DAG] Legalize umin(x, y) -> sub(x, usubsat(x, y)) and umax(x, y) -> add(x, usubsat(y, x)) iff usubsat is legal

[Simon Pilgrim via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2020-11-27T11:18:58Z
New Revision: 969918e177adcfd526da7d8e21e5d76860e09c9e

URL: 
https://github.com/llvm/llvm-project/commit/969918e177adcfd526da7d8e21e5d76860e09c9e
DIFF: 
https://github.com/llvm/llvm-project/commit/969918e177adcfd526da7d8e21e5d76860e09c9e.diff

LOG: [DAG] Legalize umin(x,y) -> sub(x,usubsat(x,y)) and umax(x,y) -> 
add(x,usubsat(y,x)) iff usubsat is legal

If usubsat() is legal, this is likely to result in smaller codegen expansion 
than the default cmp+select codegen expansion.

Allows us to move the x86-specific lowering to the generic expansion code.

Differential Revision: https://reviews.llvm.org/D92183

Added: 


Modified: 
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/Analysis/CostModel/AArch64/min-max.ll
llvm/test/CodeGen/X86/midpoint-int-vec-128.ll

Removed: 




diff  --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp 
b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 3464fe87d99f..e45a311f84a4 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -7478,10 +7478,26 @@ SDValue TargetLowering::expandIntMINMAX(SDNode *Node, 
SelectionDAG &DAG) const {
   SDValue Op0 = Node->getOperand(0);
   SDValue Op1 = Node->getOperand(1);
   EVT VT = Op0.getValueType();
+  unsigned Opcode = Node->getOpcode();
+  SDLoc DL(Node);
+
+  // umin(x,y) -> sub(x,usubsat(x,y))
+  if (Opcode == ISD::UMIN && isOperationLegal(ISD::SUB, VT) &&
+  isOperationLegal(ISD::USUBSAT, VT)) {
+return DAG.getNode(ISD::SUB, DL, VT, Op0,
+   DAG.getNode(ISD::USUBSAT, DL, VT, Op0, Op1));
+  }
+
+  // umax(x,y) -> add(x,usubsat(y,x))
+  if (Opcode == ISD::UMAX && isOperationLegal(ISD::ADD, VT) &&
+  isOperationLegal(ISD::USUBSAT, VT)) {
+return DAG.getNode(ISD::ADD, DL, VT, Op0,
+   DAG.getNode(ISD::USUBSAT, DL, VT, Op1, Op0));
+  }
 
   // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
   ISD::CondCode CC;
-  switch (Node->getOpcode()) {
+  switch (Opcode) {
   default: llvm_unreachable("How did we get here?");
   case ISD::SMAX: CC = ISD::SETGT; break;
   case ISD::SMIN: CC = ISD::SETLT; break;
@@ -7494,7 +7510,6 @@ SDValue TargetLowering::expandIntMINMAX(SDNode *Node, 
SelectionDAG &DAG) const {
   if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT))
 return DAG.UnrollVectorOp(Node);
 
-  SDLoc DL(Node);
   SDValue Cond = DAG.getSetCC(DL, VT, Op0, Op1, CC);
   return DAG.getSelect(DL, VT, Cond, Op0, Op1);
 }

diff  --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp 
b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index 54bb3d0c7781..37a34023b8d0 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -217,10 +217,17 @@ AArch64TTIImpl::getIntrinsicInstrCost(const 
IntrinsicCostAttributes &ICA,
   TTI::TargetCostKind CostKind) {
   auto *RetTy = ICA.getReturnType();
   switch (ICA.getID()) {
-  case Intrinsic::smin:
   case Intrinsic::umin:
-  case Intrinsic::smax:
   case Intrinsic::umax: {
+auto LT = TLI->getTypeLegalizationCost(DL, RetTy);
+// umin(x,y) -> sub(x,usubsat(x,y))
+// umax(x,y) -> add(x,usubsat(y,x))
+if (LT.second == MVT::v2i64)
+  return LT.first * 2;
+LLVM_FALLTHROUGH;
+  }
+  case Intrinsic::smin:
+  case Intrinsic::smax: {
 static const auto ValidMinMaxTys = {MVT::v8i8,  MVT::v16i8, MVT::v4i16,
 MVT::v8i16, MVT::v2i32, MVT::v4i32};
 auto LT = TLI->getTypeLegalizationCost(DL, RetTy);

diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp 
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index fcbe1330b546..5cbca95f45f5 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -26959,22 +26959,6 @@ static SDValue LowerMINMAX(SDValue Op, SelectionDAG 
&DAG) {
   if (VT == MVT::v32i16 || VT == MVT::v64i8)
 return splitVectorIntBinary(Op, DAG);
 
-  SDLoc DL(Op);
-  unsigned Opcode = Op.getOpcode();
-  SDValue N0 = Op.getOperand(0);
-  SDValue N1 = Op.getOperand(1);
-
-  // For pre-SSE41, we can perform UMIN/UMAX v8i16 by using psubusw.
-  if (VT == MVT::v8i16) {
-assert((Opcode == ISD::UMIN || Opcode == ISD::UMAX) &&
-   "Unexpected MIN/MAX opcode");
-if (Opcode == ISD::UMIN)
-  return DAG.getNode(ISD::SUB, DL, VT, N0,
- DAG.getNode(ISD::USUBSAT, DL, VT, N0, N1));
-return DAG.getNode(ISD::ADD, DL, VT,
-   DAG.getNode(ISD::USUBSAT, DL, VT, N1, N0), N0);
-  }
-
   // Default to expand.
   return SDValue();
 }

diff  --git a/llvm/test/Analysis/CostModel/AArch64/min-max.ll 
b/llvm/test/Analysis/CostModel/AArch64

[llvm-branch-commits] [llvm] 10ad64a - [SLP] Dump Tree costs. NFC.

[Sjoerd Meijer via llvm-branch-commits]

Author: Sjoerd Meijer
Date: 2020-11-27T11:37:33Z
New Revision: 10ad64aa3bd912e638cd2c9721a6577a7f6b5ccb

URL: 
https://github.com/llvm/llvm-project/commit/10ad64aa3bd912e638cd2c9721a6577a7f6b5ccb
DIFF: 
https://github.com/llvm/llvm-project/commit/10ad64aa3bd912e638cd2c9721a6577a7f6b5ccb.diff

LOG: [SLP] Dump Tree costs. NFC.

This adds LLVM_DEBUG messages to dump the (intermediate) tree cost
calculations, which is useful to trace and see how the final cost is
calculated.

Added: 


Modified: 
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp 
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 19c088b6ac9b..a68c8c10e8f3 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -1744,6 +1744,19 @@ class BoUpSLP {
 #endif
   };
 
+#ifndef NDEBUG
+  void dumpTreeCosts(TreeEntry *E, int ReuseShuffleCost, int VecCost,
+ int ScalarCost) const {
+dbgs() << "SLP: Calculated costs for Tree:\n"; E->dump();
+dbgs() << "SLP: Costs:\n";
+dbgs() << "SLP: ReuseShuffleCost = " << ReuseShuffleCost << "\n";
+dbgs() << "SLP: VectorCost = " << VecCost << "\n";
+dbgs() << "SLP: ScalarCost = " << ScalarCost << "\n";
+dbgs() << "SLP: ReuseShuffleCost + VecCost - ScalarCost = " <<
+   ReuseShuffleCost + VecCost - ScalarCost << "\n";
+  }
+#endif
+
   /// Create a new VectorizableTree entry.
   TreeEntry *newTreeEntry(ArrayRef VL, Optional 
Bundle,
   const InstructionsState &S,
@@ -3562,6 +3575,7 @@ int BoUpSLP::getEntryCost(TreeEntry *E) {
 TTI->getCastInstrCost(E->getOpcode(), VecTy, SrcVecTy,
   TTI::getCastContextHint(VL0), CostKind, VL0);
   }
+  LLVM_DEBUG(dumpTreeCosts(E, ReuseShuffleCost, VecCost, ScalarCost));
   return VecCost - ScalarCost;
 }
 case Instruction::FCmp:
@@ -3612,6 +3626,7 @@ int BoUpSLP::getEntryCost(TreeEntry *E) {
   CmpInst::BAD_ICMP_PREDICATE, CostKind);
 VecCost = std::min(VecCost, IntrinsicCost);
   }
+  LLVM_DEBUG(dumpTreeCosts(E, ReuseShuffleCost, VecCost, ScalarCost));
   return ReuseShuffleCost + VecCost - ScalarCost;
 }
 case Instruction::FNeg:
@@ -3681,6 +3696,7 @@ int BoUpSLP::getEntryCost(TreeEntry *E) {
   int VecCost = TTI->getArithmeticInstrCost(
   E->getOpcode(), VecTy, CostKind, Op1VK, Op2VK, Op1VP, Op2VP,
   Operands, VL0);
+  LLVM_DEBUG(dumpTreeCosts(E, ReuseShuffleCost, VecCost, ScalarCost));
   return ReuseShuffleCost + VecCost - ScalarCost;
 }
 case Instruction::GetElementPtr: {
@@ -3699,6 +3715,7 @@ int BoUpSLP::getEntryCost(TreeEntry *E) {
   int VecCost =
   TTI->getArithmeticInstrCost(Instruction::Add, VecTy, CostKind,
   Op1VK, Op2VK);
+  LLVM_DEBUG(dumpTreeCosts(E, ReuseShuffleCost, VecCost, ScalarCost));
   return ReuseShuffleCost + VecCost - ScalarCost;
 }
 case Instruction::Load: {
@@ -3726,6 +3743,7 @@ int BoUpSLP::getEntryCost(TreeEntry *E) {
 VecLdCost += TTI->getShuffleCost(
 TargetTransformInfo::SK_PermuteSingleSrc, VecTy);
   }
+  LLVM_DEBUG(dumpTreeCosts(E, ReuseShuffleCost, VecLdCost, ScalarLdCost));
   return ReuseShuffleCost + VecLdCost - ScalarLdCost;
 }
 case Instruction::Store: {
@@ -3747,6 +3765,7 @@ int BoUpSLP::getEntryCost(TreeEntry *E) {
 VecStCost += TTI->getShuffleCost(
 TargetTransformInfo::SK_PermuteSingleSrc, VecTy);
   }
+  LLVM_DEBUG(dumpTreeCosts(E, ReuseShuffleCost, VecStCost, ScalarStCost));
   return ReuseShuffleCost + VecStCost - ScalarStCost;
 }
 case Instruction::Call: {
@@ -3811,6 +3830,7 @@ int BoUpSLP::getEntryCost(TreeEntry *E) {
  TTI::CastContextHint::None, CostKind);
   }
   VecCost += TTI->getShuffleCost(TargetTransformInfo::SK_Select, VecTy, 0);
+  LLVM_DEBUG(dumpTreeCosts(E, ReuseShuffleCost, VecCost, ScalarCost));
   return ReuseShuffleCost + VecCost - ScalarCost;
 }
 default:
@@ -4034,10 +4054,11 @@ int BoUpSLP::getTreeCost() {
   continue;
 
 int C = getEntryCost(&TE);
+Cost += C;
 LLVM_DEBUG(dbgs() << "SLP: Adding cost " << C
   << " for bundle that starts with " << *TE.Scalars[0]
-  << ".\n");
-Cost += C;
+  << ".\n"
+  << "SLP: Current total cost = " << Cost << "\n");
   }
 
   SmallPtrSet ExtractCostCalculated;
@@ -5941,9 +5962,9 @@ bool 
SLPVectorizerPass::vectorizeStoreChain(ArrayRef Chain, BoUpSLP &R,
 
   int Cost = R.getTreeCost();
 
-  LLVM_DEBUG(dbgs() << "SLP: Found cost=" << Cost << " for VF=" << VF << "\n");
+  LLVM_DEBUG(dbgs() 

[llvm-branch-commits] [llvm] d939ba4 - [ARM] MVE qabs vectorization test. NFC

[David Green via llvm-branch-commits]

Author: David Green
Date: 2020-11-27T12:21:11Z
New Revision: d939ba4c6853ed469a7fd198c751a158cc7e5c59

URL: 
https://github.com/llvm/llvm-project/commit/d939ba4c6853ed469a7fd198c751a158cc7e5c59
DIFF: 
https://github.com/llvm/llvm-project/commit/d939ba4c6853ed469a7fd198c751a158cc7e5c59.diff

LOG: [ARM] MVE qabs vectorization test. NFC

Added: 
llvm/test/Transforms/LoopVectorize/ARM/mve-qabs.ll

Modified: 


Removed: 




diff  --git a/llvm/test/Transforms/LoopVectorize/ARM/mve-qabs.ll 
b/llvm/test/Transforms/LoopVectorize/ARM/mve-qabs.ll
new file mode 100644
index ..903b467c7581
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/ARM/mve-qabs.ll
@@ -0,0 +1,292 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -loop-vectorize -instcombine -simplifycfg < %s -S -o - | FileCheck 
%s
+
+target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "thumbv8.1m.main-arm-none-eabi"
+
+define void @arm_abs_q7(i8* nocapture readonly %pSrc, i8* nocapture %pDst, i32 
%blockSize) #0 {
+; CHECK-LABEL: @arm_abs_q7(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:[[CMP_NOT19:%.*]] = icmp eq i32 [[BLOCKSIZE:%.*]], 0
+; CHECK-NEXT:br i1 [[CMP_NOT19]], label [[WHILE_END:%.*]], label 
[[WHILE_BODY_PREHEADER:%.*]]
+; CHECK:   while.body.preheader:
+; CHECK-NEXT:[[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[BLOCKSIZE]], 16
+; CHECK-NEXT:br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label 
[[VECTOR_MEMCHECK:%.*]]
+; CHECK:   vector.memcheck:
+; CHECK-NEXT:[[SCEVGEP:%.*]] = getelementptr i8, i8* [[PDST:%.*]], i32 
[[BLOCKSIZE]]
+; CHECK-NEXT:[[SCEVGEP1:%.*]] = getelementptr i8, i8* [[PSRC:%.*]], i32 
[[BLOCKSIZE]]
+; CHECK-NEXT:[[BOUND0:%.*]] = icmp ugt i8* [[SCEVGEP1]], [[PDST]]
+; CHECK-NEXT:[[BOUND1:%.*]] = icmp ugt i8* [[SCEVGEP]], [[PSRC]]
+; CHECK-NEXT:[[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
+; CHECK-NEXT:br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label 
[[VECTOR_PH:%.*]]
+; CHECK:   vector.ph:
+; CHECK-NEXT:[[N_VEC:%.*]] = and i32 [[BLOCKSIZE]], -16
+; CHECK-NEXT:[[IND_END:%.*]] = getelementptr i8, i8* [[PSRC]], i32 
[[N_VEC]]
+; CHECK-NEXT:[[IND_END3:%.*]] = and i32 [[BLOCKSIZE]], 15
+; CHECK-NEXT:[[IND_END5:%.*]] = getelementptr i8, i8* [[PDST]], i32 
[[N_VEC]]
+; CHECK-NEXT:br label [[VECTOR_BODY:%.*]]
+; CHECK:   vector.body:
+; CHECK-NEXT:[[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ 
[[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:[[NEXT_GEP:%.*]] = getelementptr i8, i8* [[PSRC]], i32 
[[INDEX]]
+; CHECK-NEXT:[[NEXT_GEP6:%.*]] = getelementptr i8, i8* [[PDST]], i32 
[[INDEX]]
+; CHECK-NEXT:[[TMP0:%.*]] = bitcast i8* [[NEXT_GEP]] to <16 x i8>*
+; CHECK-NEXT:[[WIDE_LOAD:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]], 
align 1, !alias.scope !0
+; CHECK-NEXT:[[TMP1:%.*]] = icmp sgt <16 x i8> [[WIDE_LOAD]], 
zeroinitializer
+; CHECK-NEXT:[[TMP2:%.*]] = icmp eq <16 x i8> [[WIDE_LOAD]], 
+; CHECK-NEXT:[[TMP3:%.*]] = sub <16 x i8> zeroinitializer, [[WIDE_LOAD]]
+; CHECK-NEXT:[[TMP4:%.*]] = select <16 x i1> [[TMP2]], <16 x i8> , <16 x i8> [[TMP3]]
+; CHECK-NEXT:[[TMP5:%.*]] = select <16 x i1> [[TMP1]], <16 x i8> 
[[WIDE_LOAD]], <16 x i8> [[TMP4]]
+; CHECK-NEXT:[[TMP6:%.*]] = bitcast i8* [[NEXT_GEP6]] to <16 x i8>*
+; CHECK-NEXT:store <16 x i8> [[TMP5]], <16 x i8>* [[TMP6]], align 1, 
!alias.scope !3, !noalias !0
+; CHECK-NEXT:[[INDEX_NEXT]] = add i32 [[INDEX]], 16
+; CHECK-NEXT:[[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT:br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label 
[[VECTOR_BODY]], [[LOOP5:!llvm.loop !.*]]
+; CHECK:   middle.block:
+; CHECK-NEXT:[[CMP_N:%.*]] = icmp eq i32 [[N_VEC]], [[BLOCKSIZE]]
+; CHECK-NEXT:br i1 [[CMP_N]], label [[WHILE_END]], label [[SCALAR_PH]]
+; CHECK:   scalar.ph:
+; CHECK-NEXT:[[BC_RESUME_VAL:%.*]] = phi i8* [ [[IND_END]], 
[[MIDDLE_BLOCK]] ], [ [[PSRC]], [[WHILE_BODY_PREHEADER]] ], [ [[PSRC]], 
[[VECTOR_MEMCHECK]] ]
+; CHECK-NEXT:[[BC_RESUME_VAL2:%.*]] = phi i32 [ [[IND_END3]], 
[[MIDDLE_BLOCK]] ], [ [[BLOCKSIZE]], [[WHILE_BODY_PREHEADER]] ], [ 
[[BLOCKSIZE]], [[VECTOR_MEMCHECK]] ]
+; CHECK-NEXT:[[BC_RESUME_VAL4:%.*]] = phi i8* [ [[IND_END5]], 
[[MIDDLE_BLOCK]] ], [ [[PDST]], [[WHILE_BODY_PREHEADER]] ], [ [[PDST]], 
[[VECTOR_MEMCHECK]] ]
+; CHECK-NEXT:br label [[WHILE_BODY:%.*]]
+; CHECK:   while.body:
+; CHECK-NEXT:[[PSRC_ADDR_022:%.*]] = phi i8* [ [[INCDEC_PTR:%.*]], 
[[WHILE_BODY]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
+; CHECK-NEXT:[[BLKCNT_021:%.*]] = phi i32 [ [[DEC:%.*]], [[WHILE_BODY]] ], 
[ [[BC_RESUME_VAL2]], [[SCALAR_PH]] ]
+; CHECK-NEXT:[[PDST_ADDR_020:%.*]] = phi i8* [ [[INCDEC_PTR13:%.*]], 
[[WHILE_BODY]] ], [ [[BC_RESUME_VAL4]], [[SCALAR_PH]] ]
+; CHECK-NEXT:[[INCDEC_PTR]] = getelemen

[llvm-branch-commits] [llvm] c2090ff - [obj2yaml] - Don't assert when trying to calculate the expected section offset.

[Georgii Rymar via llvm-branch-commits]

Author: Georgii Rymar
Date: 2020-11-27T15:38:22+03:00
New Revision: c2090ff5942269c391c549f432258e4fd2fa12cb

URL: 
https://github.com/llvm/llvm-project/commit/c2090ff5942269c391c549f432258e4fd2fa12cb
DIFF: 
https://github.com/llvm/llvm-project/commit/c2090ff5942269c391c549f432258e4fd2fa12cb.diff

LOG: [obj2yaml] - Don't assert when trying to calculate the expected section 
offset.

The following line asserts when `sh_addralign > MAX_UINT32 && 
(uint32_t)sh_addralign == 0`:

```
ExpectedOffset = alignTo(ExpectedOffset,
 SecHdr.sh_addralign ? SecHdr.sh_addralign : 1);
```

it happens because `sh_addralign` is truncated to 32-bit value, but `alignTo`
doesn't accept `Align == 0`. We should change `1` to `1uLL`.

Differential revision: https://reviews.llvm.org/D92163

Added: 


Modified: 
llvm/test/tools/obj2yaml/ELF/offset.yaml
llvm/tools/obj2yaml/elf2yaml.cpp

Removed: 




diff  --git a/llvm/test/tools/obj2yaml/ELF/offset.yaml 
b/llvm/test/tools/obj2yaml/ELF/offset.yaml
index 417c92aed1f8..2dc04b617417 100644
--- a/llvm/test/tools/obj2yaml/ELF/offset.yaml
+++ b/llvm/test/tools/obj2yaml/ELF/offset.yaml
@@ -32,6 +32,10 @@
 # BASIC-NEXT: Type: SHT_PROGBITS
 # BASIC-NEXT: AddressAlign: 0x10
 # BASIC-NEXT: Offset:   0x200
+# BASIC-NEXT:   - Name: .bar4
+# BASIC-NEXT: Type: SHT_PROGBITS
+# BASIC-NEXT: AddressAlign: 0x1
+# BASIC-NEXT: Offset:   0x210
 
 --- !ELF
 FileHeader:
@@ -81,6 +85,12 @@ Sections:
 Type: SHT_PROGBITS
 AddressAlign: 0x10
 Offset:   0x200
+## A case where AddressAlign > MAX_UINT32 and (uint32_t)AddressAlign == 0.
+## Check we dump an offset in this case properly.
+  - Name: .bar4
+Type: SHT_PROGBITS
+AddressAlign: 0x1
+Offset:   0x210
 
 ## Show we dump the "Offset" key for the first section when
 ## it has an unexpected file offset.

diff  --git a/llvm/tools/obj2yaml/elf2yaml.cpp 
b/llvm/tools/obj2yaml/elf2yaml.cpp
index 3aa74bab0c18..4d8d471817ac 100644
--- a/llvm/tools/obj2yaml/elf2yaml.cpp
+++ b/llvm/tools/obj2yaml/elf2yaml.cpp
@@ -248,8 +248,8 @@ static void dumpSectionOffsets(const typename ELFT::Ehdr 
&Header,
 ELFYAML::Section &Sec = *cast(C.get());
 const typename ELFT::Shdr &SecHdr = S[Sec.OriginalSecNdx];
 
-ExpectedOffset =
-alignTo(ExpectedOffset, SecHdr.sh_addralign ? SecHdr.sh_addralign : 1);
+ExpectedOffset = alignTo(ExpectedOffset,
+ SecHdr.sh_addralign ? SecHdr.sh_addralign : 1uLL);
 
 // We only set the "Offset" field when it can't be naturally derived
 // from the offset and size of the previous section. This reduces



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[llvm-branch-commits] [libcxx] b215198 - [libc++] [docs] Exclude helper files from Sphinx configuration to avoid generating empty pages.

[Marek Kurdej via llvm-branch-commits]

Author: Marek Kurdej
Date: 2020-11-27T13:47:20+01:00
New Revision: b215198bb05b4274800ac6e97f4f27319227cade

URL: 
https://github.com/llvm/llvm-project/commit/b215198bb05b4274800ac6e97f4f27319227cade
DIFF: 
https://github.com/llvm/llvm-project/commit/b215198bb05b4274800ac6e97f4f27319227cade.diff

LOG: [libc++] [docs] Exclude helper files from Sphinx configuration to avoid 
generating empty pages.

Added: 
libcxx/docs/Helpers/Styles.rst

Modified: 
libcxx/docs/Cxx1yStatus.rst
libcxx/docs/Cxx1zStatus.rst
libcxx/docs/Cxx2aStatus.rst
libcxx/docs/conf.py

Removed: 
libcxx/docs/Styles.rst



diff  --git a/libcxx/docs/Cxx1yStatus.rst b/libcxx/docs/Cxx1yStatus.rst
index 3cf4938f9770..91744a7eee0c 100644
--- a/libcxx/docs/Cxx1yStatus.rst
+++ b/libcxx/docs/Cxx1yStatus.rst
@@ -4,7 +4,7 @@
 libc++ C++14 Status
 
 
-.. include:: Styles.rst
+.. include:: Helpers/Styles.rst
 
 .. contents::
:local:

diff  --git a/libcxx/docs/Cxx1zStatus.rst b/libcxx/docs/Cxx1zStatus.rst
index efa4d09fad1c..54a1629209a9 100644
--- a/libcxx/docs/Cxx1zStatus.rst
+++ b/libcxx/docs/Cxx1zStatus.rst
@@ -4,7 +4,7 @@
 libc++ C++17 Status
 
 
-.. include:: Styles.rst
+.. include:: Helpers/Styles.rst
 
 .. contents::
:local:

diff  --git a/libcxx/docs/Cxx2aStatus.rst b/libcxx/docs/Cxx2aStatus.rst
index 4fd4e356710f..fc5b779aecc9 100644
--- a/libcxx/docs/Cxx2aStatus.rst
+++ b/libcxx/docs/Cxx2aStatus.rst
@@ -4,7 +4,7 @@
 libc++ C++2a Status
 
 
-.. include:: Styles.rst
+.. include:: Helpers/Styles.rst
 
 .. contents::
:local:

diff  --git a/libcxx/docs/Styles.rst b/libcxx/docs/Helpers/Styles.rst
similarity index 100%
rename from libcxx/docs/Styles.rst
rename to libcxx/docs/Helpers/Styles.rst

diff  --git a/libcxx/docs/conf.py b/libcxx/docs/conf.py
index dee50d46d43b..95cd98bc471c 100644
--- a/libcxx/docs/conf.py
+++ b/libcxx/docs/conf.py
@@ -63,7 +63,7 @@
 
 # List of patterns, relative to source directory, that match files and
 # directories to ignore when looking for source files.
-exclude_patterns = ['_build']
+exclude_patterns = ['_build', 'Helpers']
 
 # The reST default role (used for this markup: `text`) to use for all 
documents.
 #default_role = None



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[llvm-branch-commits] [llvm] ee9ffc7 - [obj2yaml] - Dump the `EShNum` key in some cases.

[Georgii Rymar via llvm-branch-commits]

Author: Georgii Rymar
Date: 2020-11-27T15:56:10+03:00
New Revision: ee9ffc73452a0b500db18d422562918d389b1d14

URL: 
https://github.com/llvm/llvm-project/commit/ee9ffc73452a0b500db18d422562918d389b1d14
DIFF: 
https://github.com/llvm/llvm-project/commit/ee9ffc73452a0b500db18d422562918d389b1d14.diff

LOG: [obj2yaml] - Dump the `EShNum` key in some cases.

This patch starts emitting the `EShNum` key, when the `e_shnum = 0`
and the section header table exists.

`e_shnum` might be 0, when the the number of entries in the section header
table is larger than or equal to SHN_LORESERVE (0xff00).
In this case the real number of entries
in the section header table is held in the `sh_size`
member of the initial entry in section header table.

Currently, obj2yaml crashes when an object has `e_shoff != 0` and the `sh_size`
member of the initial entry in section header table is `0`.
This patch fixes it.

Differential revision: https://reviews.llvm.org/D92098

Added: 
llvm/test/tools/obj2yaml/ELF/eshnum.yaml

Modified: 
llvm/tools/obj2yaml/elf2yaml.cpp

Removed: 




diff  --git a/llvm/test/tools/obj2yaml/ELF/eshnum.yaml 
b/llvm/test/tools/obj2yaml/ELF/eshnum.yaml
new file mode 100644
index ..35c7cfddf58c
--- /dev/null
+++ b/llvm/test/tools/obj2yaml/ELF/eshnum.yaml
@@ -0,0 +1,67 @@
+## Test cases related to the value of the e_shnum field of the ELF header live 
here.
+
+## Normally an object that does not have sections has e_shnum == 0.
+## Also, e_shnum might be 0, when the the number of entries in the section
+## header table is larger than or equal to SHN_LORESERVE (0xff00). In this case
+## the real number of entries in the section header table is held in the 
sh_size
+## member of the initial entry in the section header table.
+
+## In the test case below we have an object that has e_shnum = 0 and the real
+## number of sections is written to the sh_size member of the initial entry in
+## the section header table. Check that we emit the `EShNum` key properly.
+
+# RUN: yaml2obj %s -o %t1
+# RUN: obj2yaml %t1 | FileCheck %s --check-prefix=PRESERVE
+
+# PRESERVE:  --- !ELF
+# PRESERVE-NEXT: FileHeader:
+# PRESERVE-NEXT:   Class:  ELFCLASS64
+# PRESERVE-NEXT:   Data:   ELFDATA2LSB
+# PRESERVE-NEXT:   Type:   ET_REL
+# PRESERVE-NEXT:   EShNum: 0x0
+# PRESERVE-NEXT: Sections:
+# PRESERVE-NEXT:   - Type: SHT_NULL
+# PRESERVE-NEXT: Size: 0x3
+# PRESERVE-NEXT: ...
+
+--- !ELF
+FileHeader:
+  Class:  ELFCLASS64
+  Data:   ELFDATA2LSB
+  Type:   ET_REL
+  EShNum: 0x0
+  EShOff: [[ESHOFF=]]
+Sections:
+ - Type: SHT_NULL
+## 3 sections total: SHT_NULL + 2 implicit sections: .strtab and .shstrtab.
+   Size: [[SIZE=0x3]]
+
+## In the test case below we have an object with a non-zero section header 
table
+## file offset and an initial entry in the section header table with sh_size 
of 0.
+## Here we check that we are able to dump such objects properly.
+
+# RUN: yaml2obj %s -DSIZE=0x0 -o %t2
+# RUN: obj2yaml %t2 | FileCheck %s --check-prefix=NO-SECTIONS
+
+# NO-SECTIONS:  --- !ELF
+# NO-SECTIONS-NEXT: FileHeader:
+# NO-SECTIONS-NEXT:   Class:  ELFCLASS64
+# NO-SECTIONS-NEXT:   Data:   ELFDATA2LSB
+# NO-SECTIONS-NEXT:   Type:   ET_REL
+# NO-SECTIONS-NEXT:   EShNum: 0x0
+## Note: yaml2obj will create the SHT_NULL section with sh_size = 0 implicitly.
+# NO-SECTIONS-NEXT: ...
+
+## In the test case below we have an object without a section header table and 
e_shnum == 0.
+## Document how we dump it.
+## FIXME: we should emit the `SectionHeaderTable` key with `NoHeaders=true` 
for this case.
+
+# RUN: yaml2obj %s -DESHOFF=0x0 -o %t3
+# RUN: obj2yaml %t3 | FileCheck %s --check-prefix=NO-HEADERS
+
+# NO-HEADERS:  --- !ELF
+# NO-HEADERS-NEXT: FileHeader:
+# NO-HEADERS-NEXT:   Class: ELFCLASS64
+# NO-HEADERS-NEXT:   Data:  ELFDATA2LSB
+# NO-HEADERS-NEXT:   Type:  ET_REL
+# NO-HEADERS-NEXT: ...

diff  --git a/llvm/tools/obj2yaml/elf2yaml.cpp 
b/llvm/tools/obj2yaml/elf2yaml.cpp
index 4d8d471817ac..ea2f2911712b 100644
--- a/llvm/tools/obj2yaml/elf2yaml.cpp
+++ b/llvm/tools/obj2yaml/elf2yaml.cpp
@@ -237,6 +237,9 @@ static void dumpSectionOffsets(const typename ELFT::Ehdr 
&Header,
ArrayRef Phdrs,
std::vector> &V,
ArrayRef S) {
+  if (V.empty())
+return;
+
   uint64_t ExpectedOffset;
   if (Header.e_phoff > 0)
 ExpectedOffset = Header.e_phoff + Header.e_phentsize * Header.e_phnum;
@@ -289,6 +292,14 @@ template  Expected 
ELFDumper::dump() {
   Sections = *SectionsOrErr;
   SectionNames.resize(Sections.size());
 
+  // Normally an object that does not have sections has e_shnum == 0.
+  // Also, e_shnum might be 0, when the the number of entries in the section
+  // header table is larger than or equal to SHN_LORESERVE (0xff00). In this
+  // case the real number of entries is held in the sh_size member of the
+  // initial en

[llvm-branch-commits] [mlir] 63d3198 - [mlir] Fix typos and broken links in LangRef

[Alex Zinenko via llvm-branch-commits]

Author: Felipe de Azevedo Piovezan
Date: 2020-11-27T14:07:32+01:00
New Revision: 63d3198cedbca8cf51ce2c73e6c2192cc819d079

URL: 
https://github.com/llvm/llvm-project/commit/63d3198cedbca8cf51ce2c73e6c2192cc819d079
DIFF: 
https://github.com/llvm/llvm-project/commit/63d3198cedbca8cf51ce2c73e6c2192cc819d079.diff

LOG: [mlir] Fix typos and broken links in LangRef

Many pages have had their titles renamed over time,
causing broken links to spread throughout the documentation.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D92093

Added: 


Modified: 
mlir/docs/LangRef.md
mlir/docs/Rationale/Rationale.md

Removed: 




diff  --git a/mlir/docs/LangRef.md b/mlir/docs/LangRef.md
index 9cd3e657b4d3..82272d1b729f 100644
--- a/mlir/docs/LangRef.md
+++ b/mlir/docs/LangRef.md
@@ -34,7 +34,7 @@ system](#type-system).  [Operations](#operations) are 
contained in
 [Blocks](#blocks) and Blocks are contained in [Regions](#regions). Operations
 are also ordered within their containing block and Blocks are ordered in their
 containing region, although this order may or may not be semantically
-meaningful in a given [kind of region](Interfaces.md#regionkindinterface)).
+meaningful in a given [kind of region](Interfaces.md#regionkindinterfaces)).
 Operations may also contain regions, enabling hierarchical structures to be
 represented.
 
@@ -55,8 +55,8 @@ allowing operation semantics to be described abstractly using
 [Traits](Traits.md) and [Interfaces](Interfaces.md), enabling transformations
 to operate on operations more generically.  Traits often describe verification
 constraints on valid IR, enabling complex invariants to be captured and
-checked. (see
-[docs/Tutorials/Toy/Ch-2/#op-vs-operation-using-mlir-operations])
+checked. (see [Op vs
+Operation](docs/Tutorials/Toy/Ch-2/#op-vs-operation-using-mlir-operations))
 
 One obvious application of MLIR is to represent an
 [SSA-based](https://en.wikipedia.org/wiki/Static_single_assignment_form) IR,
@@ -438,7 +438,7 @@ block-arg-list ::= `(` value-id-and-type-list? `)`
 A *Block* is an ordered list of operations, concluding with a single
 [terminator operation](#terminator-operations). In [SSACFG
 regions](#control-flow-and-ssacfg-regions), each block represents a compiler
-[basic block] (https://en.wikipedia.org/wiki/Basic_block) where instructions
+[basic block](https://en.wikipedia.org/wiki/Basic_block) where instructions
 inside the block are executed in order and terminator operations implement
 control flow branches between basic blocks.
 
@@ -505,7 +505,7 @@ regions: [SSACFG 
regions](#control-flow-and-ssacfg-regions), which describe
 control flow between blocks, and [Graph regions](#graph-regions), which do not
 require control flow between block. The kinds of regions within an operation
 are described using the
-[RegionKindInterface](Interfaces.md#regionkindinterface).
+[RegionKindInterface](Interfaces.md#regionkindinterfaces).
 
 Regions do not have a name or an address, only the blocks contained in a
 region do. Regions must be contained within operations and have no type or
@@ -561,7 +561,7 @@ defined in a region can never be used outside of the region.
 ### Control Flow and SSACFG Regions
 
 In MLIR, control flow semantics of a region is indicated by
-[RegionKind::SSACFG](Interfaces.md#regionkindinterface).  Informally, these
+[RegionKind::SSACFG](Interfaces.md#regionkindinterfaces).  Informally, these
 regions support semantics where operations in a region 'execute
 sequentially'. Before an operation executes, its operands have well-defined
 values. After an operation executes, the operands have the same values and
@@ -647,7 +647,7 @@ directly used values remain live.
 ### Graph Regions
 
 In MLIR, graph-like semantics in a region is indicated by
-[RegionKind::Graph](Interfaces.md#regionkindinterface). Graph regions are
+[RegionKind::Graph](Interfaces.md#regionkindinterfaces). Graph regions are
 appropriate for concurrent semantics without control flow, or for modeling
 generic directed graph data structures. Graph regions are appropriate for
 representing cyclic relationships between coupled values where there is no
@@ -869,7 +869,7 @@ function-type ::= type-list-parens `->` function-result-type
 ```
 
 MLIR supports first-class functions: for example, the
-[`constant` operation](Dialects/Standard.md#constant-operation) produces the
+[`constant` operation](Dialects/Standard.md#stdconstant-constantop) produces 
the
 address of a function as a value. This value may be passed to and
 returned from functions, merged across control flow boundaries with
 [block arguments](#blocks), and called with the
@@ -888,10 +888,11 @@ index-type ::= `index`
 ```
 
 The `index` type is a signless integer whose size is equal to the natural
-machine word of the target 
([rationale](Rationale/Rationale.md#signless-types)) and is
-used by the affine constructs in MLIR

[llvm-branch-commits] [clang] 7793db3 - [OpenCL] Check for extension string extension lookup

[Fraser Cormack via llvm-branch-commits]

Author: Erik Tomusk
Date: 2020-11-27T13:16:39Z
New Revision: 7793db35ca2c1fe63687c0a7140cbec540a9aded

URL: 
https://github.com/llvm/llvm-project/commit/7793db35ca2c1fe63687c0a7140cbec540a9aded
DIFF: 
https://github.com/llvm/llvm-project/commit/7793db35ca2c1fe63687c0a7140cbec540a9aded.diff

LOG: [OpenCL] Check for extension string extension lookup

Calling any of the OpenCLOptions::is*() functions (except isKnown())
with an unknown extension string results in a seg fault. This patch
checks that the extension exists in the map before attempting to access
it.

Reviewed By: Anastasia

Differential Revision: https://reviews.llvm.org/D90928

Added: 


Modified: 
clang/include/clang/Basic/OpenCLOptions.h

Removed: 




diff  --git a/clang/include/clang/Basic/OpenCLOptions.h 
b/clang/include/clang/Basic/OpenCLOptions.h
index 15661154eab5..66dd06db5b83 100644
--- a/clang/include/clang/Basic/OpenCLOptions.h
+++ b/clang/include/clang/Basic/OpenCLOptions.h
@@ -32,38 +32,71 @@ class OpenCLOptions {
   };
   llvm::StringMap OptMap;
 public:
+  /// Check if \c Ext is a recognized OpenCL extension.
+  ///
+  /// \param Ext - Extension to look up.
+  /// \returns \c true if \c Ext is known, \c false otherwise.
   bool isKnown(llvm::StringRef Ext) const {
 return OptMap.find(Ext) != OptMap.end();
   }
 
+  /// Check if \c Ext is an enabled OpenCL extension.
+  ///
+  /// \param Ext - Extension to look up.
+  /// \returns \c true if \c Ext is known and enabled, \c false otherwise.
   bool isEnabled(llvm::StringRef Ext) const {
-return OptMap.find(Ext)->second.Enabled;
+auto E = OptMap.find(Ext);
+return E != OptMap.end() && E->second.Enabled;
   }
 
-  // Is supported as either an extension or an (optional) core feature for
-  // OpenCL version \p CLVer.
+  /// Check if \c Ext is supported as either an extension or an (optional) core
+  /// feature for the given OpenCL version.
+  ///
+  /// \param Ext - Extension to look up.
+  /// \param LO - \c LangOptions specifying the OpenCL version.
+  /// \returns \c true if \c Ext is known and supported, \c false otherwise.
   bool isSupported(llvm::StringRef Ext, const LangOptions &LO) const {
+auto E = OptMap.find(Ext);
+if (E == OptMap.end()) {
+  return false;
+}
 // In C++ mode all extensions should work at least as in v2.0.
 auto CLVer = LO.OpenCLCPlusPlus ? 200 : LO.OpenCLVersion;
-auto I = OptMap.find(Ext)->getValue();
+auto I = E->getValue();
 return I.Supported && I.Avail <= CLVer;
   }
 
-  // Is supported (optional) OpenCL core features for OpenCL version \p CLVer.
-  // For supported extension, return false.
+  /// Check if \c Ext is supported as an (optional) OpenCL core features for
+  /// the given OpenCL version.
+  ///
+  /// \param Ext - Extension to look up.
+  /// \param LO - \c LangOptions specifying the OpenCL version.
+  /// \returns \c true if \c Ext is known and supported, \c false otherwise.
   bool isSupportedCore(llvm::StringRef Ext, const LangOptions &LO) const {
+auto E = OptMap.find(Ext);
+if (E == OptMap.end()) {
+  return false;
+}
 // In C++ mode all extensions should work at least as in v2.0.
 auto CLVer = LO.OpenCLCPlusPlus ? 200 : LO.OpenCLVersion;
-auto I = OptMap.find(Ext)->getValue();
+auto I = E->getValue();
 return I.Supported && I.Avail <= CLVer && I.Core != ~0U && CLVer >= I.Core;
   }
 
-  // Is supported OpenCL extension for OpenCL version \p CLVer.
-  // For supported (optional) core feature, return false.
+  /// Check if \c Ext is a supported OpenCL extension for the given OpenCL
+  /// version.
+  ///
+  /// \param Ext - Extension to look up.
+  /// \param LO - \c LangOptions specifying the OpenCL version.
+  /// \returns \c true if \c Ext is known and supported, \c false otherwise.
   bool isSupportedExtension(llvm::StringRef Ext, const LangOptions &LO) const {
+auto E = OptMap.find(Ext);
+if (E == OptMap.end()) {
+  return false;
+}
 // In C++ mode all extensions should work at least as in v2.0.
 auto CLVer = LO.OpenCLCPlusPlus ? 200 : LO.OpenCLVersion;
-auto I = OptMap.find(Ext)->getValue();
+auto I = E->getValue();
 return I.Supported && I.Avail <= CLVer && (I.Core == ~0U || CLVer < 
I.Core);
   }
 



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[llvm-branch-commits] [llvm] a2016dc - [AArch64][SLP] Precommit tests which would be better not to SLP vectorize. NFC.

[Sjoerd Meijer via llvm-branch-commits]

Author: Sjoerd Meijer
Date: 2020-11-27T13:43:16Z
New Revision: a2016dc887c5fce33f5a41eefadf0b15a02b08b6

URL: 
https://github.com/llvm/llvm-project/commit/a2016dc887c5fce33f5a41eefadf0b15a02b08b6
DIFF: 
https://github.com/llvm/llvm-project/commit/a2016dc887c5fce33f5a41eefadf0b15a02b08b6.diff

LOG: [AArch64][SLP] Precommit tests which would be better not to SLP vectorize. 
NFC.

Added: 
llvm/test/Transforms/SLPVectorizer/AArch64/mul.ll

Modified: 


Removed: 




diff  --git a/llvm/test/Transforms/SLPVectorizer/AArch64/mul.ll 
b/llvm/test/Transforms/SLPVectorizer/AArch64/mul.ll
new file mode 100644
index ..228a4d773f0c
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/mul.ll
@@ -0,0 +1,108 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -basic-aa -slp-vectorizer -S | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64--linux-gnu"
+
+; These examples correspond to input code like:
+;
+;   void t(long * __restrict a, long * __restrict b) {
+; a[0] *= b[0];
+; a[1] *= b[1];
+;   }
+;
+; If we SLP vectorise this then we end up with something like this because we
+; don't have a mul.2d:
+;
+;ldr q0, [x1]
+;ldr q1, [x0]
+;fmovx8, d0
+;mov x10, v0.d[1]
+;fmovx9, d1
+;mov x11, v1.d[1]
+;mul x8, x9, x8
+;mul x9, x11, x10
+;fmovd0, x8
+;mov v0.d[1], x9
+;str q0, [x0]
+;ret
+;
+; but if we don't SLP vectorise these examples we get this which is smaller
+; and faster:
+;
+;ldp x8, x9, [x1]
+;ldp x10, x11, [x0]
+;mul x9, x11, x9
+;mul x8, x10, x8
+;stp x8, x9, [x0]
+;ret
+;
+; FIXME: don't SLP vectorise this.
+
+define void @mul(i64* noalias nocapture %a, i64* noalias nocapture readonly 
%b) {
+; CHECK-LABEL: @mul(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:[[ARRAYIDX2:%.*]] = getelementptr inbounds i64, i64* 
[[B:%.*]], i64 1
+; CHECK-NEXT:[[TMP0:%.*]] = bitcast i64* [[B]] to <2 x i64>*
+; CHECK-NEXT:[[TMP1:%.*]] = load <2 x i64>, <2 x i64>* [[TMP0]], align 8
+; CHECK-NEXT:[[ARRAYIDX3:%.*]] = getelementptr inbounds i64, i64* 
[[A:%.*]], i64 1
+; CHECK-NEXT:[[TMP2:%.*]] = bitcast i64* [[A]] to <2 x i64>*
+; CHECK-NEXT:[[TMP3:%.*]] = load <2 x i64>, <2 x i64>* [[TMP2]], align 8
+; CHECK-NEXT:[[TMP4:%.*]] = mul nsw <2 x i64> [[TMP3]], [[TMP1]]
+; CHECK-NEXT:[[TMP5:%.*]] = bitcast i64* [[A]] to <2 x i64>*
+; CHECK-NEXT:store <2 x i64> [[TMP4]], <2 x i64>* [[TMP5]], align 8
+; CHECK-NEXT:ret void
+;
+entry:
+  %0 = load i64, i64* %b, align 8
+  %1 = load i64, i64* %a, align 8
+  %mul = mul nsw i64 %1, %0
+  store i64 %mul, i64* %a, align 8
+  %arrayidx2 = getelementptr inbounds i64, i64* %b, i64 1
+  %2 = load i64, i64* %arrayidx2, align 8
+  %arrayidx3 = getelementptr inbounds i64, i64* %a, i64 1
+  %3 = load i64, i64* %arrayidx3, align 8
+  %mul4 = mul nsw i64 %3, %2
+  store i64 %mul4, i64* %arrayidx3, align 8
+  ret void
+}
+
+; Similar example, but now a multiply-accumulate:
+;
+;  void x (long * __restrict a, long * __restrict b) {
+;a[0] *= b[0];
+;a[1] *= b[1];
+;a[0] += b[0];
+;a[1] += b[1];
+;  }
+;
+define void @mac(i64* noalias nocapture %a, i64* noalias nocapture readonly 
%b) {
+; CHECK-LABEL: @mac(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:[[ARRAYIDX2:%.*]] = getelementptr inbounds i64, i64* 
[[B:%.*]], i64 1
+; CHECK-NEXT:[[TMP0:%.*]] = bitcast i64* [[B]] to <2 x i64>*
+; CHECK-NEXT:[[TMP1:%.*]] = load <2 x i64>, <2 x i64>* [[TMP0]], align 8
+; CHECK-NEXT:[[ARRAYIDX3:%.*]] = getelementptr inbounds i64, i64* 
[[A:%.*]], i64 1
+; CHECK-NEXT:[[TMP2:%.*]] = bitcast i64* [[A]] to <2 x i64>*
+; CHECK-NEXT:[[TMP3:%.*]] = load <2 x i64>, <2 x i64>* [[TMP2]], align 8
+; CHECK-NEXT:[[TMP4:%.*]] = mul nsw <2 x i64> [[TMP3]], [[TMP1]]
+; CHECK-NEXT:[[TMP5:%.*]] = add nsw <2 x i64> [[TMP4]], [[TMP1]]
+; CHECK-NEXT:[[TMP6:%.*]] = bitcast i64* [[A]] to <2 x i64>*
+; CHECK-NEXT:store <2 x i64> [[TMP5]], <2 x i64>* [[TMP6]], align 8
+; CHECK-NEXT:ret void
+;
+entry:
+  %0 = load i64, i64* %b, align 8
+  %1 = load i64, i64* %a, align 8
+  %mul = mul nsw i64 %1, %0
+  %arrayidx2 = getelementptr inbounds i64, i64* %b, i64 1
+  %2 = load i64, i64* %arrayidx2, align 8
+  %arrayidx3 = getelementptr inbounds i64, i64* %a, i64 1
+  %3 = load i64, i64* %arrayidx3, align 8
+  %mul4 = mul nsw i64 %3, %2
+  %add = add nsw i64 %mul, %0
+  store i64 %add, i64* %a, align 8
+  %add9 = add nsw i64 %mul4, %2
+  store i64 %add9, i64* %arrayidx3, align 8
+  ret void
+}



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[llvm-branch-commits] [clang] 0ce32a7 - Revert "[ASTMatchers] Matcher macros with params move params instead of copying"

[Hans Wennborg via llvm-branch-commits]

Author: Hans Wennborg
Date: 2020-11-27T14:51:27+01:00
New Revision: 0ce32a79825f307d2f46b8a5823489a67d6d072f

URL: 
https://github.com/llvm/llvm-project/commit/0ce32a79825f307d2f46b8a5823489a67d6d072f
DIFF: 
https://github.com/llvm/llvm-project/commit/0ce32a79825f307d2f46b8a5823489a67d6d072f.diff

LOG: Revert "[ASTMatchers] Matcher macros with params move params instead of 
copying"

This broke some clang matcher tests in 32-bit MSVC builds; see PR46781.

> Summary: Use move semantics instead of copying for AST Matchers with 
> parameters
>
> Reviewers: aaron.ballman, gribozavr2
>
> Reviewed By: gribozavr2
>
> Subscribers: cfe-commits
>
> Tags: #clang
>
> Differential Revision: https://reviews.llvm.org/D75096

This reverts commit 3e9a7b2ba470bbe9cf3de3e4b15ba09dcfd206aa.

Added: 


Modified: 
clang/include/clang/ASTMatchers/ASTMatchersMacros.h

Removed: 




diff  --git a/clang/include/clang/ASTMatchers/ASTMatchersMacros.h 
b/clang/include/clang/ASTMatchers/ASTMatchersMacros.h
index 45e8b1a88b81..7e01ab0c6ee9 100644
--- a/clang/include/clang/ASTMatchers/ASTMatchersMacros.h
+++ b/clang/include/clang/ASTMatchers/ASTMatchersMacros.h
@@ -134,8 +134,9 @@
   class matcher_##DefineMatcher##OverloadId##Matcher   
\
   : public ::clang::ast_matchers::internal::MatcherInterface {   
\
   public:  
\
-explicit matcher_##DefineMatcher##OverloadId##Matcher(ParamType A##Param)  
\
-: Param(std::move(A##Param)) {}
\
+explicit matcher_##DefineMatcher##OverloadId##Matcher( 
\
+ParamType const &A##Param) 
\
+: Param(A##Param) {}   
\
 bool matches(const Type &Node, 
\
  ::clang::ast_matchers::internal::ASTMatchFinder *Finder,  
\
  ::clang::ast_matchers::internal::BoundNodesTreeBuilder
\
@@ -146,13 +147,12 @@
   };   
\
   }
\
   inline ::clang::ast_matchers::internal::Matcher DefineMatcher( 
\
-  ParamType Param) {   
\
+  ParamType const &Param) {
\
 return ::clang::ast_matchers::internal::makeMatcher(   
\
-new internal::matcher_##DefineMatcher##OverloadId##Matcher(
\
-std::move(Param)));
\
+new internal::matcher_##DefineMatcher##OverloadId##Matcher(Param));
\
   }
\
-  typedef ::clang::ast_matchers::internal::Matcher ( 
\
-  &DefineMatcher##_Type##OverloadId)(ParamType Param); 
\
+  typedef ::clang::ast_matchers::internal::Matcher(  
\
+  &DefineMatcher##_Type##OverloadId)(ParamType const &Param);  
\
   inline bool internal::matcher_##DefineMatcher##OverloadId##Matcher::matches( 
\
   const Type &Node,
\
   ::clang::ast_matchers::internal::ASTMatchFinder *Finder, 
\
@@ -183,9 +183,9 @@
   class matcher_##DefineMatcher##OverloadId##Matcher   
\
   : public ::clang::ast_matchers::internal::MatcherInterface {   
\
   public:  
\
-matcher_##DefineMatcher##OverloadId##Matcher(ParamType1 A##Param1, 
\
- ParamType2 A##Param2) 
\
-: Param1(std::move(A##Param1)), Param2(std::move(A##Param2)) {}
\
+matcher_##DefineMatcher##OverloadId##Matcher(ParamType1 const &A##Param1,  
\
+ ParamType2 const &A##Param2)  
\
+: Param1(A##Param1), Param2(A##Param2) {}  
\
 bool matches(const Type &Node, 
\
  ::clang::ast_matchers::internal::ASTMatchFinder *Finder,  
\
  ::clang::ast_matchers::internal::BoundNodesTreeBuilder
\
@@ -197,14 +197,14 @@
   };   
\
   }
\
   inline ::clang::ast_matchers::internal::Matcher DefineMatcher( 
\
-  ParamType1 Param1, ParamType2 Param2) {  
\
+  ParamType1 const &Param1, ParamType2 const &Param2)

[llvm-branch-commits] [mlir] e4c74fd - Don't elide splat attributes during printing

[Tamas Berghammer via llvm-branch-commits]

Author: Tamas Berghammer
Date: 2020-11-27T14:42:26Z
New Revision: e4c74fd9ddd90fd269620c0c669455dbd6b29bb9

URL: 
https://github.com/llvm/llvm-project/commit/e4c74fd9ddd90fd269620c0c669455dbd6b29bb9
DIFF: 
https://github.com/llvm/llvm-project/commit/e4c74fd9ddd90fd269620c0c669455dbd6b29bb9.diff

LOG: Don't elide splat attributes during printing

A splat attribute have a single element during printing so we should
treat it as such when we decide if we elide it or not based on the flag
intended to elide large attributes.

Reviewed By: rriddle, mehdi_amini

Differential Revision: https://reviews.llvm.org/D92165

Added: 


Modified: 
mlir/lib/IR/AsmPrinter.cpp
mlir/test/IR/pretty-attributes.mlir

Removed: 




diff  --git a/mlir/lib/IR/AsmPrinter.cpp b/mlir/lib/IR/AsmPrinter.cpp
index 73d272cf5f22..9d3e26112200 100644
--- a/mlir/lib/IR/AsmPrinter.cpp
+++ b/mlir/lib/IR/AsmPrinter.cpp
@@ -158,7 +158,8 @@ OpPrintingFlags &OpPrintingFlags::useLocalScope() {
 /// Return if the given ElementsAttr should be elided.
 bool OpPrintingFlags::shouldElideElementsAttr(ElementsAttr attr) const {
   return elementsAttrElementLimit.hasValue() &&
- *elementsAttrElementLimit < int64_t(attr.getNumElements());
+ *elementsAttrElementLimit < int64_t(attr.getNumElements()) &&
+ !attr.isa();
 }
 
 /// Return the size limit for printing large ElementsAttr.

diff  --git a/mlir/test/IR/pretty-attributes.mlir 
b/mlir/test/IR/pretty-attributes.mlir
index e4e5b34f0a6d..d4ac8e773935 100644
--- a/mlir/test/IR/pretty-attributes.mlir
+++ b/mlir/test/IR/pretty-attributes.mlir
@@ -16,3 +16,6 @@
 
 // CHECK: opaque<"", "0xDEADBEEF"> : tensor<100xf32>
 "test.opaque_attr"() {foo.opaque_attr = opaque<"", "0xEBFE"> : tensor<100xf32> 
} : () -> ()
+
+// CHECK: dense<1> : tensor<3xi32>
+"test.dense_splat"() {foo.dense_attr = dense<1> : tensor<3xi32>} : () -> ()



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[llvm-branch-commits] [clang] ff8e8c1 - [AIX] Enabling vector type arguments and return for AIX

[Zarko Todorovski via llvm-branch-commits]

Author: Zarko Todorovski
Date: 2020-11-27T09:55:52-05:00
New Revision: ff8e8c1b14eafbcdc2778dcf1c9fc12c82f078d7

URL: 
https://github.com/llvm/llvm-project/commit/ff8e8c1b14eafbcdc2778dcf1c9fc12c82f078d7
DIFF: 
https://github.com/llvm/llvm-project/commit/ff8e8c1b14eafbcdc2778dcf1c9fc12c82f078d7.diff

LOG: [AIX] Enabling vector type arguments and return for AIX

This patch enables vector type arguments on AIX.  All non-aggregate Altivec 
vector types are 16bytes in size and are 16byte aligned.

Reviewed By: Xiangling_L

Differential Revision: https://reviews.llvm.org/D92117

Added: 
clang/test/CodeGen/aix-altivec.c

Modified: 
clang/lib/CodeGen/TargetInfo.cpp

Removed: 
clang/test/CodeGen/aix-vector.c



diff  --git a/clang/lib/CodeGen/TargetInfo.cpp 
b/clang/lib/CodeGen/TargetInfo.cpp
index 06b24c0384d8..3469bc6bf081 100644
--- a/clang/lib/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CodeGen/TargetInfo.cpp
@@ -4514,7 +4514,7 @@ ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy) 
const {
 return ABIArgInfo::getDirect();
 
   if (RetTy->isVectorType())
-llvm::report_fatal_error("vector type is not supported on AIX yet");
+return ABIArgInfo::getDirect();
 
   if (RetTy->isVoidType())
 return ABIArgInfo::getIgnore();
@@ -4533,7 +4533,7 @@ ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) 
const {
 return ABIArgInfo::getDirect();
 
   if (Ty->isVectorType())
-llvm::report_fatal_error("vector type is not supported on AIX yet");
+return ABIArgInfo::getDirect();
 
   if (isAggregateTypeForABI(Ty)) {
 // Records with non-trivial destructors/copy-constructors should not be
@@ -4558,7 +4558,7 @@ CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) 
const {
 Ty = CTy->getElementType();
 
   if (Ty->isVectorType())
-llvm::report_fatal_error("vector type is not supported on AIX yet");
+return CharUnits::fromQuantity(16);
 
   // If the structure contains a vector type, the alignment is 16.
   if (isRecordWithSIMDVectorType(getContext(), Ty))
@@ -4573,7 +4573,8 @@ Address AIXABIInfo::EmitVAArg(CodeGenFunction &CGF, 
Address VAListAddr,
 llvm::report_fatal_error("complex type is not supported on AIX yet");
 
   if (Ty->isVectorType())
-llvm::report_fatal_error("vector type is not supported on AIX yet");
+llvm::report_fatal_error(
+"vector types are not yet supported for variadic functions on AIX");
 
   auto TypeInfo = getContext().getTypeInfoInChars(Ty);
   TypeInfo.Align = getParamTypeAlignment(Ty);

diff  --git a/clang/test/CodeGen/aix-altivec.c 
b/clang/test/CodeGen/aix-altivec.c
new file mode 100644
index ..011aa47b6317
--- /dev/null
+++ b/clang/test/CodeGen/aix-altivec.c
@@ -0,0 +1,44 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-feature +altivec 
-target-cpu pwr8 -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-feature +altivec 
-target-cpu pwr8 -emit-llvm %s -o - | FileCheck %s
+vector float foo1(vector float x) { return x; }
+// CHECK:  define <4 x float> @foo1(<4 x float> %x) [[ATTR:#[0-9]+]] {
+// CHECK:  entry:
+// CHECK:%x.addr = alloca <4 x float>, align 16
+// CHECK:store <4 x float> %x, <4 x float>* %x.addr, align 16
+// CHECK:%0 = load <4 x float>, <4 x float>* %x.addr, align 16
+// CHECK:ret <4 x float> %0
+// CHECK:  }
+vector double foo2(vector double x) { return x; }
+// CHECK:  define <2 x double> @foo2(<2 x double> %x) [[ATTR]] {
+// CHECK:  entry:
+// CHECK:%x.addr = alloca <2 x double>, align 16
+// CHECK:store <2 x double> %x, <2 x double>* %x.addr, align 16
+// CHECK:%0 = load <2 x double>, <2 x double>* %x.addr, align 16
+// CHECK:ret <2 x double> %0
+// CHECK:  }
+vector int foo3(vector int x) { return x; }
+// CHECK:  define <4 x i32> @foo3(<4 x i32> %x) [[ATTR]] {
+// CHECK:  entry:
+// CHECK:%x.addr = alloca <4 x i32>, align 16
+// CHECK:store <4 x i32> %x, <4 x i32>* %x.addr, align 16
+// CHECK:%0 = load <4 x i32>, <4 x i32>* %x.addr, align 16
+// CHECK:ret <4 x i32> %0
+// CHECK:  }
+vector short int foo4(vector short int x) { return x; }
+// CHECK:  define <8 x i16> @foo4(<8 x i16> %x) [[ATTR]] {
+// CHECK:  entry:
+// CHECK:%x.addr = alloca <8 x i16>, align 16
+// CHECK:store <8 x i16> %x, <8 x i16>* %x.addr, align 16
+// CHECK:%0 = load <8 x i16>, <8 x i16>* %x.addr, align 16
+// CHECK:ret <8 x i16> %0
+// CHECK:  }
+vector char foo5(vector char x) { return x; }
+// CHECK:  define <16 x i8> @foo5(<16 x i8> %x) [[ATTR]] {
+// CHECK:  entry:
+// CHECK:%x.addr = alloca <16 x i8>, align 16
+// CHECK:store <16 x i8> %x, <16 x i8>* %x.addr, align 16
+// CHECK:%0 = load <16 x i8>, <16 x i8>* %x.addr, align 16
+// CHECK:ret <16 x i8> %0
+// CHECK:  }
+

diff  --git a/clang/test/CodeGen/aix-vector.c b/clang/test/CodeGen/aix-vector.c
deleted fil

[llvm-branch-commits] [llvm] 4c419c4 - [TableGen][SchedModels] Get rid of hasVariant. NFC

[Evgeny Leviant via llvm-branch-commits]

Author: Evgeny Leviant
Date: 2020-11-27T18:00:02+03:00
New Revision: 4c419c454ad255437331987dbd3ada6070432999

URL: 
https://github.com/llvm/llvm-project/commit/4c419c454ad255437331987dbd3ada6070432999
DIFF: 
https://github.com/llvm/llvm-project/commit/4c419c454ad255437331987dbd3ada6070432999.diff

LOG: [TableGen][SchedModels] Get rid of hasVariant. NFC

Differential revision: https://reviews.llvm.org/D92026

Added: 


Modified: 
llvm/utils/TableGen/CodeGenSchedule.cpp

Removed: 




diff  --git a/llvm/utils/TableGen/CodeGenSchedule.cpp 
b/llvm/utils/TableGen/CodeGenSchedule.cpp
index abb242018811..0851c0f321b8 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -1337,11 +1337,11 @@ class PredTransitions {
 
   PredTransitions(CodeGenSchedModels &sm): SchedModels(sm) {}
 
-  void substituteVariantOperand(const SmallVectorImpl &RWSeq,
+  bool substituteVariantOperand(const SmallVectorImpl &RWSeq,
 bool IsRead, bool IsForAnyCPU,
 unsigned StartIdx);
 
-  void substituteVariants(const PredTransition &Trans);
+  bool substituteVariants(const PredTransition &Trans);
 
 #ifndef NDEBUG
   void dump() const;
@@ -1436,22 +1436,6 @@ static bool hasAliasedVariants(const CodeGenSchedRW &RW,
   return false;
 }
 
-static bool hasVariant(ArrayRef Transitions,
-   CodeGenSchedModels &SchedModels) {
-  for (const PredTransition &PTI : Transitions) {
-for (const SmallVectorImpl &WSI : PTI.WriteSequences)
-  for (unsigned WI : WSI)
-if (hasAliasedVariants(SchedModels.getSchedWrite(WI), SchedModels))
-  return true;
-
-for (const SmallVectorImpl &RSI : PTI.ReadSequences)
-  for (unsigned RI : RSI)
-if (hasAliasedVariants(SchedModels.getSchedRead(RI), SchedModels))
-  return true;
-  }
-  return false;
-}
-
 static std::vector getAllPredicates(ArrayRef Variants,
   ArrayRef ProcIndices) {
   std::vector Preds;
@@ -1628,7 +1612,7 @@ pushVariant(const TransVariant &VInfo, bool IsRead) {
 // operand. StartIdx is an index into TransVec where partial results
 // starts. RWSeq must be applied to all transitions between StartIdx and the 
end
 // of TransVec.
-void PredTransitions::substituteVariantOperand(
+bool PredTransitions::substituteVariantOperand(
 const SmallVectorImpl &RWSeq, bool IsRead, bool IsForAnyCPU,
 unsigned StartIdx) {
 
@@ -1644,6 +1628,7 @@ void PredTransitions::substituteVariantOperand(
 return !IntersectingVariants.empty();
   };
 
+  bool Subst = false;
   // Visit each original RW within the current sequence.
   for (SmallVectorImpl::const_iterator
  RWI = RWSeq.begin(), RWE = RWSeq.end(); RWI != RWE; ++RWI) {
@@ -1664,6 +1649,7 @@ void PredTransitions::substituteVariantOperand(
   }
   HasAliases = true;
   WasPushed |= CollectAndAddVariants(TransIdx, SchedRW);
+  Subst |= WasPushed;
 }
 if (IsRead && IsForAnyCPU && HasAliases && !WasPushed) {
   // If we're here this means that in some sched class:
@@ -1678,9 +1664,10 @@ void PredTransitions::substituteVariantOperand(
   TransVec.reserve(TransVec.size() + 1);
   TransVec.emplace_back(TransVec[StartIdx].PredTerm);
   TransVec.back().ReadSequences.emplace_back();
-  CollectAndAddVariants(TransVec.size() - 1, SchedRW);
+  Subst |= CollectAndAddVariants(TransVec.size() - 1, SchedRW);
 }
   }
+  return Subst;
 }
 
 // For each variant of a Read/Write in Trans, substitute the sequence of
@@ -1689,10 +1676,11 @@ void PredTransitions::substituteVariantOperand(
 // predicates should result in linear growth in the total number variants.
 //
 // This is one step in a breadth-first search of nested variants.
-void PredTransitions::substituteVariants(const PredTransition &Trans) {
+bool PredTransitions::substituteVariants(const PredTransition &Trans) {
   // Build up a set of partial results starting at the back of
   // PredTransitions. Remember the first new transition.
   unsigned StartIdx = TransVec.size();
+  bool Subst = false;
   TransVec.emplace_back(Trans.PredTerm, Trans.ProcIndices);
 
   bool IsForAnyCPU = llvm::count(Trans.ProcIndices, 0);
@@ -1705,7 +1693,8 @@ void PredTransitions::substituteVariants(const 
PredTransition &Trans) {
TransVec.begin() + StartIdx, E = TransVec.end(); I != E; ++I) {
   I->WriteSequences.emplace_back();
 }
-substituteVariantOperand(*WSI, /*IsRead=*/false, IsForAnyCPU, StartIdx);
+Subst |=
+substituteVariantOperand(*WSI, /*IsRead=*/false, IsForAnyCPU, 
StartIdx);
   }
   // Visit each original read sequence.
   for (SmallVectorImpl>::const_iterator
@@ -1716,8 +1705,10 @@ void PredTransitions::substituteVariants(const 
PredTransition &Trans) {
TransVec.begin() + StartIdx, E = TransVec.end(); I != E; +

[llvm-branch-commits] [libcxxabi] 527a7fd - [libc++] Replace several uses of 0 by nullptr

[Louis Dionne via llvm-branch-commits]

Author: Bruce Mitchener
Date: 2020-11-27T10:00:21-05:00
New Revision: 527a7fdfbd7461e2aaa9eb279543c5d9dc8efa5a

URL: 
https://github.com/llvm/llvm-project/commit/527a7fdfbd7461e2aaa9eb279543c5d9dc8efa5a
DIFF: 
https://github.com/llvm/llvm-project/commit/527a7fdfbd7461e2aaa9eb279543c5d9dc8efa5a.diff

LOG: [libc++] Replace several uses of 0 by nullptr

Differential Revision: https://reviews.llvm.org/D43159

Added: 


Modified: 
libcxx/include/__locale
libcxx/include/__sso_allocator
libcxx/include/__string
libcxx/include/__threading_support
libcxx/include/algorithm
libcxx/include/bitset
libcxx/include/chrono
libcxx/include/fstream
libcxx/include/functional
libcxx/include/ios
libcxx/include/istream
libcxx/include/iterator
libcxx/include/locale
libcxx/include/memory
libcxx/include/regex
libcxx/include/sstream
libcxx/include/streambuf
libcxx/include/string
libcxx/include/strstream
libcxx/include/system_error
libcxx/include/valarray
libcxx/src/new.cpp
libcxxabi/src/stdlib_new_delete.cpp

Removed: 




diff  --git a/libcxx/include/__locale b/libcxx/include/__locale
index fd09206b6c5d..23ad424e3c0f 100644
--- a/libcxx/include/__locale
+++ b/libcxx/include/__locale
@@ -628,7 +628,7 @@ class _LIBCPP_TYPE_VIS ctype
 public:
 typedef char char_type;
 
-explicit ctype(const mask* __tab = 0, bool __del = false, size_t __refs = 
0);
+explicit ctype(const mask* __tab = nullptr, bool __del = false, size_t 
__refs = 0);
 
 _LIBCPP_INLINE_VISIBILITY
 bool is(mask __m, char_type __c) const

diff  --git a/libcxx/include/__sso_allocator b/libcxx/include/__sso_allocator
index 117b728f1499..c50ae24c9212 100644
--- a/libcxx/include/__sso_allocator
+++ b/libcxx/include/__sso_allocator
@@ -48,7 +48,7 @@ public:
 private:
 __sso_allocator& operator=(const __sso_allocator&);
 public:
-_LIBCPP_INLINE_VISIBILITY pointer allocate(size_type __n, typename 
__sso_allocator::const_pointer = 0)
+_LIBCPP_INLINE_VISIBILITY pointer allocate(size_type __n, typename 
__sso_allocator::const_pointer = nullptr)
 {
 if (!__allocated_ && __n <= _Np)
 {

diff  --git a/libcxx/include/__string b/libcxx/include/__string
index f9d02064401e..08be8f1a7641 100644
--- a/libcxx/include/__string
+++ b/libcxx/include/__string
@@ -268,7 +268,7 @@ char_traits<_CharT>::find(const char_type* __s, size_t __n, 
const char_type& __a
 return __s;
 ++__s;
 }
-return 0;
+return nullptr;
 }
 
 template 
@@ -683,7 +683,7 @@ char_traits::find(const char_type* __s, size_t 
__n, const char_type& __
 return __s;
 ++__s;
 }
-return 0;
+return nullptr;
 }
 
 #endif // #_LIBCPP_NO_HAS_CHAR8_T
@@ -765,7 +765,7 @@ char_traits::find(const char_type* __s, size_t 
__n, const char_type& _
 return __s;
 ++__s;
 }
-return 0;
+return nullptr;
 }
 
 inline _LIBCPP_CONSTEXPR_AFTER_CXX17
@@ -885,7 +885,7 @@ char_traits::find(const char_type* __s, size_t 
__n, const char_type& _
 return __s;
 ++__s;
 }
-return 0;
+return nullptr;
 }
 
 inline _LIBCPP_CONSTEXPR_AFTER_CXX17
@@ -943,7 +943,7 @@ __str_find(const _CharT *__p, _SizeT __sz,
 if (__pos >= __sz)
 return __npos;
 const _CharT* __r = _Traits::find(__p + __pos, __sz - __pos, __c);
-if (__r == 0)
+if (__r == nullptr)
 return __npos;
 return static_cast<_SizeT>(__r - __p);
 }
@@ -972,7 +972,7 @@ __search_substring(const _CharT *__first1, const _CharT 
*__last1,
 
 // Find __f2 the first byte matching in __first1.
 __first1 = _Traits::find(__first1, __len1 - __len2 + 1, __f2);
-if (__first1 == 0)
+if (__first1 == nullptr)
   return __last1;
 
 // It is faster to compare from the first byte of __first1 even if we
@@ -1095,7 +1095,7 @@ __str_find_first_not_of(const _CharT *__p, _SizeT __sz,
 {
 const _CharT* __pe = __p + __sz;
 for (const _CharT* __ps = __p + __pos; __ps != __pe; ++__ps)
-if (_Traits::find(__s, __n, *__ps) == 0)
+if (_Traits::find(__s, __n, *__ps) == nullptr)
 return static_cast<_SizeT>(__ps - __p);
 }
 return __npos;
@@ -1129,7 +1129,7 @@ __str_find_last_not_of(const _CharT *__p, _SizeT __sz,
 else
 __pos = __sz;
 for (const _CharT* __ps = __p + __pos; __ps != __p;)
-if (_Traits::find(__s, __n, *--__ps) == 0)
+if (_Traits::find(__s, __n, *--__ps) == nullptr)
 return static_cast<_SizeT>(__ps - __p);
 return __npos;
 }

diff  --git a/libcxx/include/__threading_support 
b/libcxx/include/__threading_support
index 85bb96bdc6ba..2d0ccf5cb244 100644
--- a/libcxx/include/__threading_support
+++ b/libcxx/include/__threading_support
@@ -497,13 +497,13 @@ bool __libcpp_thread_id_less(__libcpp_thread_id t1, 
__lib

[llvm-branch-commits] [libcxx] da1b50d - [libc++] Formalize what configurations are covered by the ABI lists

[Louis Dionne via llvm-branch-commits]

Author: Louis Dionne
Date: 2020-11-27T10:01:07-05:00
New Revision: da1b50d7df213a3eaf583d576b8d7d2ec77bd97f

URL: 
https://github.com/llvm/llvm-project/commit/da1b50d7df213a3eaf583d576b8d7d2ec77bd97f
DIFF: 
https://github.com/llvm/llvm-project/commit/da1b50d7df213a3eaf583d576b8d7d2ec77bd97f.diff

LOG: [libc++] Formalize what configurations are covered by the ABI lists

By encoding ABI-affecting properties in the name of the ABI list, it
makes it clear when an ABI list test should or should not be available,
and what results we should expect.

Note that we clearly don't encode all ABI-affecting parameters in the
name right now -- I just ported over what we supported in the code that
was there previously. As we encounter configurations that we wish to
support but produce different ABI lists, we can add those to the ABI
identifier and start supporting them.

This commit also starts checking the ABI list in the CI jobs that run
a supported configuration. Eventually, all configurations should have
a generated ABI list and the test should even run implicitly as part of
the Lit test suite.

Differential Revision: https://reviews.llvm.org/D92194

Added: 

libcxx/lib/abi/x86_64-apple-darwin.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist

libcxx/lib/abi/x86_64-unknown-linux-gnu.libcxxabi.v1.stable.exceptions.no_new_in_libcxx.abilist

Modified: 
libcxx/lib/abi/CMakeLists.txt
libcxx/utils/ci/run-buildbot

Removed: 
libcxx/lib/abi/x86_64-apple-darwin.v1.abilist
libcxx/lib/abi/x86_64-unknown-linux-gnu.v1.abilist



diff  --git a/libcxx/lib/abi/CMakeLists.txt b/libcxx/lib/abi/CMakeLists.txt
index 98cfe8bf1e14..e25c09b7a348 100644
--- a/libcxx/lib/abi/CMakeLists.txt
+++ b/libcxx/lib/abi/CMakeLists.txt
@@ -1,43 +1,75 @@
 
-if (DEFINED TARGET_TRIPLE)
-if (TARGET_TRIPLE MATCHES "darwin")
-# Ignore the major, minor, and patchlevel versions of darwin targets.
-string(REGEX REPLACE "darwin[0-9]+\\.[0-9]+\\.[0-9]+" "darwin"
-   GENERIC_TARGET_TRIPLE "${TARGET_TRIPLE}")
-elseif(TARGET_TRIPLE MATCHES "freebsd")
-# Ignore the major and minor versions of freebsd targets.
-string(REGEX REPLACE "freebsd[0-9]+\\.[0-9]+" "freebsd"
-   GENERIC_TARGET_TRIPLE "${TARGET_TRIPLE}")
-else()
-set(GENERIC_TARGET_TRIPLE "${TARGET_TRIPLE}")
-endif()
-endif()
+# This function generates a "unique" identifier based on various properties
+# given as arguments. The idea is to encode all ABI-affecting properties
+# in that identifier, so that we can store ABI information and associate it
+# to a specific ABI configuration.
+#
+# Right now, this is done by using the ABI identifier as the filename 
containing
+# the list of symbols exported by libc++ for that configuration, however we 
could
+# make it more sophisticated if the number of ABI-affecting parameters grew.
+function(cxx_abi_list_identifier result triple abi_library abi_version 
unstable exceptions new_delete_in_libcxx)
+  set(abi_properties)
+
+  if ("${triple}" MATCHES "darwin")
+# Ignore the major, minor, and patchlevel versions of darwin targets.
+string(REGEX REPLACE "darwin[0-9]+\\.[0-9]+\\.[0-9]+" "darwin" triple 
"${triple}")
+  elseif("${triple}" MATCHES "freebsd")
+# Ignore the major and minor versions of freebsd targets.
+string(REGEX REPLACE "freebsd[0-9]+\\.[0-9]+" "freebsd" triple "${triple}")
+  endif()
+  list(APPEND abi_properties "${triple}")
+  list(APPEND abi_properties "${abi_library}")
+  list(APPEND abi_properties "v${abi_version}")
+  if (${unstable})
+list(APPEND abi_properties "unstable")
+  else()
+list(APPEND abi_properties "stable")
+  endif()
+  if (${exceptions})
+list(APPEND abi_properties "exceptions")
+  else()
+list(APPEND abi_properties "noexceptions")
+  endif()
+  if (${new_delete_in_libcxx})
+list(APPEND abi_properties "new_in_libcxx")
+  else()
+list(APPEND abi_properties "no_new_in_libcxx")
+  endif()
+
+  list(JOIN abi_properties "." tmp)
+  set(${result} "${tmp}" PARENT_SCOPE)
+endfunction()
+
+cxx_abi_list_identifier(abi_list_identifier
+  "${TARGET_TRIPLE}"
+  "${LIBCXX_CXX_ABI_LIBNAME}"
+  "${LIBCXX_ABI_VERSION}"
+  "${LIBCXX_ABI_UNSTABLE}"
+  "${LIBCXX_ENABLE_EXCEPTIONS}"
+  "${LIBCXX_ENABLE_NEW_DELETE_DEFINITIONS}"
+)
+
+if (TARGET cxx_shared)
+  set(abi_list_file 
"${CMAKE_CURRENT_SOURCE_DIR}/${abi_list_identifier}.abilist")
 
-# Detect if we are building in the same configuration used to generate
-# the abilist files.
-set(ABILIST_FILE 
"${CMAKE_CURRENT_LIST_DIR}/${GENERIC_TARGET_TRIPLE}.v${LIBCXX_ABI_VERSION}.abilist")
-if (EXISTS "${ABILIST_FILE}"
-AND TARGET cxx_shared
-AND ("${LIBCXX_CXX_ABI_LIBNAME}" STREQUAL "libcxxabi" OR
- (APPLE AND "${LIBCXX_CXX_ABI_LIBNAME}" STREQUAL "default"))
-AND NOT LIBCXX_ABI_UNSTABLE
-AND LIBCXX_ENABLE_EXCEPTIONS
-AND NOT LIBCXX_ENABLE_NEW_DELETE_DEFINIT

[llvm-branch-commits] [openmp] 89a0f48 - [libomptarget][cuda] Detect missing symbols in plugin at build time

[Jon Chesterfield via llvm-branch-commits]

Author: Jon Chesterfield
Date: 2020-11-27T15:39:41Z
New Revision: 89a0f48c58f82262c7ce2b9ca51ffad0ffc559ea

URL: 
https://github.com/llvm/llvm-project/commit/89a0f48c58f82262c7ce2b9ca51ffad0ffc559ea
DIFF: 
https://github.com/llvm/llvm-project/commit/89a0f48c58f82262c7ce2b9ca51ffad0ffc559ea.diff

LOG: [libomptarget][cuda] Detect missing symbols in plugin at build time

[libomptarget][cuda] Detect missing symbols in plugin at build time

Passes -z,defs to the linker. Error on unresolved symbol references.

Otherwise, those unresolved symbols present as target code running on the host
as the plugin fails to load. This is significantly harder to debug than a link
time error. Flag matches that passed by amdgcn and ve plugins.

Reviewed By: tianshilei1992

Differential Revision: https://reviews.llvm.org/D92143

Added: 


Modified: 
openmp/libomptarget/plugins/cuda/CMakeLists.txt

Removed: 




diff  --git a/openmp/libomptarget/plugins/cuda/CMakeLists.txt 
b/openmp/libomptarget/plugins/cuda/CMakeLists.txt
index 54bcdf26e9e6..e0299b1f3270 100644
--- a/openmp/libomptarget/plugins/cuda/CMakeLists.txt
+++ b/openmp/libomptarget/plugins/cuda/CMakeLists.txt
@@ -39,7 +39,8 @@ install(TARGETS omptarget.rtl.cuda LIBRARY DESTINATION 
"${OPENMP_INSTALL_LIBDIR}
 target_link_libraries(omptarget.rtl.cuda
   ${LIBOMPTARGET_DEP_CUDA_DRIVER_LIBRARIES}
   ${LIBOMPTARGET_DEP_LIBELF_LIBRARIES}
-  "-Wl,--version-script=${CMAKE_CURRENT_SOURCE_DIR}/../exports")
+  "-Wl,--version-script=${CMAKE_CURRENT_SOURCE_DIR}/../exports"
+  "-Wl,-z,defs")
 
 # Report to the parent scope that we are building a plugin for CUDA.
 set(LIBOMPTARGET_SYSTEM_TARGETS "${LIBOMPTARGET_SYSTEM_TARGETS} 
nvptx64-nvidia-cuda" PARENT_SCOPE)



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[llvm-branch-commits] [llvm] c462846 - [Hexagon] Add HVX support for ISD::SMAX/SMIN/UMAX/UMIN instead of custom dag patterns

[Simon Pilgrim via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2020-11-27T15:46:11Z
New Revision: c4628460b74bcdc34041cd11a8959ca336637ee2

URL: 
https://github.com/llvm/llvm-project/commit/c4628460b74bcdc34041cd11a8959ca336637ee2
DIFF: 
https://github.com/llvm/llvm-project/commit/c4628460b74bcdc34041cd11a8959ca336637ee2.diff

LOG: [Hexagon] Add HVX support for ISD::SMAX/SMIN/UMAX/UMIN instead of custom 
dag patterns

Followup to D92112 now that I've learnt about HVX type splitting.

This is some necessary cleanup work for min/max ops to eventually help us move 
the add/sub sat patterns into DAGCombine - D91876.

Differential Revision: https://reviews.llvm.org/D92169

Added: 


Modified: 
llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
llvm/test/CodeGen/Hexagon/autohvx/minmax-128b.ll
llvm/test/CodeGen/Hexagon/autohvx/minmax-64b.ll

Removed: 




diff  --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 
b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index 0b06e6ec9a3a..f39c8e889043 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -102,6 +102,13 @@ HexagonTargetLowering::initializeHVXLowering() {
   setOperationAction(ISD::BSWAP,T, Legal);
 }
 
+setOperationAction(ISD::SMIN,   T, Legal);
+setOperationAction(ISD::SMAX,   T, Legal);
+if (T.getScalarType() != MVT::i32) {
+  setOperationAction(ISD::UMIN, T, Legal);
+  setOperationAction(ISD::UMAX, T, Legal);
+}
+
 setOperationAction(ISD::CTTZ,   T, Custom);
 setOperationAction(ISD::LOAD,   T, Custom);
 setOperationAction(ISD::MLOAD,  T, Custom);
@@ -183,6 +190,13 @@ HexagonTargetLowering::initializeHVXLowering() {
   // Promote all shuffles to operate on vectors of bytes.
   setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteW);
 }
+
+setOperationAction(ISD::SMIN, T, Custom);
+setOperationAction(ISD::SMAX, T, Custom);
+if (T.getScalarType() != MVT::i32) {
+  setOperationAction(ISD::UMIN,   T, Custom);
+  setOperationAction(ISD::UMAX,   T, Custom);
+}
   }
 
   // Boolean vectors.
@@ -2029,6 +2043,10 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, 
SelectionDAG &DAG) const {
   case ISD::SRA:
   case ISD::SHL:
   case ISD::SRL:
+  case ISD::SMIN:
+  case ISD::SMAX:
+  case ISD::UMIN:
+  case ISD::UMAX:
   case ISD::SETCC:
   case ISD::VSELECT:
   case ISD::SIGN_EXTEND:

diff  --git a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td 
b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
index e37cfe34fa0e..cd894c555adc 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
@@ -274,21 +274,6 @@ class Vneg1
 class Vnot
   : PatFrag<(ops node:$Vs), (xor $Vs, Vneg1)>;
 
-let Predicates = [UseHVX] in {
-  let AddedComplexity = 220 in {
-defm: MinMax_pats;
-defm: MinMax_pats;
-defm: MinMax_pats;
-defm: MinMax_pats;
-defm: MinMax_pats;
-defm: MinMax_pats;
-defm: MinMax_pats;
-defm: MinMax_pats;
-defm: MinMax_pats;
-defm: MinMax_pats;
-  }
-}
-
 let Predicates = [UseHVX] in {
   let AddedComplexity = 200 in {
 def: Pat<(Vnot   HVI8:$Vs), (V6_vnot HvxVR:$Vs)>;
@@ -318,6 +303,17 @@ let Predicates = [UseHVX] in {
   def: OpR_RR_pat;
   def: OpR_RR_pat;
 
+  def: OpR_RR_pat;
+  def: OpR_RR_pat;
+  def: OpR_RR_pat;
+  def: OpR_RR_pat;
+  def: OpR_RR_pat;
+  def: OpR_RR_pat;
+  def: OpR_RR_pat;
+  def: OpR_RR_pat;
+  def: OpR_RR_pat;
+  def: OpR_RR_pat;
+
   def: Pat<(vselect HQ8:$Qu, HVI8:$Vs, HVI8:$Vt),
(V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
   def: Pat<(vselect HQ16:$Qu, HVI16:$Vs, HVI16:$Vt),

diff  --git a/llvm/test/CodeGen/Hexagon/autohvx/minmax-128b.ll 
b/llvm/test/CodeGen/Hexagon/autohvx/minmax-128b.ll
index bd5ca331e750..e3f14966be33 100644
--- a/llvm/test/CodeGen/Hexagon/autohvx/minmax-128b.ll
+++ b/llvm/test/CodeGen/Hexagon/autohvx/minmax-128b.ll
@@ -3,7 +3,7 @@
 ; minb
 
 ; CHECK: test_00:
-; CHECK: v0.b = vmin(v1.b,v0.b)
+; CHECK: v0.b = vmin(v0.b,v1.b)
 define <128 x i8> @test_00(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp slt <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v0, <128 x i8> %v1
@@ -27,7 +27,7 @@ define <128 x i8> @test_02(<128 x i8> %v0, <128 x i8> %v1) #0 
{
 }
 
 ; CHECK: test_03:
-; CHECK: v0.b = vmin(v1.b,v0.b)
+; CHECK: v0.b = vmin(v0.b,v1.b)
 define <128 x i8> @test_03(<128 x i8> %v0, <128 x i8> %v1) #0 {
   %t0 = icmp sge <128 x i8> %v0, %v1
   %t1 = select <128 x i1> %t0, <128 x i8> %v1, <128 x i8> %v0
@@ -37,7 +37,7 @@ define <128 x i8> @test_03(<128 x i8> %v0, <128 x i8> %v1) #0 
{
 ; maxb
 
 ; CHECK: test_04:
-; CHECK: v0.b = vmax(v1.b,v0.b)
+; CHECK: v0.b = vmax(v0.b,v1.b)
 define <128 x i8> @te

[llvm-branch-commits] [llvm] 2ad2e91 - [X86] Add AVX2/AVX512 test coverage in sat-add.ll

[Simon Pilgrim via llvm-branch-commits]

Author: Simon Pilgrim
Date: 2020-11-27T16:11:02Z
New Revision: 2ad2e91016151b1f0a4bb0f98115f33f0d3b5766

URL: 
https://github.com/llvm/llvm-project/commit/2ad2e91016151b1f0a4bb0f98115f33f0d3b5766
DIFF: 
https://github.com/llvm/llvm-project/commit/2ad2e91016151b1f0a4bb0f98115f33f0d3b5766.diff

LOG: [X86] Add AVX2/AVX512 test coverage in sat-add.ll

Shows the failure to combine to uaddsat

Added: 


Modified: 
llvm/test/CodeGen/X86/sat-add.ll

Removed: 




diff  --git a/llvm/test/CodeGen/X86/sat-add.ll 
b/llvm/test/CodeGen/X86/sat-add.ll
index 72ccebedc7a8..1dae100e0994 100644
--- a/llvm/test/CodeGen/X86/sat-add.ll
+++ b/llvm/test/CodeGen/X86/sat-add.ll
@@ -1,7 +1,9 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2   | FileCheck %s 
--check-prefixes=ANY,SSE2
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.1 | FileCheck %s 
--check-prefixes=ANY,SSE4,SSE41
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.2 | FileCheck %s 
--check-prefixes=ANY,SSE4,SSE42
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2   | FileCheck %s 
--check-prefixes=ANY,SSE,SSE2
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.1 | FileCheck %s 
--check-prefixes=ANY,SSE,SSE4,SSE41
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.2 | FileCheck %s 
--check-prefixes=ANY,SSE,SSE4,SSE42
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2   | FileCheck %s 
--check-prefixes=ANY,AVX,AVX2
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vl | FileCheck %s 
--check-prefixes=ANY,AVX,AVX512
 
 ; There are at least 3 potential patterns corresponding to an unsigned 
saturated add: min, cmp with sum, cmp with not.
 ; Test each of those patterns with i8/i16/i32/i64.
@@ -360,11 +362,17 @@ define i64 
@unsigned_sat_variable_i64_using_cmp_notval(i64 %x, i64 %y) {
 }
 
 define <16 x i8> @unsigned_sat_constant_v16i8_using_min(<16 x i8> %x) {
-; ANY-LABEL: unsigned_sat_constant_v16i8_using_min:
-; ANY:   # %bb.0:
-; ANY-NEXT:pminub {{.*}}(%rip), %xmm0
-; ANY-NEXT:paddb {{.*}}(%rip), %xmm0
-; ANY-NEXT:retq
+; SSE-LABEL: unsigned_sat_constant_v16i8_using_min:
+; SSE:   # %bb.0:
+; SSE-NEXT:pminub {{.*}}(%rip), %xmm0
+; SSE-NEXT:paddb {{.*}}(%rip), %xmm0
+; SSE-NEXT:retq
+;
+; AVX-LABEL: unsigned_sat_constant_v16i8_using_min:
+; AVX:   # %bb.0:
+; AVX-NEXT:vpminub {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT:vpaddb {{.*}}(%rip), %xmm0, %xmm0
+; AVX-NEXT:retq
   %c = icmp ult <16 x i8> %x, 
   %s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> 
   %r = add <16 x i8> %s, 
@@ -372,10 +380,24 @@ define <16 x i8> 
@unsigned_sat_constant_v16i8_using_min(<16 x i8> %x) {
 }
 
 define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_sum(<16 x i8> %x) {
-; ANY-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum:
-; ANY:   # %bb.0:
-; ANY-NEXT:paddusb {{.*}}(%rip), %xmm0
-; ANY-NEXT:retq
+; SSE-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum:
+; SSE:   # %bb.0:
+; SSE-NEXT:paddusb {{.*}}(%rip), %xmm0
+; SSE-NEXT:retq
+;
+; AVX2-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum:
+; AVX2:   # %bb.0:
+; AVX2-NEXT:vpaddusb {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT:retq
+;
+; AVX512-LABEL: unsigned_sat_constant_v16i8_using_cmp_sum:
+; AVX512:   # %bb.0:
+; AVX512-NEXT:vpaddb {{.*}}(%rip), %xmm0, %xmm1
+; AVX512-NEXT:vpminub %xmm1, %xmm0, %xmm2
+; AVX512-NEXT:vpcmpeqb %xmm2, %xmm0, %xmm2
+; AVX512-NEXT:vpcmpeqd %xmm0, %xmm0, %xmm0
+; AVX512-NEXT:vpternlogq $222, %xmm2, %xmm1, %xmm0
+; AVX512-NEXT:retq
   %a = add <16 x i8> %x, 
   %c = icmp ugt <16 x i8> %x, %a
   %r = select <16 x i1> %c, <16 x i8> , <16 
x i8> %a
@@ -383,10 +405,23 @@ define <16 x i8> 
@unsigned_sat_constant_v16i8_using_cmp_sum(<16 x i8> %x) {
 }
 
 define <16 x i8> @unsigned_sat_constant_v16i8_using_cmp_notval(<16 x i8> %x) {
-; ANY-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval:
-; ANY:   # %bb.0:
-; ANY-NEXT:paddusb {{.*}}(%rip), %xmm0
-; ANY-NEXT:retq
+; SSE-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval:
+; SSE:   # %bb.0:
+; SSE-NEXT:paddusb {{.*}}(%rip), %xmm0
+; SSE-NEXT:retq
+;
+; AVX2-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval:
+; AVX2:   # %bb.0:
+; AVX2-NEXT:vpaddusb {{.*}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT:retq
+;
+; AVX512-LABEL: unsigned_sat_constant_v16i8_using_cmp_notval:
+; AVX512:   # %bb.0:
+; AVX512-NEXT:vpaddb {{.*}}(%rip), %xmm0, %xmm1
+; AVX512-NEXT:vpmaxub {{.*}}(%rip), %xmm0, %xmm2
+; AVX512-NEXT:vpcmpeqb %xmm2, %xmm0, %xmm0
+; AVX512-NEXT:vpor %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:retq
   %a = add <16 x i8> %x, 
   %c = icmp ugt <16 x i8> %x, 
   %r = select <16 x i1> %c, <16 x i8> , <16 
x i8> %a
@@ -407,6 +442,12 @@ define <8 x i16> @unsigned_sat_constant_v8i16_using_min(<8 
x i16> %x) {
 ; SSE4-NEXT:pminuw {{.*}}(%rip), %xmm0
 ; SSE4-NEXT:padd

[llvm-branch-commits] [llvm] 8e0148d - [AllocaInst] Update `getAllocationSizeInBits` to return `TypeSize`.

[Francesco Petrogalli via llvm-branch-commits]

Author: Francesco Petrogalli
Date: 2020-11-27T16:39:10Z
New Revision: 8e0148dff703dd1ff12cc143482274233a8dacf3

URL: 
https://github.com/llvm/llvm-project/commit/8e0148dff703dd1ff12cc143482274233a8dacf3
DIFF: 
https://github.com/llvm/llvm-project/commit/8e0148dff703dd1ff12cc143482274233a8dacf3.diff

LOG: [AllocaInst] Update `getAllocationSizeInBits` to return `TypeSize`.

Reviewed By: peterwaller-arm, sdesmalen

Differential Revision: https://reviews.llvm.org/D92020

Added: 


Modified: 
llvm/include/llvm/IR/Instructions.h
llvm/lib/IR/Instructions.cpp
llvm/lib/Transforms/Coroutines/CoroFrame.cpp
llvm/unittests/IR/InstructionsTest.cpp

Removed: 




diff  --git a/llvm/include/llvm/IR/Instructions.h 
b/llvm/include/llvm/IR/Instructions.h
index ea1a60d52c87..eb855972256b 100644
--- a/llvm/include/llvm/IR/Instructions.h
+++ b/llvm/include/llvm/IR/Instructions.h
@@ -106,7 +106,7 @@ class AllocaInst : public UnaryInstruction {
 
   /// Get allocation size in bits. Returns None if size can't be determined,
   /// e.g. in case of a VLA.
-  Optional getAllocationSizeInBits(const DataLayout &DL) const;
+  Optional getAllocationSizeInBits(const DataLayout &DL) const;
 
   /// Return the type that is being allocated by the instruction.
   Type *getAllocatedType() const { return AllocatedType; }

diff  --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp
index ee667cfc42e8..10427b22d5d7 100644
--- a/llvm/lib/IR/Instructions.cpp
+++ b/llvm/lib/IR/Instructions.cpp
@@ -49,13 +49,14 @@ using namespace llvm;
 //AllocaInst Class
 
//===--===//
 
-Optional
+Optional
 AllocaInst::getAllocationSizeInBits(const DataLayout &DL) const {
-  uint64_t Size = DL.getTypeAllocSizeInBits(getAllocatedType());
+  TypeSize Size = DL.getTypeAllocSizeInBits(getAllocatedType());
   if (isArrayAllocation()) {
 auto *C = dyn_cast(getArraySize());
 if (!C)
   return None;
+assert(!Size.isScalable() && "Array elements cannot have a scalable size");
 Size *= C->getZExtValue();
   }
   return Size;

diff  --git a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp 
b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
index 204fb5d8f4c7..1a000c1913c6 100644
--- a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
+++ b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
@@ -576,9 +576,10 @@ void FrameTypeBuilder::addFieldForAllocas(const Function 
&F,
 StackLifetimeAnalyzer.getLiveRange(AI2));
   };
   auto GetAllocaSize = [&](const AllocaInfo &A) {
-Optional RetSize = A.Alloca->getAllocationSizeInBits(DL);
-assert(RetSize && "We can't handle scalable type now.\n");
-return RetSize.getValue();
+Optional RetSize = A.Alloca->getAllocationSizeInBits(DL);
+assert(RetSize && "Variable Length Arrays (VLA) are not supported.\n");
+assert(!RetSize->isScalable() && "Scalable vectors are not yet supported");
+return RetSize->getFixedSize();
   };
   // Put larger allocas in the front. So the larger allocas have higher
   // priority to merge, which can save more space potentially. Also each

diff  --git a/llvm/unittests/IR/InstructionsTest.cpp 
b/llvm/unittests/IR/InstructionsTest.cpp
index 93801b84e73f..dfd292ff60bb 100644
--- a/llvm/unittests/IR/InstructionsTest.cpp
+++ b/llvm/unittests/IR/InstructionsTest.cpp
@@ -1400,5 +1400,45 @@ TEST(InstructionsTest, BranchWeightOverflow) {
   ASSERT_EQ(ProfWeight, UINT32_MAX);
 }
 
+TEST(InstructionsTest, AllocaInst) {
+  LLVMContext Ctx;
+  std::unique_ptr M = parseIR(Ctx, R"(
+  %T = type { i64, [3 x i32]}
+  define void @f(i32 %n) {
+  entry:
+%A = alloca i32, i32 1
+%B = alloca i32, i32 4
+%C = alloca i32, i32 %n
+%D = alloca <8 x double>
+%E = alloca 
+%F = alloca [2 x half]
+%G = alloca [2 x [3 x i128]]
+%H = alloca %T
+ret void
+  }
+)");
+  const DataLayout &DL = M->getDataLayout();
+  ASSERT_TRUE(M);
+  Function *Fun = cast(M->getNamedValue("f"));
+  BasicBlock &BB = Fun->front();
+  auto It = BB.begin();
+  AllocaInst &A = cast(*It++);
+  AllocaInst &B = cast(*It++);
+  AllocaInst &C = cast(*It++);
+  AllocaInst &D = cast(*It++);
+  AllocaInst &E = cast(*It++);
+  AllocaInst &F = cast(*It++);
+  AllocaInst &G = cast(*It++);
+  AllocaInst &H = cast(*It++);
+  EXPECT_EQ(A.getAllocationSizeInBits(DL), TypeSize::getFixed(32));
+  EXPECT_EQ(B.getAllocationSizeInBits(DL), TypeSize::getFixed(128));
+  EXPECT_FALSE(C.getAllocationSizeInBits(DL));
+  EXPECT_EQ(D.getAllocationSizeInBits(DL), TypeSize::getFixed(512));
+  EXPECT_EQ(E.getAllocationSizeInBits(DL), TypeSize::getScalable(512));
+  EXPECT_EQ(F.getAllocationSizeInBits(DL), TypeSize::getFixed(32));
+  EXPECT_EQ(G.getAllocationSizeInBits(DL), TypeSize::getFixed(768));
+  EXPECT_EQ(H.getAllocationSizeInBits(DL), TypeSize::getFixed(

[llvm-branch-commits] [llvm] ae00879 - [VPlan] Use VPTransformState::set in widenGEP.

[Florian Hahn via llvm-branch-commits]

Author: Florian Hahn
Date: 2020-11-27T17:01:55Z
New Revision: ae008798a42943da709aaedb32936217422e2a6b

URL: 
https://github.com/llvm/llvm-project/commit/ae008798a42943da709aaedb32936217422e2a6b
DIFF: 
https://github.com/llvm/llvm-project/commit/ae008798a42943da709aaedb32936217422e2a6b.diff

LOG: [VPlan] Use VPTransformState::set in widenGEP.

This patch updates widenGEP to manage the resulting vector values using
the VPValue of VPWidenGEP recipe.

Added: 


Modified: 
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Removed: 




diff  --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp 
b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index d72c18061b82..0f519d136b31 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -4322,7 +4322,7 @@ void InnerLoopVectorizer::widenGEP(GetElementPtrInst 
*GEP, VPValue *VPDef,
 auto *Clone = Builder.Insert(GEP->clone());
 for (unsigned Part = 0; Part < UF; ++Part) {
   Value *EntryPart = Builder.CreateVectorSplat(VF, Clone);
-  VectorLoopValueMap.setVectorValue(GEP, Part, EntryPart);
+  State.set(VPDef, GEP, EntryPart, Part);
   addMetadata(EntryPart, GEP);
 }
   } else {
@@ -4359,7 +4359,7 @@ void InnerLoopVectorizer::widenGEP(GetElementPtrInst 
*GEP, VPValue *VPDef,
   : Builder.CreateGEP(GEP->getSourceElementType(), Ptr, Indices);
   assert((VF.isScalar() || NewGEP->getType()->isVectorTy()) &&
  "NewGEP is not a pointer vector");
-  VectorLoopValueMap.setVectorValue(GEP, Part, NewGEP);
+  State.set(VPDef, GEP, NewGEP, Part);
   addMetadata(NewGEP, GEP);
 }
   }



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[llvm-branch-commits] [llvm] fa39b9e - TargetProcessControl.cpp - Remove warning: extra ‘;’

[Sylvestre Ledru via llvm-branch-commits]

Author: Sylvestre Ledru
Date: 2020-11-27T18:19:58+01:00
New Revision: fa39b9eab1fed1dfe53444afd7eccc02f7d03015

URL: 
https://github.com/llvm/llvm-project/commit/fa39b9eab1fed1dfe53444afd7eccc02f7d03015
DIFF: 
https://github.com/llvm/llvm-project/commit/fa39b9eab1fed1dfe53444afd7eccc02f7d03015.diff

LOG: TargetProcessControl.cpp - Remove warning: extra ‘;’

Added: 


Modified: 
llvm/lib/ExecutionEngine/Orc/TargetProcessControl.cpp

Removed: 




diff  --git a/llvm/lib/ExecutionEngine/Orc/TargetProcessControl.cpp 
b/llvm/lib/ExecutionEngine/Orc/TargetProcessControl.cpp
index bbbc2d60d936..78fc5a69d46b 100644
--- a/llvm/lib/ExecutionEngine/Orc/TargetProcessControl.cpp
+++ b/llvm/lib/ExecutionEngine/Orc/TargetProcessControl.cpp
@@ -110,7 +110,7 @@ SelfTargetProcessControl::runWrapper(JITTargetAddress 
WrapperFnAddr,
   tpctypes::CWrapperFunctionResult (*)(const uint8_t *Data, uint64_t Size);
   auto *WrapperFn = jitTargetAddressToFunction(WrapperFnAddr);
   return WrapperFn(ArgBuffer.data(), ArgBuffer.size());
-};
+}
 
 Error SelfTargetProcessControl::disconnect() { return Error::success(); }
 



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[llvm-branch-commits] [clang] a4b80ef - [AArch64] Define __ARM_FEATURE_{CRC32, ATOMICS}

[Andre Vieira via llvm-branch-commits]

Author: Andre Vieira
Date: 2020-11-27T17:42:43Z
New Revision: a4b80efea98fc0b6421db40f9718c5c369fecec0

URL: 
https://github.com/llvm/llvm-project/commit/a4b80efea98fc0b6421db40f9718c5c369fecec0
DIFF: 
https://github.com/llvm/llvm-project/commit/a4b80efea98fc0b6421db40f9718c5c369fecec0.diff

LOG: [AArch64] Define __ARM_FEATURE_{CRC32,ATOMICS}

This patch implements the definition of __ARM_FEATURE_ATOMICS and fixes the
missing definition of __ARM_FEATURE_CRC32 for Armv8.1-A.

Differential Revision: https://reviews.llvm.org/D91438

Added: 


Modified: 
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/AArch64.h
clang/test/Preprocessor/aarch64-target-features.c

Removed: 




diff  --git a/clang/lib/Basic/Targets/AArch64.cpp 
b/clang/lib/Basic/Targets/AArch64.cpp
index 37f0212b7001..6282abca1326 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -155,8 +155,9 @@ void AArch64TargetInfo::fillValidCPUList(
 
 void AArch64TargetInfo::getTargetDefinesARMV81A(const LangOptions &Opts,
 MacroBuilder &Builder) const {
-  // FIXME: Armv8.1 makes __ARM_FEATURE_CRC32 mandatory. Handle it here.
   Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
+  Builder.defineMacro("__ARM_FEATURE_ATOMICS", "1");
+  Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
 }
 
 void AArch64TargetInfo::getTargetDefinesARMV82A(const LangOptions &Opts,
@@ -176,8 +177,6 @@ void AArch64TargetInfo::getTargetDefinesARMV83A(const 
LangOptions &Opts,
 void AArch64TargetInfo::getTargetDefinesARMV84A(const LangOptions &Opts,
 MacroBuilder &Builder) const {
   // Also include the Armv8.3 defines
-  // FIXME: Armv8.4 makes __ARM_FEATURE_ATOMICS, defined in GCC, mandatory.
-  // Add and handle it here.
   getTargetDefinesARMV83A(Opts, Builder);
 }
 
@@ -304,6 +303,9 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions 
&Opts,
   if (HasMatMul)
 Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
 
+  if (HasLSE)
+Builder.defineMacro("__ARM_FEATURE_ATOMICS", "1");
+
   if (HasBFloat16) {
 Builder.defineMacro("__ARM_FEATURE_BF16", "1");
 Builder.defineMacro("__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", "1");
@@ -418,6 +420,7 @@ bool 
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
   HasSVE2BitPerm = false;
   HasMatmulFP64 = false;
   HasMatmulFP32 = false;
+  HasLSE = false;
 
   ArchKind = llvm::AArch64::ArchKind::ARMV8A;
 
@@ -499,6 +502,8 @@ bool 
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
   HasMatMul = true;
 if (Feature == "+bf16")
   HasBFloat16 = true;
+if (Feature == "+lse")
+  HasLSE = true;
   }
 
   setDataLayout();

diff  --git a/clang/lib/Basic/Targets/AArch64.h 
b/clang/lib/Basic/Targets/AArch64.h
index d1982897d84e..a70abb7bfd90 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -44,6 +44,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public 
TargetInfo {
   bool HasSVE2BitPerm;
   bool HasMatmulFP64;
   bool HasMatmulFP32;
+  bool HasLSE;
 
   llvm::AArch64::ArchKind ArchKind;
 

diff  --git a/clang/test/Preprocessor/aarch64-target-features.c 
b/clang/test/Preprocessor/aarch64-target-features.c
index af4f6a1c0e0e..f0b01f519a85 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -62,6 +62,8 @@
 // RUN: %clang -target arm64-none-linux-gnu -mcrc -x c -E -dM %s -o - | 
FileCheck --check-prefix=CHECK-CRC32 %s
 // RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+crc -x c -E -dM 
%s -o - | FileCheck --check-prefix=CHECK-CRC32 %s
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+crc -x c -E -dM %s 
-o - | FileCheck --check-prefix=CHECK-CRC32 %s
+// RUN: %clang -target aarch64-none-linux-gnu -march=armv8.1-a -x c -E -dM %s 
-o - | FileCheck --check-prefix=CHECK-CRC32 %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8.1-a -x c -E -dM %s -o 
- | FileCheck --check-prefix=CHECK-CRC32 %s
 // CHECK-CRC32: __ARM_FEATURE_CRC32 1
 
 // RUN: %clang -target aarch64-none-linux-gnu -fno-math-errno 
-fno-signed-zeros\
@@ -447,3 +449,10 @@
 // RUN: %clang -target aarch64-arm-none-eabi -march=armv8-a+sve 
-msve-vector-bits=2048 -x c -E -dM %s -o - 2>&1 | FileCheck 
-check-prefix=CHECK-SVE-VECTOR-BITS -D#VBITS=2048 %s
 // CHECK-SVE-VECTOR-BITS: __ARM_FEATURE_SVE_BITS [[#VBITS:]]
 // CHECK-SVE-VECTOR-BITS: __ARM_FEATURE_SVE_VECTOR_OPERATORS 1
+
+// == Check Largse System Extensions (LSE)
+// RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+lse -x c -E -dM 
%s -o - | FileCheck --check-prefix=CHECK-LSE %s
+// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+lse -x c -E -dM %s 
-o - | FileCheck --check-prefix=CHECK-LSE %s
+// RUN: %clang -target aarch64-none-linux-gnu -march=

[llvm-branch-commits] [lld] a0994cb - lld-link: Let LLD_REPRODUCE control /reproduce:, like in ld.lld

[Nico Weber via llvm-branch-commits]

Author: Nico Weber
Date: 2020-11-27T13:33:55-05:00
New Revision: a0994cbe2799bf4ec5bc6d72b4fb1e0fe638972f

URL: 
https://github.com/llvm/llvm-project/commit/a0994cbe2799bf4ec5bc6d72b4fb1e0fe638972f
DIFF: 
https://github.com/llvm/llvm-project/commit/a0994cbe2799bf4ec5bc6d72b4fb1e0fe638972f.diff

LOG: lld-link: Let LLD_REPRODUCE control /reproduce:, like in ld.lld

Also sync help texts for the option between elf and coff ports.

Decisions:
- Do this even if /lldignoreenv is passed. /reproduce: does not affect
  the main output, and this makes the env var more convenient to use.
  (On the other hand, it's now possible to set this env var and forget
  about it, and all future builds in the same shell will be much slower.
  That's true for ld.lld, but posix shells have an easy way to set an
  env var for a single command; in cmd.exe this is not possible without
  contortions. Then again, lld-link runs in posix shells too.)

Original patch rebased across D68378 and D68381.

Differential Revision: https://reviews.llvm.org/D67707

Added: 


Modified: 
lld/COFF/Driver.cpp
lld/COFF/Options.td
lld/ELF/Options.td
lld/test/COFF/linkrepro.test

Removed: 




diff  --git a/lld/COFF/Driver.cpp b/lld/COFF/Driver.cpp
index d52abd100375..35b253ded3ec 100644
--- a/lld/COFF/Driver.cpp
+++ b/lld/COFF/Driver.cpp
@@ -1188,6 +1188,11 @@ Optional getReproduceFile(const 
opt::InputArgList &args) {
 return std::string(path);
   }
 
+  // This is intentionally not guarded by OPT_lldignoreenv since writing
+  // a repro tar file doesn't affect the main output.
+  if (auto *path = getenv("LLD_REPRODUCE"))
+return std::string(path);
+
   return None;
 }
 

diff  --git a/lld/COFF/Options.td b/lld/COFF/Options.td
index a694c671f9cd..2b8e65587ad7 100644
--- a/lld/COFF/Options.td
+++ b/lld/COFF/Options.td
@@ -58,8 +58,9 @@ def implib  : P<"implib", "Import library name">;
 def lib : F<"lib">,
 HelpText<"Act like lib.exe; must be first argument if present">;
 def libpath : P<"libpath", "Additional library search path">;
-def linkrepro : P<"linkrepro",
-"Dump linker invocation and input files for debugging">;
+def linkrepro : Joined<["/", "-", "/?", "-?"], "linkrepro:">,
+MetaVarName<"directory">,
+HelpText<"Write repro.tar containing inputs and command to reproduce 
link">;
 def lldignoreenv : F<"lldignoreenv">,
 HelpText<"Ignore environment variables like %LIB%">;
 def lldltocache : P<"lldltocache",
@@ -135,8 +136,9 @@ def noentry : F<"noentry">,
 def profile : F<"profile">;
 def repro : F<"Brepro">,
 HelpText<"Use a hash of the executable as the PE header timestamp">;
-def reproduce : P<"reproduce",
-"Dump linker invocation and input files for debugging">;
+def reproduce : Joined<["/", "-", "/?", "-?"], "reproduce:">,
+MetaVarName<"filename">,
+HelpText<"Write tar file containing inputs and command to reproduce link">;
 def swaprun : P<"swaprun",
   "Comma-separated list of 'cd' or 'net'">;
 def swaprun_cd : F<"swaprun:cd">, Alias, AliasArgs<["cd"]>,
@@ -200,7 +202,7 @@ def help_q : Flag<["/??", "-??", "/?", "-?"], "">, 
Alias;
 defm auto_import : B_priv<"auto-import">;
 defm runtime_pseudo_reloc : B_priv<"runtime-pseudo-reloc">;
 def end_lib : F<"end-lib">,
-  HelpText<"Ends group of objects treated as if they were in a library">;
+  HelpText<"End group of objects treated as if they were in a library">;
 def exclude_all_symbols : F<"exclude-all-symbols">;
 def export_all_symbols : F<"export-all-symbols">;
 defm demangle : B<"demangle",
@@ -218,7 +220,7 @@ def pdb_source_path : P<"pdbsourcepath",
 def rsp_quoting : Joined<["--"], "rsp-quoting=">,
   HelpText<"Quoting style for response files, 'windows' (default) or 'posix'">;
 def start_lib : F<"start-lib">,
-  HelpText<"Starts group of objects treated as if they were in a library">;
+  HelpText<"Start group of objects treated as if they were in a library">;
 def thinlto_emit_imports_files :
 F<"thinlto-emit-imports-files">,
 HelpText<"Emit .imports files with -thinlto-index-only">;

diff  --git a/lld/ELF/Options.td b/lld/ELF/Options.td
index db1c5d969842..f81f13d4d445 100644
--- a/lld/ELF/Options.td
+++ b/lld/ELF/Options.td
@@ -340,7 +340,9 @@ def push_state: F<"push-state">,
 def print_map: F<"print-map">,
   HelpText<"Print a link map to the standard output">;
 
-defm reproduce: Eq<"reproduce", "Write a tar file containing input files and 
command line options to reproduce link">;
+defm reproduce:
+  Eq<"reproduce",
+ "Write tar file containing inputs and command to reproduce link">;
 
 defm rosegment: BB<"rosegment",
   "Put read-only non-executable sections in their own segment (default)",

diff  --git a/lld/test/COFF/linkrepro.test b/lld/test/COFF/linkrepro.test
index 9a1db6e26369..29208fd6652a 100644
--- a/lld/test/COFF/linkrepro.test
+++ b/lld/test/COFF/linkrepro.test
@@ -1,7 +1,7 @@
 # REQUIRES: x86, shell
 
 # RUN: rm -rf 

[llvm-branch-commits] [llvm] 8517796 - [AIX][XCOFF][NFC] Change geNumberOfVRSaved function name to getNumberOfVRSaved.

[via llvm-branch-commits]

Author: diggerlin
Date: 2020-11-27T13:37:43-05:00
New Revision: 851779652a3b5da7dff0a1ddecd6a64a7ef1eea7

URL: 
https://github.com/llvm/llvm-project/commit/851779652a3b5da7dff0a1ddecd6a64a7ef1eea7
DIFF: 
https://github.com/llvm/llvm-project/commit/851779652a3b5da7dff0a1ddecd6a64a7ef1eea7.diff

LOG: [AIX][XCOFF][NFC] Change geNumberOfVRSaved function name to 
getNumberOfVRSaved.

SUMMARY:

  Change geNumberOfVRSaved function name to getNumberOfVRSaved of class 
TBVectorExt

Reviewers: hubert.reinterpretcast, Jason Liu
Differential Revision: https://reviews.llvm.org/D92225

Added: 


Modified: 
llvm/include/llvm/Object/XCOFFObjectFile.h
llvm/lib/Object/XCOFFObjectFile.cpp
llvm/unittests/Object/XCOFFObjectFileTest.cpp

Removed: 




diff  --git a/llvm/include/llvm/Object/XCOFFObjectFile.h 
b/llvm/include/llvm/Object/XCOFFObjectFile.h
index ba1df5e8dc0a..1ac00ed5e2c7 100644
--- a/llvm/include/llvm/Object/XCOFFObjectFile.h
+++ b/llvm/include/llvm/Object/XCOFFObjectFile.h
@@ -404,7 +404,7 @@ class TBVectorExt {
   TBVectorExt(StringRef TBvectorStrRef);
 
 public:
-  uint8_t geNumberOfVRSaved() const;
+  uint8_t getNumberOfVRSaved() const;
   bool isVRSavedOnStack() const;
   bool hasVarArgs() const;
   uint8_t getNumberOfVectorParms() const;

diff  --git a/llvm/lib/Object/XCOFFObjectFile.cpp 
b/llvm/lib/Object/XCOFFObjectFile.cpp
index 1a8afe4c95a4..e908096969aa 100644
--- a/llvm/lib/Object/XCOFFObjectFile.cpp
+++ b/llvm/lib/Object/XCOFFObjectFile.cpp
@@ -854,7 +854,7 @@ TBVectorExt::TBVectorExt(StringRef TBvectorStrRef) {
 #define GETVALUEWITHMASK(X) (Data & (TracebackTable::X))
 #define GETVALUEWITHMASKSHIFT(X, S)
\
   ((Data & (TracebackTable::X)) >> (TracebackTable::S))
-uint8_t TBVectorExt::geNumberOfVRSaved() const {
+uint8_t TBVectorExt::getNumberOfVRSaved() const {
   return GETVALUEWITHMASKSHIFT(NumberOfVRSavedMask, NumberOfVRSavedShift);
 }
 

diff  --git a/llvm/unittests/Object/XCOFFObjectFileTest.cpp 
b/llvm/unittests/Object/XCOFFObjectFileTest.cpp
index 51ba0f7f66f7..cb1cfe44e077 100644
--- a/llvm/unittests/Object/XCOFFObjectFileTest.cpp
+++ b/llvm/unittests/Object/XCOFFObjectFileTest.cpp
@@ -198,7 +198,7 @@ TEST(XCOFFObjectFileTest, 
XCOFFTracebackTableAPIHasVectorInfo) {
   ASSERT_TRUE(TT.getVectorExt());
   TBVectorExt VecExt = TT.getVectorExt().getValue();
 
-  EXPECT_EQ(VecExt.geNumberOfVRSaved(), 0);
+  EXPECT_EQ(VecExt.getNumberOfVRSaved(), 0);
   EXPECT_TRUE(VecExt.isVRSavedOnStack());
   EXPECT_FALSE(VecExt.hasVarArgs());
 
@@ -232,7 +232,7 @@ TEST(XCOFFObjectFileTest, 
XCOFFTracebackTableAPIHasVectorInfo1) {
   ASSERT_TRUE(TT.getVectorExt());
   TBVectorExt VecExt = TT.getVectorExt().getValue();
 
-  EXPECT_EQ(VecExt.geNumberOfVRSaved(), 4);
+  EXPECT_EQ(VecExt.getNumberOfVRSaved(), 4);
   EXPECT_FALSE(VecExt.isVRSavedOnStack());
   EXPECT_TRUE(VecExt.hasVarArgs());
 



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[llvm-branch-commits] [libcxx] b294376 - [libc++] Use std::move in numeric algorithms (P0616R0).

[via llvm-branch-commits]

Author: zoecarver
Date: 2020-11-27T11:09:44-08:00
New Revision: b2943765e72ee240aa7e9f3a6b8e8a336cadc7ae

URL: 
https://github.com/llvm/llvm-project/commit/b2943765e72ee240aa7e9f3a6b8e8a336cadc7ae
DIFF: 
https://github.com/llvm/llvm-project/commit/b2943765e72ee240aa7e9f3a6b8e8a336cadc7ae.diff

LOG: [libc++] Use std::move in numeric algorithms (P0616R0).

This patch updates algorithms in  to use std::move
based on p0616r0. Moving values instead of copying them
creates huge speed improvements (see the paper for details).

Differential Revision: https://reviews.llvm.org/D61170

Added: 


Modified: 
libcxx/docs/Cxx2aStatusPaperStatus.csv
libcxx/include/numeric
libcxx/test/std/numerics/numeric.ops/accumulate/accumulate_op.pass.cpp

libcxx/test/std/numerics/numeric.ops/adjacent.difference/adjacent_difference_op.pass.cpp

libcxx/test/std/numerics/numeric.ops/inner.product/inner_product_comp.pass.cpp
libcxx/test/std/numerics/numeric.ops/partial.sum/partial_sum_op.pass.cpp

Removed: 




diff  --git a/libcxx/docs/Cxx2aStatusPaperStatus.csv 
b/libcxx/docs/Cxx2aStatusPaperStatus.csv
index cf476c87a130..456ac647b7a3 100644
--- a/libcxx/docs/Cxx2aStatusPaperStatus.csv
+++ b/libcxx/docs/Cxx2aStatusPaperStatus.csv
@@ -10,7 +10,7 @@
 "`P0457R2 `__","LWG","String Prefix and Suffix 
Checking","Albuquerque","|Complete|","6.0"
 "`P0550R2 `__","LWG","Transformation Trait 
``remove_cvref``\ ","Albuquerque","|Complete|","6.0"
 "`P0600R1 `__","LWG","nodiscard in the 
Library","Albuquerque","|In Progress| [#note-P0600]_","7.0"
-"`P0616R0 `__","LWG","de-pessimize legacy  
algorithms with std::move","Albuquerque","",""
+"`P0616R0 `__","LWG","de-pessimize legacy  
algorithms with std::move","Albuquerque","|Complete|","12.0"
 "`P0653R2 `__","LWG","Utility to convert a pointer 
to a raw pointer","Albuquerque","|Complete|","6.0"
 "`P0718R2 `__","LWG","Atomic 
shared_ptr","Albuquerque","",""
 "`P0767R1 `__","CWG","Deprecate 
POD","Albuquerque","|Complete|","7.0"

diff  --git a/libcxx/include/numeric b/libcxx/include/numeric
index 50070ded8fed..088bd7438d2b 100644
--- a/libcxx/include/numeric
+++ b/libcxx/include/numeric
@@ -163,7 +163,11 @@ _Tp
 accumulate(_InputIterator __first, _InputIterator __last, _Tp __init)
 {
 for (; __first != __last; ++__first)
+#if _LIBCPP_STD_VER > 17
+__init = _VSTD::move(__init) + *__first;
+#else
 __init = __init + *__first;
+#endif
 return __init;
 }
 
@@ -173,7 +177,11 @@ _Tp
 accumulate(_InputIterator __first, _InputIterator __last, _Tp __init, 
_BinaryOperation __binary_op)
 {
 for (; __first != __last; ++__first)
+#if _LIBCPP_STD_VER > 17
+__init = __binary_op(_VSTD::move(__init), *__first);
+#else
 __init = __binary_op(__init, *__first);
+#endif
 return __init;
 }
 
@@ -212,7 +220,11 @@ _Tp
 inner_product(_InputIterator1 __first1, _InputIterator1 __last1, 
_InputIterator2 __first2, _Tp __init)
 {
 for (; __first1 != __last1; ++__first1, (void) ++__first2)
+#if _LIBCPP_STD_VER > 17
+__init = _VSTD::move(__init) + *__first1 * *__first2;
+#else
 __init = __init + *__first1 * *__first2;
+#endif
 return __init;
 }
 
@@ -223,7 +235,11 @@ inner_product(_InputIterator1 __first1, _InputIterator1 
__last1, _InputIterator2
   _Tp __init, _BinaryOperation1 __binary_op1, _BinaryOperation2 
__binary_op2)
 {
 for (; __first1 != __last1; ++__first1, (void) ++__first2)
+#if _LIBCPP_STD_VER > 17
+__init = __binary_op1(_VSTD::move(__init), __binary_op2(*__first1, 
*__first2));
+#else
 __init = __binary_op1(__init, __binary_op2(*__first1, *__first2));
+#endif
 return __init;
 }
 
@@ -273,7 +289,11 @@ partial_sum(_InputIterator __first, _InputIterator __last, 
_OutputIterator __res
 *__result = __t;
 for (++__first, (void) ++__result; __first != __last; ++__first, 
(void) ++__result)
 {
+#if _LIBCPP_STD_VER > 17
+__t = _VSTD::move(__t) + *__first;
+#else
 __t = __t + *__first;
+#endif
 *__result = __t;
 }
 }
@@ -292,7 +312,11 @@ partial_sum(_InputIterator __first, _InputIterator __last, 
_OutputIterator __res
 *__result = __t;
 for (++__first, (void) ++__result; __first != __last; ++__first, 
(void) ++__result)
 {
+#if _LIBCPP_STD_VER > 17
+__t = __binary_op(_VSTD::move(__t), *__first);
+#else
 __t = __binary_op(__t, *__first);
+#endif
 *__result = __t;
 }
 }
@@ -417,13 +441,17 @@ adjacent_
diff erence(_InputIterator __first, _InputIterator __last, _OutputIterat
 {
 if (__first != __last)
 {
-typename iterator_traits<_InputIterator>::v

[llvm-branch-commits] [llvm] b7bde0e - [Hexagon] Improve check for HVX types

[Krzysztof Parzyszek via llvm-branch-commits]

Author: Krzysztof Parzyszek
Date: 2020-11-27T13:33:10-06:00
New Revision: b7bde0e4f3d2ca9d2fb25f911ba7eb9d2a4cbd05

URL: 
https://github.com/llvm/llvm-project/commit/b7bde0e4f3d2ca9d2fb25f911ba7eb9d2a4cbd05
DIFF: 
https://github.com/llvm/llvm-project/commit/b7bde0e4f3d2ca9d2fb25f911ba7eb9d2a4cbd05.diff

LOG: [Hexagon] Improve check for HVX types

Allow non-simple types, like <17 x i32> to be treated as HVX vector
types.

Added: 
llvm/test/CodeGen/Hexagon/autohvx/non-simple-hvx-type.ll

Modified: 
llvm/lib/Target/Hexagon/HexagonSubtarget.cpp

Removed: 




diff  --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp 
b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
index 76fe0bec92e3..b79e7c213a37 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -168,14 +168,31 @@ bool HexagonSubtarget::isTypeForHVX(Type *VecTy, bool 
IncludeBool) const {
   // Avoid types like <2 x i32*>.
   if (!cast(VecTy)->getElementType()->isIntegerTy())
 return false;
+  // The given type may be something like <17 x i32>, which is not MVT,
+  // but can be represented as (non-simple) EVT.
   EVT Ty = EVT::getEVT(VecTy, /*HandleUnknown*/false);
-  if (!Ty.isSimple() || Ty.getSizeInBits() <= 64)
+  if (Ty.getSizeInBits() <= 64 || !Ty.getVectorElementType().isSimple())
 return false;
-  if (isHVXVectorType(Ty.getSimpleVT(), IncludeBool))
-return true;
-  auto Action =
-  getTargetLowering()->getPreferredVectorAction(Ty.getSimpleVT());
-  return Action == TargetLoweringBase::TypeWidenVector;
+
+  auto isHvxTy = [this, IncludeBool](MVT SimpleTy) {
+if (isHVXVectorType(SimpleTy, IncludeBool))
+  return true;
+auto Action = getTargetLowering()->getPreferredVectorAction(SimpleTy);
+return Action == TargetLoweringBase::TypeWidenVector;
+  };
+
+  // Round up EVT to have power-of-2 elements, and keep checking if it
+  // qualifies for HVX, dividing it in half after each step.
+  MVT ElemTy = Ty.getVectorElementType().getSimpleVT();
+  unsigned VecLen = PowerOf2Ceil(Ty.getVectorNumElements());
+  while (ElemTy.getSizeInBits() * VecLen > 64) {
+MVT SimpleTy = MVT::getVectorVT(ElemTy, VecLen);
+if (SimpleTy.isValid() && isHvxTy(SimpleTy))
+  return true;
+VecLen /= 2;
+  }
+
+  return false;
 }
 
 void HexagonSubtarget::UsrOverflowMutation::apply(ScheduleDAGInstrs *DAG) {

diff  --git a/llvm/test/CodeGen/Hexagon/autohvx/non-simple-hvx-type.ll 
b/llvm/test/CodeGen/Hexagon/autohvx/non-simple-hvx-type.ll
new file mode 100644
index ..18523ccc682f
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/autohvx/non-simple-hvx-type.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Check that <24 x i32> is treated as an HVX vector type.
+
+define <24 x i32> @f0(<24 x i32>* %a0, <24 x i32> %a1, <24 x i32> %a2) #0 {
+; CHECK-LABEL: f0:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:{
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: v0 = vmemu(r0+#0)
+; CHECK-NEXT:}
+  %v1 = icmp ne <24 x i32> %a1, zeroinitializer
+  %v2 = call <24 x i32> @llvm.masked.load.v24i1.p0v24i1(<24 x i32>* %a0, i32 
4, <24 x i1> %v1, <24 x i32> undef)
+  ret <24 x i32> %v2
+}
+
+declare <24 x i32> @llvm.masked.load.v24i1.p0v24i1(<24 x i32>*, i32, <24 x 
i1>, <24 x i32>)
+
+attributes #0 = { nounwind readnone "target-cpu"="hexagonv62" 
"target-features"="+hvx,+hvx-length128b" }
+



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[llvm-branch-commits] [llvm] f325b4b - [RISCV] Replace sexti32/zexti32 in isel patterns where only one part of their PatFrags can match. NFCI

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2020-11-27T11:37:25-08:00
New Revision: f325b4bbceb5e680e64532dd018b3c0a36d1b01a

URL: 
https://github.com/llvm/llvm-project/commit/f325b4bbceb5e680e64532dd018b3c0a36d1b01a
DIFF: 
https://github.com/llvm/llvm-project/commit/f325b4bbceb5e680e64532dd018b3c0a36d1b01a.diff

LOG: [RISCV] Replace sexti32/zexti32 in isel patterns where only one part of 
their PatFrags can match. NFCI

We had an zexti32 after a sign_extend_inreg. The AND X, 0x
part of the zexti32 should never occur since SimplifyDemandedBits
from the sign_extend_inreg would have removed it.

We also had sexti32 as the root node of a pattern, but SelectionDAGISel
matches assertsext early before the tablegen based patterns are
evaluated.

Added: 


Modified: 
llvm/lib/Target/RISCV/RISCVInstrInfoD.td
llvm/lib/Target/RISCV/RISCVInstrInfoF.td

Removed: 




diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
index 6c36f53cd563..3aaae2de9d8b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -368,7 +368,7 @@ def : Pat<(bitconvert FPR64:$rs1), (FMV_X_D FPR64:$rs1)>;
 // because fpto[u|s]i produce poison if the value can't fit into the target.
 // We match the single case below because fcvt.wu.d sign-extends its result so
 // is cheaper than fcvt.lu.d+sext.w.
-def : Pat<(sext_inreg (zexti32 (fp_to_uint FPR64:$rs1)), i32),
+def : Pat<(sext_inreg (assertzexti32 (fp_to_uint FPR64:$rs1)), i32),
   (FCVT_WU_D $rs1, 0b001)>;
 
 // [u]int32->fp

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index 79281e7d8a5b..5162b5ca4291 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -400,7 +400,7 @@ def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_WU $rs1, 0b111)>;
 let Predicates = [HasStdExtF, IsRV64] in {
 def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>;
 def : Pat<(riscv_fmv_x_anyextw_rv64 FPR32:$src), (FMV_X_W FPR32:$src)>;
-def : Pat<(sexti32 (riscv_fmv_x_anyextw_rv64 FPR32:$src)),
+def : Pat<(sext_inreg (riscv_fmv_x_anyextw_rv64 FPR32:$src), i32),
   (FMV_X_W FPR32:$src)>;
 
 // FP->[u]int32 is mostly handled by the FP->[u]int64 patterns. This is safe



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[llvm-branch-commits] [llvm] fa0f01a - [RISCV][LegalizeTypes] Teach type legalizer that it can promote UMIN/UMAX using SExtPromotedInteger if that's better for the target.

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2020-11-27T11:37:25-08:00
New Revision: fa0f01a3c0e1bdc1a0b4e1188445335184eae03c

URL: 
https://github.com/llvm/llvm-project/commit/fa0f01a3c0e1bdc1a0b4e1188445335184eae03c
DIFF: 
https://github.com/llvm/llvm-project/commit/fa0f01a3c0e1bdc1a0b4e1188445335184eae03c.diff

LOG: [RISCV][LegalizeTypes] Teach type legalizer that it can promote UMIN/UMAX 
using SExtPromotedInteger if that's better for the target.

If Sext is cheaper than Zext for a target, we can use that to promote the 
operands of UMIN/UMAX. Using sext just makes numbers with the sign bit set even 
larger when treated as an unsigned number and it has no effect on number 
without the sign bit set. So the relative order doesn't change. This is similar 
to what we already do for promoting SETCC.

This is helpful on RISCV where i32 arguments are sign extended on RV64 and many 
instructions are able to produce results with 33 sign bits.

Differential Revision: https://reviews.llvm.org/D92128

Added: 


Modified: 
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/test/CodeGen/RISCV/rv64Zbb.ll

Removed: 




diff  --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 
b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 414e7692df2a..8468f51a922c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -82,7 +82,7 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, 
unsigned ResNo) {
   case ISD::SMIN:
   case ISD::SMAX:Res = PromoteIntRes_SExtIntBinOp(N); break;
   case ISD::UMIN:
-  case ISD::UMAX:Res = PromoteIntRes_ZExtIntBinOp(N); break;
+  case ISD::UMAX:Res = PromoteIntRes_UMINUMAX(N); break;
 
   case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
   case ISD::SIGN_EXTEND_INREG:
@@ -1101,6 +1101,15 @@ SDValue 
DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
  LHS.getValueType(), LHS, RHS);
 }
 
+SDValue DAGTypeLegalizer::PromoteIntRes_UMINUMAX(SDNode *N) {
+  // It doesn't matter if we sign extend or zero extend in the inputs. So do
+  // whatever is best for the target.
+  SDValue LHS = SExtOrZExtPromotedInteger(N->getOperand(0));
+  SDValue RHS = SExtOrZExtPromotedInteger(N->getOperand(1));
+  return DAG.getNode(N->getOpcode(), SDLoc(N),
+ LHS.getValueType(), LHS, RHS);
+}
+
 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
   // The input value must be properly sign extended.
   SDValue LHS = SExtPromotedInteger(N->getOperand(0));

diff  --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h 
b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index fdc829b61b65..fed111f4d64e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -331,6 +331,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
   SDValue PromoteIntRes_SimpleIntBinOp(SDNode *N);
   SDValue PromoteIntRes_ZExtIntBinOp(SDNode *N);
   SDValue PromoteIntRes_SExtIntBinOp(SDNode *N);
+  SDValue PromoteIntRes_UMINUMAX(SDNode *N);
   SDValue PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N);
   SDValue PromoteIntRes_SRA(SDNode *N);
   SDValue PromoteIntRes_SRL(SDNode *N);

diff  --git a/llvm/test/CodeGen/RISCV/rv64Zbb.ll 
b/llvm/test/CodeGen/RISCV/rv64Zbb.ll
index 3c96af27c057..eb9698adba87 100644
--- a/llvm/test/CodeGen/RISCV/rv64Zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64Zbb.ll
@@ -856,18 +856,12 @@ define signext i32 @minu_i32(i32 signext %a, i32 signext 
%b) nounwind {
 ;
 ; RV64IB-LABEL: minu_i32:
 ; RV64IB:   # %bb.0:
-; RV64IB-NEXT:zext.w a1, a1
-; RV64IB-NEXT:zext.w a0, a0
 ; RV64IB-NEXT:minu a0, a0, a1
-; RV64IB-NEXT:sext.w a0, a0
 ; RV64IB-NEXT:ret
 ;
 ; RV64IBB-LABEL: minu_i32:
 ; RV64IBB:   # %bb.0:
-; RV64IBB-NEXT:zext.w a1, a1
-; RV64IBB-NEXT:zext.w a0, a0
 ; RV64IBB-NEXT:minu a0, a0, a1
-; RV64IBB-NEXT:sext.w a0, a0
 ; RV64IBB-NEXT:ret
   %cmp = icmp ult i32 %a, %b
   %cond = select i1 %cmp, i32 %a, i32 %b
@@ -908,18 +902,12 @@ define signext i32 @maxu_i32(i32 signext %a, i32 signext 
%b) nounwind {
 ;
 ; RV64IB-LABEL: maxu_i32:
 ; RV64IB:   # %bb.0:
-; RV64IB-NEXT:zext.w a1, a1
-; RV64IB-NEXT:zext.w a0, a0
 ; RV64IB-NEXT:maxu a0, a0, a1
-; RV64IB-NEXT:sext.w a0, a0
 ; RV64IB-NEXT:ret
 ;
 ; RV64IBB-LABEL: maxu_i32:
 ; RV64IBB:   # %bb.0:
-; RV64IBB-NEXT:zext.w a1, a1
-; RV64IBB-NEXT:zext.w a0, a0
 ; RV64IBB-NEXT:maxu a0, a0, a1
-; RV64IBB-NEXT:sext.w a0, a0
 ; RV64IBB-NEXT:ret
   %cmp = icmp ugt i32 %a, %b
   %cond = select i1 %cmp, i32 %a, i32 %b



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[llvm-branch-commits] [llvm] fa10383 - Revert "[BasicAA] Fix BatchAA results for phi-phi assumptions"

[Martin Storsjö via llvm-branch-commits]

Author: Martin Storsjö
Date: 2020-11-27T21:50:59+02:00
New Revision: fa103836649c8c37cf4e49523d3448c1ae1a160f

URL: 
https://github.com/llvm/llvm-project/commit/fa103836649c8c37cf4e49523d3448c1ae1a160f
DIFF: 
https://github.com/llvm/llvm-project/commit/fa103836649c8c37cf4e49523d3448c1ae1a160f.diff

LOG: Revert "[BasicAA] Fix BatchAA results for phi-phi assumptions"

This reverts commit 8166ed1a7a26ee8ea8db9005cc8ee5d156adad9b,
as it caused some compilations to hang/loop indefinitely, see
https://reviews.llvm.org/D91936 for details.

Added: 


Modified: 
llvm/include/llvm/Analysis/BasicAliasAnalysis.h
llvm/lib/Analysis/BasicAliasAnalysis.cpp
llvm/unittests/Analysis/AliasAnalysisTest.cpp

Removed: 




diff  --git a/llvm/include/llvm/Analysis/BasicAliasAnalysis.h 
b/llvm/include/llvm/Analysis/BasicAliasAnalysis.h
index 6f5a31d6a4b5..3717fc9e2c36 100644
--- a/llvm/include/llvm/Analysis/BasicAliasAnalysis.h
+++ b/llvm/include/llvm/Analysis/BasicAliasAnalysis.h
@@ -162,10 +162,6 @@ class BasicAAResult : public AAResultBase {
   /// Tracks instructions visited by pointsToConstantMemory.
   SmallPtrSet Visited;
 
-  /// Whether to disable persistent caching in AAQI. This is used to prevent
-  /// caching of results based on temporary assumptions.
-  bool DisableCache = false;
-
   static const Value *
   GetLinearExpression(const Value *V, APInt &Scale, APInt &Offset,
   unsigned &ZExtBits, unsigned &SExtBits,
@@ -220,12 +216,6 @@ class BasicAAResult : public AAResultBase {
  LocationSize V2Size, const AAMDNodes &V2AATag,
  AAQueryInfo &AAQI, const Value *O1 = nullptr,
  const Value *O2 = nullptr);
-
-  AliasResult aliasCheckRecursive(const Value *V1, LocationSize V1Size,
-  const AAMDNodes &V1AATag, const Value *V2,
-  LocationSize V2Size, const AAMDNodes 
&V2AATag,
-  AAQueryInfo &AAQI, const Value *O1,
-  const Value *O2);
 };
 
 /// Analysis pass providing a never-invalidated alias analysis result.

diff  --git a/llvm/lib/Analysis/BasicAliasAnalysis.cpp 
b/llvm/lib/Analysis/BasicAliasAnalysis.cpp
index 0f13f98868cf..5e6afd908ba3 100644
--- a/llvm/lib/Analysis/BasicAliasAnalysis.cpp
+++ b/llvm/lib/Analysis/BasicAliasAnalysis.cpp
@@ -1489,10 +1489,8 @@ AliasResult BasicAAResult::aliasPHI(const PHINode *PN, 
LocationSize PNSize,
   // operand from outside the PHIs' cycle that is MayAlias/MustAlias or
   // there must be an operation on the PHIs within the PHIs' value cycle
   // that causes a MayAlias.
-  // Disable persistent caching, so intermediate results based on a
-  // possibly incorrect assumption do not get cached.
-  bool OrigDisableCache = DisableCache;
-  DisableCache = true;
+  // Pretend the phis do not alias.
+  AliasResult Alias = NoAlias;
   AliasResult OrigAliasResult;
   {
 // Limited lifetime iterator invalidated by the aliasCheck call below.
@@ -1503,7 +1501,6 @@ AliasResult BasicAAResult::aliasPHI(const PHINode *PN, 
LocationSize PNSize,
 CacheIt->second = NoAlias;
   }
 
-  AliasResult Alias = NoAlias;
   for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
 AliasResult ThisAlias =
 aliasCheck(PN->getIncomingValue(i), PNSize, PNAAInfo,
@@ -1517,7 +1514,6 @@ AliasResult BasicAAResult::aliasPHI(const PHINode *PN, 
LocationSize PNSize,
   // Reset if speculation failed.
   if (Alias != NoAlias)
 AAQI.updateResult(Locs, OrigAliasResult);
-  DisableCache = OrigDisableCache;
   return Alias;
 }
 
@@ -1757,73 +1753,59 @@ AliasResult BasicAAResult::aliasCheck(const Value *V1, 
LocationSize V1Size,
   if (!Pair.second)
 return Pair.first->second;
 
-  AliasResult Result = aliasCheckRecursive(V1, V1Size, V1AAInfo, V2, V2Size,
-   V2AAInfo, AAQI, O1, O2);
-
-  // If caching is disabled, remove the entry once the recursive checks are
-  // done. We only needed it to prevent infinite recursion.
-  if (DisableCache)
-AAQI.AliasCache.erase(AAQI.AliasCache.find(Locs));
-  else if (Result != MayAlias)
-AAQI.updateResult(Locs, Result);
-  return Result;
-}
-
-AliasResult BasicAAResult::aliasCheckRecursive(
-const Value *V1, LocationSize V1Size, const AAMDNodes &V1AAInfo,
-const Value *V2, LocationSize V2Size, const AAMDNodes &V2AAInfo,
-AAQueryInfo &AAQI, const Value *O1, const Value *O2) {
   if (const GEPOperator *GV1 = dyn_cast(V1)) {
 AliasResult Result =
 aliasGEP(GV1, V1Size, V1AAInfo, V2, V2Size, V2AAInfo, O1, O2, AAQI);
 if (Result != MayAlias)
-  return Result;
+  return AAQI.updateResult(Locs, Result);
   } else if (const GEPOperator *GV2 = dyn_cast(V2)) {
 Al

[llvm-branch-commits] [llvm] 29807a0 - [RISCV] Remove stale FIXMEs from a couple test cases. NFC

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2020-11-27T12:07:27-08:00
New Revision: 29807a023ce506db913af58b412062475810c2e9

URL: 
https://github.com/llvm/llvm-project/commit/29807a023ce506db913af58b412062475810c2e9
DIFF: 
https://github.com/llvm/llvm-project/commit/29807a023ce506db913af58b412062475810c2e9.diff

LOG: [RISCV] Remove stale FIXMEs from a couple test cases. NFC

Added: 


Modified: 
llvm/test/CodeGen/RISCV/rv64Zbp.ll

Removed: 




diff  --git a/llvm/test/CodeGen/RISCV/rv64Zbp.ll 
b/llvm/test/CodeGen/RISCV/rv64Zbp.ll
index 763e85dc9220..1d444ad333da 100644
--- a/llvm/test/CodeGen/RISCV/rv64Zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv64Zbp.ll
@@ -1858,7 +1858,6 @@ define signext i32 @bswap_i32(i32 signext %a) nounwind {
 }
 
 ; Similar to bswap_i32 but the result is not sign extended.
-; FIXME: We should use greviw here.
 define void @bswap_i32_nosext(i32 signext %a, i32* %x) nounwind {
 ; RV64I-LABEL: bswap_i32_nosext:
 ; RV64I:   # %bb.0:
@@ -2049,7 +2048,6 @@ define signext i32 @bitreverse_i32(i32 signext %a) 
nounwind {
 }
 
 ; Similar to bitreverse_i32 but the result is not sign extended.
-; FIXME: We should use greviw here.
 define void @bitreverse_i32_nosext(i32 signext %a, i32* %x) nounwind {
 ; RV64I-LABEL: bitreverse_i32_nosext:
 ; RV64I:   # %bb.0:



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[llvm-branch-commits] [llvm] 8351f9b - [ValueTracking] Fix assert on shufflevector of pointers

[Nikita Popov via llvm-branch-commits]

Author: Nikita Popov
Date: 2020-11-27T21:19:31+01:00
New Revision: 8351f9b5ce7e3e2af5773c83e618d68a21d93d7e

URL: 
https://github.com/llvm/llvm-project/commit/8351f9b5ce7e3e2af5773c83e618d68a21d93d7e
DIFF: 
https://github.com/llvm/llvm-project/commit/8351f9b5ce7e3e2af5773c83e618d68a21d93d7e.diff

LOG: [ValueTracking] Fix assert on shufflevector of pointers

In this case getScalarSizeInBits() is not well-defined. Use the
existing TyBits variable that handles vectors of pointers correctly.

Added: 


Modified: 
llvm/lib/Analysis/ValueTracking.cpp
llvm/unittests/Analysis/ValueTrackingTest.cpp

Removed: 




diff  --git a/llvm/lib/Analysis/ValueTracking.cpp 
b/llvm/lib/Analysis/ValueTracking.cpp
index 90f8dff87472..32e0ca321dec 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -2900,8 +2900,7 @@ static unsigned ComputeNumSignBitsImpl(const Value *V,
   // fall-back.
   if (Tmp == 1)
 break;
-  assert(Tmp <= Ty->getScalarSizeInBits() &&
- "Failed to determine minimum sign bits");
+  assert(Tmp <= TyBits && "Failed to determine minimum sign bits");
   return Tmp;
 }
 case Instruction::Call: {

diff  --git a/llvm/unittests/Analysis/ValueTrackingTest.cpp 
b/llvm/unittests/Analysis/ValueTrackingTest.cpp
index 35ede6cb9319..721a342040ba 100644
--- a/llvm/unittests/Analysis/ValueTrackingTest.cpp
+++ b/llvm/unittests/Analysis/ValueTrackingTest.cpp
@@ -690,6 +690,15 @@ TEST_F(ValueTrackingTest, ComputeNumSignBits_Shuffle2) {
   EXPECT_EQ(ComputeNumSignBits(A, M->getDataLayout()), 1u);
 }
 
+TEST_F(ValueTrackingTest, ComputeNumSignBits_Shuffle_Pointers) {
+  parseAssembly(
+  "define <2 x i32*> @test(<2 x i32*> %x) {\n"
+  "  %A = shufflevector <2 x i32*> zeroinitializer, <2 x i32*> undef, <2 x 
i32> zeroinitializer\n"
+  "  ret <2 x i32*> %A\n"
+  "}\n");
+  EXPECT_EQ(ComputeNumSignBits(A, M->getDataLayout()), 64u);
+}
+
 TEST(ValueTracking, propagatesPoison) {
   std::string AsmHead = "declare i32 @g(i32)\n"
 "define void @f(i32 %x, i32 %y, float %fx, float %fy, "



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[llvm-branch-commits] [clang-tools-extra] ca64c89 - [NFC] SmallVector to SmallString<...>

[Nathan James via llvm-branch-commits]

Author: Nathan James
Date: 2020-11-27T20:36:09Z
New Revision: ca64c8948f495ccdfb33f30675e72b7362b390ff

URL: 
https://github.com/llvm/llvm-project/commit/ca64c8948f495ccdfb33f30675e72b7362b390ff
DIFF: 
https://github.com/llvm/llvm-project/commit/ca64c8948f495ccdfb33f30675e72b7362b390ff.diff

LOG: [NFC] SmallVector to SmallString<...>

Added: 


Modified: 
clang-tools-extra/clang-move/Move.cpp

clang-tools-extra/clang-tidy/readability/InconsistentDeclarationParameterNameCheck.cpp
clang-tools-extra/clangd/tool/ClangdMain.cpp

Removed: 




diff  --git a/clang-tools-extra/clang-move/Move.cpp 
b/clang-tools-extra/clang-move/Move.cpp
index 24f819ca4ca2..8e0ec0f73c4d 100644
--- a/clang-tools-extra/clang-move/Move.cpp
+++ b/clang-tools-extra/clang-move/Move.cpp
@@ -691,11 +691,10 @@ void ClangMoveTool::addIncludes(llvm::StringRef 
IncludeHeader, bool IsAngled,
 llvm::StringRef FileName,
 CharSourceRange IncludeFilenameRange,
 const SourceManager &SM) {
-  SmallVector HeaderWithSearchPath;
+  SmallString<128> HeaderWithSearchPath;
   llvm::sys::path::append(HeaderWithSearchPath, SearchPath, IncludeHeader);
   std::string AbsoluteIncludeHeader =
-  MakeAbsolutePath(SM, llvm::StringRef(HeaderWithSearchPath.data(),
-   HeaderWithSearchPath.size()));
+  MakeAbsolutePath(SM, HeaderWithSearchPath);
   std::string IncludeLine =
   IsAngled ? ("#include <" + IncludeHeader + ">\n").str()
: ("#include \"" + IncludeHeader + "\"\n").str();

diff  --git 
a/clang-tools-extra/clang-tidy/readability/InconsistentDeclarationParameterNameCheck.cpp
 
b/clang-tools-extra/clang-tidy/readability/InconsistentDeclarationParameterNameCheck.cpp
index f95b1c9cb2ad..43d2f6a69cd1 100644
--- 
a/clang-tools-extra/clang-tidy/readability/InconsistentDeclarationParameterNameCheck.cpp
+++ 
b/clang-tools-extra/clang-tidy/readability/InconsistentDeclarationParameterNameCheck.cpp
@@ -196,18 +196,16 @@ getParameterSourceDeclaration(const FunctionDecl 
*OriginalDeclaration) {
 std::string joinParameterNames(
 const DifferingParamsContainer &DifferingParams,
 llvm::function_ref ChooseParamName) 
{
-  llvm::SmallVector Buffer;
-  llvm::raw_svector_ostream Str(Buffer);
+  llvm::SmallString<40> Str;
   bool First = true;
   for (const DifferingParamInfo &ParamInfo : DifferingParams) {
 if (First)
   First = false;
 else
-  Str << ", ";
-
-Str << "'" << ChooseParamName(ParamInfo).str() << "'";
+  Str += ", ";
+Str.append({"'", ChooseParamName(ParamInfo), "'"});
   }
-  return Str.str().str();
+  return std::string(Str);
 }
 
 void formatDifferingParamsDiagnostic(

diff  --git a/clang-tools-extra/clangd/tool/ClangdMain.cpp 
b/clang-tools-extra/clangd/tool/ClangdMain.cpp
index d0eab3650750..331241115302 100644
--- a/clang-tools-extra/clangd/tool/ClangdMain.cpp
+++ b/clang-tools-extra/clangd/tool/ClangdMain.cpp
@@ -529,10 +529,10 @@ class TestScheme : public URIScheme {
   "Expect URI body to be an absolute path starting with '/': {0}",
   Body);
 Body = Body.ltrim('/');
-llvm::SmallVector Path(Body.begin(), Body.end());
+llvm::SmallString<16> Path(Body);
 path::native(Path);
 fs::make_absolute(TestScheme::TestDir, Path);
-return std::string(Path.begin(), Path.end());
+return std::string(Path);
   }
 
   llvm::Expected



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[llvm-branch-commits] [llvm] 8709d9d - [RISCV] Replace getSimpleValueType() with getValueType() in DAG combines to prevent asserts with weird types.

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2020-11-27T12:49:12-08:00
New Revision: 8709d9d8724a41e7fa65601bc03a85a32eb4aae7

URL: 
https://github.com/llvm/llvm-project/commit/8709d9d8724a41e7fa65601bc03a85a32eb4aae7
DIFF: 
https://github.com/llvm/llvm-project/commit/8709d9d8724a41e7fa65601bc03a85a32eb4aae7.diff

LOG: [RISCV] Replace getSimpleValueType() with getValueType() in DAG combines 
to prevent asserts with weird types.

Added: 


Modified: 
llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 




diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp 
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index e855b77bfa64..7a0d7979d200 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1222,14 +1222,15 @@ static Optional 
matchRISCVBitmanipPat(SDValue Op) {
 //   (or (BITMANIP_SHL x), (BITMANIP_SRL x))
 static SDValue combineORToGREV(SDValue Op, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
-  if (Op.getSimpleValueType() == Subtarget.getXLenVT() ||
-  (Subtarget.is64Bit() && Op.getSimpleValueType() == MVT::i32)) {
+  EVT VT = Op.getValueType();
+
+  if (VT == Subtarget.getXLenVT() || (Subtarget.is64Bit() && VT == MVT::i32)) {
 auto LHS = matchRISCVBitmanipPat(Op.getOperand(0));
 auto RHS = matchRISCVBitmanipPat(Op.getOperand(1));
 if (LHS && RHS && LHS->formsPairWith(*RHS)) {
   SDLoc DL(Op);
   return DAG.getNode(
-  RISCVISD::GREVI, DL, Op.getValueType(), LHS->Op,
+  RISCVISD::GREVI, DL, VT, LHS->Op,
   DAG.getTargetConstant(LHS->ShAmt, DL, Subtarget.getXLenVT()));
 }
   }
@@ -1246,8 +1247,9 @@ static SDValue combineORToGREV(SDValue Op, SelectionDAG 
&DAG,
 // pattern will be matched to GORC via the first rule above.
 static SDValue combineORToGORC(SDValue Op, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
-  if (Op.getSimpleValueType() == Subtarget.getXLenVT() ||
-  (Subtarget.is64Bit() && Op.getSimpleValueType() == MVT::i32)) {
+  EVT VT = Op.getValueType();
+
+  if (VT == Subtarget.getXLenVT() || (Subtarget.is64Bit() && VT == MVT::i32)) {
 SDLoc DL(Op);
 SDValue Op0 = Op.getOperand(0);
 SDValue Op1 = Op.getOperand(1);
@@ -1257,8 +1259,8 @@ static SDValue combineORToGORC(SDValue Op, SelectionDAG 
&DAG,
  {std::make_pair(Op0, Op1), std::make_pair(Op1, Op0)}) {
   if (OpPair.first.getOpcode() == RISCVISD::GREVI &&
   OpPair.first.getOperand(0) == OpPair.second)
-return DAG.getNode(RISCVISD::GORCI, DL, Op.getValueType(),
-   OpPair.second, OpPair.first.getOperand(1));
+return DAG.getNode(RISCVISD::GORCI, DL, VT, OpPair.second,
+   OpPair.first.getOperand(1));
 }
 
 // OR is commutable so canonicalize its OR operand to the left
@@ -1278,7 +1280,7 @@ static SDValue combineORToGORC(SDValue Op, SelectionDAG 
&DAG,
 auto RHS = matchRISCVBitmanipPat(Op1);
 if (LHS && RHS && LHS->formsPairWith(*RHS) && LHS->Op == OrOp1) {
   return DAG.getNode(
-  RISCVISD::GORCI, DL, Op.getValueType(), LHS->Op,
+  RISCVISD::GORCI, DL, VT, LHS->Op,
   DAG.getTargetConstant(LHS->ShAmt, DL, Subtarget.getXLenVT()));
 }
   }



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[llvm-branch-commits] [clang] 979bcbd - Add -fintegrated-as to clang invocation

[Zarko Todorovski via llvm-branch-commits]

Author: Zarko Todorovski
Date: 2020-11-27T15:54:37-05:00
New Revision: 979bcbd3a6f7ea784f2098ad4cf613fbd6b09e38

URL: 
https://github.com/llvm/llvm-project/commit/979bcbd3a6f7ea784f2098ad4cf613fbd6b09e38
DIFF: 
https://github.com/llvm/llvm-project/commit/979bcbd3a6f7ea784f2098ad4cf613fbd6b09e38.diff

LOG: Add -fintegrated-as to clang invocation

On platforms where the integrated as isn't called by default this
test fails since the output is not what it expects.  Adding this
option generates the expected output on those platforms as well.

Added: 


Modified: 
clang/test/Driver/report-stat.c

Removed: 




diff  --git a/clang/test/Driver/report-stat.c b/clang/test/Driver/report-stat.c
index 4b53f90d8733..621b99384b27 100644
--- a/clang/test/Driver/report-stat.c
+++ b/clang/test/Driver/report-stat.c
@@ -1,4 +1,4 @@
-// RUN: %clang -c -fproc-stat-report %s | FileCheck %s
+// RUN: %clang -c -fproc-stat-report -fintegrated-as %s | FileCheck %s
 // CHECK: clang{{.*}}: output={{.*}}.o, total={{[0-9.]+}} ms, user={{[0-9.]+}} 
ms, mem={{[0-9]+}} Kb
 
 // RUN: %clang -c -fproc-stat-report=%t %s



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[llvm-branch-commits] [libcxx] 03ee461 - [libc++] Consistently unparenthesize `numeric_limits::max`. NFCI.

[Arthur O'Dwyer via llvm-branch-commits]

Author: Arthur O'Dwyer
Date: 2020-11-27T17:27:36-05:00
New Revision: 03ee46127621934c030d37f50aaefdef6bf9d4b0

URL: 
https://github.com/llvm/llvm-project/commit/03ee46127621934c030d37f50aaefdef6bf9d4b0
DIFF: 
https://github.com/llvm/llvm-project/commit/03ee46127621934c030d37f50aaefdef6bf9d4b0.diff

LOG: [libc++] Consistently unparenthesize `numeric_limits::max`. NFCI.

I think people were sometimes parenthesizing `(foo::max)()` out of
misplaced concern that an unparenthesized `foo::max()` would trip up
Windows' `max(a,b)` macro. However, this is not the case: `max(a,b)`
should be tripped up only by an unparenthesized call to `foo::max(a,b)`,
and in fact we already do `_VSTD::max(a,b)` all over the place anyway
without any guards.

However, in order to do it without guards, we must also
wrap the header in _LIBCPP_PUSH_MACROS, which  was not.

Differential Revision: https://reviews.llvm.org/D92240

Added: 


Modified: 
libcxx/include/charconv
libcxx/include/span

Removed: 




diff  --git a/libcxx/include/charconv b/libcxx/include/charconv
index c830457154d7..4664f5b1d034 100644
--- a/libcxx/include/charconv
+++ b/libcxx/include/charconv
@@ -207,7 +207,7 @@ __mul_overflowed(unsigned char __a, _Tp __b, unsigned char& 
__r)
 {
 auto __c = __a * __b;
 __r = __c;
-return __c > (numeric_limits::max)();
+return __c > numeric_limits::max();
 }
 
 template 
@@ -216,7 +216,7 @@ __mul_overflowed(unsigned short __a, _Tp __b, unsigned 
short& __r)
 {
 auto __c = __a * __b;
 __r = __c;
-return __c > (numeric_limits::max)();
+return __c > numeric_limits::max();
 }
 
 template 
@@ -227,7 +227,7 @@ __mul_overflowed(_Tp __a, _Tp __b, _Tp& __r)
 #if !defined(_LIBCPP_COMPILER_MSVC)
 return __builtin_mul_overflow(__a, __b, &__r);
 #else
-bool __did = __b && ((numeric_limits<_Tp>::max)() / __b) < __a;
+bool __did = __b && (numeric_limits<_Tp>::max() / __b) < __a;
 __r = __a * __b;
 return __did;
 #endif
@@ -435,7 +435,7 @@ __sign_combinator(_It __first, _It __last, _Tp& __value, 
_Fn __f, _Ts... __args)
 }
 else
 {
-if (__x <= (__tl::max)())
+if (__x <= __tl::max())
 {
 __value = __x;
 return __r;
@@ -526,7 +526,7 @@ __from_chars_atoi(const char* __first, const char* __last, 
_Tp& __value)
 auto __p = __tx::__read(__first, __last, __a, __b);
 if (__p == __last || !__in_pattern(*__p))
 {
-__output_type __m = (numeric_limits<_Tp>::max)();
+__output_type __m = numeric_limits<_Tp>::max();
 if (__m >= __a && __m - __a >= __b)
 {
 __value = __a + __b;
@@ -581,7 +581,7 @@ __from_chars_integral(const char* __first, const char* 
__last, _Tp& __value,
 
 if (__p == __last || !__in_pattern(*__p, __base))
 {
-if ((__tl::max)() - __a >= __b)
+if (__tl::max() - __a >= __b)
 {
 __value = __a + __b;
 return {__p, {}};

diff  --git a/libcxx/include/span b/libcxx/include/span
index b307c98aee20..4f63d0ac4e1f 100644
--- a/libcxx/include/span
+++ b/libcxx/include/span
@@ -132,11 +132,14 @@ template
 #pragma GCC system_header
 #endif
 
+_LIBCPP_PUSH_MACROS
+#include <__undef_macros>
+
 _LIBCPP_BEGIN_NAMESPACE_STD
 
 #if _LIBCPP_STD_VER > 17
 
-inline constexpr size_t dynamic_extent = (numeric_limits::max)();
+inline constexpr size_t dynamic_extent = numeric_limits::max();
 template  class span;
 
 
@@ -546,4 +549,6 @@ template
 
 _LIBCPP_END_NAMESPACE_STD
 
+_LIBCPP_POP_MACROS
+
 #endif // _LIBCPP_SPAN



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[llvm-branch-commits] [libcxx] 24b3c57 - [libc++] Support no libc++ namespace in the iterator test.

[Vladimir Vereschaka via llvm-branch-commits]

Author: Vladimir Vereschaka
Date: 2020-11-27T15:01:09-08:00
New Revision: 24b3c57adecd0867a2194dfe79643e1f0c962590

URL: 
https://github.com/llvm/llvm-project/commit/24b3c57adecd0867a2194dfe79643e1f0c962590
DIFF: 
https://github.com/llvm/llvm-project/commit/24b3c57adecd0867a2194dfe79643e1f0c962590.diff

LOG: [libc++] Support no libc++ namespace in the iterator test.

The 5f12f4ff9078455cad9d4806da01f570553a5bf9 commit suppress printing of
inline namespace names in diagnostics by default that breaks the libc++
iterator test, which expects __1 in the namespace.

This patch fixes the test by supporting a test case without __1 in the
namespace.

Differential Revision: https://reviews.llvm.org/D92142

Added: 


Modified: 
libcxx/test/std/iterators/iterator.primitives/iterator.traits/empty.fail.cpp

Removed: 




diff  --git 
a/libcxx/test/std/iterators/iterator.primitives/iterator.traits/empty.fail.cpp 
b/libcxx/test/std/iterators/iterator.primitives/iterator.traits/empty.fail.cpp
index 728909e693cc..2c75fc8aebf9 100644
--- 
a/libcxx/test/std/iterators/iterator.primitives/iterator.traits/empty.fail.cpp
+++ 
b/libcxx/test/std/iterators/iterator.primitives/iterator.traits/empty.fail.cpp
@@ -67,56 +67,56 @@ int main(int, char**)
 {
 {
 typedef std::iterator_traits T;
-typedef T::
diff erence_type   DT; // expected-error-re {{no type named '
diff erence_type' in 'std::{{.+}}::iterator_traits<{{.+}}>}}
-typedef T::value_typeVT; // expected-error-re {{no type named 
'value_type' in 'std::{{.+}}::iterator_traits<{{.+}}>}}
-typedef T::pointer   PT; // expected-error-re {{no type named 
'pointer' in 'std::{{.+}}::iterator_traits<{{.+}}>}}
-typedef T::reference RT; // expected-error-re {{no type named 
'reference' in 'std::{{.+}}::iterator_traits<{{.+}}>}}
-typedef T::iterator_category CT; // expected-error-re {{no type named 
'iterator_category' in 'std::{{.+}}::iterator_traits<{{.+}}>}}
+typedef T::
diff erence_type   DT; // expected-error-re {{no type named '
diff erence_type' in 'std{{(::.+)?}}::iterator_traits<{{.+}}>}}
+typedef T::value_typeVT; // expected-error-re {{no type named 
'value_type' in 'std{{(::.+)?}}::iterator_traits<{{.+}}>}}
+typedef T::pointer   PT; // expected-error-re {{no type named 
'pointer' in 'std{{(::.+)?}}::iterator_traits<{{.+}}>}}
+typedef T::reference RT; // expected-error-re {{no type named 
'reference' in 'std{{(::.+)?}}::iterator_traits<{{.+}}>}}
+typedef T::iterator_category CT; // expected-error-re {{no type named 
'iterator_category' in 'std{{(::.+)?}}::iterator_traits<{{.+}}>}}
 }
 
 {
 typedef std::iterator_traits T;
-typedef T::
diff erence_type   DT; // expected-error-re {{no type named '
diff erence_type' in 'std::{{.+}}::iterator_traits<{{.+}}>}}
-typedef T::value_typeVT; // expected-error-re {{no type named 
'value_type' in 'std::{{.+}}::iterator_traits<{{.+}}>}}
-typedef T::pointer   PT; // expected-error-re {{no type named 
'pointer' in 'std::{{.+}}::iterator_traits<{{.+}}>}}
-typedef T::reference RT; // expected-error-re {{no type named 
'reference' in 'std::{{.+}}::iterator_traits<{{.+}}>}}
-typedef T::iterator_category CT; // expected-error-re {{no type named 
'iterator_category' in 'std::{{.+}}::iterator_traits<{{.+}}>}}
+typedef T::
diff erence_type   DT; // expected-error-re {{no type named '
diff erence_type' in 'std{{(::.+)?}}::iterator_traits<{{.+}}>}}
+typedef T::value_typeVT; // expected-error-re {{no type named 
'value_type' in 'std{{(::.+)?}}::iterator_traits<{{.+}}>}}
+typedef T::pointer   PT; // expected-error-re {{no type named 
'pointer' in 'std{{(::.+)?}}::iterator_traits<{{.+}}>}}
+typedef T::reference RT; // expected-error-re {{no type named 
'reference' in 'std{{(::.+)?}}::iterator_traits<{{.+}}>}}
+typedef T::iterator_category CT; // expected-error-re {{no type named 
'iterator_category' in 'std{{(::.+)?}}::iterator_traits<{{.+}}>}}
 }
 
 {
 typedef std::iterator_traits T;
-typedef T::
diff erence_type   DT; // expected-error-re {{no type named '
diff erence_type' in 'std::{{.+}}::iterator_traits<{{.+}}>}}
-typedef T::value_typeVT; // expected-error-re {{no type named 
'value_type' in 'std::{{.+}}::iterator_traits<{{.+}}>}}
-typedef T::pointer   PT; // expected-error-re {{no type named 
'pointer' in 'std::{{.+}}::iterator_traits<{{.+}}>}}
-typedef T::reference RT; // expected-error-re {{no type named 
'reference' in 'std::{{.+}}::iterator_traits<{{.+}}>}}
-typedef T::iterator_category CT; // expected-error-re {{no type named 
'iterator_category' in 'std::{{.+}}::iterator_traits<{{.+}}>}}
+typedef T::
diff erence_type   DT; // expected-error-re {{no type named '
diff erence_type' in 'std{{(::.+)?}}::iterator_t

[llvm-branch-commits] [llvm] 3bd78b7 - [VE] Optimize emitSPAdjustment function

[Kazushi Marukawa via llvm-branch-commits]

Author: Kazushi (Jam) Marukawa
Date: 2020-11-28T08:06:31+09:00
New Revision: 3bd78b7cc00d842782226bb9884ebf8d9d1f07bd

URL: 
https://github.com/llvm/llvm-project/commit/3bd78b7cc00d842782226bb9884ebf8d9d1f07bd
DIFF: 
https://github.com/llvm/llvm-project/commit/3bd78b7cc00d842782226bb9884ebf8d9d1f07bd.diff

LOG: [VE] Optimize emitSPAdjustment function

Optimize emitSPAdjustment function to generate as small as possible
instructions to adjust SP.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D92174

Added: 


Modified: 
llvm/lib/Target/VE/VEFrameLowering.cpp
llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll
llvm/test/CodeGen/VE/Scalar/stackframe_align.ll
llvm/test/CodeGen/VE/Scalar/stackframe_call.ll
llvm/test/CodeGen/VE/Scalar/stackframe_nocall.ll
llvm/test/CodeGen/VE/Scalar/stackframe_size.ll

Removed: 




diff  --git a/llvm/lib/Target/VE/VEFrameLowering.cpp 
b/llvm/lib/Target/VE/VEFrameLowering.cpp
index e15e4130f74b..951430be8f61 100644
--- a/llvm/lib/Target/VE/VEFrameLowering.cpp
+++ b/llvm/lib/Target/VE/VEFrameLowering.cpp
@@ -225,33 +225,40 @@ void VEFrameLowering::emitSPAdjustment(MachineFunction 
&MF,
int64_t NumBytes,
MaybeAlign MaybeAlign) const {
   DebugLoc DL;
-  const VEInstrInfo &TII =
-  *static_cast(MF.getSubtarget().getInstrInfo());
+  const VEInstrInfo &TII = *STI.getInstrInfo();
 
-  if (NumBytes >= -64 && NumBytes < 63) {
+  if (NumBytes == 0) {
+// Nothing to do here.
+  } else if (isInt<7>(NumBytes)) {
+// adds.l %s11, NumBytes@lo, %s11
 BuildMI(MBB, MBBI, DL, TII.get(VE::ADDSLri), VE::SX11)
 .addReg(VE::SX11)
 .addImm(NumBytes);
-return;
+  } else if (isInt<32>(NumBytes)) {
+// lea %s11, NumBytes@lo(, %s11)
+BuildMI(MBB, MBBI, DL, TII.get(VE::LEArii), VE::SX11)
+.addReg(VE::SX11)
+.addImm(0)
+.addImm(Lo_32(NumBytes));
+  } else {
+// Emit following codes.  This clobbers SX13 which we always know is
+// available here.
+//   lea %s13, NumBytes@lo
+//   and %s13, %s13, (32)0
+//   lea.sl  %sp, NumBytes@hi(%s13, %sp)
+BuildMI(MBB, MBBI, DL, TII.get(VE::LEAzii), VE::SX13)
+.addImm(0)
+.addImm(0)
+.addImm(Lo_32(NumBytes));
+BuildMI(MBB, MBBI, DL, TII.get(VE::ANDrm), VE::SX13)
+.addReg(VE::SX13)
+.addImm(M0(32));
+BuildMI(MBB, MBBI, DL, TII.get(VE::LEASLrri), VE::SX11)
+.addReg(VE::SX11)
+.addReg(VE::SX13)
+.addImm(Hi_32(NumBytes));
   }
 
-  // Emit following codes.  This clobbers SX13 which we always know is
-  // available here.
-  //   lea %s13,%lo(NumBytes)
-  //   and %s13,%s13,(32)0
-  //   lea.sl  %sp,%hi(NumBytes)(%sp, %s13)
-  BuildMI(MBB, MBBI, DL, TII.get(VE::LEAzii), VE::SX13)
-  .addImm(0)
-  .addImm(0)
-  .addImm(Lo_32(NumBytes));
-  BuildMI(MBB, MBBI, DL, TII.get(VE::ANDrm), VE::SX13)
-  .addReg(VE::SX13)
-  .addImm(M0(32));
-  BuildMI(MBB, MBBI, DL, TII.get(VE::LEASLrri), VE::SX11)
-  .addReg(VE::SX11)
-  .addReg(VE::SX13)
-  .addImm(Hi_32(NumBytes));
-
   if (MaybeAlign) {
 // and %sp, %sp, Align-1
 BuildMI(MBB, MBBI, DL, TII.get(VE::ANDrm), VE::SX11)

diff  --git a/llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll 
b/llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll
index 1d6314a02070..bc3f9d633e95 100644
--- a/llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll
+++ b/llvm/test/CodeGen/VE/Scalar/function_prologue_epilogue.ll
@@ -33,9 +33,7 @@ define i8 @func_gv() {
 ; PIC-NEXT:st %s15, 24(, %s11)
 ; PIC-NEXT:st %s16, 32(, %s11)
 ; PIC-NEXT:or %s9, 0, %s11
-; PIC-NEXT:lea %s13, -176
-; PIC-NEXT:and %s13, %s13, (32)0
-; PIC-NEXT:lea.sl %s11, -1(%s13, %s11)
+; PIC-NEXT:lea %s11, -176(, %s11)
 ; PIC-NEXT:brge.l.t %s11, %s8, .LBB1_2
 ; PIC-NEXT:  # %bb.1:
 ; PIC-NEXT:ld %s61, 24(, %s14)
@@ -75,9 +73,7 @@ define i32 @func_alloca(i32 signext %0) {
 ; CHECK-NEXT:st %s15, 24(, %s11)
 ; CHECK-NEXT:st %s16, 32(, %s11)
 ; CHECK-NEXT:or %s9, 0, %s11
-; CHECK-NEXT:lea %s13, -192
-; CHECK-NEXT:and %s13, %s13, (32)0
-; CHECK-NEXT:lea.sl %s11, -1(%s13, %s11)
+; CHECK-NEXT:lea %s11, -192(, %s11)
 ; CHECK-NEXT:brge.l.t %s11, %s8, .LBB2_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:ld %s61, 24(, %s14)
@@ -104,9 +100,7 @@ define i32 @func_alloca(i32 signext %0) {
 ; PIC-NEXT:st %s15, 24(, %s11)
 ; PIC-NEXT:st %s16, 32(, %s11)
 ; PIC-NEXT:or %s9, 0, %s11
-; PIC-NEXT:lea %s13, -192
-; PIC-NEXT:and %s13, %s13, (32)0
-; PIC-NEXT:lea.sl %s11, -1(%s13, %s11)
+; PIC-NEXT:lea %s11, -192(, %s11)
 ; PIC-NEXT:brge.l.t %s11, %s8, .LBB2_2
 ; PIC-NEXT:  # %bb.1:
 ; PIC-NEXT:ld %s61, 24(, %s14)

diff  --git a/llvm/test/CodeGen/VE/Scalar/stackfram

[llvm-branch-commits] [libcxx] 530c69e - [libc++] s/constpexr/constexpr/ in some comments. NFC.

[Arthur O'Dwyer via llvm-branch-commits]

Author: Arthur O'Dwyer
Date: 2020-11-27T18:53:08-05:00
New Revision: 530c69e9096bc916d38b337105ab44f0961b

URL: 
https://github.com/llvm/llvm-project/commit/530c69e9096bc916d38b337105ab44f0961b
DIFF: 
https://github.com/llvm/llvm-project/commit/530c69e9096bc916d38b337105ab44f0961b.diff

LOG: [libc++] s/constpexr/constexpr/ in some comments. NFC.

Added: 


Modified: 

libcxx/test/std/algorithms/alg.modifying.operations/alg.partitions/is_partitioned.pass.cpp

libcxx/test/std/algorithms/alg.modifying.operations/alg.partitions/partition_point.pass.cpp
libcxx/test/std/algorithms/alg.nonmodifying/alg.all_of/all_of.pass.cpp
libcxx/test/std/algorithms/alg.nonmodifying/alg.any_of/any_of.pass.cpp

libcxx/test/std/algorithms/alg.sorting/alg.set.operations/set.intersection/set_intersection.pass.cpp

libcxx/test/std/algorithms/alg.sorting/alg.set.operations/set.intersection/set_intersection_comp.pass.cpp

Removed: 




diff  --git 
a/libcxx/test/std/algorithms/alg.modifying.operations/alg.partitions/is_partitioned.pass.cpp
 
b/libcxx/test/std/algorithms/alg.modifying.operations/alg.partitions/is_partitioned.pass.cpp
index 5622f554078a..831fcf16c028 100644
--- 
a/libcxx/test/std/algorithms/alg.modifying.operations/alg.partitions/is_partitioned.pass.cpp
+++ 
b/libcxx/test/std/algorithms/alg.modifying.operations/alg.partitions/is_partitioned.pass.cpp
@@ -9,7 +9,7 @@
 // 
 
 // template 
-// constpexr bool   // constexpr after C++17
+// constexpr bool   // constexpr after C++17
 // is_partitioned(InputIterator first, InputIterator last, Predicate pred);
 
 #include 

diff  --git 
a/libcxx/test/std/algorithms/alg.modifying.operations/alg.partitions/partition_point.pass.cpp
 
b/libcxx/test/std/algorithms/alg.modifying.operations/alg.partitions/partition_point.pass.cpp
index 5da1b8150437..2dc17868f80e 100644
--- 
a/libcxx/test/std/algorithms/alg.modifying.operations/alg.partitions/partition_point.pass.cpp
+++ 
b/libcxx/test/std/algorithms/alg.modifying.operations/alg.partitions/partition_point.pass.cpp
@@ -9,7 +9,7 @@
 // 
 
 // template
-// constpexr ForwardIterator   // constexpr after C++17
+// constexpr ForwardIterator   // constexpr after C++17
 // partition_point(ForwardIterator first, ForwardIterator last, Predicate 
pred);
 
 #include 

diff  --git 
a/libcxx/test/std/algorithms/alg.nonmodifying/alg.all_of/all_of.pass.cpp 
b/libcxx/test/std/algorithms/alg.nonmodifying/alg.all_of/all_of.pass.cpp
index 5c49878f6a49..126845af046e 100644
--- a/libcxx/test/std/algorithms/alg.nonmodifying/alg.all_of/all_of.pass.cpp
+++ b/libcxx/test/std/algorithms/alg.nonmodifying/alg.all_of/all_of.pass.cpp
@@ -9,7 +9,7 @@
 // 
 
 // template 
-// constpexr bool   // constexpr after C++17
+// constexpr bool   // constexpr after C++17
 //   all_of(InputIterator first, InputIterator last, Predicate pred);
 
 #include 

diff  --git 
a/libcxx/test/std/algorithms/alg.nonmodifying/alg.any_of/any_of.pass.cpp 
b/libcxx/test/std/algorithms/alg.nonmodifying/alg.any_of/any_of.pass.cpp
index 22ae581d64b0..cdd7b8a53328 100644
--- a/libcxx/test/std/algorithms/alg.nonmodifying/alg.any_of/any_of.pass.cpp
+++ b/libcxx/test/std/algorithms/alg.nonmodifying/alg.any_of/any_of.pass.cpp
@@ -9,7 +9,7 @@
 // 
 
 // template 
-// constpexr bool   // constexpr after C++17
+// constexpr bool   // constexpr after C++17
 //   any_of(InputIterator first, InputIterator last, Predicate pred);
 
 #include 

diff  --git 
a/libcxx/test/std/algorithms/alg.sorting/alg.set.operations/set.intersection/set_intersection.pass.cpp
 
b/libcxx/test/std/algorithms/alg.sorting/alg.set.operations/set.intersection/set_intersection.pass.cpp
index 08e08f672aed..b90aaf7f63fe 100644
--- 
a/libcxx/test/std/algorithms/alg.sorting/alg.set.operations/set.intersection/set_intersection.pass.cpp
+++ 
b/libcxx/test/std/algorithms/alg.sorting/alg.set.operations/set.intersection/set_intersection.pass.cpp
@@ -13,7 +13,7 @@
 // && OutputIterator
 // && HasLess
 // && HasLess
-//   constpexr OutIter   // constexpr after C++17
+//   constexpr OutIter   // constexpr after C++17
 //   set_intersection(InIter1 first1, InIter1 last1, InIter2 first2, InIter2 
last2,
 //OutIter result);
 

diff  --git 
a/libcxx/test/std/algorithms/alg.sorting/alg.set.operations/set.intersection/set_intersection_comp.pass.cpp
 
b/libcxx/test/std/algorithms/alg.sorting/alg.set.operations/set.intersection/set_intersection_comp.pass.cpp
index acdd7b0191b7..b1796df78dd7 100644
--- 
a/libcxx/test/std/algorithms/alg.sorting/alg.set.operations/set.intersection/set_intersection_comp.pass.cpp
+++ 
b/libcxx/test/std/algorithms/alg.sorting/alg.set.operations/set.intersection/set_intersection_comp.pass.cpp
@@ -14,7 +14,7 @@
 // && OutputIterator
 // && Predicate
 // && Predi

[llvm-branch-commits] [llvm] bf899e8 - [IRSim][IROutliner] Adding the extraction basics for the IROutliner.

[Andrew Litteken via llvm-branch-commits]

Author: Andrew Litteken
Date: 2020-11-27T19:08:29-06:00
New Revision: bf899e891387d07dfd12de195ce2a16f62afd5e0

URL: 
https://github.com/llvm/llvm-project/commit/bf899e891387d07dfd12de195ce2a16f62afd5e0
DIFF: 
https://github.com/llvm/llvm-project/commit/bf899e891387d07dfd12de195ce2a16f62afd5e0.diff

LOG: [IRSim][IROutliner] Adding the extraction basics for the IROutliner.

Extracting the similar regions is the first step in the IROutliner.

Using the IRSimilarityIdentifier, we collect the SimilarityGroups and
sort them by how many instructions will be removed.  Each
IRSimilarityCandidate is used to define an OutlinableRegion.  Each
region is ordered by their occurrence in the Module and the regions that
are not compatible with previously outlined regions are discarded.

Each region is then extracted with the CodeExtractor into its own
function.

We test that correctly extract in:
test/Transforms/IROutliner/extraction.ll
test/Transforms/IROutliner/address-taken.ll
test/Transforms/IROutliner/outlining-same-globals.ll
test/Transforms/IROutliner/outlining-same-constants.ll
test/Transforms/IROutliner/outlining-different-structure.ll

Reviewers: paquette, jroelofs, yroux

Differential Revision: https://reviews.llvm.org/D86975

Added: 
llvm/include/llvm/Transforms/IPO/IROutliner.h
llvm/lib/Transforms/IPO/IROutliner.cpp
llvm/test/Transforms/IROutliner/extraction.ll
llvm/test/Transforms/IROutliner/outlining-address-taken.ll
llvm/test/Transforms/IROutliner/outlining-different-structure.ll
llvm/test/Transforms/IROutliner/outlining-same-constants.ll
llvm/test/Transforms/IROutliner/outlining-same-globals.ll

Modified: 
llvm/include/llvm/InitializePasses.h
llvm/include/llvm/Transforms/IPO.h
llvm/lib/Passes/PassBuilder.cpp
llvm/lib/Passes/PassRegistry.def
llvm/lib/Transforms/IPO/CMakeLists.txt
llvm/lib/Transforms/IPO/IPO.cpp
llvm/lib/Transforms/IPO/PassManagerBuilder.cpp

Removed: 




diff  --git a/llvm/include/llvm/InitializePasses.h 
b/llvm/include/llvm/InitializePasses.h
index 0d0eaf0bca83..0ec87fb09e49 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -183,6 +183,7 @@ void 
initializeHotColdSplittingLegacyPassPass(PassRegistry&);
 void initializeHWAddressSanitizerLegacyPassPass(PassRegistry &);
 void initializeIPSCCPLegacyPassPass(PassRegistry&);
 void initializeIRCELegacyPassPass(PassRegistry&);
+void initializeIROutlinerLegacyPassPass(PassRegistry&);
 void initializeIRSimilarityIdentifierWrapperPassPass(PassRegistry&);
 void initializeIRTranslatorPass(PassRegistry&);
 void initializeIVUsersWrapperPassPass(PassRegistry&);

diff  --git a/llvm/include/llvm/Transforms/IPO.h 
b/llvm/include/llvm/Transforms/IPO.h
index 1918ad76a270..af357181597a 100644
--- a/llvm/include/llvm/Transforms/IPO.h
+++ b/llvm/include/llvm/Transforms/IPO.h
@@ -215,6 +215,11 @@ ModulePass *createMergeFunctionsPass();
 /// function(s).
 ModulePass *createHotColdSplittingPass();
 
+//===--===//
+/// createIROutlinerPass - This pass finds similar code regions and factors
+/// those regions out into functions.
+ModulePass *createIROutlinerPass();
+
 
//===--===//
 /// createPartialInliningPass - This pass inlines parts of functions.
 ///

diff  --git a/llvm/include/llvm/Transforms/IPO/IROutliner.h 
b/llvm/include/llvm/Transforms/IPO/IROutliner.h
new file mode 100644
index ..dd169602f004
--- /dev/null
+++ b/llvm/include/llvm/Transforms/IPO/IROutliner.h
@@ -0,0 +1,186 @@
+//===- IROutliner.h - Extract similar IR regions into functions 
==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// \file
+// The interface file for the IROutliner which is used by the IROutliner Pass.
+//
+// The outliner uses the IRSimilarityIdentifier to identify the similar regions
+// of code.  It evaluates each set of IRSimilarityCandidates with an estimate 
of
+// whether it will provide code size reduction.  Each region is extracted using
+// the code extractor.  These extracted functions are consolidated into a 
single
+// function and called from the extracted call site.
+//
+// For example:
+// \code
+//   %1 = add i32 %a, %b
+//   %2 = add i32 %b, %a
+//   %3 = add i32 %b, %a
+//   %4 = add i32 %a, %b
+// \endcode
+// would become function
+// \code
+// define internal void outlined_ir_function(i32 %0, i32 %1) {
+//   %1 = add i32 %0, %1
+//   %2 = add i32 %1, %0
+//   ret void
+// }
+// \endcode
+// with calls:
+// \code
+//   call void outlined_ir_function(i32 %a, i32 %b)
+// 

[llvm-branch-commits] [llvm] cbc8c1e - [gn build] Port bf899e89138

[LLVM GN Syncbot via llvm-branch-commits]

Author: LLVM GN Syncbot
Date: 2020-11-28T01:09:33Z
New Revision: cbc8c1eb48c5ec552989d0c2ef93827e2e5fa445

URL: 
https://github.com/llvm/llvm-project/commit/cbc8c1eb48c5ec552989d0c2ef93827e2e5fa445
DIFF: 
https://github.com/llvm/llvm-project/commit/cbc8c1eb48c5ec552989d0c2ef93827e2e5fa445.diff

LOG: [gn build] Port bf899e89138

Added: 


Modified: 
llvm/utils/gn/secondary/llvm/lib/Transforms/IPO/BUILD.gn

Removed: 




diff  --git a/llvm/utils/gn/secondary/llvm/lib/Transforms/IPO/BUILD.gn 
b/llvm/utils/gn/secondary/llvm/lib/Transforms/IPO/BUILD.gn
index 8a6bd84a856d..70fc47b32211 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Transforms/IPO/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Transforms/IPO/BUILD.gn
@@ -40,6 +40,7 @@ static_library("IPO") {
 "GlobalSplit.cpp",
 "HotColdSplitting.cpp",
 "IPO.cpp",
+"IROutliner.cpp",
 "InferFunctionAttrs.cpp",
 "InlineSimple.cpp",
 "Inliner.cpp",



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[llvm-branch-commits] [llvm] a8a43b6 - Revert "[IRSim][IROutliner] Adding the extraction basics for the IROutliner."

[Andrew Litteken via llvm-branch-commits]

Author: Andrew Litteken
Date: 2020-11-27T19:55:57-06:00
New Revision: a8a43b63388f4d348eaa1f1017d6ab3be89b4945

URL: 
https://github.com/llvm/llvm-project/commit/a8a43b63388f4d348eaa1f1017d6ab3be89b4945
DIFF: 
https://github.com/llvm/llvm-project/commit/a8a43b63388f4d348eaa1f1017d6ab3be89b4945.diff

LOG: Revert "[IRSim][IROutliner] Adding the extraction basics for the 
IROutliner."

Reverting commit due to address sanitizer errors.

> Extracting the similar regions is the first step in the IROutliner.
> 
> Using the IRSimilarityIdentifier, we collect the SimilarityGroups and
> sort them by how many instructions will be removed.  Each
> IRSimilarityCandidate is used to define an OutlinableRegion.  Each
> region is ordered by their occurrence in the Module and the regions that
> are not compatible with previously outlined regions are discarded.
> 
> Each region is then extracted with the CodeExtractor into its own
> function.
> 
> We test that correctly extract in:
> test/Transforms/IROutliner/extraction.ll
> test/Transforms/IROutliner/address-taken.ll
> test/Transforms/IROutliner/outlining-same-globals.ll
> test/Transforms/IROutliner/outlining-same-constants.ll
> test/Transforms/IROutliner/outlining-different-structure.ll
> 
> Reviewers: paquette, jroelofs, yroux
> 
> Differential Revision: https://reviews.llvm.org/D86975

This reverts commit bf899e891387d07dfd12de195ce2a16f62afd5e0.

Added: 


Modified: 
llvm/include/llvm/InitializePasses.h
llvm/include/llvm/Transforms/IPO.h
llvm/lib/Passes/PassBuilder.cpp
llvm/lib/Passes/PassRegistry.def
llvm/lib/Transforms/IPO/CMakeLists.txt
llvm/lib/Transforms/IPO/IPO.cpp
llvm/lib/Transforms/IPO/PassManagerBuilder.cpp

Removed: 
llvm/include/llvm/Transforms/IPO/IROutliner.h
llvm/lib/Transforms/IPO/IROutliner.cpp
llvm/test/Transforms/IROutliner/extraction.ll
llvm/test/Transforms/IROutliner/outlining-address-taken.ll
llvm/test/Transforms/IROutliner/outlining-different-structure.ll
llvm/test/Transforms/IROutliner/outlining-same-constants.ll
llvm/test/Transforms/IROutliner/outlining-same-globals.ll



diff  --git a/llvm/include/llvm/InitializePasses.h 
b/llvm/include/llvm/InitializePasses.h
index 0ec87fb09e49..0d0eaf0bca83 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -183,7 +183,6 @@ void 
initializeHotColdSplittingLegacyPassPass(PassRegistry&);
 void initializeHWAddressSanitizerLegacyPassPass(PassRegistry &);
 void initializeIPSCCPLegacyPassPass(PassRegistry&);
 void initializeIRCELegacyPassPass(PassRegistry&);
-void initializeIROutlinerLegacyPassPass(PassRegistry&);
 void initializeIRSimilarityIdentifierWrapperPassPass(PassRegistry&);
 void initializeIRTranslatorPass(PassRegistry&);
 void initializeIVUsersWrapperPassPass(PassRegistry&);

diff  --git a/llvm/include/llvm/Transforms/IPO.h 
b/llvm/include/llvm/Transforms/IPO.h
index af357181597a..1918ad76a270 100644
--- a/llvm/include/llvm/Transforms/IPO.h
+++ b/llvm/include/llvm/Transforms/IPO.h
@@ -215,11 +215,6 @@ ModulePass *createMergeFunctionsPass();
 /// function(s).
 ModulePass *createHotColdSplittingPass();
 
-//===--===//
-/// createIROutlinerPass - This pass finds similar code regions and factors
-/// those regions out into functions.
-ModulePass *createIROutlinerPass();
-
 
//===--===//
 /// createPartialInliningPass - This pass inlines parts of functions.
 ///

diff  --git a/llvm/include/llvm/Transforms/IPO/IROutliner.h 
b/llvm/include/llvm/Transforms/IPO/IROutliner.h
deleted file mode 100644
index dd169602f004..
--- a/llvm/include/llvm/Transforms/IPO/IROutliner.h
+++ /dev/null
@@ -1,186 +0,0 @@
-//===- IROutliner.h - Extract similar IR regions into functions 
==//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===--===//
-//
-// \file
-// The interface file for the IROutliner which is used by the IROutliner Pass.
-//
-// The outliner uses the IRSimilarityIdentifier to identify the similar regions
-// of code.  It evaluates each set of IRSimilarityCandidates with an estimate 
of
-// whether it will provide code size reduction.  Each region is extracted using
-// the code extractor.  These extracted functions are consolidated into a 
single
-// function and called from the extracted call site.
-//
-// For example:
-// \code
-//   %1 = add i32 %a, %b
-//   %2 = add i32 %b, %a
-//   %3 = add i32 %b, %a
-//   %4 = add i32 %a, %b
-// \endcode
-// would become function
-// \code
-// define internal void outlined_ir_function(i32 %0, i32 %1) {

[llvm-branch-commits] [llvm] 88974e8 - [gn build] Port a8a43b63388

[LLVM GN Syncbot via llvm-branch-commits]

Author: LLVM GN Syncbot
Date: 2020-11-28T01:56:55Z
New Revision: 88974e829ec343ad922698207703a68acd98

URL: 
https://github.com/llvm/llvm-project/commit/88974e829ec343ad922698207703a68acd98
DIFF: 
https://github.com/llvm/llvm-project/commit/88974e829ec343ad922698207703a68acd98.diff

LOG: [gn build] Port a8a43b63388

Added: 


Modified: 
llvm/utils/gn/secondary/llvm/lib/Transforms/IPO/BUILD.gn

Removed: 




diff  --git a/llvm/utils/gn/secondary/llvm/lib/Transforms/IPO/BUILD.gn 
b/llvm/utils/gn/secondary/llvm/lib/Transforms/IPO/BUILD.gn
index 70fc47b32211..8a6bd84a856d 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Transforms/IPO/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Transforms/IPO/BUILD.gn
@@ -40,7 +40,6 @@ static_library("IPO") {
 "GlobalSplit.cpp",
 "HotColdSplitting.cpp",
 "IPO.cpp",
-"IROutliner.cpp",
 "InferFunctionAttrs.cpp",
 "InlineSimple.cpp",
 "Inliner.cpp",



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[llvm-branch-commits] [llvm] 6ee22ca - [RISCV] Add tests for existing (rotr (bswap X), (i32 16))->grevi pattern for RV32. Extend same pattern to rotl and GREVIW.

[Craig Topper via llvm-branch-commits]

Author: Craig Topper
Date: 2020-11-27T18:09:01-08:00
New Revision: 6ee22ca6ceb71661e8dbc296b471ace0614c07e5

URL: 
https://github.com/llvm/llvm-project/commit/6ee22ca6ceb71661e8dbc296b471ace0614c07e5
DIFF: 
https://github.com/llvm/llvm-project/commit/6ee22ca6ceb71661e8dbc296b471ace0614c07e5.diff

LOG: [RISCV] Add tests for existing (rotr (bswap X), (i32 16))->grevi pattern 
for RV32. Extend same pattern to rotl and GREVIW.

Not sure why bswap was treated specially. This also applies to bitreverse
or generic grevi. We can improve this in future patches.
For now I just wanted to get the consistency and the test coverage
as I plan to make some other changes around bswap.

Added: 


Modified: 
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/rv32Zbp.ll
llvm/test/CodeGen/RISCV/rv64Zbp.ll

Removed: 




diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index 7a8a1bc364e1..af6a367f95fe 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -730,7 +730,8 @@ def : Pat<(riscv_gorci GPR:$rs1, timm:$shamt), (GORCI 
GPR:$rs1, timm:$shamt)>;
 } // Predicates = [HasStdExtZbp]
 
 let Predicates = [HasStdExtZbp, IsRV32] in {
-def : Pat<(rotr (bswap GPR:$rs1), (i32 16)), (GREVI GPR:$rs1, (i32 8))>;
+def : Pat<(rotr (bswap GPR:$rs1), (i32 16)), (GREVI GPR:$rs1, 8)>;
+def : Pat<(rotl (bswap GPR:$rs1), (i32 16)), (GREVI GPR:$rs1, 8)>;
 def : Pat<(bswap GPR:$rs1), (GREVI GPR:$rs1, (i32 24))>;
 def : Pat<(bitreverse GPR:$rs1), (GREVI GPR:$rs1, (i32 31))>;
 } // Predicates = [HasStdExtZbp, IsRV32]
@@ -921,6 +922,8 @@ def : Pat<(SROIWPat GPR:$rs1, uimmlog2xlen:$shamt),
 } // Predicates = [HasStdExtZbb, IsRV64]
 
 let Predicates = [HasStdExtZbp, IsRV64] in {
+def : Pat<(riscv_rorw (riscv_greviw GPR:$rs1, 24), (i64 16)), (GREVIW 
GPR:$rs1, 8)>;
+def : Pat<(riscv_rolw (riscv_greviw GPR:$rs1, 24), (i64 16)), (GREVIW 
GPR:$rs1, 8)>;
 def : Pat<(riscv_greviw GPR:$rs1, timm:$shamt), (GREVIW GPR:$rs1, 
timm:$shamt)>;
 def : Pat<(riscv_gorciw GPR:$rs1, timm:$shamt), (GORCIW GPR:$rs1, 
timm:$shamt)>;
 } // Predicates = [HasStdExtZbp, IsRV64]

diff  --git a/llvm/test/CodeGen/RISCV/rv32Zbp.ll 
b/llvm/test/CodeGen/RISCV/rv32Zbp.ll
index 1382e1b71459..8442c8df8c0b 100644
--- a/llvm/test/CodeGen/RISCV/rv32Zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv32Zbp.ll
@@ -1781,6 +1781,74 @@ define i64 @bitreverse_i64(i64 %a) nounwind {
   ret i64 %1
 }
 
+define i32 @bswap_rotr_i32(i32 %a) {
+; RV32I-LABEL: bswap_rotr_i32:
+; RV32I:   # %bb.0:
+; RV32I-NEXT:srli a1, a0, 8
+; RV32I-NEXT:lui a2, 16
+; RV32I-NEXT:addi a2, a2, -256
+; RV32I-NEXT:and a1, a1, a2
+; RV32I-NEXT:srli a2, a0, 24
+; RV32I-NEXT:or a1, a1, a2
+; RV32I-NEXT:slli a2, a0, 8
+; RV32I-NEXT:lui a3, 4080
+; RV32I-NEXT:and a2, a2, a3
+; RV32I-NEXT:slli a0, a0, 24
+; RV32I-NEXT:or a0, a0, a2
+; RV32I-NEXT:or a0, a0, a1
+; RV32I-NEXT:slli a1, a0, 16
+; RV32I-NEXT:srli a0, a0, 16
+; RV32I-NEXT:or a0, a0, a1
+; RV32I-NEXT:ret
+;
+; RV32IB-LABEL: bswap_rotr_i32:
+; RV32IB:   # %bb.0:
+; RV32IB-NEXT:rev8.h a0, a0
+; RV32IB-NEXT:ret
+;
+; RV32IBP-LABEL: bswap_rotr_i32:
+; RV32IBP:   # %bb.0:
+; RV32IBP-NEXT:rev8.h a0, a0
+; RV32IBP-NEXT:ret
+  %1 = call i32 @llvm.bswap.i32(i32 %a)
+  %2 = call i32 @llvm.fshr.i32(i32 %1, i32 %1, i32 16)
+  ret i32 %2
+}
+
+define i32 @bswap_rotl_i32(i32 %a) {
+; RV32I-LABEL: bswap_rotl_i32:
+; RV32I:   # %bb.0:
+; RV32I-NEXT:srli a1, a0, 8
+; RV32I-NEXT:lui a2, 16
+; RV32I-NEXT:addi a2, a2, -256
+; RV32I-NEXT:and a1, a1, a2
+; RV32I-NEXT:srli a2, a0, 24
+; RV32I-NEXT:or a1, a1, a2
+; RV32I-NEXT:slli a2, a0, 8
+; RV32I-NEXT:lui a3, 4080
+; RV32I-NEXT:and a2, a2, a3
+; RV32I-NEXT:slli a0, a0, 24
+; RV32I-NEXT:or a0, a0, a2
+; RV32I-NEXT:or a0, a0, a1
+; RV32I-NEXT:srli a1, a0, 16
+; RV32I-NEXT:slli a0, a0, 16
+; RV32I-NEXT:or a0, a0, a1
+; RV32I-NEXT:ret
+;
+; RV32IB-LABEL: bswap_rotl_i32:
+; RV32IB:   # %bb.0:
+; RV32IB-NEXT:rev8.h a0, a0
+; RV32IB-NEXT:ret
+;
+; RV32IBP-LABEL: bswap_rotl_i32:
+; RV32IBP:   # %bb.0:
+; RV32IBP-NEXT:rev8.h a0, a0
+; RV32IBP-NEXT:ret
+  %1 = call i32 @llvm.bswap.i32(i32 %a)
+  %2 = call i32 @llvm.fshl.i32(i32 %1, i32 %1, i32 16)
+  ret i32 %2
+}
+
 define i32 @shfl1_i32(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: shfl1_i32:
 ; RV32I:   # %bb.0:

diff  --git a/llvm/test/CodeGen/RISCV/rv64Zbp.ll 
b/llvm/test/CodeGen/RISCV/rv64Zbp.ll
index 1d444ad333da..b1f270e00b8f 100644
--- a/llvm/test/CodeGen/RISCV/rv64Zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv64Zbp.ll
@@ -2265,6 +2265,118 @@ define i64 @bitreverse_i64(i64 %a) nounwind {
   ret i64 %1
 }
 
+define i32 @bswap_rotr_i32(i32 %a) {
+; RV64I-LABEL: bswap_rotr_i32:
+; RV64I:   # %bb.0:
+; RV64I-NEXT: