[llvm-branch-commits] [lld] e6ec96f - [docs] Add release notes for the 11.x release
Author: Martin Storsjö
Date: 2020-08-17T11:17:15+03:00
New Revision: e6ec96f4215a4f5302e4dd5d0ac287a1b0563586
URL:
https://github.com/llvm/llvm-project/commit/e6ec96f4215a4f5302e4dd5d0ac287a1b0563586
DIFF:
https://github.com/llvm/llvm-project/commit/e6ec96f4215a4f5302e4dd5d0ac287a1b0563586.diff
LOG: [docs] Add release notes for the 11.x release
Added:
Modified:
clang/docs/ReleaseNotes.rst
lld/docs/ReleaseNotes.rst
llvm/docs/ReleaseNotes.rst
Removed:
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 3264846506c6..6f336088750f 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -191,6 +191,16 @@ Attribute Changes in Clang
Windows Support
---
+- Don't warn about `ms_struct may not produce Microsoft-compatible layouts
+ for classes with base classes or virtual functions` if the option is
+ enabled globally, as opposed to enabled on a specific class/struct or
+ on a specific section in the source files. This avoids needing to
+ couple `-mms-bitfields` with `-Wno-incompatible-ms-struct` if building
+ C++ code.
+
+- Enable `-mms-bitfields` by default for MinGW targets, matching a similar
+ change in GCC 4.7.
+
C Language Changes in Clang
---
diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst
index fe3de8306cd8..f0482c2428c4 100644
--- a/lld/docs/ReleaseNotes.rst
+++ b/lld/docs/ReleaseNotes.rst
@@ -40,12 +40,17 @@ Breaking changes
COFF Improvements
-
-* ...
+* Fixed exporting symbols whose names contain a period (``.``), which was
+ a regression in lld 7.
MinGW Improvements
--
-* ...
+* Implemented new options for disabling auto import and runtime pseudo
+ relocations (``--disable-auto-import`` and
+ ``--disable-runtime-pseudo-reloc``), the ``--no-seh`` flag and options
+ for selecting file and section alignment (``--file-alignment`` and
+ ``--section-alignment``).
MachO Improvements
--
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index ed1718a95054..c9ac61d29676 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -81,6 +81,15 @@ Changes to the LLVM IR
Changes to building LLVM
+Changes to the AArch64 Backend
+--
+
+* Back up and restore x18 in functions with windows calling convention on
+ non-windows OSes.
+
+* Clearly error out on unsupported relocations when targeting COFF, instead
+ of silently accepting some (without being able to do what was requested).
+
Changes to the ARM Backend
--
@@ -157,6 +166,12 @@ Changes to the WebAssembly Target
* `__attribute__((visibility("protected")))` now evokes a warning, as
WebAssembly does not support "protected" visibility.
+Changes to the Windows Target
+-
+
+* Produce COFF weak external symbols for IR level weak symbols without a comdat
+ (e.g. for `__attribute__((weak))` in C)
+
Changes to the OCaml bindings
-
@@ -195,6 +210,12 @@ Changes to the LLVM tools
symbols, i.e. mapping symbols on ARM and AArch64, by default. This matches
the GNU nm behavior.
+* llvm-rc now tolerates -1 as menu item ID, supports the language id option
+ and allows string table values to be split into multiple string literals
+
+* llvm-lib supports adding import library objects in addition to regular
+ object files
+
Changes to LLDB
===
___
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Re: [llvm-branch-commits] [clang-tools-extra] f0c41f1 - [clangd] Release notes for 11.x
Very nice. Thanks!
On Mon, Aug 10, 2020 at 12:38 PM Sam McCall via llvm-branch-commits
wrote:
>
>
> Author: Sam McCall
> Date: 2020-08-10T12:38:24+02:00
> New Revision: f0c41f1d63627a29055474e6df73f78761ca8213
>
> URL:
> https://github.com/llvm/llvm-project/commit/f0c41f1d63627a29055474e6df73f78761ca8213
> DIFF:
> https://github.com/llvm/llvm-project/commit/f0c41f1d63627a29055474e6df73f78761ca8213.diff
>
> LOG: [clangd] Release notes for 11.x
>
> Added:
>
>
> Modified:
> clang-tools-extra/docs/ReleaseNotes.rst
>
> Removed:
>
>
>
>
> diff --git a/clang-tools-extra/docs/ReleaseNotes.rst
> b/clang-tools-extra/docs/ReleaseNotes.rst
> index 0238ef5149b0..9f96d6eab38e 100644
> --- a/clang-tools-extra/docs/ReleaseNotes.rst
> +++ b/clang-tools-extra/docs/ReleaseNotes.rst
> @@ -47,7 +47,196 @@ Major New Features
> Improvements to clangd
> --
>
> -The improvements are...
> +Performance
> +^^^
> +
> +- Eliminated long delays after adding/removing includes ("async preambles")
> +
> +- Faster indexing
> +
> +- Less memory used to index headers used by open files ("dynamic index")
> +
> +- Many requests are implicitly cancelled rather than queued when the file is
> + edited, preventing a backlog
> +
> +- Background indexing can be selectively disabled per-path through config
> +
> +Selecting and targeting
> +^^^
> +
> +- Improved understanding and selection around broken code ("recovery AST")
> +
> +- Operations like "go-to-definition" will target things on the left of the
> + cursor, if there is nothing eligible on the right.
> +
> +- Arguments to ``assert()``-like macros can be properly selected.
> +
> +Diagnostics
> +^^^
> +
> +- When a header is saved, diagnostics for files that use it are updated.
> +
> +- Calls ``std::make_unique`` produce diagnostics for the constructor call.
> + (Template functions *in general* are not expanded for performance reasons).
> +
> +- Diagnostics update more quickly for files that build quickly (no 500ms
> delay)
> +
> +- Automatic fixes are offered even when they affect macro arguments.
> +
> +- Warnings from included headers are not shown (but errors still are).
> +
> +- A handful of high-quality clang-tidy checks are enabled by default:
> +
> + - readability-misleading-indentation,
> +
> + - readability-deleted-default,
> +
> + - bugprone-integer-division,
> +
> + - bugprone-sizeof-expression,
> +
> + - bugprone-suspicious-missing-comma,
> +
> + - bugprone-unused-raii,
> +
> + - bugprone-unused-return-value,
> +
> + - misc-unused-using-decls,
> +
> + - misc-unused-alias-decls,
> +
> + - misc-definitions-in-headers
> +
> +Refactorings
> +
> +
> +- Rename applies across the project, using the index.
> +
> +- Accuracy of rename improved in many places.
> +
> +- New refactoring: add using declaration for qualified name.
> +
> +- New refactoring: move function definition out-of-line.
> +
> +Code completion
> +^^^
> +
> +- Function call parentheses are not inserted if they already exist.
> +
> +- Completion of ``#include`` filenames triggers earlier (after ``<``, ``"``,
> and
> + ``/``) and is less aggressive about replacing existing text.
> +
> +- Documentation is reflowed in the same way as on hover.
> +
> +Go-to-definition
> +
> +
> +- Dependent names in templates may be heuristically resolved
> +
> +- Identifiers in comments may be resolved using other occurrences in the file
> + or in the index.
> +
> +- Go-to-definition on an ``override`` or ``final`` specifier jumps to the
> + overridden method.
> +
> +Hover
> +^
> +
> +- Expressions passed as function arguments show parameter name, conversions
> etc.
> +
> +- Members now include the access specifier in the displayed declaration.
> +
> +- Classes and fields show memory layout information (size and offset).
> +
> +- Somewhat improved understanding of formatting in documentation comments.
> +
> +- Trivial inline getters/setters are implicitly documented as such.
> +
> +Highlighting
> +
> +
> +- The ``semanticTokens`` protocol from LSP 3.16 is supported.
> + (Only token types are exposed, no modifiers yet).
> +
> +- The non-standard ``textDocument/semanticHighlighting`` notification is
> + deprecated and will be removed in clangd 12.
> +
> +- Placing the cursor on a control flow keyword highlights related flow
> + (e.g. ``break`` -> ``for``).
> +
> +Language support
> +
> +
> +- clangd features now work inside templates on windows.
> + (MSVC-compatible delayed-template-parsing is no longer used).
> +
> +- Objective-C properties can be targeted and cross-references are indexed.
> +
> +- Field names in designated initializers (C++20) can be targeted, and code
> + completion works in many cases.
> +
> +- ``goto`` labels: go-to-defintion, cross-references, and rename all work.
> +
> +- Concepts (C
[llvm-branch-commits] [llvm] 3d0470a - [AArch64][SVE] Fix CFA calculation in presence of SVE objects.
Author: Sander de Smalen
Date: 2020-08-17T13:58:09+02:00
New Revision: 3d0470ae802ae443a2df39f495d2ddd92805c8f8
URL:
https://github.com/llvm/llvm-project/commit/3d0470ae802ae443a2df39f495d2ddd92805c8f8
DIFF:
https://github.com/llvm/llvm-project/commit/3d0470ae802ae443a2df39f495d2ddd92805c8f8.diff
LOG: [AArch64][SVE] Fix CFA calculation in presence of SVE objects.
The CFA is calculated as (SP/FP + offset), but when there are
SVE objects on the stack the SP offset is partly scalable and
should instead be expressed as the DWARF expression:
SP + offset + scalable_offset * VG
where VG is the Vector Granule register, containing the
number of 64bits 'granules' in a scalable vector.
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D84043
(cherry picked from commit fd6584a22043b254a323635c142b28ce80ae5b5b)
Added:
Modified:
llvm/include/llvm/MC/MCDwarf.h
llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
llvm/lib/Target/AArch64/AArch64FrameLowering.h
llvm/lib/Target/AArch64/AArch64RegisterInfo.td
llvm/lib/Target/AArch64/AArch64StackOffset.h
llvm/test/CodeGen/AArch64/framelayout-sve.mir
llvm/test/CodeGen/AArch64/sve-trunc.ll
Removed:
diff --git a/llvm/include/llvm/MC/MCDwarf.h b/llvm/include/llvm/MC/MCDwarf.h
index e3cea0ae64cf..70da5f76e766 100644
--- a/llvm/include/llvm/MC/MCDwarf.h
+++ b/llvm/include/llvm/MC/MCDwarf.h
@@ -467,10 +467,12 @@ class MCCFIInstruction {
unsigned Register2;
};
std::vector Values;
+ std::string Comment;
- MCCFIInstruction(OpType Op, MCSymbol *L, unsigned R, int O, StringRef V)
+ MCCFIInstruction(OpType Op, MCSymbol *L, unsigned R, int O, StringRef V,
+ StringRef Comment = "")
: Operation(Op), Label(L), Register(R), Offset(O),
-Values(V.begin(), V.end()) {
+Values(V.begin(), V.end()), Comment(Comment) {
assert(Op != OpRegister);
}
@@ -570,8 +572,9 @@ class MCCFIInstruction {
/// .cfi_escape Allows the user to add arbitrary bytes to the unwind
/// info.
- static MCCFIInstruction createEscape(MCSymbol *L, StringRef Vals) {
-return MCCFIInstruction(OpEscape, L, 0, 0, Vals);
+ static MCCFIInstruction createEscape(MCSymbol *L, StringRef Vals,
+ StringRef Comment = "") {
+return MCCFIInstruction(OpEscape, L, 0, 0, Vals, Comment);
}
/// A special wrapper for .cfi_escape that indicates GNU_ARGS_SIZE
@@ -606,6 +609,10 @@ class MCCFIInstruction {
assert(Operation == OpEscape);
return StringRef(&Values[0], Values.size());
}
+
+ StringRef getComment() const {
+return Comment;
+ }
};
struct MCDwarfFrameInfo {
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
index d81a9be26d39..b6a9a9568360 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
@@ -241,6 +241,7 @@ void AsmPrinter::emitCFIInstruction(const MCCFIInstruction
&Inst) const {
OutStreamer->emitCFIGnuArgsSize(Inst.getOffset());
break;
case MCCFIInstruction::OpEscape:
+OutStreamer->AddComment(Inst.getComment());
OutStreamer->emitCFIEscape(Inst.getValues());
break;
case MCCFIInstruction::OpRestore:
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index 4789a9f02937..177d5e24fdb3 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -148,6 +148,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/LEB128.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
@@ -399,6 +400,64 @@ static bool ShouldSignReturnAddress(MachineFunction &MF) {
return false;
}
+// Convenience function to create a DWARF expression for
+// Expr + NumBytes + NumVGScaledBytes * AArch64::VG
+static void appendVGScaledOffsetExpr(SmallVectorImpl &Expr,
+ int NumBytes, int NumVGScaledBytes,
unsigned VG,
+ llvm::raw_string_ostream &Comment) {
+ uint8_t buffer[16];
+
+ if (NumBytes) {
+Expr.push_back(dwarf::DW_OP_consts);
+Expr.append(buffer, buffer + encodeSLEB128(NumBytes, buffer));
+Expr.push_back((uint8_t)dwarf::DW_OP_plus);
+Comment << (NumBytes < 0 ? " - " : " + ") << std::abs(NumBytes);
+ }
+
+ if (NumVGScaledBytes) {
+Expr.push_back((uint8_t)dwarf::DW_OP_consts);
+Expr.append(buffer, buffer + encodeSLEB128(NumVGScaledBytes, buffer));
+
+Expr.push_back((uint8_t)dwarf::DW_OP_bregx);
+Expr.append(buffer, buffer + encodeULEB128(VG, buffer));
+Expr.push_back(0);
+
[llvm-branch-commits] [llvm] a318950 - Fix -Wconstant-conversion warning with explicit cast
Author: David Blaikie Date: 2020-08-17T14:01:44+02:00 New Revision: a318950c0f9b166245b3d912be2642af7584a078 URL: https://github.com/llvm/llvm-project/commit/a318950c0f9b166245b3d912be2642af7584a078 DIFF: https://github.com/llvm/llvm-project/commit/a318950c0f9b166245b3d912be2642af7584a078.diff LOG: Fix -Wconstant-conversion warning with explicit cast Introduced by fd6584a22043b254a323635c142b28ce80ae5b5b Following similar use of casts in AsmParser.cpp, for instance - ideally this type would use unsigned chars as they're more representative of raw data and don't get confused around implementation defined choices of char's signedness, but this is what it is & the signed/unsigned conversions are (so far as I understand) safe/bit preserving in this usage and what's intended, given the API design here. (cherry picked from commit e31cfc4cd3e39332e9c519787c96e3b67bab) Added: Modified: llvm/lib/Target/AArch64/AArch64FrameLowering.cpp Removed: diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp index 30666009801c..83653dcbb8cf 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -442,7 +442,7 @@ MCCFIInstruction AArch64FrameLowering::createDefCFAExpressionFromSP( // Build up the expression (SP + NumBytes + NumVGScaledBytes * AArch64::VG) SmallString<64> Expr; - Expr.push_back(dwarf::DW_OP_breg0 + /*SP*/ 31); + Expr.push_back((uint8_t)(dwarf::DW_OP_breg0 + /*SP*/ 31)); Expr.push_back(0); appendVGScaledOffsetExpr(Expr, NumBytes, NumVGScaledBytes, TRI.getDwarfRegNum(AArch64::VG, true), Comment); ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] d485dbd - [AArch64][SVE] Disable tail calls if callee does not preserve SVE regs.
Author: Sander de Smalen
Date: 2020-08-17T13:58:10+02:00
New Revision: d485dbdcd1e90dd0a715e78c6532227e7ed10e4d
URL:
https://github.com/llvm/llvm-project/commit/d485dbdcd1e90dd0a715e78c6532227e7ed10e4d
DIFF:
https://github.com/llvm/llvm-project/commit/d485dbdcd1e90dd0a715e78c6532227e7ed10e4d.diff
LOG: [AArch64][SVE] Disable tail calls if callee does not preserve SVE regs.
This fixes an issue triggered by the following code, where emitEpilogue
got confused when trying to restore the SVE registers after the call,
whereas the call to bar() is implemented as a TCReturn:
int non_sve();
int sve(svint32_t x) { return non_sve(); }
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D84869
(cherry picked from commit f2916636f83dfeb4808a16045db0025783743471)
Added:
llvm/test/CodeGen/AArch64/sve-tailcall.ll
Modified:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
llvm/lib/Target/AArch64/AArch64RegisterInfo.h
Removed:
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 1500da2fdfc7..45bfa85bdc07 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -4107,6 +4107,7 @@ static bool canGuaranteeTCO(CallingConv::ID CC) {
static bool mayTailCallThisCC(CallingConv::ID CC) {
switch (CC) {
case CallingConv::C:
+ case CallingConv::AArch64_SVE_VectorCall:
case CallingConv::PreserveMost:
case CallingConv::Swift:
return true;
@@ -4126,6 +4127,15 @@ bool
AArch64TargetLowering::isEligibleForTailCallOptimization(
MachineFunction &MF = DAG.getMachineFunction();
const Function &CallerF = MF.getFunction();
CallingConv::ID CallerCC = CallerF.getCallingConv();
+
+ // If this function uses the C calling convention but has an SVE signature,
+ // then it preserves more registers and should assume the SVE_VectorCall CC.
+ // The check for matching callee-saved regs will determine whether it is
+ // eligible for TCO.
+ if (CallerCC == CallingConv::C &&
+ AArch64RegisterInfo::hasSVEArgsOrReturn(&MF))
+CallerCC = CallingConv::AArch64_SVE_VectorCall;
+
bool CCMatch = CallerCC == CalleeCC;
// When using the Windows calling convention on a non-windows OS, we want
@@ -4313,6 +4323,20 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
bool IsSibCall = false;
+ // Check callee args/returns for SVE registers and set calling convention
+ // accordingly.
+ if (CallConv == CallingConv::C) {
+bool CalleeOutSVE = any_of(Outs, [](ISD::OutputArg &Out){
+ return Out.VT.isScalableVector();
+});
+bool CalleeInSVE = any_of(Ins, [](ISD::InputArg &In){
+ return In.VT.isScalableVector();
+});
+
+if (CalleeInSVE || CalleeOutSVE)
+ CallConv = CallingConv::AArch64_SVE_VectorCall;
+ }
+
if (IsTailCall) {
// Check if it's really possible to do a tail call.
IsTailCall = isEligibleForTailCallOptimization(
@@ -4666,20 +4690,6 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
Ops.push_back(DAG.getRegister(RegToPass.first,
RegToPass.second.getValueType()));
- // Check callee args/returns for SVE registers and set calling convention
- // accordingly.
- if (CallConv == CallingConv::C) {
-bool CalleeOutSVE = any_of(Outs, [](ISD::OutputArg &Out){
- return Out.VT.isScalableVector();
-});
-bool CalleeInSVE = any_of(Ins, [](ISD::InputArg &In){
- return In.VT.isScalableVector();
-});
-
-if (CalleeInSVE || CalleeOutSVE)
- CallConv = CallingConv::AArch64_SVE_VectorCall;
- }
-
// Add a register mask operand representing the call-preserved registers.
const uint32_t *Mask;
const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index 62cc865fd1c3..3e9c8c7b6df2 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -63,7 +63,7 @@ bool AArch64RegisterInfo::regNeedsCFI(unsigned Reg,
return true;
}
-static bool hasSVEArgsOrReturn(const MachineFunction *MF) {
+bool AArch64RegisterInfo::hasSVEArgsOrReturn(const MachineFunction *MF) {
const Function &F = MF->getFunction();
return isa(F.getReturnType()) ||
any_of(F.args(), [](const Argument &Arg) {
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
index 91064787d3da..7b20f181e76d 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
@@ -42,6 +42,8 @@ class AArch64RegisterInfo final : public
AArch64GenRegisterInfo {
void UpdateCustom
[llvm-branch-commits] [llvm] 2d52adc - [SVE][CodeGen] Fix bug with store of unpacked FP scalable vectors
Author: David Sherwood
Date: 2020-08-17T13:58:11+02:00
New Revision: 2d52adc4ade0d194a3341742b01d088c5fdd70c6
URL:
https://github.com/llvm/llvm-project/commit/2d52adc4ade0d194a3341742b01d088c5fdd70c6
DIFF:
https://github.com/llvm/llvm-project/commit/2d52adc4ade0d194a3341742b01d088c5fdd70c6.diff
LOG: [SVE][CodeGen] Fix bug with store of unpacked FP scalable vectors
Fixed an incorrect pattern in lib/Target/AArch64/AArch64SVEInstrInfo.td
for storing out unpacked scalable vectors. Added
a couple of tests to
test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
Differential Revision: https://reviews.llvm.org/D85441
(cherry picked from commit 0905d9f31ead399d054c5d2a2c353e690f5c8daa)
Added:
Modified:
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
Removed:
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 3449a8bd16d2..4f29f2f18185 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1765,7 +1765,7 @@ multiclass sve_prefetch;
defm : unpred_store< store, nxv2f16, ST1H_D_IMM, PTRUE_D>;
defm : unpred_store< store, nxv4f32, ST1W_IMM, PTRUE_S>;
- defm : unpred_store< store, nxv4f32, ST1W_D_IMM, PTRUE_D>;
+ defm : unpred_store< store, nxv2f32, ST1W_D_IMM, PTRUE_D>;
defm : unpred_store< store, nxv2f64, ST1D_IMM, PTRUE_D>;
multiclass unpred_load %data,
* %a) {
store %data, * %base
ret void
}
+
+
+; Splat stores of unpacked FP scalable vectors
+
+define void @store_nxv2f32(* %out) {
+; CHECK-LABEL: store_nxv2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT:fmov z0.s, #1.
+; CHECK-NEXT:ptrue p0.d
+; CHECK-NEXT:st1w { z0.d }, p0, [x0]
+; CHECK-NEXT:ret
+ %ins = insertelement undef, float 1.0, i32 0
+ %splat = shufflevector %ins,
undef, zeroinitializer
+ store %splat, * %out
+ ret void
+}
+
+define void @store_nxv4f16(* %out) {
+; CHECK-LABEL: store_nxv4f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT:fmov z0.h, #1.
+; CHECK-NEXT:ptrue p0.s
+; CHECK-NEXT:st1h { z0.s }, p0, [x0]
+; CHECK-NEXT:ret
+ %ins = insertelement undef, half 1.0, i32 0
+ %splat = shufflevector %ins, undef,
zeroinitializer
+ store %splat, * %out
+ ret void
+}
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[llvm-branch-commits] [llvm] 8a755a4 - [AArch64][SVE] Add missing unwind info for SVE registers.
Author: Sander de Smalen
Date: 2020-08-17T13:58:10+02:00
New Revision: 8a755a4c3ee7738bbeea92829dfc2876445ff366
URL:
https://github.com/llvm/llvm-project/commit/8a755a4c3ee7738bbeea92829dfc2876445ff366
DIFF:
https://github.com/llvm/llvm-project/commit/8a755a4c3ee7738bbeea92829dfc2876445ff366.diff
LOG: [AArch64][SVE] Add missing unwind info for SVE registers.
This patch adds a CFI entry for each SVE callee saved register
that needs unwind info at an offset from the CFA. The offset is
a DWARF expression because the offset is partly scalable.
The CFI entries only cover a subset of the SVE callee-saves and
only encodes the lower 64-bits, thus implementing the lowest
common denominator ABI. Existing unwinders may support VG but
only restore the lower 64-bits.
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D84044
(cherry picked from commit bb3344c7d8c2703c910dd481ada43ecaf11536a6)
Added:
Modified:
llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
llvm/lib/Target/AArch64/AArch64FrameLowering.h
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
llvm/lib/Target/AArch64/AArch64RegisterInfo.h
llvm/test/CodeGen/AArch64/framelayout-sve.mir
llvm/test/CodeGen/AArch64/sve-trunc.ll
Removed:
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index 177d5e24fdb3..30666009801c 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -458,12 +458,44 @@ MCCFIInstruction
AArch64FrameLowering::createDefCFAExpressionFromSP(
Comment.str());
}
+MCCFIInstruction AArch64FrameLowering::createCfaOffset(
+const TargetRegisterInfo &TRI, unsigned Reg,
+const StackOffset &OffsetFromDefCFA) const {
+ int64_t NumBytes, NumVGScaledBytes;
+ OffsetFromDefCFA.getForDwarfOffset(NumBytes, NumVGScaledBytes);
+
+ unsigned DwarfReg = TRI.getDwarfRegNum(Reg, true);
+
+ // Non-scalable offsets can use DW_CFA_offset directly.
+ if (!NumVGScaledBytes)
+return MCCFIInstruction::createOffset(nullptr, DwarfReg, NumBytes);
+
+ std::string CommentBuffer;
+ llvm::raw_string_ostream Comment(CommentBuffer);
+ Comment << printReg(Reg, &TRI) << " @ cfa";
+
+ // Build up expression (NumBytes + NumVGScaledBytes * AArch64::VG)
+ SmallString<64> OffsetExpr;
+ appendVGScaledOffsetExpr(OffsetExpr, NumBytes, NumVGScaledBytes,
+ TRI.getDwarfRegNum(AArch64::VG, true), Comment);
+
+ // Wrap this into DW_CFA_expression
+ SmallString<64> CfaExpr;
+ CfaExpr.push_back(dwarf::DW_CFA_expression);
+ uint8_t buffer[16];
+ CfaExpr.append(buffer, buffer + encodeULEB128(DwarfReg, buffer));
+ CfaExpr.append(buffer, buffer + encodeULEB128(OffsetExpr.size(), buffer));
+ CfaExpr.append(OffsetExpr.str());
+
+ return MCCFIInstruction::createEscape(nullptr, CfaExpr.str(), Comment.str());
+}
+
void AArch64FrameLowering::emitCalleeSavedFrameMoves(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
const TargetSubtargetInfo &STI = MF.getSubtarget();
- const MCRegisterInfo *MRI = STI.getRegisterInfo();
+ const TargetRegisterInfo *TRI = STI.getRegisterInfo();
const TargetInstrInfo *TII = STI.getInstrInfo();
DebugLoc DL = MBB.findDebugLoc(MBBI);
@@ -474,11 +506,26 @@ void AArch64FrameLowering::emitCalleeSavedFrameMoves(
for (const auto &Info : CSI) {
unsigned Reg = Info.getReg();
-int64_t Offset =
-MFI.getObjectOffset(Info.getFrameIdx()) - getOffsetOfLocalArea();
-unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
-unsigned CFIIndex = MF.addFrameInst(
-MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
+
+// Not all unwinders may know about SVE registers, so assume the lowest
+// common demoninator.
+unsigned NewReg;
+if (static_cast(TRI)->regNeedsCFI(Reg,
NewReg))
+ Reg = NewReg;
+else
+ continue;
+
+StackOffset Offset;
+if (MFI.getStackID(Info.getFrameIdx()) == TargetStackID::SVEVector) {
+ AArch64FunctionInfo *AFI = MF.getInfo();
+ Offset = StackOffset(MFI.getObjectOffset(Info.getFrameIdx()),
MVT::nxv1i8) -
+ StackOffset(AFI->getCalleeSavedStackSize(MFI), MVT::i8);
+} else {
+ Offset = {MFI.getObjectOffset(Info.getFrameIdx()) -
+getOffsetOfLocalArea(),
+MVT::i8};
+}
+unsigned CFIIndex = MF.addFrameInst(createCfaOffset(*TRI, Reg, Offset));
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
.addCFIIndex(CFIIndex)
.setMIFlags(MachineInstr::FrameSetup);
@@ -2074,6 +2121,7 @@ static void computeCalleeSaveRegisterPairs(
// available unwind codes. This flag assures that the alignment fixup is
done
// on
Re: [llvm-branch-commits] [lld] e6ec96f - [docs] Add release notes for the 11.x release
Thanks for writing release notes!
On Mon, Aug 17, 2020 at 10:17 AM Martin Storsjö via
llvm-branch-commits wrote:
>
>
> Author: Martin Storsjö
> Date: 2020-08-17T11:17:15+03:00
> New Revision: e6ec96f4215a4f5302e4dd5d0ac287a1b0563586
>
> URL:
> https://github.com/llvm/llvm-project/commit/e6ec96f4215a4f5302e4dd5d0ac287a1b0563586
> DIFF:
> https://github.com/llvm/llvm-project/commit/e6ec96f4215a4f5302e4dd5d0ac287a1b0563586.diff
>
> LOG: [docs] Add release notes for the 11.x release
>
> Added:
>
>
> Modified:
> clang/docs/ReleaseNotes.rst
> lld/docs/ReleaseNotes.rst
> llvm/docs/ReleaseNotes.rst
>
> Removed:
>
>
>
>
> diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
> index 3264846506c6..6f336088750f 100644
> --- a/clang/docs/ReleaseNotes.rst
> +++ b/clang/docs/ReleaseNotes.rst
> @@ -191,6 +191,16 @@ Attribute Changes in Clang
> Windows Support
> ---
>
> +- Don't warn about `ms_struct may not produce Microsoft-compatible layouts
> + for classes with base classes or virtual functions` if the option is
> + enabled globally, as opposed to enabled on a specific class/struct or
> + on a specific section in the source files. This avoids needing to
> + couple `-mms-bitfields` with `-Wno-incompatible-ms-struct` if building
> + C++ code.
> +
> +- Enable `-mms-bitfields` by default for MinGW targets, matching a similar
> + change in GCC 4.7.
> +
> C Language Changes in Clang
> ---
>
>
> diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst
> index fe3de8306cd8..f0482c2428c4 100644
> --- a/lld/docs/ReleaseNotes.rst
> +++ b/lld/docs/ReleaseNotes.rst
> @@ -40,12 +40,17 @@ Breaking changes
> COFF Improvements
> -
>
> -* ...
> +* Fixed exporting symbols whose names contain a period (``.``), which was
> + a regression in lld 7.
>
> MinGW Improvements
> --
>
> -* ...
> +* Implemented new options for disabling auto import and runtime pseudo
> + relocations (``--disable-auto-import`` and
> + ``--disable-runtime-pseudo-reloc``), the ``--no-seh`` flag and options
> + for selecting file and section alignment (``--file-alignment`` and
> + ``--section-alignment``).
>
> MachO Improvements
> --
>
> diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
> index ed1718a95054..c9ac61d29676 100644
> --- a/llvm/docs/ReleaseNotes.rst
> +++ b/llvm/docs/ReleaseNotes.rst
> @@ -81,6 +81,15 @@ Changes to the LLVM IR
> Changes to building LLVM
>
>
> +Changes to the AArch64 Backend
> +--
> +
> +* Back up and restore x18 in functions with windows calling convention on
> + non-windows OSes.
> +
> +* Clearly error out on unsupported relocations when targeting COFF, instead
> + of silently accepting some (without being able to do what was requested).
> +
> Changes to the ARM Backend
> --
>
> @@ -157,6 +166,12 @@ Changes to the WebAssembly Target
> * `__attribute__((visibility("protected")))` now evokes a warning, as
>WebAssembly does not support "protected" visibility.
>
> +Changes to the Windows Target
> +-
> +
> +* Produce COFF weak external symbols for IR level weak symbols without a
> comdat
> + (e.g. for `__attribute__((weak))` in C)
> +
> Changes to the OCaml bindings
> -
>
> @@ -195,6 +210,12 @@ Changes to the LLVM tools
>symbols, i.e. mapping symbols on ARM and AArch64, by default. This matches
>the GNU nm behavior.
>
> +* llvm-rc now tolerates -1 as menu item ID, supports the language id option
> + and allows string table values to be split into multiple string literals
> +
> +* llvm-lib supports adding import library objects in addition to regular
> + object files
> +
> Changes to LLDB
> ===
>
>
>
>
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