[llvm-branch-commits] [llvm] 4a07a17 - [Xtensa] Add Xtensa basic assembler parser.
Author: Andrei Safronov
Date: 2020-07-21T13:25:50+03:00
New Revision: 4a07a17a1bfa99dfc88753a6fee305e6532959ad
URL:
https://github.com/llvm/llvm-project/commit/4a07a17a1bfa99dfc88753a6fee305e6532959ad
DIFF:
https://github.com/llvm/llvm-project/commit/4a07a17a1bfa99dfc88753a6fee305e6532959ad.diff
LOG: [Xtensa] Add Xtensa basic assembler parser.
Added:
llvm/lib/Target/Xtensa/AsmParser/CMakeLists.txt
llvm/lib/Target/Xtensa/AsmParser/LLVMBuild.txt
llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
Modified:
llvm/lib/Target/Xtensa/CMakeLists.txt
llvm/lib/Target/Xtensa/LLVMBuild.txt
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h
llvm/lib/Target/Xtensa/Xtensa.td
Removed:
diff --git a/llvm/lib/Target/Xtensa/AsmParser/CMakeLists.txt
b/llvm/lib/Target/Xtensa/AsmParser/CMakeLists.txt
new file mode 100644
index ..57d355cfc790
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/AsmParser/CMakeLists.txt
@@ -0,0 +1,7 @@
+include_directories( ${CMAKE_CURRENT_BINARY_DIR}/..
${CMAKE_CURRENT_SOURCE_DIR}/.. )
+
+add_llvm_component_library(LLVMXtensaAsmParser
+ XtensaAsmParser.cpp
+ )
+
+add_dependencies(LLVMXtensaAsmParser XtensaCommonTableGen)
diff --git a/llvm/lib/Target/Xtensa/AsmParser/LLVMBuild.txt
b/llvm/lib/Target/Xtensa/AsmParser/LLVMBuild.txt
new file mode 100644
index ..8c89a39424ca
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/AsmParser/LLVMBuild.txt
@@ -0,0 +1,22 @@
+;===- ./lib/Target/AsmParser/LLVMBuild.txt *- Conf -*--===;
+;
+; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+;
+;======;
+;
+; This is an LLVMBuild description file for the components in this
subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+; http://llvm.org/docs/LLVMBuild.html
+;
+;======;
+
+[component_0]
+type = Library
+name = XtensaAsmParser
+parent = Xtensa
+required_libraries = XtensaDesc XtensaInfo MC MCParser Support
+add_to_library_groups = Xtensa
diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
new file mode 100644
index ..555ff46c8a83
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
@@ -0,0 +1,454 @@
+//===- XtensaAsmParser.cpp - Parse Xtensa assembly to MCInst instructions
-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "MCTargetDesc/XtensaMCTargetDesc.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringSwitch.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCParser/MCAsmLexer.h"
+#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
+#include "llvm/MC/MCParser/MCTargetAsmParser.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/TargetRegistry.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "xtensa-asm-parser"
+
+struct XtensaOperand;
+
+class XtensaAsmParser : public MCTargetAsmParser {
+
+ SMLoc getLoc() const { return getParser().getTok().getLoc(); }
+
+ // Override MCTargetAsmParser.
+ bool ParseDirective(AsmToken DirectiveID) override;
+ bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
+ bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+SMLoc NameLoc, OperandVector &Operands) override;
+ bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+ OperandVector &Operands, MCStreamer &Out,
+ uint64_t &ErrorInfo,
+ bool MatchingInlineAsm) override;
+ unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
+ unsigned Kind) override;
+
+// Auto-generated instruction matching functions
+#define GET_ASSEMBLER_HEADER
+#include "XtensaGenAsmMatcher.inc"
+
+ OperandMatchResultTy parseImmediate(OperandVector &Operands);
+ OperandMatchResultTy parseRegister(OperandVector &Operands,
+ bool AllowParens = false, bool SR =
false);
+ OperandMatchResultTy parseOperandWithModifier(OperandVector &Operands);
+ bool parseOperand(OperandVector &Operands);
+
+public:
+ enum XtensaMatchRes
[llvm-branch-commits] [llvm] 1ade5a7 - [Xtensa] Add Constant Pool
Author: Andrei Safronov
Date: 2020-07-21T13:25:50+03:00
New Revision: 1ade5a7d2b920756900291fca1e32b212a8c667c
URL:
https://github.com/llvm/llvm-project/commit/1ade5a7d2b920756900291fca1e32b212a8c667c
DIFF:
https://github.com/llvm/llvm-project/commit/1ade5a7d2b920756900291fca1e32b212a8c667c.diff
LOG: [Xtensa] Add Constant Pool
Added:
llvm/lib/Target/Xtensa/XtensaConstantPoolValue.cpp
llvm/lib/Target/Xtensa/XtensaConstantPoolValue.h
Modified:
llvm/lib/Target/Xtensa/CMakeLists.txt
Removed:
diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt
b/llvm/lib/Target/Xtensa/CMakeLists.txt
index ffa3d60e120f..a4c11ea256f7 100644
--- a/llvm/lib/Target/Xtensa/CMakeLists.txt
+++ b/llvm/lib/Target/Xtensa/CMakeLists.txt
@@ -14,6 +14,7 @@ add_public_tablegen_target(XtensaCommonTableGen)
add_llvm_target(XtensaCodeGen
XtensaAsmPrinter.cpp
+ XtensaConstantPoolValue.cpp
XtensaFrameLowering.cpp
XtensaInstrInfo.cpp
XtensaISelDAGToDAG.cpp
diff --git a/llvm/lib/Target/Xtensa/XtensaConstantPoolValue.cpp
b/llvm/lib/Target/Xtensa/XtensaConstantPoolValue.cpp
new file mode 100644
index ..33bc3a80018e
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaConstantPoolValue.cpp
@@ -0,0 +1,234 @@
+//===- XtensaConstantPoolValue.cpp - Xtensa constantpool value
===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file implements the Xtensa specific constantpool value class.
+//
+//===--===//
+
+#include "XtensaConstantPoolValue.h"
+#include "llvm/ADT/FoldingSet.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/IR/Constant.h"
+#include "llvm/IR/Constants.h"
+#include "llvm/IR/GlobalValue.h"
+#include "llvm/IR/Type.h"
+#include "llvm/Support/raw_ostream.h"
+#include
+using namespace llvm;
+
+XtensaConstantPoolValue::XtensaConstantPoolValue(
+Type *Ty, unsigned id, XtensaCP::XtensaCPKind kind, bool addCurrentAddress,
+XtensaCP::XtensaCPModifier modifier)
+: MachineConstantPoolValue(Ty), LabelId(id), Kind(kind),
Modifier(modifier),
+ AddCurrentAddress(addCurrentAddress) {}
+
+XtensaConstantPoolValue::XtensaConstantPoolValue(
+LLVMContext &C, unsigned id, XtensaCP::XtensaCPKind kind,
+bool addCurrentAddress, XtensaCP::XtensaCPModifier modifier)
+: MachineConstantPoolValue((Type *)Type::getInt32Ty(C)), LabelId(id),
+ Kind(kind), Modifier(modifier), AddCurrentAddress(addCurrentAddress) {}
+
+XtensaConstantPoolValue::~XtensaConstantPoolValue() {}
+
+StringRef XtensaConstantPoolValue::getModifierText() const {
+ switch (Modifier) {
+ case XtensaCP::no_modifier:
+return "";
+ case XtensaCP::TPOFF:
+return "@TPOFF";
+ }
+ llvm_unreachable("Unknown modifier!");
+}
+
+int XtensaConstantPoolValue::getExistingMachineCPValue(MachineConstantPool *CP,
+ unsigned Alignment) {
+ llvm_unreachable("Shouldn't be calling this directly!");
+}
+
+void XtensaConstantPoolValue::addSelectionDAGCSEId(FoldingSetNodeID &ID) {
+ ID.AddInteger(LabelId);
+}
+
+bool XtensaConstantPoolValue::hasSameValue(XtensaConstantPoolValue *ACPV) {
+ if (ACPV->Kind == Kind) {
+if (ACPV->LabelId == LabelId)
+ return true;
+// Two PC relative constpool entries containing the same GV address or
+// external symbols. FIXME: What about blockaddress?
+if (Kind == XtensaCP::CPValue || Kind == XtensaCP::CPExtSymbol)
+ return true;
+ }
+ return false;
+}
+
+void XtensaConstantPoolValue::dump() const { errs() << " " << *this; }
+
+void XtensaConstantPoolValue::print(raw_ostream &O) const {}
+
+//===--===//
+// XtensaConstantPoolConstant
+//===--===//
+
+XtensaConstantPoolConstant::XtensaConstantPoolConstant(
+Type *Ty, const Constant *C, unsigned ID, XtensaCP::XtensaCPKind Kind,
+bool AddCurrentAddress)
+: XtensaConstantPoolValue((Type *)C->getType(), ID, Kind,
+ AddCurrentAddress),
+ CVal(C) {}
+
+XtensaConstantPoolConstant::XtensaConstantPoolConstant(
+const Constant *C, unsigned ID, XtensaCP::XtensaCPKind Kind,
+bool AddCurrentAddress)
+: XtensaConstantPoolValue((Type *)C->getType(), ID, Kind,
+ AddCurrentAddress),
+ CVal(C) {}
+
+XtensaConstantPoolConstant *
+XtensaConstantPoolConstant::Create(const Constant *C, unsigned ID,
+ XtensaCP::XtensaCPKind Kind) {
+ re
[llvm-branch-commits] [llvm] b43a204 - [Xtensa] Implement lowering constants.
Author: Andrei Safronov
Date: 2020-07-21T13:25:50+03:00
New Revision: b43a2047fe8b324ffea4475ecf3766e385d9e71c
URL:
https://github.com/llvm/llvm-project/commit/b43a2047fe8b324ffea4475ecf3766e385d9e71c
DIFF:
https://github.com/llvm/llvm-project/commit/b43a2047fe8b324ffea4475ecf3766e385d9e71c.diff
LOG: [Xtensa] Implement lowering constants.
Added:
Modified:
llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
llvm/lib/Target/Xtensa/XtensaISelLowering.h
Removed:
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index 3f4337936479..9ed24c994fd8 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -44,7 +44,12 @@ XtensaTargetLowering::XtensaTargetLowering(const
TargetMachine &tm,
setBooleanVectorContents(ZeroOrOneBooleanContent);
setMinFunctionAlignment(Align(4));
-
+
+ setOperationAction(ISD::Constant, MVT::i32, Custom);
+ setOperationAction(ISD::Constant, MVT::i64, Expand);
+ setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
+ setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
+
// No sign extend instructions for i1
for (MVT VT : MVT::integer_valuetypes()) {
setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
@@ -56,6 +61,11 @@ XtensaTargetLowering::XtensaTargetLowering(const
TargetMachine &tm,
computeRegisterProperties(STI.getRegisterInfo());
}
+bool XtensaTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
+bool ForCodeSize) const {
+ return false;
+}
+
//===--===//
// Calling conventions
//===--===//
@@ -297,9 +307,45 @@ XtensaTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv,
return DAG.getNode(XtensaISD::RET_FLAG, DL, MVT::Other, RetOps);
}
+SDValue XtensaTargetLowering::LowerImmediate(SDValue Op,
+ SelectionDAG &DAG) const {
+ const ConstantSDNode *CN = cast(Op);
+ SDLoc DL(CN);
+ APInt apval = CN->getAPIntValue();
+ int64_t value = apval.getSExtValue();
+ if (Op.getValueType() == MVT::i32) {
+if (value > -2048 && value <= 2047)
+ return Op;
+Type *Ty = Type::getInt32Ty(*DAG.getContext());
+Constant *CV = ConstantInt::get(Ty, value);
+SDValue CP = DAG.getConstantPool(CV, MVT::i32, 0, 0, false);
+return CP;
+ }
+ return Op;
+}
+
+SDValue XtensaTargetLowering::LowerImmediateFP(SDValue Op,
+ SelectionDAG &DAG) const {
+ const ConstantFPSDNode *CN = cast(Op);
+ SDLoc DL(CN);
+ APFloat apval = CN->getValueAPF();
+ int64_t value = FloatToBits(CN->getValueAPF().convertToFloat());
+ if (Op.getValueType() == MVT::f32) {
+Type *Ty = Type::getInt32Ty(*DAG.getContext());
+Constant *CV = ConstantInt::get(Ty, value);
+SDValue CP = DAG.getConstantPool(CV, MVT::i32, 0, 0, false);
+return DAG.getNode(ISD::BITCAST, DL, MVT::f32, CP);
+ }
+ return Op;
+}
+
SDValue XtensaTargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
switch (Op.getOpcode()) {
+ case ISD::Constant:
+return LowerImmediate(Op, DAG);
+ case ISD::ConstantFP:
+return LowerImmediateFP(Op, DAG);
default:
llvm_unreachable("Unexpected node to lower");
}
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h
b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
index 2df2a074fe25..e2ed301e45eb 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
@@ -36,6 +36,8 @@ class XtensaTargetLowering : public TargetLowering {
explicit XtensaTargetLowering(const TargetMachine &TM,
const XtensaSubtarget &STI);
+ bool isFPImmLegal(const APFloat &Imm, EVT VT,
+bool ForCodeSize) const override;
const char *getTargetNodeName(unsigned Opcode) const override;
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
@@ -57,6 +59,9 @@ class XtensaTargetLowering : public TargetLowering {
private:
const XtensaSubtarget &Subtarget;
+ SDValue LowerImmediate(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerImmediateFP(SDValue Op, SelectionDAG &DAG) const;
+
CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
};
___
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[llvm-branch-commits] [llvm] ae4dd5f - [Xtensa] Add basic *td files with Xtensa architecture
Author: Andrei Safronov
Date: 2020-07-21T13:25:50+03:00
New Revision: ae4dd5fc0aa67ff3b9a00fbc93a57ff1a7a8ad31
URL:
https://github.com/llvm/llvm-project/commit/ae4dd5fc0aa67ff3b9a00fbc93a57ff1a7a8ad31
DIFF:
https://github.com/llvm/llvm-project/commit/ae4dd5fc0aa67ff3b9a00fbc93a57ff1a7a8ad31.diff
LOG: [Xtensa] Add basic *td files with Xtensa architecture
description.
Add Xtensa.td, XtensaInstrInfo.td etc. Currently add just part of Core
Instructions like ALU, processor control, memory barrier and some move
instructions. Add instructions formats and basic registers.
Added:
llvm/lib/Target/Xtensa/Xtensa.td
llvm/lib/Target/Xtensa/XtensaInstrFormats.td
llvm/lib/Target/Xtensa/XtensaInstrInfo.td
llvm/lib/Target/Xtensa/XtensaOperands.td
llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
Modified:
llvm/lib/Target/Xtensa/CMakeLists.txt
Removed:
diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt
b/llvm/lib/Target/Xtensa/CMakeLists.txt
index 2a3a6f6a79e6..a68b54551d15 100644
--- a/llvm/lib/Target/Xtensa/CMakeLists.txt
+++ b/llvm/lib/Target/Xtensa/CMakeLists.txt
@@ -1,3 +1,10 @@
+set(LLVM_TARGET_DEFINITIONS Xtensa.td)
+
+tablegen(LLVM XtensaGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM XtensaGenRegisterInfo.inc -gen-register-info)
+
+add_public_tablegen_target(XtensaCommonTableGen)
+
add_llvm_target(XtensaCodeGen
XtensaTargetMachine.cpp
)
diff --git a/llvm/lib/Target/Xtensa/Xtensa.td
b/llvm/lib/Target/Xtensa/Xtensa.td
new file mode 100644
index ..9a09d9769fcd
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/Xtensa.td
@@ -0,0 +1,53 @@
+//===- Xtensa.td - Describe the Xtensa Target Machine ---*- tablegen
-*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---===//
+
+//===--===//
+// Target-independent interfaces
+//===--===//
+
+include "llvm/Target/Target.td"
+
+//===--===//
+// Subtarget Features.
+//===--===//
+def FeatureDensity : SubtargetFeature<"density", "HasDensity", "true",
+"Enable Density instructions">;
+def HasDensity : Predicate<"Subtarget->hasDensity()">,
+ AssemblerPredicate<"FeatureDensity">;
+//===--===//
+// Xtensa supported processors.
+//===--===//
+class Proc Features>
+: Processor;
+
+def : Proc<"generic", []>;
+
+//===--===//
+// Register File Description
+//===--===//
+
+include "XtensaRegisterInfo.td"
+
+//===--===//
+// Instruction Descriptions
+//===--===//
+
+include "XtensaInstrInfo.td"
+
+def XtensaInstrInfo : InstrInfo;
+
+//===--===//
+// Target Declaration
+//===--===//
+
+def Xtensa : Target
+{
+ let InstructionSet = XtensaInstrInfo;
+}
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrFormats.td
b/llvm/lib/Target/Xtensa/XtensaInstrFormats.td
new file mode 100644
index ..b8cff7c93732
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaInstrFormats.td
@@ -0,0 +1,237 @@
+//===- XtensaInstrFormats.td - Xtensa Instruction Formats ---*- tablegen
-*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---===//
+
+// Base class for Xtensa 16 & 24 bit Formats
+class XtensaInst pattern,
+ InstrItinClass itin = NoItinerary>: Instruction
+{
+ let Namespace = "Xtensa";
+
+ let Size = size;
+
+ let OutOperandList = outs;
+ let InOperandList = ins;
+
+ let AsmString = asmstr;
+ let Pattern = pattern;
+ let Itinerary = itin;
+
+}
+
+// Base class for Xtensa 24 bit Format
+class XtensaInst24 pattern,
+ InstrItinClass itin = NoItinerary>:
+
[llvm-branch-commits] [llvm] 5d977f2 - [Xtensa] Implement assembler representation of the Constant Pool.
Author: Andrei Safronov
Date: 2020-07-21T13:25:50+03:00
New Revision: 5d977f2260f4f37b6da9e7727ca2106a64a27596
URL:
https://github.com/llvm/llvm-project/commit/5d977f2260f4f37b6da9e7727ca2106a64a27596
DIFF:
https://github.com/llvm/llvm-project/commit/5d977f2260f4f37b6da9e7727ca2106a64a27596.diff
LOG: [Xtensa] Implement assembler representation of the Constant Pool.
Added:
Modified:
llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
Removed:
diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
index 4b5b824420bc..94085c93c4e1 100644
--- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
@@ -14,6 +14,7 @@
//===--===//
#include "XtensaAsmPrinter.h"
+#include "XtensaConstantPoolValue.h"
#include "XtensaMCInstLower.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/CodeGen/MachineModuleInfoImpls.h"
@@ -27,6 +28,17 @@
using namespace llvm;
+static MCSymbolRefExpr::VariantKind
+getModifierVariantKind(XtensaCP::XtensaCPModifier Modifier) {
+ switch (Modifier) {
+ case XtensaCP::no_modifier:
+return MCSymbolRefExpr::VK_None;
+ case XtensaCP::TPOFF:
+return MCSymbolRefExpr::VK_TPOFF;
+ }
+ llvm_unreachable("Invalid XtensaCPModifier!");
+}
+
void XtensaAsmPrinter::EmitInstruction(const MachineInstr *MI) {
XtensaMCInstLower Lower(MF->getContext(), *this);
MCInst LoweredMI;
@@ -34,6 +46,164 @@ void XtensaAsmPrinter::EmitInstruction(const MachineInstr
*MI) {
EmitToStreamer(*OutStreamer, LoweredMI);
}
+/// EmitConstantPool - Print to the current output stream assembly
+/// representations of the constants in the constant pool MCP. This is
+/// used to print out constants which have been "spilled to memory" by
+/// the code generator.
+void XtensaAsmPrinter::EmitConstantPool() {
+ const Function &F = MF->getFunction();
+ const MachineConstantPool *MCP = MF->getConstantPool();
+ const std::vector &CP = MCP->getConstants();
+ if (CP.empty())
+return;
+
+ for (unsigned i = 0, e = CP.size(); i != e; ++i) {
+const MachineConstantPoolEntry &CPE = CP[i];
+
+if (i == 0) {
+ if (OutStreamer->hasRawTextSupport()) {
+OutStreamer->SwitchSection(
+getObjFileLowering().SectionForGlobal(&F, TM));
+OutStreamer->EmitRawText("\t.literal_position\n");
+ } else {
+MCSectionELF *CS =
+(MCSectionELF *)getObjFileLowering().SectionForGlobal(&F, TM);
+std::string CSectionName = CS->getSectionName();
+std::size_t Pos = CSectionName.find(".text");
+std::string SectionName;
+if (Pos != std::string::npos) {
+ if (Pos > 0)
+SectionName = CSectionName.substr(0, Pos + 5);
+ else
+SectionName = "";
+ SectionName += ".literal";
+ SectionName += CSectionName.substr(Pos + 5);
+} else {
+ SectionName = CSectionName;
+ SectionName += ".literal";
+}
+
+MCSectionELF *S =
+OutContext.getELFSection(SectionName, ELF::SHT_PROGBITS,
+ ELF::SHF_EXECINSTR | ELF::SHF_ALLOC);
+S->setAlignment(Align(4));
+OutStreamer->SwitchSection(S);
+ }
+}
+
+if (CPE.isMachineConstantPoolEntry()) {
+ XtensaConstantPoolValue *ACPV =
+ static_cast(CPE.Val.MachineCPVal);
+ ACPV->setLabelId(i);
+ EmitMachineConstantPoolValue(CPE.Val.MachineCPVal);
+} else {
+ MCSymbol *LblSym = GetCPISymbol(i);
+ // TODO find a better way to check whether we emit data to .s file
+ if (OutStreamer->hasRawTextSupport()) {
+std::string str("\t.literal ");
+str += LblSym->getName();
+str += ", ";
+const Constant *C = CPE.Val.ConstVal;
+
+Type *Ty = C->getType();
+if (const auto *CFP = dyn_cast(C)) {
+ str += CFP->getValueAPF().bitcastToAPInt().toString(10, true);
+} else if (const auto *CI = dyn_cast(C)) {
+ str += CI->getValue().toString(10, true);
+} else if (isa(Ty)) {
+ const MCExpr *ME = lowerConstant(C);
+ const MCSymbolRefExpr &SRE = cast(*ME);
+ const MCSymbol &Sym = SRE.getSymbol();
+ str += Sym.getName();
+} else {
+ unsigned NumElements;
+ if (isa(Ty))
+NumElements = Ty->getVectorNumElements();
+ else
+NumElements = Ty->getArrayNumElements();
+
+ for (unsigned I = 0; I < NumElements; I++) {
+const Constant *CAE = C->getAggregateElement(I);
+if (I > 0)
+ str += ", ";
+if (const auto *CFP = dyn_cast(CAE)) {
+ str += CFP->getValueAPF().bitcastToAPInt().toString(10, true);
+} e
[llvm-branch-commits] [llvm] a5de2cb - [Xtensa] Add definitions and relocs for Xtensa ELF.
Author: Andrei Safronov
Date: 2020-07-21T13:25:50+03:00
New Revision: a5de2cb07ee51335238913565f9a58ed73f1bac8
URL:
https://github.com/llvm/llvm-project/commit/a5de2cb07ee51335238913565f9a58ed73f1bac8
DIFF:
https://github.com/llvm/llvm-project/commit/a5de2cb07ee51335238913565f9a58ed73f1bac8.diff
LOG: [Xtensa] Add definitions and relocs for Xtensa ELF.
Added:
llvm/include/llvm/BinaryFormat/ELFRelocs/Xtensa.def
llvm/test/tools/llvm-readobj/ELF/reloc-types-xtensa.test
Modified:
llvm/include/llvm/BinaryFormat/ELF.h
llvm/include/llvm/Object/ELFObjectFile.h
llvm/include/llvm/module.modulemap
llvm/lib/Object/ELF.cpp
llvm/lib/ObjectYAML/ELFYAML.cpp
llvm/test/Object/obj2yaml.test
Removed:
diff --git a/llvm/include/llvm/BinaryFormat/ELF.h
b/llvm/include/llvm/BinaryFormat/ELF.h
index caab91da9c83..47ee28101513 100644
--- a/llvm/include/llvm/BinaryFormat/ELF.h
+++ b/llvm/include/llvm/BinaryFormat/ELF.h
@@ -767,6 +767,21 @@ enum {
#include "ELFRelocs/MSP430.def"
};
+// Xtensa specific e_flags
+enum : unsigned {
+ // Four-bit Xtensa machine type mask.
+ EF_XTENSA_MACH = 0x000f,
+ // Various CPU types.
+ EF_XTENSA_MACH_NONE = 0x, //A base Xtensa implementation
+ EF_XTENSA_XT_INSN = 0x0100,
+ EF_XTENSA_XT_LIT = 0x0200,
+};
+
+// ELF Relocation types for Xtensa
+enum {
+#include "ELFRelocs/Xtensa.def"
+};
+
#undef ELF_RELOC
// Section header.
diff --git a/llvm/include/llvm/BinaryFormat/ELFRelocs/Xtensa.def
b/llvm/include/llvm/BinaryFormat/ELFRelocs/Xtensa.def
new file mode 100644
index ..becc5fb46920
--- /dev/null
+++ b/llvm/include/llvm/BinaryFormat/ELFRelocs/Xtensa.def
@@ -0,0 +1,59 @@
+#ifndef ELF_RELOC
+#error "ELF_RELOC must be defined"
+#endif
+
+ELF_RELOC (R_XTENSA_NONE, 0)
+ELF_RELOC (R_XTENSA_32, 1)
+ELF_RELOC (R_XTENSA_RTLD, 2)
+ELF_RELOC (R_XTENSA_GLOB_DAT, 3)
+ELF_RELOC (R_XTENSA_JMP_SLOT, 4)
+ELF_RELOC (R_XTENSA_RELATIVE, 5)
+ELF_RELOC (R_XTENSA_PLT, 6)
+ELF_RELOC (R_XTENSA_OP0, 8)
+ELF_RELOC (R_XTENSA_OP1, 9)
+ELF_RELOC (R_XTENSA_OP2, 10)
+ELF_RELOC (R_XTENSA_ASM_EXPAND, 11)
+ELF_RELOC (R_XTENSA_ASM_SIMPLIFY, 12)
+ELF_RELOC (R_XTENSA_32_PCREL, 14)
+ELF_RELOC (R_XTENSA_GNU_VTINHERIT, 15)
+ELF_RELOC (R_XTENSA_GNU_VTENTRY, 16)
+ELF_RELOC (R_XTENSA_DIFF8, 17)
+ELF_RELOC (R_XTENSA_DIFF16, 18)
+ELF_RELOC (R_XTENSA_DIFF32, 19)
+ELF_RELOC (R_XTENSA_SLOT0_OP, 20)
+ELF_RELOC (R_XTENSA_SLOT1_OP, 21)
+ELF_RELOC (R_XTENSA_SLOT2_OP, 22)
+ELF_RELOC (R_XTENSA_SLOT3_OP, 23)
+ELF_RELOC (R_XTENSA_SLOT4_OP, 24)
+ELF_RELOC (R_XTENSA_SLOT5_OP, 25)
+ELF_RELOC (R_XTENSA_SLOT6_OP, 26)
+ELF_RELOC (R_XTENSA_SLOT7_OP, 27)
+ELF_RELOC (R_XTENSA_SLOT8_OP, 28)
+ELF_RELOC (R_XTENSA_SLOT9_OP, 29)
+ELF_RELOC (R_XTENSA_SLOT10_OP, 30)
+ELF_RELOC (R_XTENSA_SLOT11_OP, 31)
+ELF_RELOC (R_XTENSA_SLOT12_OP, 32)
+ELF_RELOC (R_XTENSA_SLOT13_OP, 33)
+ELF_RELOC (R_XTENSA_SLOT14_OP, 34)
+ELF_RELOC (R_XTENSA_SLOT0_ALT, 35)
+ELF_RELOC (R_XTENSA_SLOT1_ALT, 36)
+ELF_RELOC (R_XTENSA_SLOT2_ALT, 37)
+ELF_RELOC (R_XTENSA_SLOT3_ALT, 38)
+ELF_RELOC (R_XTENSA_SLOT4_ALT, 39)
+ELF_RELOC (R_XTENSA_SLOT5_ALT, 40)
+ELF_RELOC (R_XTENSA_SLOT6_ALT, 41)
+ELF_RELOC (R_XTENSA_SLOT7_ALT, 42)
+ELF_RELOC (R_XTENSA_SLOT8_ALT, 43)
+ELF_RELOC (R_XTENSA_SLOT9_ALT, 44)
+ELF_RELOC (R_XTENSA_SLOT10_ALT, 45)
+ELF_RELOC (R_XTENSA_SLOT11_ALT, 46)
+ELF_RELOC (R_XTENSA_SLOT12_ALT, 47)
+ELF_RELOC (R_XTENSA_SLOT13_ALT, 48)
+ELF_RELOC (R_XTENSA_SLOT14_ALT, 49)
+ELF_RELOC (R_XTENSA_TLSDESC_FN, 50)
+ELF_RELOC (R_XTENSA_TLSDESC_ARG, 51)
+ELF_RELOC (R_XTENSA_TLS_DTPOFF, 52)
+ELF_RELOC (R_XTENSA_TLS_TPOFF, 53)
+ELF_RELOC (R_XTENSA_TLS_FUNC, 54)
+ELF_RELOC (R_XTENSA_TLS_ARG, 55)
+ELF_RELOC (R_XTENSA_TLS_CALL, 56)
diff --git a/llvm/include/llvm/Object/ELFObjectFile.h
b/llvm/include/llvm/Object/ELFObjectFile.h
index 8a68e49477fd..10e07dd13ca5 100644
--- a/llvm/include/llvm/Object/ELFObjectFile.h
+++ b/llvm/include/llvm/Object/ELFObjectFile.h
@@ -1085,6 +1085,8 @@ StringRef ELFObjectFile::getFileFormatName() const {
return "ELF32-sparc";
case ELF::EM_AMDGPU:
return "ELF32-amdgpu";
+case ELF::EM_XTENSA:
+ return "ELF32-Xtensa";
default:
return "ELF32-unknown";
}
@@ -1187,7 +1189,8 @@ template Triple::ArchType
ELFObjectFile::getArch() const {
case ELF::EM_BPF:
return IsLittleEndian ? Triple::bpfel : Triple::bpfeb;
-
+ case ELF::EM_XTENSA:
+return Triple::xtensa;
default:
return Triple::UnknownArch;
}
diff --git a/llvm/include/llvm/module.modulemap
b/llvm/include/llvm/module.modulemap
index d281682ae003..67e4dcf92656 100644
--- a/llvm/include/llvm/module.modulemap
+++ b/llvm/include/llvm/module.modulemap
@@ -72,6 +72,7 @@ module LLVM_BinaryFormat {
textual header "BinaryFormat/ELFRelocs/Sparc.def"
textual header "BinaryFormat/ELFRelocs/SystemZ.def"
textual header "BinaryFormat/ELFRelocs/x86_64.def"
+textual header "BinaryFormat/ELFR
[llvm-branch-commits] [llvm] 11f4719 - [Xtensa] Codegen support for memory operations
Author: Andrei Safronov
Date: 2020-07-21T13:25:50+03:00
New Revision: 11f471988303a529ea0dbca706a9c7c27f49d47b
URL:
https://github.com/llvm/llvm-project/commit/11f471988303a529ea0dbca706a9c7c27f49d47b
DIFF:
https://github.com/llvm/llvm-project/commit/11f471988303a529ea0dbca706a9c7c27f49d47b.diff
LOG: [Xtensa] Codegen support for memory operations
Added:
Modified:
llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
Removed:
diff --git a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
index d5244a74b0b1..456ecc1ae8d0 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
@@ -42,7 +42,62 @@ class XtensaDAGToDAGISel : public SelectionDAGISel {
bool selectMemRegAddr(SDValue Addr, SDValue &Base, SDValue &Offset,
int Scale) {
-report_fatal_error("MemReg address is not implemented yet");
+EVT ValTy = Addr.getValueType();
+
+// if Address is FI, get the TargetFrameIndex.
+if (FrameIndexSDNode *FIN = dyn_cast(Addr)) {
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
+ Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy);
+
+ return true;
+}
+
+if (TM.isPositionIndependent())
+ report_fatal_error("PIC relocations is not supported");
+
+if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
+ Addr.getOpcode() == ISD::TargetGlobalAddress))
+ return false;
+
+// Addresses of the form FI+const or FI|const
+bool Valid = false;
+if (CurDAG->isBaseWithConstantOffset(Addr)) {
+ ConstantSDNode *CN = dyn_cast(Addr.getOperand(1));
+ int64_t OffsetVal = CN->getSExtValue();
+
+ switch (Scale) {
+ case 1:
+Valid = (OffsetVal >= 0 && OffsetVal <= 255);
+break;
+ case 2:
+Valid =
+(OffsetVal >= 0 && OffsetVal <= 510) && ((OffsetVal & 0x1) == 0);
+break;
+ case 4:
+Valid =
+(OffsetVal >= 0 && OffsetVal <= 1020) && ((OffsetVal & 0x3) == 0);
+break;
+ default:
+break;
+ }
+
+ if (Valid) {
+// If the first operand is a FI, get the TargetFI Node
+if (FrameIndexSDNode *FIN =
+dyn_cast(Addr.getOperand(0)))
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
+else
+ Base = Addr.getOperand(0);
+
+Offset =
+CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr), ValTy);
+return true;
+ }
+}
+
+// Last case
+Base = Addr;
+Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType());
return true;
}
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index c9fe87762c7b..3f4337936479 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -44,6 +44,13 @@ XtensaTargetLowering::XtensaTargetLowering(const
TargetMachine &tm,
setBooleanVectorContents(ZeroOrOneBooleanContent);
setMinFunctionAlignment(Align(4));
+
+ // No sign extend instructions for i1
+ for (MVT VT : MVT::integer_valuetypes()) {
+setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
+setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
+setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
+ }
// Compute derived properties from the register classes
computeRegisterProperties(STI.getRegisterInfo());
___
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[llvm-branch-commits] [llvm] 52c60b8 - [Xtensa] Add support of the rest part of Xtensa Core
Author: Andrei Safronov
Date: 2020-07-21T13:25:50+03:00
New Revision: 52c60b8d91e95dec05bb0701b8c54ce0e1cec5cd
URL:
https://github.com/llvm/llvm-project/commit/52c60b8d91e95dec05bb0701b8c54ce0e1cec5cd
DIFF:
https://github.com/llvm/llvm-project/commit/52c60b8d91e95dec05bb0701b8c54ce0e1cec5cd.diff
LOG: [Xtensa] Add support of the rest part of Xtensa Core
Instructions.
Add relocations and fixups support in object files generation.
Modify tests to support new instructions. Add tests for relocations
and fixups.
Added:
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaFixupKinds.h
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCExpr.cpp
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCExpr.h
llvm/test/MC/Xtensa/fixups-diagnostics.s
llvm/test/MC/Xtensa/fixups.s
llvm/test/MC/Xtensa/relocations.s
Modified:
llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaELFObjectWriter.cpp
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
llvm/lib/Target/Xtensa/XtensaInstrInfo.td
llvm/lib/Target/Xtensa/XtensaOperands.td
llvm/test/MC/Xtensa/xtensa-invalid.s
llvm/test/MC/Xtensa/xtensa-valid.s
Removed:
diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
index 2bc7178b865c..3d4c8de58ada 100644
--- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
+++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
@@ -57,6 +57,7 @@ class XtensaAsmParser : public MCTargetAsmParser {
bool SR = false);
bool ParseInstructionWithSR(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc, OperandVector &Operands);
+ OperandMatchResultTy parsePCRelTarget(OperandVector &Operands);
public:
enum XtensaMatchResultTy {
@@ -174,6 +175,66 @@ struct XtensaOperand : public MCParsedAsmOperand {
bool isImm1_16() const { return isImm(1, 16); }
+ bool isB4const() const {
+if (Kind != Immediate)
+ return false;
+if (auto *CE = dyn_cast(getImm())) {
+ int64_t Value = CE->getValue();
+ switch (Value) {
+ case -1:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ case 8:
+ case 10:
+ case 12:
+ case 16:
+ case 32:
+ case 64:
+ case 128:
+ case 256:
+return true;
+ default:
+return false;
+ }
+}
+return false;
+ }
+
+ bool isB4constu() const {
+if (Kind != Immediate)
+ return false;
+if (auto *CE = dyn_cast(getImm())) {
+ int64_t Value = CE->getValue();
+ switch (Value) {
+ case 32768:
+ case 65536:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ case 8:
+ case 10:
+ case 12:
+ case 16:
+ case 32:
+ case 64:
+ case 128:
+ case 256:
+return true;
+ default:
+return false;
+ }
+}
+return false;
+ }
+
/// getStartLoc - Gets location of the first token of this operand
SMLoc getStartLoc() const override { return StartLoc; }
/// getEndLoc - Gets location of the last token of this operand
@@ -322,6 +383,12 @@ bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc,
unsigned &Opcode,
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected immediate in range [-32768, 32512], first 8 bits "
"should be zero");
+ case Match_InvalidB4const:
+return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected b4const immediate");
+ case Match_InvalidB4constu:
+return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected b4constu immediate");
case Match_InvalidImm12:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected immediate in range [-2048, 2047]");
@@ -360,6 +427,30 @@ bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc,
unsigned &Opcode,
llvm_unreachable("Unknown match type detected!");
}
+OperandMatchResultTy
+XtensaAsmParser::parsePCRelTarget(OperandVector &Operands) {
+ MCAsmParser &Parser = getParser();
+ LLVM_DEBUG(dbgs() << "parsePCRelTarget\n");
+
+ SMLoc S = getLexer().getLoc();
+
+ // Expressions are acceptable
+ const MCExpr *Expr = nullptr;
+ if (Parser.parseExpression(Expr)) {
+// We have no way of knowing if a symbol was consumed so we must ParseFail
+return MatchOperand_ParseFail;
+ }
+
+ // Currently not support constants
+ if (Expr->getKind()
[llvm-branch-commits] [llvm] 82bd91c - [Xtensa] Add initial version of the Xtensa backend.
Author: Andrei Safronov Date: 2020-07-21T13:25:50+03:00 New Revision: 82bd91c55a4374cbe11d171e1a25e84aa701791e URL: https://github.com/llvm/llvm-project/commit/82bd91c55a4374cbe11d171e1a25e84aa701791e DIFF: https://github.com/llvm/llvm-project/commit/82bd91c55a4374cbe11d171e1a25e84aa701791e.diff LOG: [Xtensa] Add initial version of the Xtensa backend. Added: llvm/lib/Target/Xtensa/CMakeLists.txt llvm/lib/Target/Xtensa/LLVMBuild.txt llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt llvm/lib/Target/Xtensa/MCTargetDesc/LLVMBuild.txt llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h llvm/lib/Target/Xtensa/TargetInfo/CMakeLists.txt llvm/lib/Target/Xtensa/TargetInfo/LLVMBuild.txt llvm/lib/Target/Xtensa/TargetInfo/XtensaTargetInfo.cpp llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp llvm/lib/Target/Xtensa/XtensaTargetMachine.h Modified: llvm/lib/Target/LLVMBuild.txt Removed: diff --git a/llvm/lib/Target/LLVMBuild.txt b/llvm/lib/Target/LLVMBuild.txt index 7403f7713a9f..e6a67b7e4cb3 100644 --- a/llvm/lib/Target/LLVMBuild.txt +++ b/llvm/lib/Target/LLVMBuild.txt @@ -36,6 +36,7 @@ subdirectories = WebAssembly X86 XCore + Xtensa VE ; This is a special group whose required libraries are extended (by llvm-build) diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt b/llvm/lib/Target/Xtensa/CMakeLists.txt new file mode 100644 index ..2a3a6f6a79e6 --- /dev/null +++ b/llvm/lib/Target/Xtensa/CMakeLists.txt @@ -0,0 +1,6 @@ +add_llvm_target(XtensaCodeGen + XtensaTargetMachine.cpp + ) + +add_subdirectory(MCTargetDesc) +add_subdirectory(TargetInfo) diff --git a/llvm/lib/Target/Xtensa/LLVMBuild.txt b/llvm/lib/Target/Xtensa/LLVMBuild.txt new file mode 100644 index ..e12ab339883c --- /dev/null +++ b/llvm/lib/Target/Xtensa/LLVMBuild.txt @@ -0,0 +1,30 @@ +;===- ./lib/Target/Xtensa/LLVMBuild.txt *- Conf -*--===; +; +; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +; See https://llvm.org/LICENSE.txt for license information. +; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +; +;======; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;======; + +[common] +subdirectories = TargetInfo MCTargetDesc + +[component_0] +type = TargetGroup +name = Xtensa +parent = Target + +[component_1] +type = Library +name = XtensaCodeGen +parent = Xtensa +required_libraries = CodeGen Core XtensaInfo Support Target +add_to_library_groups = Xtensa diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt new file mode 100644 index ..dad428b96129 --- /dev/null +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt @@ -0,0 +1,3 @@ +add_llvm_component_library(LLVMXtensaDesc + XtensaMCTargetDesc.cpp + ) diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/LLVMBuild.txt b/llvm/lib/Target/Xtensa/MCTargetDesc/LLVMBuild.txt new file mode 100644 index ..8b31bbf0c087 --- /dev/null +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/LLVMBuild.txt @@ -0,0 +1,22 @@ +;===- ./lib/Target/MCTargetDesc/LLVMBuild.txt --*- Conf -*--===; +; +; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +; See https://llvm.org/LICENSE.txt for license information. +; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +; +;======; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;======; + +[component_0] +type = Library +name = XtensaDesc +parent = Xtensa +required_libraries = MC XtensaInfo Support +add_to_library_groups = Xtensa diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp new file mode 100644 index ..c9c0996b07a9 --- /dev/null +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp @@ -0,0 +1,13 @@ +//===-- XtensaMCTargetDesc.cpp - Xtebsa target descriptions ---===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===
[llvm-branch-commits] [llvm] 34385c2 - [Xtensa] Add basic Xtensa instruction printer.
Author: Andrei Safronov
Date: 2020-07-21T13:25:50+03:00
New Revision: 34385c2abb851926b88160a10cf05792c255e20a
URL:
https://github.com/llvm/llvm-project/commit/34385c2abb851926b88160a10cf05792c255e20a
DIFF:
https://github.com/llvm/llvm-project/commit/34385c2abb851926b88160a10cf05792c255e20a.diff
LOG: [Xtensa] Add basic Xtensa instruction printer.
Add instruction printer and basic tests of the
Xtensa instructions.
Added:
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
llvm/test/MC/Xtensa/elf-header.s
llvm/test/MC/Xtensa/lit.local.cfg
llvm/test/MC/Xtensa/xtensa-invalid.s
llvm/test/MC/Xtensa/xtensa-valid.s
Modified:
llvm/lib/Target/Xtensa/CMakeLists.txt
llvm/lib/Target/Xtensa/LLVMBuild.txt
llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
llvm/lib/Target/Xtensa/Xtensa.td
Removed:
diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt
b/llvm/lib/Target/Xtensa/CMakeLists.txt
index 67b79b18ba38..d2bdea4cb0f9 100644
--- a/llvm/lib/Target/Xtensa/CMakeLists.txt
+++ b/llvm/lib/Target/Xtensa/CMakeLists.txt
@@ -1,6 +1,7 @@
set(LLVM_TARGET_DEFINITIONS Xtensa.td)
tablegen(LLVM XtensaGenAsmMatcher.inc -gen-asm-matcher)
+tablegen(LLVM XtensaGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM XtensaGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM XtensaGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM XtensaGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/Xtensa/LLVMBuild.txt
b/llvm/lib/Target/Xtensa/LLVMBuild.txt
index e1577083ca01..360a01479840 100644
--- a/llvm/lib/Target/Xtensa/LLVMBuild.txt
+++ b/llvm/lib/Target/Xtensa/LLVMBuild.txt
@@ -22,10 +22,11 @@ type = TargetGroup
name = Xtensa
parent = Target
has_asmparser = 1
+has_asmprinter = 1
[component_1]
type = Library
name = XtensaCodeGen
parent = Xtensa
-required_libraries = CodeGen Core XtensaInfo Support Target
+required_libraries = AsmPrinter CodeGen Core MC XtensaDesc XtensaInfo Support
Target
add_to_library_groups = Xtensa
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
b/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
index ee905f70136a..c1a06f35f6b7 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
@@ -1,6 +1,7 @@
add_llvm_component_library(LLVMXtensaDesc
XtensaAsmBackend.cpp
XtensaELFObjectWriter.cpp
+ XtensaInstPrinter.cpp
XtensaMCAsmInfo.cpp
XtensaMCCodeEmitter.cpp
XtensaMCTargetDesc.cpp
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
new file mode 100644
index ..7cd363ac4314
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
@@ -0,0 +1,105 @@
+//===- XtensaInstPrinter.cpp - Convert Xtensa MCInst to asm syntax
===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This class prints an Xtensa MCInst to a .s file.
+//
+//===--===//
+
+#include "XtensaInstPrinter.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCSymbol.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "asm-printer"
+
+#include "XtensaGenAsmWriter.inc"
+
+static void printExpr(const MCExpr *Expr, raw_ostream &OS) {
+ int Offset = 0;
+ const MCSymbolRefExpr *SRE;
+
+ if (!(SRE = dyn_cast(Expr)))
+assert(false && "Unexpected MCExpr type.");
+
+ MCSymbolRefExpr::VariantKind Kind = SRE->getKind();
+
+ switch (Kind) {
+ case MCSymbolRefExpr::VK_None:
+break;
+ // TODO
+ default:
+llvm_unreachable("Invalid kind!");
+ }
+
+ OS << SRE->getSymbol();
+
+ if (Offset) {
+if (Offset > 0)
+ OS << '+';
+OS << Offset;
+ }
+
+ if (Kind != MCSymbolRefExpr::VK_None)
+OS << ')';
+}
+
+void XtensaInstPrinter::printOperand(const MCOperand &MC, raw_ostream &O) {
+ if (MC.isReg())
+O << getRegisterName(MC.getReg());
+ else if (MC.isImm())
+O << MC.getImm();
+ else if (MC.isExpr())
+printExpr(MC.getExpr(), O);
+ else
+llvm_unreachable("Invalid operand");
+}
+
+void XtensaInstPrinter::printInst(const MCInst *MI, uint64_t Address,
+ StringRef Annot, const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+ printInstruction(MI, Address, O);
+ printAnnotation(O, Annot);
+}
+
+v
[llvm-branch-commits] [llvm] 033e45a - [Xtensa] Initial codegen support for simple ALU operations.
Author: Andrei Safronov
Date: 2020-07-21T13:25:50+03:00
New Revision: 033e45a8a8daf67efbd0985292e35551d83dd291
URL:
https://github.com/llvm/llvm-project/commit/033e45a8a8daf67efbd0985292e35551d83dd291
DIFF:
https://github.com/llvm/llvm-project/commit/033e45a8a8daf67efbd0985292e35551d83dd291.diff
LOG: [Xtensa] Initial codegen support for simple ALU operations.
Added:
llvm/lib/Target/Xtensa/Xtensa.h
llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
llvm/lib/Target/Xtensa/XtensaCallingConv.td
llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
llvm/lib/Target/Xtensa/XtensaFrameLowering.h
llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
llvm/lib/Target/Xtensa/XtensaISelLowering.h
llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
llvm/lib/Target/Xtensa/XtensaInstrInfo.h
llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp
llvm/lib/Target/Xtensa/XtensaMCInstLower.h
llvm/lib/Target/Xtensa/XtensaOperators.td
llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
llvm/lib/Target/Xtensa/XtensaRegisterInfo.h
llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
llvm/lib/Target/Xtensa/XtensaSubtarget.h
Modified:
llvm/lib/Target/Xtensa/CMakeLists.txt
llvm/lib/Target/Xtensa/LLVMBuild.txt
llvm/lib/Target/Xtensa/Xtensa.td
llvm/lib/Target/Xtensa/XtensaInstrInfo.td
llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
llvm/lib/Target/Xtensa/XtensaTargetMachine.h
Removed:
diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt
b/llvm/lib/Target/Xtensa/CMakeLists.txt
index 28deec14ddb1..ffa3d60e120f 100644
--- a/llvm/lib/Target/Xtensa/CMakeLists.txt
+++ b/llvm/lib/Target/Xtensa/CMakeLists.txt
@@ -2,6 +2,8 @@ set(LLVM_TARGET_DEFINITIONS Xtensa.td)
tablegen(LLVM XtensaGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM XtensaGenAsmWriter.inc -gen-asm-writer)
+tablegen(LLVM XtensaGenCallingConv.inc -gen-callingconv)
+tablegen(LLVM XtensaGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM XtensaGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM XtensaGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM XtensaGenMCCodeEmitter.inc -gen-emitter)
@@ -11,6 +13,14 @@ tablegen(LLVM XtensaGenSubtargetInfo.inc -gen-subtarget)
add_public_tablegen_target(XtensaCommonTableGen)
add_llvm_target(XtensaCodeGen
+ XtensaAsmPrinter.cpp
+ XtensaFrameLowering.cpp
+ XtensaInstrInfo.cpp
+ XtensaISelDAGToDAG.cpp
+ XtensaISelLowering.cpp
+ XtensaMCInstLower.cpp
+ XtensaRegisterInfo.cpp
+ XtensaSubtarget.cpp
XtensaTargetMachine.cpp
)
diff --git a/llvm/lib/Target/Xtensa/LLVMBuild.txt
b/llvm/lib/Target/Xtensa/LLVMBuild.txt
index 90b88fc4c1b6..0b07de55125d 100644
--- a/llvm/lib/Target/Xtensa/LLVMBuild.txt
+++ b/llvm/lib/Target/Xtensa/LLVMBuild.txt
@@ -29,5 +29,5 @@ has_disassembler = 1
type = Library
name = XtensaCodeGen
parent = Xtensa
-required_libraries = AsmPrinter CodeGen Core MC XtensaDesc XtensaInfo Support
Target
+required_libraries = AsmPrinter CodeGen Core MC SelectionDAG XtensaDesc
XtensaInfo Support Target
add_to_library_groups = Xtensa
diff --git a/llvm/lib/Target/Xtensa/Xtensa.h b/llvm/lib/Target/Xtensa/Xtensa.h
new file mode 100644
index ..1eedbace7210
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/Xtensa.h
@@ -0,0 +1,29 @@
+//===- Xtensa.h - Top-level interface for Xtensa representation -*- C++
-*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file contains the entry points for global functions defined in
+// the LLVM Xtensa back-end.
+//
+//===--===//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_XTENSA_H
+#define LLVM_LIB_TARGET_XTENSA_XTENSA_H
+
+#include "MCTargetDesc/XtensaMCTargetDesc.h"
+#include "llvm/PassRegistry.h"
+
+namespace llvm {
+class XtensaTargetMachine;
+class FunctionPass;
+
+FunctionPass *createXtensaISelDag(XtensaTargetMachine &TM,
+ CodeGenOpt::Level OptLevel);
+} // namespace llvm
+#endif /* LLVM_LIB_TARGET_XTENSA_XTENSA_H */
diff --git a/llvm/lib/Target/Xtensa/Xtensa.td
b/llvm/lib/Target/Xtensa/Xtensa.td
index 65d2945d1f90..e95287aee464 100644
--- a/llvm/lib/Target/Xtensa/Xtensa.td
+++ b/llvm/lib/Target/Xtensa/Xtensa.td
@@ -35,6 +35,12 @@ def : Proc<"generic", []>;
include "XtensaRegisterInfo.td"
+//===--===//
+// Calling Convention Description
+//===--===//
+
+include "XtensaCallingConv.td"
+
//===
[llvm-branch-commits] [clang] f467b6a - [Xtensa] Recognize Xtensa in triple parsing code.
Author: Andrei Safronov
Date: 2020-07-21T13:25:47+03:00
New Revision: f467b6ae04919a9ef8cd0d4a3c4639ba2bf85cc3
URL:
https://github.com/llvm/llvm-project/commit/f467b6ae04919a9ef8cd0d4a3c4639ba2bf85cc3
DIFF:
https://github.com/llvm/llvm-project/commit/f467b6ae04919a9ef8cd0d4a3c4639ba2bf85cc3.diff
LOG: [Xtensa] Recognize Xtensa in triple parsing code.
Added:
Modified:
clang/lib/CodeGen/CGOpenMPRuntime.cpp
llvm/include/llvm/ADT/Triple.h
llvm/lib/Support/Triple.cpp
llvm/unittests/ADT/TripleTest.cpp
Removed:
diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.cpp
b/clang/lib/CodeGen/CGOpenMPRuntime.cpp
index 97b17799a03e..bd4ca476b7b5 100644
--- a/clang/lib/CodeGen/CGOpenMPRuntime.cpp
+++ b/clang/lib/CodeGen/CGOpenMPRuntime.cpp
@@ -8,6 +8,7 @@ bool checkContext(
case llvm::Triple::renderscript32:
case llvm::Triple::renderscript64:
case llvm::Triple::ve:
+case llvm::Triple::xtensa:
return false;
}
}
diff --git a/llvm/include/llvm/ADT/Triple.h b/llvm/include/llvm/ADT/Triple.h
index 76a754d671fb..eed0ee0de34c 100644
--- a/llvm/include/llvm/ADT/Triple.h
+++ b/llvm/include/llvm/ADT/Triple.h
@@ -78,6 +78,7 @@ class Triple {
x86,// X86: i[3-9]86
x86_64, // X86-64: amd64, x86_64
xcore, // XCore: xcore
+xtensa, // Tensilica Xtensa
nvptx, // NVPTX: 32-bit
nvptx64,// NVPTX: 64-bit
le32, // le32: generic little-endian 32-bit CPU (PNaCl)
diff --git a/llvm/lib/Support/Triple.cpp b/llvm/lib/Support/Triple.cpp
index 2c480c1094a5..6349b9fbeff9 100644
--- a/llvm/lib/Support/Triple.cpp
+++ b/llvm/lib/Support/Triple.cpp
@@ -71,6 +71,7 @@ StringRef Triple::getArchTypeName(ArchType Kind) {
case x86:return "i386";
case x86_64: return "x86_64";
case xcore: return "xcore";
+ case xtensa: return "xtensa";
}
llvm_unreachable("Invalid ArchType!");
@@ -147,6 +148,8 @@ StringRef Triple::getArchTypePrefix(ArchType Kind) {
case riscv64: return "riscv";
case ve: return "ve";
+
+ case xtensa: return "xtensa";
}
}
@@ -317,6 +320,7 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef
Name) {
.Case("renderscript32", renderscript32)
.Case("renderscript64", renderscript64)
.Case("ve", ve)
+.Case("xtensa", xtensa)
.Default(UnknownArch);
}
@@ -446,6 +450,7 @@ static Triple::ArchType parseArch(StringRef ArchName) {
.Case("ve", Triple::ve)
.Case("wasm32", Triple::wasm32)
.Case("wasm64", Triple::wasm64)
+.Case("xtensa", Triple::xtensa)
.Default(Triple::UnknownArch);
// Some architectures require special parsing logic just to compute the
@@ -706,6 +711,7 @@ static Triple::ObjectFormatType getDefaultFormat(const
Triple &T) {
case Triple::thumbeb:
case Triple::ve:
case Triple::xcore:
+ case Triple::xtensa:
return Triple::ELF;
case Triple::ppc64:
@@ -1267,6 +1273,7 @@ static unsigned
getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
case llvm::Triple::wasm32:
case llvm::Triple::x86:
case llvm::Triple::xcore:
+ case llvm::Triple::xtensa:
return 32;
case llvm::Triple::aarch64:
@@ -1350,6 +1357,7 @@ Triple Triple::get32BitArchVariant() const {
case Triple::wasm32:
case Triple::x86:
case Triple::xcore:
+ case Triple::xtensa:
// Already 32-bit.
break;
@@ -1388,6 +1396,7 @@ Triple Triple::get64BitArchVariant() const {
case Triple::tce:
case Triple::tcele:
case Triple::xcore:
+ case Triple::xtensa:
T.setArch(UnknownArch);
break;
@@ -1471,6 +1480,7 @@ Triple Triple::getBigEndianArchVariant() const {
case Triple::x86_64:
case Triple::xcore:
case Triple::ve:
+ case Triple::xtensa:
// ARM is intentionally unsupported here, changing the architecture would
// drop any arch suffixes.
@@ -1563,6 +1573,7 @@ bool Triple::isLittleEndian() const {
case Triple::x86:
case Triple::x86_64:
case Triple::xcore:
+ case Triple::xtensa:
return true;
default:
return false;
diff --git a/llvm/unittests/ADT/TripleTest.cpp
b/llvm/unittests/ADT/TripleTest.cpp
index ef7f82d268e2..3fd30e4c009d 100644
--- a/llvm/unittests/ADT/TripleTest.cpp
+++ b/llvm/unittests/ADT/TripleTest.cpp
@@ -579,6 +579,18 @@ TEST(TripleTest, ParsedIDs) {
EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
EXPECT_TRUE(T.isArch32Bit());
+ T = Triple("xtensa");
+ EXPECT_EQ(Triple::xtensa, T.getArch());
+ EXPECT_EQ(Triple::UnknownVendor, T.getVendor());
+ EXPECT_EQ(Triple::UnknownOS, T.getOS());
+ EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
+
+ T = Triple("xtensa-unknown-unknown");
+ EXPECT_EQ(Triple::xtensa, T.getArch());
+ EXPECT_EQ(Triple::UnknownVendor, T.getVendor());
+ EXPECT_EQ(Triple::UnknownOS, T.getOS());
+ EXPECT_EQ(Triple::UnknownEnvi
[llvm-branch-commits] [llvm] f07fbd5 - [Xtensa] Add basic support of Xtensa disassembler.
Author: Andrei Safronov
Date: 2020-07-21T13:25:50+03:00
New Revision: f07fbd56c00c020e5ca1db11eeb5d561287446db
URL:
https://github.com/llvm/llvm-project/commit/f07fbd56c00c020e5ca1db11eeb5d561287446db
DIFF:
https://github.com/llvm/llvm-project/commit/f07fbd56c00c020e5ca1db11eeb5d561287446db.diff
LOG: [Xtensa] Add basic support of Xtensa disassembler.
Added:
llvm/lib/Target/Xtensa/Disassembler/CMakeLists.txt
llvm/lib/Target/Xtensa/Disassembler/LLVMBuild.txt
llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
Modified:
llvm/lib/Target/Xtensa/CMakeLists.txt
llvm/lib/Target/Xtensa/LLVMBuild.txt
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
llvm/lib/Target/Xtensa/XtensaOperands.td
Removed:
diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt
b/llvm/lib/Target/Xtensa/CMakeLists.txt
index d2bdea4cb0f9..28deec14ddb1 100644
--- a/llvm/lib/Target/Xtensa/CMakeLists.txt
+++ b/llvm/lib/Target/Xtensa/CMakeLists.txt
@@ -2,6 +2,7 @@ set(LLVM_TARGET_DEFINITIONS Xtensa.td)
tablegen(LLVM XtensaGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM XtensaGenAsmWriter.inc -gen-asm-writer)
+tablegen(LLVM XtensaGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM XtensaGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM XtensaGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM XtensaGenRegisterInfo.inc -gen-register-info)
@@ -14,6 +15,7 @@ add_llvm_target(XtensaCodeGen
)
add_subdirectory(AsmParser)
+add_subdirectory(Disassembler)
add_subdirectory(MCTargetDesc)
add_subdirectory(TargetInfo)
diff --git a/llvm/lib/Target/Xtensa/Disassembler/CMakeLists.txt
b/llvm/lib/Target/Xtensa/Disassembler/CMakeLists.txt
new file mode 100644
index ..541a9ede26a0
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/Disassembler/CMakeLists.txt
@@ -0,0 +1,3 @@
+add_llvm_component_library(LLVMXtensaDisassembler
+ XtensaDisassembler.cpp
+ )
diff --git a/llvm/lib/Target/Xtensa/Disassembler/LLVMBuild.txt
b/llvm/lib/Target/Xtensa/Disassembler/LLVMBuild.txt
new file mode 100644
index ..417c7338cb9f
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/Disassembler/LLVMBuild.txt
@@ -0,0 +1,24 @@
+;===-- ./lib/Target/Xtensa/Disassembler/LLVMBuild.txt -*- Conf -*--===;
+;
+; The LLVM Compiler Infrastructure
+;
+; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+; See https://llvm.org/LICENSE.txt for license information.
+; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+;
+;======;
+;
+; This is an LLVMBuild description file for the components in this
subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+; http://llvm.org/docs/LLVMBuild.html
+;
+;======;
+
+[component_0]
+type = Library
+name = XtensaDisassembler
+parent = Xtensa
+required_libraries = MCDisassembler Support XtensaInfo
+add_to_library_groups = Xtensa
diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
new file mode 100644
index ..2da7b51a8ab9
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
@@ -0,0 +1,207 @@
+//===-- XtensaDisassembler.cpp - Disassembler for Xtensa
--===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file implements the XtensaDisassembler class.
+//
+//===--===//
+
+#include "MCTargetDesc/XtensaMCTargetDesc.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCDisassembler/MCDisassembler.h"
+#include "llvm/MC/MCFixedLenDisassembler.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/Endian.h"
+#include "llvm/Support/TargetRegistry.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "Xtensa-disassembler"
+
+using DecodeStatus = MCDisassembler::DecodeStatus;
+
+namespace {
+
+class XtensaDisassembler : public MCDisassembler {
+ bool IsLittleEndian;
+
+public:
+ XtensaDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool isLE)
+ : MCDisassembler(STI, Ctx), IsLittleEndian(isLE) {}
+
+ bool hasDensity() const {
+return STI.getFeatureBits()[Xtensa::FeatureDensity];
+ }
+
+ DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
+ ArrayRef Bytes, uint64_t Address,
+ raw_ostream &CStream) const ove
[llvm-branch-commits] [llvm] 31422c0 - [Xtensa] Add Xtensa MCTargetDescr initial
Author: Andrei Safronov
Date: 2020-07-21T13:25:50+03:00
New Revision: 31422c08942d68891dcc028a478e4beb19af6946
URL:
https://github.com/llvm/llvm-project/commit/31422c08942d68891dcc028a478e4beb19af6946
DIFF:
https://github.com/llvm/llvm-project/commit/31422c08942d68891dcc028a478e4beb19af6946.diff
LOG: [Xtensa] Add Xtensa MCTargetDescr initial
functionality.
Add FDE CFI encoding for Xtensa.
Added:
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaELFObjectWriter.cpp
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCAsmInfo.cpp
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCAsmInfo.h
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
Modified:
llvm/lib/MC/MCObjectFileInfo.cpp
llvm/lib/Target/Xtensa/CMakeLists.txt
llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.h
llvm/lib/Target/Xtensa/XtensaOperands.td
Removed:
diff --git a/llvm/lib/MC/MCObjectFileInfo.cpp
b/llvm/lib/MC/MCObjectFileInfo.cpp
index 8cbe09f040be..a6c8164e556c 100644
--- a/llvm/lib/MC/MCObjectFileInfo.cpp
+++ b/llvm/lib/MC/MCObjectFileInfo.cpp
@@ -326,6 +326,9 @@ void MCObjectFileInfo::initELFMCObjectFileInfo(const Triple
&T, bool Large) {
FDECFIEncoding =
PositionIndependent ? dwarf::DW_EH_PE_pcrel : dwarf::DW_EH_PE_absptr;
break;
+ case Triple::xtensa:
+FDECFIEncoding = dwarf::DW_EH_PE_sdata4;
+break;
default:
FDECFIEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4;
break;
diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt
b/llvm/lib/Target/Xtensa/CMakeLists.txt
index a68b54551d15..592fe83a772d 100644
--- a/llvm/lib/Target/Xtensa/CMakeLists.txt
+++ b/llvm/lib/Target/Xtensa/CMakeLists.txt
@@ -1,6 +1,7 @@
set(LLVM_TARGET_DEFINITIONS Xtensa.td)
tablegen(LLVM XtensaGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM XtensaGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM XtensaGenRegisterInfo.inc -gen-register-info)
add_public_tablegen_target(XtensaCommonTableGen)
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
b/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
index dad428b96129..ee905f70136a 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt
@@ -1,3 +1,7 @@
add_llvm_component_library(LLVMXtensaDesc
+ XtensaAsmBackend.cpp
+ XtensaELFObjectWriter.cpp
+ XtensaMCAsmInfo.cpp
+ XtensaMCCodeEmitter.cpp
XtensaMCTargetDesc.cpp
)
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
new file mode 100644
index ..2fa7469303a0
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaAsmBackend.cpp
@@ -0,0 +1,118 @@
+//===-- XtensaMCAsmBackend.cpp - Xtensa assembler backend ---===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//======//
+
+#include "MCTargetDesc/XtensaMCTargetDesc.h"
+#include "llvm/MC/MCAsmBackend.h"
+#include "llvm/MC/MCAssembler.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCELFObjectWriter.h"
+#include "llvm/MC/MCFixupKindInfo.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCObjectWriter.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+namespace llvm {
+class MCObjectTargetWriter;
+class XtensaMCAsmBackend : public MCAsmBackend {
+ uint8_t OSABI;
+ bool IsLittleEndian;
+
+public:
+ XtensaMCAsmBackend(uint8_t osABI, bool isLE)
+ : MCAsmBackend(support::little), OSABI(osABI), IsLittleEndian(isLE) {}
+
+ unsigned getNumFixupKinds() const override { return 1; }
+ const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
+ void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
+ const MCValue &Target, MutableArrayRef Data,
+ uint64_t Value, bool IsResolved,
+ const MCSubtargetInfo *STI) const override;
+ bool mayNeedRelaxation(const MCInst &Inst,
+ const MCSubtargetInfo &STI) const override;
+ bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
+const MCRelaxableFragment *Fragment,
+const MCAsmLayout &Layout) const override;
+ void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
+MCInst &Res) const override;
+ bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+
+ std::unique_p
[llvm-branch-commits] [llvm] c6dce21 - [Xtensa] Add descriptions of the Xtensa
Author: Andrei Safronov
Date: 2020-07-21T13:25:50+03:00
New Revision: c6dce21897ec70408f4dc6f6e40a49550835308f
URL:
https://github.com/llvm/llvm-project/commit/c6dce21897ec70408f4dc6f6e40a49550835308f
DIFF:
https://github.com/llvm/llvm-project/commit/c6dce21897ec70408f4dc6f6e40a49550835308f.diff
LOG: [Xtensa] Add descriptions of the Xtensa
shift/load/store instructions.
Added:
Modified:
llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
llvm/lib/Target/Xtensa/XtensaInstrInfo.td
llvm/lib/Target/Xtensa/XtensaOperands.td
llvm/test/MC/Xtensa/xtensa-invalid.s
llvm/test/MC/Xtensa/xtensa-valid.s
Removed:
diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
index 555ff46c8a83..2bc7178b865c 100644
--- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
+++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
@@ -53,7 +53,10 @@ class XtensaAsmParser : public MCTargetAsmParser {
OperandMatchResultTy parseRegister(OperandVector &Operands,
bool AllowParens = false, bool SR =
false);
OperandMatchResultTy parseOperandWithModifier(OperandVector &Operands);
- bool parseOperand(OperandVector &Operands);
+ bool parseOperand(OperandVector &Operands, StringRef Mnemonic,
+bool SR = false);
+ bool ParseInstructionWithSR(ParseInstructionInfo &Info, StringRef Name,
+ SMLoc NameLoc, OperandVector &Operands);
public:
enum XtensaMatchResultTy {
@@ -138,6 +141,39 @@ struct XtensaOperand : public MCParsedAsmOperand {
((dyn_cast(getImm())->getValue() & 0xFF) == 0);
}
+ bool isImm12() const { return isImm(-2048, 2047); }
+
+ bool isImm12m() const { return isImm(-2048, 2047); }
+
+ bool isOffset4m32() const {
+return isImm(0, 60) &&
+ ((dyn_cast(getImm())->getValue() & 0x3) == 0);
+ }
+
+ bool isOffset8m8() const { return isImm(0, 255); }
+
+ bool isOffset8m16() const {
+return isImm(0, 510) &&
+ ((dyn_cast(getImm())->getValue() & 0x1) == 0);
+ }
+
+ bool isOffset8m32() const {
+return isImm(0, 1020) &&
+ ((dyn_cast(getImm())->getValue() & 0x3) == 0);
+ }
+
+ bool isUimm4() const { return isImm(0, 15); }
+
+ bool isUimm5() const { return isImm(0, 31); }
+
+ bool isImm8n_7() const { return isImm(-8, 7); }
+
+ bool isShimm1_31() const { return isImm(1, 31); }
+
+ bool isImm16_31() const { return isImm(16, 31); }
+
+ bool isImm1_16() const { return isImm(1, 16); }
+
/// getStartLoc - Gets location of the first token of this operand
SMLoc getStartLoc() const override { return StartLoc; }
/// getEndLoc - Gets location of the last token of this operand
@@ -286,6 +322,39 @@ bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc,
unsigned &Opcode,
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected immediate in range [-32768, 32512], first 8 bits "
"should be zero");
+ case Match_InvalidImm12:
+return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [-2048, 2047]");
+ case Match_InvalidImm12m:
+return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [-2048, 2047]");
+ case Match_InvalidImm1_16:
+return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [1, 16]");
+ case Match_InvalidShimm1_31:
+return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [1, 31]");
+ case Match_InvalidUimm4:
+return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [0, 15]");
+ case Match_InvalidUimm5:
+return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [0, 31]");
+ case Match_InvalidOffset8m8:
+return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [0, 255]");
+ case Match_InvalidOffset8m16:
+return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [0, 510], first bit "
+ "should be zero");
+ case Match_InvalidOffset8m32:
+return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [0, 1020], first 2 bits "
+ "should be zero");
+ case Match_InvalidOffset4m32:
+return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected immediate in range [0, 60], first 2 bits "
+ "should be zero");
}
llvm_unrea
