[llvm-branch-commits] [lld] 70b2872 - [LLD] [MinGW] Implement the --no-seh flag
Author: Martin Storsjö
Date: 2020-07-29T16:56:29+02:00
New Revision: 70b2872f4810569173c7042c51333d83deb16d88
URL:
https://github.com/llvm/llvm-project/commit/70b2872f4810569173c7042c51333d83deb16d88
DIFF:
https://github.com/llvm/llvm-project/commit/70b2872f4810569173c7042c51333d83deb16d88.diff
LOG: [LLD] [MinGW] Implement the --no-seh flag
Previously this flag was just ignored. If set, set the
IMAGE_DLL_CHARACTERISTICS_NO_SEH bit, regardless of the normal safeSEH
machinery.
In mingw configurations, the safeSEH bit might not be set in e.g. object
files built from handwritten assembly, making it impossible to use the
normal safeseh flag. As mingw setups don't generally use SEH on 32 bit
x86 at all, it should be fine to set that flag bit though - hook up
the existing GNU ld flag for controlling that.
Differential Revision: https://reviews.llvm.org/D84701
(cherry picked from commit 745eb02496b515cc8292dd7f9d7f0db43e162013)
Added:
lld/test/COFF/noseh.s
Modified:
lld/COFF/Config.h
lld/COFF/Driver.cpp
lld/COFF/Options.td
lld/COFF/Writer.cpp
lld/MinGW/Driver.cpp
lld/MinGW/Options.td
lld/test/MinGW/driver.test
Removed:
diff --git a/lld/COFF/Config.h b/lld/COFF/Config.h
index 72d826b8bd17..7c439176f3a4 100644
--- a/lld/COFF/Config.h
+++ b/lld/COFF/Config.h
@@ -140,6 +140,7 @@ struct Configuration {
bool safeSEH = false;
Symbol *sehTable = nullptr;
Symbol *sehCount = nullptr;
+ bool noSEH = false;
// Used for /opt:lldlto=N
unsigned ltoo = 2;
diff --git a/lld/COFF/Driver.cpp b/lld/COFF/Driver.cpp
index 7372505bb616..9ceccef86779 100644
--- a/lld/COFF/Driver.cpp
+++ b/lld/COFF/Driver.cpp
@@ -1700,9 +1700,10 @@ void LinkerDriver::link(ArrayRef argsArr) {
config->wordsize = config->is64() ? 8 : 4;
// Handle /safeseh, x86 only, on by default, except for mingw.
- if (config->machine == I386 &&
- args.hasFlag(OPT_safeseh, OPT_safeseh_no, !config->mingw))
-config->safeSEH = true;
+ if (config->machine == I386) {
+config->safeSEH = args.hasFlag(OPT_safeseh, OPT_safeseh_no,
!config->mingw);
+config->noSEH = args.hasArg(OPT_noseh);
+ }
// Handle /functionpadmin
for (auto *arg : args.filtered(OPT_functionpadmin, OPT_functionpadmin_opt))
diff --git a/lld/COFF/Options.td b/lld/COFF/Options.td
index 212879e1d60b..087d53b5d2dd 100644
--- a/lld/COFF/Options.td
+++ b/lld/COFF/Options.td
@@ -204,6 +204,7 @@ def include_optional : Joined<["/", "-", "/?", "-?"],
"includeoptional:">,
HelpText<"Add symbol as undefined, but allow it to remain undefined">;
def kill_at : F<"kill-at">;
def lldmingw : F<"lldmingw">;
+def noseh : F<"noseh">;
def output_def : Joined<["/", "-", "/?", "-?"], "output-def:">;
def pdb_source_path : P<"pdbsourcepath",
"Base path used to make relative source file path absolute in PDB">;
diff --git a/lld/COFF/Writer.cpp b/lld/COFF/Writer.cpp
index 3bcc1777f7ac..082de5b8c1d6 100644
--- a/lld/COFF/Writer.cpp
+++ b/lld/COFF/Writer.cpp
@@ -1393,7 +1393,7 @@ template void Writer::writeHeader()
{
pe->DLLCharacteristics |= IMAGE_DLL_CHARACTERISTICS_GUARD_CF;
if (config->integrityCheck)
pe->DLLCharacteristics |= IMAGE_DLL_CHARACTERISTICS_FORCE_INTEGRITY;
- if (setNoSEHCharacteristic)
+ if (setNoSEHCharacteristic || config->noSEH)
pe->DLLCharacteristics |= IMAGE_DLL_CHARACTERISTICS_NO_SEH;
if (config->terminalServerAware)
pe->DLLCharacteristics |= IMAGE_DLL_CHARACTERISTICS_TERMINAL_SERVER_AWARE;
diff --git a/lld/MinGW/Driver.cpp b/lld/MinGW/Driver.cpp
index f33b5e19502c..d60765c70c09 100644
--- a/lld/MinGW/Driver.cpp
+++ b/lld/MinGW/Driver.cpp
@@ -288,6 +288,8 @@ bool mingw::link(ArrayRef argsArr, bool
canExitEarly,
add("-kill-at");
if (args.hasArg(OPT_appcontainer))
add("-appcontainer");
+ if (args.hasArg(OPT_no_seh))
+add("-noseh");
if (args.getLastArgValue(OPT_m) != "thumb2pe" &&
args.getLastArgValue(OPT_m) != "arm64pe" &&
!args.hasArg(OPT_dynamicbase))
diff --git a/lld/MinGW/Options.td b/lld/MinGW/Options.td
index 3281951dc89d..fe4416660050 100644
--- a/lld/MinGW/Options.td
+++ b/lld/MinGW/Options.td
@@ -56,6 +56,7 @@ defm minor_subsystem_version:
EqLong<"minor-subsystem-version",
"Set the OS and subsystem minor version">;
def no_insert_timestamp: F<"no-insert-timestamp">,
HelpText<"Don't include PE header timestamp">;
+def no_seh: F<"no-seh">, HelpText<"Set the 'no SEH' flag in the executable">;
def no_whole_archive: F<"no-whole-archive">,
HelpText<"No longer include all object files for following archives">;
def large_address_aware: Flag<["--"], "large-address-aware">,
@@ -111,7 +112,6 @@ def: Flag<["--"], "full-shutdown">;
def: F<"high-entropy-va">;
def: S<"major-image-version">;
def: S<"minor-image-version">;
-def: F<"no-seh">;
def: F<"nxcompat">;
def: F<"pic-executable">;
def: S<"plugin">;
diff --git a/lld/test/COFF/nos
[llvm-branch-commits] [llvm] 7f2a078 - [InstCombine] avoid crashing on vector constant expression (PR46872)
Author: Sanjay Patel
Date: 2020-07-29T17:16:52+02:00
New Revision: 7f2a078b11316e11b89ee09215b0e7c0b78f359b
URL:
https://github.com/llvm/llvm-project/commit/7f2a078b11316e11b89ee09215b0e7c0b78f359b
DIFF:
https://github.com/llvm/llvm-project/commit/7f2a078b11316e11b89ee09215b0e7c0b78f359b.diff
LOG: [InstCombine] avoid crashing on vector constant expression (PR46872)
(cherry picked from commit f75cf240d6ed528e1ce7770bbe09b417338b40ef)
Added:
Modified:
llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
llvm/test/Transforms/InstCombine/vec_shuffle.ll
Removed:
diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
index b3254c10a0b2..17a5ec3f87fa 100644
--- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
@@ -1543,7 +1543,7 @@ Instruction *InstCombiner::foldVectorBinop(BinaryOperator
&Inst) {
Constant *C;
if (match(&Inst,
m_c_BinOp(m_OneUse(m_Shuffle(m_Value(V1), m_Undef(),
m_Mask(Mask))),
- m_Constant(C))) &&
+ m_Constant(C))) && !isa(C) &&
cast(V1->getType())->getNumElements() <= NumElts) {
assert(Inst.getType()->getScalarType() == V1->getType()->getScalarType() &&
"Shuffle should not change scalar type");
diff --git a/llvm/test/Transforms/InstCombine/vec_shuffle.ll
b/llvm/test/Transforms/InstCombine/vec_shuffle.ll
index e7e55b07b7cd..3f3431c5d904 100644
--- a/llvm/test/Transforms/InstCombine/vec_shuffle.ll
+++ b/llvm/test/Transforms/InstCombine/vec_shuffle.ll
@@ -1745,3 +1745,18 @@ define <4 x i32> @splat_assoc_add_mul(<4 x i32> %x, <4 x
i32> %y) {
%r = mul <4 x i32> %splatx, %a
ret <4 x i32> %r
}
+
+
+; Do not crash on constant expressions.
+
+define <4 x i32> @PR46872(<4 x i32> %x) {
+; CHECK-LABEL: @PR46872(
+; CHECK-NEXT:[[S:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32>
undef, <4 x i32>
+; CHECK-NEXT:[[A:%.*]] = and <4 x i32> [[S]], bitcast (<2 x i64> (<4 x i32>)* @PR46872 to i64), i64 ptrtoint (<4 x i32> (<4
x i32>)* @PR46872 to i64)> to <4 x i32>)
+; CHECK-NEXT:ret <4 x i32> [[A]]
+;
+ %s = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32>
+ %a = and <4 x i32> %s, bitcast (<2 x i64> (<4 x
i32>)* @PR46872 to i64), i64 ptrtoint (<4 x i32> (<4 x i32>)* @PR46872 to i64)>
to <4 x i32>)
+ ret <4 x i32> %a
+}
+
___
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[llvm-branch-commits] [clang-tools-extra] baf2999 - [clang-tidy] Fix RedundantStringCStrCheck with r values
Author: Nathan James
Date: 2020-07-29T17:22:12+02:00
New Revision: baf2999b49c6aff2fcd5448c7d299eb2f4bf8b86
URL:
https://github.com/llvm/llvm-project/commit/baf2999b49c6aff2fcd5448c7d299eb2f4bf8b86
DIFF:
https://github.com/llvm/llvm-project/commit/baf2999b49c6aff2fcd5448c7d299eb2f4bf8b86.diff
LOG: [clang-tidy] Fix RedundantStringCStrCheck with r values
The previous fix for this, https://reviews.llvm.org/D76761, Passed test cases
but failed in the real world as std::string has a non trivial destructor so
creates a CXXBindTemporaryExpr.
This handles that shortfall and updates the test case std::basic_string
implementation to use a non trivial destructor to reflect real world behaviour.
Reviewed By: gribozavr2
Differential Revision: https://reviews.llvm.org/D84831
(cherry picked from commit b99630e432614d06b380afb15c45065eaa0a)
Added:
Modified:
clang-tools-extra/clang-tidy/readability/RedundantStringCStrCheck.cpp
clang-tools-extra/test/clang-tidy/checkers/readability-redundant-string-cstr.cpp
Removed:
diff --git
a/clang-tools-extra/clang-tidy/readability/RedundantStringCStrCheck.cpp
b/clang-tools-extra/clang-tidy/readability/RedundantStringCStrCheck.cpp
index bea02a6ba111..1f371eed2db8 100644
--- a/clang-tools-extra/clang-tidy/readability/RedundantStringCStrCheck.cpp
+++ b/clang-tools-extra/clang-tidy/readability/RedundantStringCStrCheck.cpp
@@ -92,16 +92,18 @@ void RedundantStringCStrCheck::registerMatchers(
callee(memberExpr().bind("member")),
callee(cxxMethodDecl(hasAnyName("c_str", "data"
.bind("call");
-
+ const auto HasRValueTempParent =
+ hasParent(materializeTemporaryExpr(unless(isBoundToLValue(;
// Detect redundant 'c_str()' calls through a string constructor.
// If CxxConstructExpr is the part of some CallExpr we need to
// check that matched ParamDecl of the ancestor CallExpr is not rvalue.
Finder->addMatcher(
- traverse(ast_type_traits::TK_AsIs,
- cxxConstructExpr(StringConstructorExpr,
-hasArgument(0, StringCStrCallExpr),
-unless(hasParent(materializeTemporaryExpr(
-unless(isBoundToLValue())),
+ traverse(
+ ast_type_traits::TK_AsIs,
+ cxxConstructExpr(
+ StringConstructorExpr, hasArgument(0, StringCStrCallExpr),
+ unless(anyOf(HasRValueTempParent, hasParent(cxxBindTemporaryExpr(
+HasRValueTempParent)),
this);
// Detect: 's == str.c_str()' -> 's == str'
diff --git
a/clang-tools-extra/test/clang-tidy/checkers/readability-redundant-string-cstr.cpp
b/clang-tools-extra/test/clang-tidy/checkers/readability-redundant-string-cstr.cpp
index 2561b81805bd..e1df810b 100644
---
a/clang-tools-extra/test/clang-tidy/checkers/readability-redundant-string-cstr.cpp
+++
b/clang-tools-extra/test/clang-tidy/checkers/readability-redundant-string-cstr.cpp
@@ -15,6 +15,8 @@ struct basic_string {
basic_string();
basic_string(const C *p, const A &a = A());
+ ~basic_string();
+
const C *c_str() const;
const C *data() const;
___
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[llvm-branch-commits] [openmp] fdb1299 - [OpenMP] add missed REQUIRES:ompt for 2 OMPT tests
Author: AndreyChurbanov Date: 2020-07-29T17:27:30+02:00 New Revision: fdb1299e70c24fd35dae7804323769bd470c06b8 URL: https://github.com/llvm/llvm-project/commit/fdb1299e70c24fd35dae7804323769bd470c06b8 DIFF: https://github.com/llvm/llvm-project/commit/fdb1299e70c24fd35dae7804323769bd470c06b8.diff LOG: [OpenMP] add missed REQUIRES:ompt for 2 OMPT tests (cherry picked from commit 617787ea77a22f752ba1fcd4ac7cb9a62a710756) Added: Modified: openmp/runtime/test/ompt/tasks/task_early_fulfill.c openmp/runtime/test/ompt/tasks/task_late_fulfill.c Removed: diff --git a/openmp/runtime/test/ompt/tasks/task_early_fulfill.c b/openmp/runtime/test/ompt/tasks/task_early_fulfill.c index f1d07a1503c8..e1324e6af681 100644 --- a/openmp/runtime/test/ompt/tasks/task_early_fulfill.c +++ b/openmp/runtime/test/ompt/tasks/task_early_fulfill.c @@ -1,5 +1,6 @@ // RUN: %libomp-compile -fopenmp-version=50 && env OMP_NUM_THREADS='3' \ // RUN:%libomp-run | %sort-threads | FileCheck %s +// REQUIRES: ompt // Checked gcc 10.1 still does not support detach clause on task construct. // UNSUPPORTED: gcc-4, gcc-5, gcc-6, gcc-7, gcc-8, gcc-9, gcc-10 diff --git a/openmp/runtime/test/ompt/tasks/task_late_fulfill.c b/openmp/runtime/test/ompt/tasks/task_late_fulfill.c index 4824f3358cfd..13a2a54a60df 100644 --- a/openmp/runtime/test/ompt/tasks/task_late_fulfill.c +++ b/openmp/runtime/test/ompt/tasks/task_late_fulfill.c @@ -1,5 +1,6 @@ // RUN: %libomp-compile -fopenmp-version=50 && env OMP_NUM_THREADS='3' \ // RUN:%libomp-run | %sort-threads | FileCheck %s +// REQUIRES: ompt // Checked gcc 10.1 still does not support detach clause on task construct. // UNSUPPORTED: gcc-4, gcc-5, gcc-6, gcc-7, gcc-8, gcc-9, gcc-10 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] b88690b - [AMDGPU] Don't combine memory intrs to v3i16
Author: Sebastian Neubauer
Date: 2020-07-29T17:31:02+02:00
New Revision: b88690b737518f8776c8f95063b89e8bbbd97428
URL:
https://github.com/llvm/llvm-project/commit/b88690b737518f8776c8f95063b89e8bbbd97428
DIFF:
https://github.com/llvm/llvm-project/commit/b88690b737518f8776c8f95063b89e8bbbd97428.diff
LOG: [AMDGPU] Don't combine memory intrs to v3i16
v3i16 and v3f16 currently cannot be legalized and lowered so they should
not be emitted by inst combining.
Moved the check down to still allow extracting 1 or 2 elements via the dmask.
Fixes image intrinsics being combined to return v3x16.
Differential Revision: https://reviews.llvm.org/D84223
(cherry picked from commit 2c659082bda6319732118e746fe025d8d5f9bfac)
Added:
Modified:
llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
Removed:
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index 7cfe4c8b5892..c7f2f4ec3ca1 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -1030,12 +1030,6 @@ Value
*InstCombiner::simplifyAMDGCNMemoryIntrinsicDemanded(IntrinsicInst *II,
APInt DemandedElts,
int DMaskIdx) {
- // FIXME: Allow v3i16/v3f16 in buffer intrinsics when the types are fully
supported.
- if (DMaskIdx < 0 &&
- II->getType()->getScalarSizeInBits() != 32 &&
- DemandedElts.getActiveBits() == 3)
-return nullptr;
-
auto *IIVTy = cast(II->getType());
unsigned VWidth = IIVTy->getNumElements();
if (VWidth == 1)
@@ -1124,6 +1118,11 @@ Value
*InstCombiner::simplifyAMDGCNMemoryIntrinsicDemanded(IntrinsicInst *II,
if (!NewNumElts)
return UndefValue::get(II->getType());
+ // FIXME: Allow v3i16/v3f16 in buffer and image intrinsics when the types are
+ // fully supported.
+ if (II->getType()->getScalarSizeInBits() == 16 && NewNumElts == 3)
+return nullptr;
+
if (NewNumElts >= VWidth && DemandedElts.isMask()) {
if (DMaskIdx >= 0)
II->setArgOperand(DMaskIdx, Args[DMaskIdx]);
diff --git
a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
index c2f5e2857be0..3d58f0608081 100644
--- a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
+++ b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
@@ -2965,6 +2965,64 @@ declare <4 x float>
@llvm.amdgcn.image.sample.cd.1d.v4f32.f32.f32(i32, float, fl
; llvm.amdgcn.image.sample.cd.cl
;
+; CHECK-LABEL: @extract_elt3_image_sample_cd_cl_1d_v4f16_f32_f32(
+; CHECK-NEXT: %data = call half
@llvm.amdgcn.image.sample.cd.cl.1d.f16.f32.f32(i32 8, float %dsdh, float %dsdv,
float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0,
i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt3_image_sample_cd_cl_1d_v4f16_f32_f32(float
%dsdh, float %dsdv, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32>
inreg %rsrc) #0 {
+ %data = call <4 x half> @llvm.amdgcn.image.sample.cd.cl.1d.v4f16.f32.f32(i32
15, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x
i32> %rsrc, i1 false, i32 0, i32 0)
+ %elt0 = extractelement <4 x half> %data, i32 3
+ ret half %elt0
+}
+
+; CHECK-LABEL: @extract_elt2_image_sample_cd_cl_1d_v4f16_f32_f32(
+; CHECK-NEXT: %data = call half
@llvm.amdgcn.image.sample.cd.cl.1d.f16.f32.f32(i32 4, float %dsdh, float %dsdv,
float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0,
i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt2_image_sample_cd_cl_1d_v4f16_f32_f32(float
%dsdh, float %dsdv, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32>
inreg %rsrc) #0 {
+ %data = call <4 x half> @llvm.amdgcn.image.sample.cd.cl.1d.v4f16.f32.f32(i32
15, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x
i32> %rsrc, i1 false, i32 0, i32 0)
+ %elt0 = extractelement <4 x half> %data, i32 2
+ ret half %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_image_sample_cd_cl_1d_v4f16_f32_f32(
+; CHECK-NEXT: %data = call half
@llvm.amdgcn.image.sample.cd.cl.1d.f16.f32.f32(i32 2, float %dsdh, float %dsdv,
float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0,
i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt1_image_sample_cd_cl_1d_v4f16_f32_f32(float
%dsdh, float %dsdv, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32>
inreg %rsrc) #0 {
+ %data = call <4 x half> @llvm.amdgcn.image.sample
