[llvm-branch-commits] [llvm] 0b8a540 - [AArch64][ARM] Always expand ordered vector reductions (PR44600)
Author: Nikita Popov
Date: 2020-02-05T13:51:46+01:00
New Revision: 0b8a540dff86662fc9426bb4dd8797c547db5000
URL:
https://github.com/llvm/llvm-project/commit/0b8a540dff86662fc9426bb4dd8797c547db5000
DIFF:
https://github.com/llvm/llvm-project/commit/0b8a540dff86662fc9426bb4dd8797c547db5000.diff
LOG: [AArch64][ARM] Always expand ordered vector reductions (PR44600)
fadd/fmul reductions without reassoc are lowered to
VECREDUCE_STRICT_FADD/FMUL nodes, which don't have legalization
support. Until that is in place, expand these intrinsics on
ARM and AArch64. Other targets always expand the vector reduction
intrinsics.
Additionally expand fmax/fmin reductions without nonan flag on
AArch64, as the backend asserts that the flag is present when
lowering VECREDUCE_FMIN/FMAX.
This fixes https://bugs.llvm.org/show_bug.cgi?id=44600.
Differential Revision: https://reviews.llvm.org/D73135
(cherry picked from commit 70d345e687caba4ac1f95655c6924dfa91e0083f)
Added:
llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll
llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
llvm/test/CodeGen/AArch64/vecreduce-fmul-legalization-strict.ll
llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll
llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll
Modified:
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
llvm/lib/Target/ARM/ARMTargetTransformInfo.h
Removed:
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
index 6f4569a49783..131219ca6944 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
@@ -183,7 +183,21 @@ class AArch64TTIImpl : public
BasicTTIImplBase {
bool &AllowPromotionWithoutCommonHeader);
bool shouldExpandReduction(const IntrinsicInst *II) const {
-return false;
+switch (II->getIntrinsicID()) {
+case Intrinsic::experimental_vector_reduce_v2_fadd:
+case Intrinsic::experimental_vector_reduce_v2_fmul:
+ // We don't have legalization support for ordered FP reductions.
+ return !II->getFastMathFlags().allowReassoc();
+
+case Intrinsic::experimental_vector_reduce_fmax:
+case Intrinsic::experimental_vector_reduce_fmin:
+ // Lowering asserts that there are no NaNs.
+ return !II->getFastMathFlags().noNaNs();
+
+default:
+ // Don't expand anything else, let legalization deal with it.
+ return false;
+}
}
unsigned getGISelRematGlobalCost() const {
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
index 880588adfdfd..4a9a8f688ab5 100644
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
@@ -171,7 +171,16 @@ class ARMTTIImpl : public BasicTTIImplBase {
TTI::ReductionFlags Flags) const;
bool shouldExpandReduction(const IntrinsicInst *II) const {
-return false;
+switch (II->getIntrinsicID()) {
+case Intrinsic::experimental_vector_reduce_v2_fadd:
+case Intrinsic::experimental_vector_reduce_v2_fmul:
+ // We don't have legalization support for ordered FP reductions.
+ return !II->getFastMathFlags().allowReassoc();
+
+default:
+ // Don't expand anything else, let legalization deal with it.
+ return false;
+}
}
int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll
b/llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll
new file mode 100644
index ..5d6f2e40d4d5
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll
@@ -0,0 +1,128 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
--check-prefix=CHECK
+
+; Same as vecreduce-fadd-legalization.ll, but without fmf.
+
+declare half @llvm.experimental.vector.reduce.v2.fadd.f16.v1f16(half, <1 x
half>)
+declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v1f32(float, <1 x
float>)
+declare double @llvm.experimental.vector.reduce.v2.fadd.f64.v1f64(double, <1 x
double>)
+declare fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v1f128(fp128, <1 x
fp128>)
+
+declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float, <3 x
float>)
+declare fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v2f128(fp128, <2 x
fp128>)
+declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v16f32(float, <16 x
float>)
+
+define half @test_v1f16(<1 x half> %a) nounwind {
+; CHECK-LABEL: test_v1f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT:fcvt s0, h0
+; CHECK-NEXT:fmov s1, wzr
+; CHECK-NEXT:fadd s0, s0, s1
+; CHECK-NEXT:fcvt h0,
[llvm-branch-commits] [llvm] 99c6a4e - [ARM] Expand vector reduction intrinsics on soft float
Author: Nikita Popov
Date: 2020-02-05T13:52:41+01:00
New Revision: 99c6a4ea9201f09e8107bb83675f1e7235456b6d
URL:
https://github.com/llvm/llvm-project/commit/99c6a4ea9201f09e8107bb83675f1e7235456b6d
DIFF:
https://github.com/llvm/llvm-project/commit/99c6a4ea9201f09e8107bb83675f1e7235456b6d.diff
LOG: [ARM] Expand vector reduction intrinsics on soft float
Followup to D73135. If the target doesn't have hard float (default
for ARM), then we assert when trying to soften the result of vector
reduction intrinsics. This patch marks these for expansion as well.
(A bit odd to use vectors on a target without hard float ... but
that's where you end up if you expose target-independent vector types.)
Differential Revision: https://reviews.llvm.org/D73854
(cherry picked from commit 1cc4f8d17247cd9be88addd75d060f9321b6f8b0)
Added:
llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll
Modified:
llvm/lib/Target/ARM/ARMTargetTransformInfo.h
Removed:
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
index 4a9a8f688ab5..b860df62b782 100644
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
@@ -175,7 +175,14 @@ class ARMTTIImpl : public BasicTTIImplBase {
case Intrinsic::experimental_vector_reduce_v2_fadd:
case Intrinsic::experimental_vector_reduce_v2_fmul:
// We don't have legalization support for ordered FP reductions.
- return !II->getFastMathFlags().allowReassoc();
+ if (!II->getFastMathFlags().allowReassoc())
+return true;
+ LLVM_FALLTHROUGH;
+
+case Intrinsic::experimental_vector_reduce_fmin:
+case Intrinsic::experimental_vector_reduce_fmax:
+ // Can't legalize reductions with soft floats.
+ return TLI->useSoftFloat() || !TLI->getSubtarget()->hasFPRegs();
default:
// Don't expand anything else, let legalization deal with it.
diff --git a/llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll
b/llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll
new file mode 100644
index ..f3eeb11a17fd
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll
@@ -0,0 +1,63 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=arm-none-eabi -mattr=-neon | FileCheck %s
--check-prefix=CHECK
+
+declare float @llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float, <4 x
float>)
+declare double @llvm.experimental.vector.reduce.v2.fadd.f64.v2f64(double, <2 x
double>)
+declare fp128 @llvm.experimental.vector.reduce.v2.fadd.f128.v2f128(fp128, <2 x
fp128>)
+
+define float @test_v4f32(<4 x float> %a) nounwind {
+; CHECK-LABEL: test_v4f32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT:.save {r4, r5, r6, lr}
+; CHECK-NEXT:push {r4, r5, r6, lr}
+; CHECK-NEXT:mov r5, r1
+; CHECK-NEXT:mov r1, r2
+; CHECK-NEXT:mov r4, r3
+; CHECK-NEXT:bl __aeabi_fadd
+; CHECK-NEXT:mov r6, r0
+; CHECK-NEXT:mov r0, r5
+; CHECK-NEXT:mov r1, r4
+; CHECK-NEXT:bl __aeabi_fadd
+; CHECK-NEXT:mov r1, r0
+; CHECK-NEXT:mov r0, r6
+; CHECK-NEXT:bl __aeabi_fadd
+; CHECK-NEXT:pop {r4, r5, r6, lr}
+; CHECK-NEXT:mov pc, lr
+ %b = call fast float
@llvm.experimental.vector.reduce.v2.fadd.f32.v4f32(float 0.0, <4 x float> %a)
+ ret float %b
+}
+
+define double @test_v2f64(<2 x double> %a) nounwind {
+; CHECK-LABEL: test_v2f64:
+; CHECK: @ %bb.0:
+; CHECK-NEXT:.save {r11, lr}
+; CHECK-NEXT:push {r11, lr}
+; CHECK-NEXT:bl __aeabi_dadd
+; CHECK-NEXT:pop {r11, lr}
+; CHECK-NEXT:mov pc, lr
+ %b = call fast double
@llvm.experimental.vector.reduce.v2.fadd.f64.v2f64(double zeroinitializer, <2 x
double> %a)
+ ret double %b
+}
+
+define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
+; CHECK-LABEL: test_v2f128:
+; CHECK: @ %bb.0:
+; CHECK-NEXT:.save {r11, lr}
+; CHECK-NEXT:push {r11, lr}
+; CHECK-NEXT:.pad #16
+; CHECK-NEXT:sub sp, sp, #16
+; CHECK-NEXT:ldr r12, [sp, #36]
+; CHECK-NEXT:str r12, [sp, #12]
+; CHECK-NEXT:ldr r12, [sp, #32]
+; CHECK-NEXT:str r12, [sp, #8]
+; CHECK-NEXT:ldr r12, [sp, #28]
+; CHECK-NEXT:str r12, [sp, #4]
+; CHECK-NEXT:ldr r12, [sp, #24]
+; CHECK-NEXT:str r12, [sp]
+; CHECK-NEXT:bl __addtf3
+; CHECK-NEXT:add sp, sp, #16
+; CHECK-NEXT:pop {r11, lr}
+; CHECK-NEXT:mov pc, lr
+ %b = call fast fp128
@llvm.experimental.vector.reduce.v2.fadd.f128.v2f128(fp128 zeroinitializer, <2
x fp128> %a)
+ ret fp128 %b
+}
___
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[llvm-branch-commits] [clang] b4efc29 - Update for Clang 10 release notes in order to have reference to D66404.
Author: Andi-Bogdan Postelnicu Date: 2020-02-05T16:03:23+02:00 New Revision: b4efc29f1ccbc03453590bf7aae337853c91c91f URL: https://github.com/llvm/llvm-project/commit/b4efc29f1ccbc03453590bf7aae337853c91c91f DIFF: https://github.com/llvm/llvm-project/commit/b4efc29f1ccbc03453590bf7aae337853c91c91f.diff LOG: Update for Clang 10 release notes in order to have reference to D66404. Summary: Since `D66404` adds some significat modifications to the `CFG` we should include it in the release notes. Reviewers: hans Subscribers: cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D74031 Added: Modified: clang/docs/ReleaseNotes.rst Removed: diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 753dab9e8bc3..c7fe7437558a 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -399,7 +399,24 @@ clang-format libclang -- ... +- Various changes to reduce discrepancies in destructor calls between the + generated ``CFG`` and the actual ``codegen``. + + In particular: + + - Respect C++17 copy elision; previously it would generate destructor calls +for elided temporaries, including in initialization and return statements. + + - Don't generate duplicate destructor calls for statement expressions. + + - Fix initialization lists. + + - Fix comma operator. + + - Change printing of implicit destructors to print the type instead of the +class name directly, matching the code for temporary object destructors. +The class name was blank for lambdas. + Static Analyzer --- ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 4c96b36 - [X86] -fpatchable-function-entry=N, 0: place patch label after ENDBR{32, 64}
Author: Fangrui Song
Date: 2020-02-05T15:19:04+01:00
New Revision: 4c96b369a074e93a0be536dd795d3f245ef6f18b
URL:
https://github.com/llvm/llvm-project/commit/4c96b369a074e93a0be536dd795d3f245ef6f18b
DIFF:
https://github.com/llvm/llvm-project/commit/4c96b369a074e93a0be536dd795d3f245ef6f18b.diff
LOG: [X86] -fpatchable-function-entry=N,0: place patch label after ENDBR{32,64}
Similar to D73680 (AArch64 BTI).
A local linkage function whose address is not taken does not need
ENDBR32/ENDBR64. Placing the patch label after ENDBR32/ENDBR64 has the
advantage that code does not need to differentiate whether the function has an
initial ENDBR.
Also, add 32-bit tests and test that .cfi_startproc is at the function
entry. The line information has a general implementation and is tested
by AArch64/patchable-function-entry-empty.mir
Reviewed By: nickdesaulniers
Differential Revision: https://reviews.llvm.org/D73760
(cherry picked from commit 8ff86fcf4c038c7156ed4f01e7ed35cae49489e2)
Added:
Modified:
llvm/lib/Target/X86/X86MCInstLower.cpp
llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll
llvm/test/CodeGen/X86/patchable-function-entry-ibt.ll
Removed:
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp
b/llvm/lib/Target/X86/X86MCInstLower.cpp
index 2fc9a2af01d7..7f49c6e861d4 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -2002,6 +2002,25 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr
*MI) {
break;
}
+ case X86::ENDBR32:
+ case X86::ENDBR64: {
+// CurrentPatchableFunctionEntrySym can be CurrentFnBegin only for
+// -fpatchable-function-entry=N,0. The entry MBB is guaranteed to be
+// non-empty. If MI is the initial ENDBR, place the
+// __patchable_function_entries label after ENDBR.
+if (CurrentPatchableFunctionEntrySym &&
+CurrentPatchableFunctionEntrySym == CurrentFnBegin &&
+MI == &MF->front().front()) {
+ MCInst Inst;
+ MCInstLowering.Lower(MI, Inst);
+ EmitAndCountInstruction(Inst);
+ CurrentPatchableFunctionEntrySym = createTempSymbol("patch");
+ OutStreamer->EmitLabel(CurrentPatchableFunctionEntrySym);
+ return;
+}
+break;
+ }
+
case X86::TAILJMPr:
case X86::TAILJMPm:
case X86::TAILJMPd:
diff --git a/llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll
b/llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll
index 4b85664673fd..19386e94383d 100644
--- a/llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll
+++ b/llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll
@@ -15,7 +15,8 @@ define void @f0() "patchable-function-entry"="0"
"branch-target-enforcement" {
define void @f1() "patchable-function-entry"="1" "branch-target-enforcement" {
; CHECK-LABEL: f1:
; CHECK-NEXT: .Lfunc_begin1:
-; CHECK: // %bb.0:
+; CHECK-NEXT: .cfi_startproc
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: hint #34
; CHECK-NEXT: .Lpatch0:
; CHECK-NEXT: nop
@@ -33,7 +34,8 @@ define void @f2_1() "patchable-function-entry"="1"
"patchable-function-prefix"="
; CHECK-NEXT: nop
; CHECK-NEXT: f2_1:
; CHECK-NEXT: .Lfunc_begin2:
-; CHECK: // %bb.0:
+; CHECK-NEXT: .cfi_startproc
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: hint #34
; CHECK-NEXT: nop
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/X86/patchable-function-entry-ibt.ll
b/llvm/test/CodeGen/X86/patchable-function-entry-ibt.ll
index 49a36b2205ce..3def5a378458 100644
--- a/llvm/test/CodeGen/X86/patchable-function-entry-ibt.ll
+++ b/llvm/test/CodeGen/X86/patchable-function-entry-ibt.ll
@@ -1,26 +1,37 @@
-; RUN: llc -mtriple=x86_64 %s -o - | FileCheck --check-prefixes=CHECK %s
+; RUN: llc -mtriple=i686 %s -o - | FileCheck --check-prefixes=CHECK,32 %s
+; RUN: llc -mtriple=x86_64 %s -o - | FileCheck --check-prefixes=CHECK,64 %s
;; -fpatchable-function-entry=0 -fcf-protection=branch
-define void @f0() "patchable-function-entry"="0" "branch-target-enforcement" {
+define void @f0() "patchable-function-entry"="0" {
; CHECK-LABEL: f0:
; CHECK-NEXT: .Lfunc_begin0:
-; CHECK: # %bb.0:
-; CHECK-NEXT: endbr64
-; CHECK-NEXT: retq
+; CHECK-NEXT: .cfi_startproc
+; CHECK-NEXT: # %bb.0:
+; 32-NEXT: endbr32
+; 64-NEXT: endbr64
+; CHECK-NEXT: ret
; CHECK-NOT: .section __patchable_function_entries
ret void
}
;; -fpatchable-function-entry=1 -fcf-protection=branch
+;; For M=0, place the label .Lpatch0 after the initial ENDBR.
+;; .cfi_startproc should be placed at the function entry.
define void @f1() "patchable-function-entry"="1" {
; CHECK-LABEL: f1:
; CHECK-NEXT: .Lfunc_begin1:
-; CHECK: endbr64
+; CHECK-NEXT: .cfi_startproc
+; CHECK-NEXT: # %bb.0:
+; 32-NEXT: endbr32
+; 64-NEXT: endbr64
+; CHECK-NEXT: .Lpatch0:
; CHECK-NEXT: nop
-; CHECK-NEXT: retq
+; CHECK-NEXT: ret
; CHECK: .section __patchable_function_entries,"awo",@progbits,f1,uniq
[llvm-branch-commits] [clang] fd271fd - Don't warn about missing declarations for partial template specializations
Author: Aaron Puchert
Date: 2020-02-05T15:22:08+01:00
New Revision: fd271fd64a284e9182c8afd8eb8084d8d43df587
URL:
https://github.com/llvm/llvm-project/commit/fd271fd64a284e9182c8afd8eb8084d8d43df587
DIFF:
https://github.com/llvm/llvm-project/commit/fd271fd64a284e9182c8afd8eb8084d8d43df587.diff
LOG: Don't warn about missing declarations for partial template specializations
Summary: Just like templates, they are excepted from the ODR rule.
Reviewed By: aaron.ballman, rsmith
Differential Revision: https://reviews.llvm.org/D68923
(cherry picked from commit 27684ae66d5545f211c0ac4393d0ba2bf3b5b47c)
Added:
Modified:
clang/lib/Sema/SemaDecl.cpp
clang/test/SemaCXX/warn-missing-variable-declarations.cpp
Removed:
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index 0bf490336537..64146f4a912f 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -12526,6 +12526,7 @@ void Sema::CheckCompleteVariableDeclaration(VarDecl
*var) {
var->getDeclContext()->getRedeclContext()->isFileContext() &&
var->isExternallyVisible() && var->hasLinkage() &&
!var->isInline() && !var->getDescribedVarTemplate() &&
+ !isa(var) &&
!isTemplateInstantiation(var->getTemplateSpecializationKind()) &&
!getDiagnostics().isIgnored(diag::warn_missing_variable_declarations,
var->getLocation())) {
diff --git a/clang/test/SemaCXX/warn-missing-variable-declarations.cpp
b/clang/test/SemaCXX/warn-missing-variable-declarations.cpp
index e2480fd663b0..b50eeed30e7a 100644
--- a/clang/test/SemaCXX/warn-missing-variable-declarations.cpp
+++ b/clang/test/SemaCXX/warn-missing-variable-declarations.cpp
@@ -70,6 +70,8 @@ template int var_template = 0;
template constexpr int const_var_template = 0;
template static int static_var_template = 0;
+template int var_template;
+
template int var_template;
int use_var_template() { return var_template; }
template int var_template;
___
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[llvm-branch-commits] [openmp] 5288d7a - [OpenMP][OMPT] fix reduction test for 32-bit x86
Author: pro...@itc.rwth-aachen.de
Date: 2020-02-05T15:28:24+01:00
New Revision: 5288d7af5bc1b6775e122df5346f7cde9f65881d
URL:
https://github.com/llvm/llvm-project/commit/5288d7af5bc1b6775e122df5346f7cde9f65881d
DIFF:
https://github.com/llvm/llvm-project/commit/5288d7af5bc1b6775e122df5346f7cde9f65881d.diff
LOG: [OpenMP][OMPT] fix reduction test for 32-bit x86
Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=44733 | TEST 'libomp ::
ompt/synchronization/reduction/tree_reduce.c' FAILED on 32-bit x86 ]]
For 32-bit we need at least 3 variables to avoid atomic reduction to be
choosen by runtime function `__kmp_determine_reduction_method`.
This patch adds reduction variables to the testcase.
Reviewers: mgorny, Hahnfeld
Differential Revision: https://reviews.llvm.org/D73850
(cherry picked from commit 90e4ebdce55fd3c1f8877f19784a5339b9890f98)
Added:
Modified:
openmp/runtime/test/ompt/synchronization/reduction/tree_reduce.c
Removed:
diff --git a/openmp/runtime/test/ompt/synchronization/reduction/tree_reduce.c
b/openmp/runtime/test/ompt/synchronization/reduction/tree_reduce.c
index 2c73fe139004..847abc109b2b 100644
--- a/openmp/runtime/test/ompt/synchronization/reduction/tree_reduce.c
+++ b/openmp/runtime/test/ompt/synchronization/reduction/tree_reduce.c
@@ -1,4 +1,5 @@
// RUN: %libomp-compile-and-run | %sort-threads | FileCheck %s
+// RUN: %libomp-compile -DNOWAIT && %libomp-run | %sort-threads | FileCheck %s
// REQUIRES: ompt
// UNSUPPORTED: gcc
#include "callback.h"
@@ -11,14 +12,17 @@
#endif
int main() {
- int sum = 0;
+ int sum = 0, a = 0, b = 0;
int i;
#pragma omp parallel num_threads(5)
-#pragma omp for reduction(+ : sum) FOR_CLAUSE
+// for 32-bit architecture we need at least 3 variables to trigger tree
+#pragma omp for reduction(+ : sum, a, b) FOR_CLAUSE
for (i = 0; i < 1; i++) {
-sum += i;
+a = b = sum += i;
}
+
+ printf("%i\n", sum);
// CHECK: 0: NULL_POINTER=[[NULL:.*$]]
// CHECK: {{^}}[[MASTER_ID:[0-9]+]]: ompt_event_parallel_begin:
___
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[llvm-branch-commits] [compiler-rt] c32d809 - [TSan] Ensure we can compile the runtime with older SDKs
Author: Julian Lettner
Date: 2020-02-05T10:57:21-08:00
New Revision: c32d809e9cae8da7d3016b6cb30e2a2a9c9e2762
URL:
https://github.com/llvm/llvm-project/commit/c32d809e9cae8da7d3016b6cb30e2a2a9c9e2762
DIFF:
https://github.com/llvm/llvm-project/commit/c32d809e9cae8da7d3016b6cb30e2a2a9c9e2762.diff
LOG: [TSan] Ensure we can compile the runtime with older SDKs
One of my changes [1] included in this release silently bumped the
minimal macOS SDK required for building the TSan runtime to SDK 10.12.
Let's ensure release 10 does not unexpectedly break builders with old
SDKs and add proper minimal SDK checking in CMake for subsequent
releases.
This fix `#ifdef`s out interceptors for newer APIs. Note that the
resulting TSan runtime is less complete: when these newer APIs are used
TSan will report false positives.
Fixes llvm 10 release blocker: #44682
https://bugs.llvm.org/show_bug.cgi?id=44682
[1] 894abb46f891cba2e0ef581650f27f512a7824b4
Reviewed By: dmajor
Differential Revision: https://reviews.llvm.org/D74059
Added:
Modified:
compiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp
Removed:
diff --git a/compiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp
b/compiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp
index aa29536d8616..91584914d868 100644
--- a/compiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp
+++ b/compiler-rt/lib/tsan/rtl/tsan_interceptors_mac.cpp
@@ -23,9 +23,12 @@
#include
#include
#include
-#include
#include
+#if defined(__has_include) && __has_include()
+#include
+#endif
+
#if defined(__has_include) && __has_include()
#include
#endif // #if defined(__has_include) && __has_include()
@@ -247,6 +250,8 @@ TSAN_INTERCEPTOR(void, os_lock_unlock, void *lock) {
REAL(os_lock_unlock)(lock);
}
+#if defined(__has_include) && __has_include()
+
TSAN_INTERCEPTOR(void, os_unfair_lock_lock, os_unfair_lock_t lock) {
if (!cur_thread()->is_inited || cur_thread()->is_dead) {
return REAL(os_unfair_lock_lock)(lock);
@@ -286,6 +291,8 @@ TSAN_INTERCEPTOR(void, os_unfair_lock_unlock,
os_unfair_lock_t lock) {
REAL(os_unfair_lock_unlock)(lock);
}
+#endif // #if defined(__has_include) && __has_include()
+
#if defined(__has_include) && __has_include()
TSAN_INTERCEPTOR(void, xpc_connection_set_event_handler,
___
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