date:20191203

[llvm-branch-commits] [lld] 0a64fe5 - [ELF] Fix lld build on Windows/MinGW

2019-12-03 Thread Tom Stellard via llvm-branch-commits


Author: Ayke van Laethem
Date: 2019-12-03T11:52:26-08:00
New Revision: 0a64fe568090a6e298669d901cdff7b356194aa5

URL: 
https://github.com/llvm/llvm-project/commit/0a64fe568090a6e298669d901cdff7b356194aa5
DIFF: 
https://github.com/llvm/llvm-project/commit/0a64fe568090a6e298669d901cdff7b356194aa5.diff

LOG: [ELF] Fix lld build on Windows/MinGW

The patch in https://reviews.llvm.org/D64077 causes a build failure
because both the Defined and SharedSymbol classes are bigger than 80
bytes on MinGW 8.

This patch fixes this build failure by changing the type of the
bitfields. It is a similar change to the bitfield changes in
https://reviews.llvm.org/D64238, but instead of changing to bool I
decided to use uint8_t because one of the bitfields takes up two bits
instead of one.

Note: the patch is slightly different from the one reviewed in
Phabricator, but it is a trivial change to align it with LLVM master
instead of LLVM 9. Also, it passes all lld tests.

Differential Revision: https://reviews.llvm.org/D70266

(cherry picked from commit 57776f71fa32a5b170a9ce82cb2c2da0a207908c)

Added: 


Modified: 
lld/ELF/Symbols.h

Removed: 




diff  --git a/lld/ELF/Symbols.h b/lld/ELF/Symbols.h
index 9c1eb387c2f4..d20d06eec4ce 100644
--- a/lld/ELF/Symbols.h
+++ b/lld/ELF/Symbols.h
@@ -108,27 +108,27 @@ class Symbol {
 
   // Symbol visibility. This is the computed minimum visibility of all
   // observed non-DSO symbols.
-  unsigned visibility : 2;
+  uint8_t visibility : 2;
 
   // True if the symbol was used for linking and thus need to be added to the
   // output file's symbol table. This is true for all symbols except for
   // unreferenced DSO symbols, lazy (archive) symbols, and bitcode symbols that
   // are unreferenced except by other bitcode objects.
-  unsigned isUsedInRegularObj : 1;
+  uint8_t isUsedInRegularObj : 1;
 
   // If this flag is true and the symbol has protected or default visibility, 
it
   // will appear in .dynsym. This flag is set by interposable DSO symbols in
   // executables, by most symbols in DSOs and executables built with
   // --export-dynamic, and by dynamic lists.
-  unsigned exportDynamic : 1;
+  uint8_t exportDynamic : 1;
 
   // False if LTO shouldn't inline whatever this symbol points to. If a symbol
   // is overwritten after LTO, LTO shouldn't inline the symbol because it
   // doesn't know the final contents of the symbol.
-  unsigned canInline : 1;
+  uint8_t canInline : 1;
 
   // True if this symbol is specified by --trace-symbol option.
-  unsigned traced : 1;
+  uint8_t traced : 1;
 
   inline void replace(const Symbol &New);
 
@@ -236,28 +236,28 @@ class Symbol {
 public:
   // True the symbol should point to its PLT entry.
   // For SharedSymbol only.
-  unsigned needsPltAddr : 1;
+  uint8_t needsPltAddr : 1;
 
   // True if this symbol is in the Iplt sub-section of the Plt and the Igot
   // sub-section of the .got.plt or .got.
-  unsigned isInIplt : 1;
+  uint8_t isInIplt : 1;
 
   // True if this symbol needs a GOT entry and its GOT entry is actually in
   // Igot. This will be true only for certain non-preemptible ifuncs.
-  unsigned gotInIgot : 1;
+  uint8_t gotInIgot : 1;
 
   // True if this symbol is preemptible at load time.
-  unsigned isPreemptible : 1;
+  uint8_t isPreemptible : 1;
 
   // True if an undefined or shared symbol is used from a live section.
-  unsigned used : 1;
+  uint8_t used : 1;
 
   // True if a call to this symbol needs to be followed by a restore of the
   // PPC64 toc pointer.
-  unsigned needsTocRestore : 1;
+  uint8_t needsTocRestore : 1;
 
   // True if this symbol is defined by a linker script.
-  unsigned scriptDefined : 1;
+  uint8_t scriptDefined : 1;
 
   // The partition whose dynamic symbol table contains this symbol's 
definition.
   uint8_t partition = 1;



___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] ed3f33f - [PowerPC] Implementing overflow version for XO-Form instructions

2019-12-03 Thread Tom Stellard via llvm-branch-commits


Author: Stefan Pintile
Date: 2019-12-03T13:21:46-08:00
New Revision: ed3f33f9dca7a036166b4daf0cbb98b0e129879a

URL: 
https://github.com/llvm/llvm-project/commit/ed3f33f9dca7a036166b4daf0cbb98b0e129879a
DIFF: 
https://github.com/llvm/llvm-project/commit/ed3f33f9dca7a036166b4daf0cbb98b0e129879a.diff

LOG: [PowerPC] Implementing overflow version for XO-Form instructions

The Overflow version of XO-Form instruction uses the SO, OV and
OV32 special registers.

This changes modifies existing multiclasses and instruction
definitions to allow for the use of the XER register to record
the various types if overflow from possible add, subtract and
multiply instructions. It then modifies the existing instructions
as to use these multiclasses as needed.

Patch By: Kamau Bridgeman

Differential Revision: https://reviews.llvm.org/D66902

(cherry picked from commit fdf3d1766bbabb48a397fae646facbe2690313f6)

Added: 


Modified: 
llvm/lib/Target/PowerPC/P9InstrResources.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
llvm/test/MC/PowerPC/invalid-instructions-spellcheck.s
llvm/test/MC/PowerPC/ppc64-encoding.s

Removed: 




diff  --git a/llvm/lib/Target/PowerPC/P9InstrResources.td 
b/llvm/lib/Target/PowerPC/P9InstrResources.td
index 2a10322d3f49..a3efc9059268 100644
--- a/llvm/lib/Target/PowerPC/P9InstrResources.td
+++ b/llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -128,14 +128,14 @@ def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C],
 (instregex "MTVSRW(A|Z)$"),
 (instregex "CMP(WI|LWI|W|LW)(8)?$"),
 (instregex "CMP(L)?D(I)?$"),
-(instregex "SUBF(I)?C(8)?$"),
+(instregex "SUBF(I)?C(8)?(O)?$"),
 (instregex "ANDI(S)?o(8)?$"),
-(instregex "ADDC(8)?$"),
+(instregex "ADDC(8)?(O)?$"),
 (instregex "ADDIC(8)?(o)?$"),
-(instregex "ADD(8|4)(o)?$"),
-(instregex "ADD(E|ME|ZE)(8)?(o)?$"),
-(instregex "SUBF(E|ME|ZE)?(8)?(o)?$"),
-(instregex "NEG(8)?(o)?$"),
+(instregex "ADD(8|4)(O)?(o)?$"),
+(instregex "ADD(E|ME|ZE)(8)?(O)?(o)?$"),
+(instregex "SUBF(E|ME|ZE)?(8)?(O)?(o)?$"),
+(instregex "NEG(8)?(O)?(o)?$"),
 (instregex "POPCNTB$"),
 (instregex "ADD(I|IS)?(8)?$"),
 (instregex "LI(S)?(8)?$"),
@@ -147,7 +147,7 @@ def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C],
 (instregex "EQV(8)?(o)?$"),
 (instregex "EXTS(B|H|W)(8)?(_32)?(_64)?(o)?$"),
 (instregex "ADD(4|8)(TLS)?(_)?$"),
-(instregex "NEG(8)?$"),
+(instregex "NEG(8)?(O)?$"),
 (instregex "ADDI(S)?toc(HA|L)$"),
 COPY,
 MCRF,
@@ -397,7 +397,7 @@ def : InstRW<[P9_DPE_7C, P9_DPO_7C, IP_EXECE_1C, 
IP_EXECO_1C, DISP_1C],
 def : InstRW<[P9_DP_5C, IP_EXEC_1C, DISP_3SLOTS_1C],
   (instrs
 (instregex "MADD(HD|HDU|LD|LD8)$"),
-(instregex "MUL(HD|HW|LD|LI|LI8|LW)(U)?$")
+(instregex "MUL(HD|HW|LD|LI|LI8|LW)(U)?(O)?$")
 )>;
 
 // 7 cycle Restricted DP operation. One DP unit, one EXEC pipeline and all 
three
@@ -456,7 +456,7 @@ def : InstRW<[P9_DP_7C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C,
 def : InstRW<[P9_DPOpAndALUOp_7C, IP_EXEC_1C, IP_EXEC_1C,
   DISP_3SLOTS_1C, DISP_1C],
   (instrs
-(instregex "MUL(H|L)(D|W)(U)?o$")
+(instregex "MUL(H|L)(D|W)(U)?(O)?o$")
 )>;
 
 // 7 cycle Restricted DP operation and one 3 cycle ALU operation.
@@ -944,7 +944,9 @@ def : InstRW<[P9_DIV_12C, IP_EXECE_1C, IP_EXECO_1C, 
DISP_EVEN_1C],
 def : InstRW<[P9_DIV_16C_8, IP_EXECO_1C, IP_EXECE_1C, DISP_EVEN_1C],
   (instrs
 DIVW,
+DIVWO,
 DIVWU,
+DIVWUO,
 MODSW
 )>;
 
@@ -954,9 +956,13 @@ def : InstRW<[P9_DIV_16C_8, IP_EXECO_1C, IP_EXECE_1C, 
DISP_EVEN_1C],
 def : InstRW<[P9_DIV_24C_8, IP_EXECO_1C, IP_EXECE_1C, DISP_EVEN_1C],
   (instrs
 DIVWE,
+DIVWEO,
 DIVD,
+DIVDO,
 DIVWEU,
+DIVWEUO,
 DIVDU,
+DIVDUO,
 MODSD,
 MODUD,
 MODUW
@@ -968,7 +974,9 @@ def : InstRW<[P9_DIV_24C_8, IP_EXECO_1C, IP_EXECE_1C, 
DISP_EVEN_1C],
 def : InstRW<[P9_DIV_40C_8, IP_EXECO_1C, IP_EXECE_1C, DISP_EVEN_1C],
   (instrs
 DIVDE,
-DIVDEU
+DIVDEO,
+DIVDEU,
+DIVDEUO
 )>;
 
 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
@@ -987,9 +995,13 @@ def : InstRW<[P9_IntDivAndALUOp_26C_8, IP_EXECE_1C, 
IP_EXECO_1C, IP_EXEC_1C,
   DISP_EVEN_1C, DISP_1C],
   (instrs
 DIVDo,
+DIVDOo,
 DIVDUo,
+DIVDUOo,
 DIVWEo,
-DIVWEUo
+DIVWEOo,
+DIVWEUo,
+DIVWEUOo
 )>;
 
 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
@@ -999,7 +1011,9 @@ def : InstRW<[P9_IntDivAndALUOp_42C_8, IP_EXECE_1C, 
IP_EXECO_1C, IP_EXEC_1C,
   DISP_EVEN_1C, DISP_1C],
   (instrs
 DIVDEo,
-DIVDEUo
+DIVDEOo,
+DIVDEUo,
+DIVDEUOo
 )>;
 
 // CR access instructions in _BrMCR, IIC

[llvm-branch-commits] [llvm] 52ac914 - [PowerPC] Fix crash in peephole optimization

2019-12-03 Thread Tom Stellard via llvm-branch-commits


Author: Nemanja Ivanovic
Date: 2019-12-03T13:43:22-08:00
New Revision: 52ac91476dcffc5ecb3a6ff0e63b27f8a13edd4a

URL: 
https://github.com/llvm/llvm-project/commit/52ac91476dcffc5ecb3a6ff0e63b27f8a13edd4a
DIFF: 
https://github.com/llvm/llvm-project/commit/52ac91476dcffc5ecb3a6ff0e63b27f8a13edd4a.diff

LOG: [PowerPC] Fix crash in peephole optimization

When converting reg+reg shifts to reg+imm rotates, we neglect to consider the
CodeGenOnly versions of the 32-bit shift mnemonics. This means we produce a
rotate with missing operands which causes a crash.

Committing this fix without review since it is non-controversial that the list
of mnemonics to consider should include the 64-bit aliases for the exact
mnemonics.

Fixes PR44183.

(cherry picked from commit 241cbf201a6f4b7658697e3c76fc6e741d049a01)

Added: 
llvm/test/CodeGen/PowerPC/pr44183.ll

Modified: 
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

Removed: 




diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp 
b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index a787bdd56b9d..b593a98e81a6 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -3529,8 +3529,10 @@ bool 
PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
 ForwardKilledOperandReg = MI.getOperand(ConstantOpNo).getReg();
 
   unsigned Opc = MI.getOpcode();
-  bool SpecialShift32 =
-Opc == PPC::SLW || Opc == PPC::SLWo || Opc == PPC::SRW || Opc == PPC::SRWo;
+  bool SpecialShift32 = Opc == PPC::SLW || Opc == PPC::SLWo ||
+Opc == PPC::SRW || Opc == PPC::SRWo ||
+Opc == PPC::SLW8 || Opc == PPC::SLW8o ||
+Opc == PPC::SRW8 || Opc == PPC::SRW8o;
   bool SpecialShift64 =
 Opc == PPC::SLD || Opc == PPC::SLDo || Opc == PPC::SRD || Opc == PPC::SRDo;
   bool SetCR = Opc == PPC::SLWo || Opc == PPC::SRWo ||

diff  --git a/llvm/test/CodeGen/PowerPC/pr44183.ll 
b/llvm/test/CodeGen/PowerPC/pr44183.ll
new file mode 100644
index ..1a6f932bc6d0
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/pr44183.ll
@@ -0,0 +1,56 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
+%struct.m.2.5.8.11 = type { %struct.l.0.3.6.9, [7 x i8], %struct.a.1.4.7.10 }
+%struct.l.0.3.6.9 = type { i8 }
+%struct.a.1.4.7.10 = type { [27 x i8], [0 x i32], [4 x i8] }
+define void @_ZN1m1nEv(%struct.m.2.5.8.11* %this) local_unnamed_addr nounwind 
align 2 {
+; CHECK-LABEL: _ZN1m1nEv:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mflr r0
+; CHECK-NEXT:std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-NEXT:std r0, 16(r1)
+; CHECK-NEXT:stdu r1, -48(r1)
+; CHECK-NEXT:mr r30, r3
+; CHECK-NEXT:ld r4, 8(r30)
+; CHECK-NEXT:lwz r5, 36(r30)
+; CHECK-NEXT:rldicl r4, r4, 60, 4
+; CHECK-NEXT:rlwinm r3, r4, 31, 0, 0
+; CHECK-NEXT:rlwinm r4, r5, 0, 31, 31
+; CHECK-NEXT:or r4, r4, r3
+; CHECK-NEXT:bl _ZN1llsE1d
+; CHECK-NEXT:nop
+; CHECK-NEXT:ld r3, 16(r30)
+; CHECK-NEXT:ld r4, 8(r30)
+; CHECK-NEXT:rldicl r4, r4, 60, 4
+; CHECK-NEXT:sldi r3, r3, 60
+; CHECK-NEXT:or r3, r4, r3
+; CHECK-NEXT:sldi r3, r3, 31
+; CHECK-NEXT:clrldi r4, r3, 32
+; CHECK-NEXT:bl _ZN1llsE1d
+; CHECK-NEXT:nop
+; CHECK-NEXT:addi r1, r1, 48
+; CHECK-NEXT:ld r0, 16(r1)
+; CHECK-NEXT:mtlr r0
+; CHECK-NEXT:ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-NEXT:blr
+entry:
+  %bc = getelementptr inbounds %struct.m.2.5.8.11, %struct.m.2.5.8.11* %this, 
i64 0, i32 2
+  %0 = bitcast %struct.a.1.4.7.10* %bc to i216*
+  %bf.load = load i216, i216* %0, align 8
+  %bf.lshr = lshr i216 %bf.load, 4
+  %shl.i23 = shl i216 %bf.lshr, 31
+  %shl.i = trunc i216 %shl.i23 to i32
+  %arrayidx = getelementptr inbounds %struct.m.2.5.8.11, %struct.m.2.5.8.11* 
%this, i64 0, i32 2, i32 1, i64 0
+  %1 = load i32, i32* %arrayidx, align 4
+  %and.i = and i32 %1, 1
+  %or.i = or i32 %and.i, %shl.i
+  tail call void @_ZN1llsE1d(%struct.l.0.3.6.9* undef, i32 %or.i) #1
+  %bf.load10 = load i216, i216* %0, align 8
+  %bf.lshr11 = lshr i216 %bf.load10, 4
+  %shl.i1524 = shl i216 %bf.lshr11, 31
+  %shl.i15 = trunc i216 %shl.i1524 to i32
+  tail call void @_ZN1llsE1d(%struct.l.0.3.6.9* undef, i32 %shl.i15) #1
+  ret void
+}
+declare void @_ZN1llsE1d(%struct.l.0.3.6.9*, i32) local_unnamed_addr #0



___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] 64bdd8b - [COFF] Don't error if the only inputs are from /wholearchive:

2019-12-03 Thread Tom Stellard via llvm-branch-commits


Author: Reid Kleckner
Date: 2019-12-03T14:35:46-08:00
New Revision: 64bdd8bc9fbff893fc435c46b307c63f5a592d30

URL: 
https://github.com/llvm/llvm-project/commit/64bdd8bc9fbff893fc435c46b307c63f5a592d30
DIFF: 
https://github.com/llvm/llvm-project/commit/64bdd8bc9fbff893fc435c46b307c63f5a592d30.diff

LOG: [COFF] Don't error if the only inputs are from /wholearchive:

Fixes PR43744

Differential Revision: https://reviews.llvm.org/D69968

(cherry picked from commit ce0f3ee5e4dc2eed5390b57d4a1e37c8bf17a995)

Added: 


Modified: 
lld/COFF/Driver.cpp
lld/test/COFF/entry-inference.test
lld/test/COFF/out.test
lld/test/COFF/wholearchive.s

Removed: 




diff  --git a/lld/COFF/Driver.cpp b/lld/COFF/Driver.cpp
index eb3aff1a8b76..15d6fb5121a1 100644
--- a/lld/COFF/Driver.cpp
+++ b/lld/COFF/Driver.cpp
@@ -1138,7 +1138,7 @@ void LinkerDriver::link(ArrayRef argsArr) {
 }
   }
 
-  if (!args.hasArg(OPT_INPUT)) {
+  if (!args.hasArg(OPT_INPUT, OPT_wholearchive_file)) {
 if (args.hasArg(OPT_deffile))
   config->noEntry = true;
 else
@@ -1626,7 +1626,7 @@ void LinkerDriver::link(ArrayRef argsArr) {
   }
 
   // Handle generation of import library from a def file.
-  if (!args.hasArg(OPT_INPUT)) {
+  if (!args.hasArg(OPT_INPUT, OPT_wholearchive_file)) {
 fixupExports();
 createImportLibrary(/*asLib=*/true);
 return;
@@ -1672,8 +1672,8 @@ void LinkerDriver::link(ArrayRef argsArr) {
 
   // Set default image name if neither /out or /def set it.
   if (config->outputFile.empty()) {
-config->outputFile =
-getOutputPath((*args.filtered(OPT_INPUT).begin())->getValue());
+config->outputFile = getOutputPath(
+(*args.filtered(OPT_INPUT, 
OPT_wholearchive_file).begin())->getValue());
   }
 
   // Fail early if an output file is not writable.

diff  --git a/lld/test/COFF/entry-inference.test 
b/lld/test/COFF/entry-inference.test
index b58a23a30e80..606cbd0bae7a 100644
--- a/lld/test/COFF/entry-inference.test
+++ b/lld/test/COFF/entry-inference.test
@@ -4,6 +4,11 @@
 # RUN: not lld-link /nodefaultlib /out:%t.exe %t.obj > %t.log 2>&1
 # RUN: FileCheck -check-prefix=MAIN %s < %t.log
 
+# Entry inference should work through /wholearchive:, they are also inputs.
+# RUN: lld-link /lib %t.obj /out:%t.lib
+# RUN: not lld-link /nodefaultlib /out:%t.exe /wholearchive:%t.lib > %t.log 
2>&1
+# RUN: FileCheck -check-prefix=MAIN %s < %t.log
+
 # RUN: sed s/ENTRYNAME/wmain/ %s | yaml2obj > %t.obj
 # RUN: not lld-link /out:%t.exe %t.obj > %t.log 2>&1
 # RUN: FileCheck -check-prefix=WMAIN %s < %t.log

diff  --git a/lld/test/COFF/out.test b/lld/test/COFF/out.test
index a7b56145996f..6d7667e906e7 100644
--- a/lld/test/COFF/out.test
+++ b/lld/test/COFF/out.test
@@ -4,14 +4,17 @@
 # RUN: cp %t.obj %T/out/out1.obj
 # RUN: cp %t.obj %T/out/tmp/out2
 # RUN: cp %t.obj %T/out/tmp/out3.xyz
+# RUN: lld-link /lib %t.obj /out:%T/out/out4.lib
 
-# RUN: rm -f out1.exe out2.exe out3.exe out3.dll
+# RUN: rm -f out1.exe out2.exe out3.exe out3.dll out4.exe
 # RUN: lld-link /entry:main %T/out/out1.obj
 # RUN: lld-link /entry:main %T/out/tmp/out2
 # RUN: lld-link /dll /entry:main %T/out/tmp/out3.xyz
+# RUN: lld-link /entry:main -wholearchive:%T/out/out4.lib
 
 # RUN: llvm-readobj out1.exe | FileCheck %s
 # RUN: llvm-readobj out2.exe | FileCheck %s
 # RUN: llvm-readobj out3.dll | FileCheck %s
+# RUN: llvm-readobj out4.exe | FileCheck %s
 
 CHECK: File:

diff  --git a/lld/test/COFF/wholearchive.s b/lld/test/COFF/wholearchive.s
index cb19d4ddde07..3592f7e9add9 100644
--- a/lld/test/COFF/wholearchive.s
+++ b/lld/test/COFF/wholearchive.s
@@ -14,6 +14,10 @@
 # RUN: lld-link -dll -out:%t.dll -entry:main %t.main.obj %t.archive.lib 
-wholearchive:%t.archive.lib -implib:%t.lib
 # RUN: llvm-readobj %t.lib | FileCheck %s -check-prefix CHECK-IMPLIB
 
+# PR43744: Test no inputs except a whole archive.
+# RUN: lld-link -dll -out:%t.dll -noentry -wholearchive:%t.archive.lib 
-implib:%t.lib
+# RUN: llvm-readobj %t.lib | FileCheck %s -check-prefix CHECK-IMPLIB
+
 # RUN: mkdir -p %t.dir
 # RUN: cp %t.archive.lib %t.dir/foo.lib
 # RUN: lld-link -dll -out:%t.dll -entry:main -libpath:%t.dir %t.main.obj 
%t.dir/./foo.lib -wholearchive:foo.lib -implib:%t.lib



___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [lld] 0a64fe5 - [ELF] Fix lld build on Windows/MinGW

[llvm-branch-commits] [llvm] ed3f33f - [PowerPC] Implementing overflow version for XO-Form instructions

[llvm-branch-commits] [llvm] 52ac914 - [PowerPC] Fix crash in peephole optimization

[llvm-branch-commits] [lld] 64bdd8b - [COFF] Don't error if the only inputs are from /wholearchive:

4 matches

Site Navigation

Mail list logo

Footer information