date:20191108

[llvm-branch-commits] [llvm] 1348294 - baseline

2019-11-08 Thread via llvm-branch-commits


Author: joanlluch
Date: 2019-10-17T12:27:20+02:00
New Revision: 134829441250e27a8c41b01cdb562f27842947bc

URL: 
https://github.com/llvm/llvm-project/commit/134829441250e27a8c41b01cdb562f27842947bc
DIFF: 
https://github.com/llvm/llvm-project/commit/134829441250e27a8c41b01cdb562f27842947bc.diff

LOG: baseline

Added: 
llvm/test/CodeGen/MSP430/shift-amount-threshold.ll

Modified: 


Removed: 




diff  --git a/llvm/test/CodeGen/MSP430/shift-amount-threshold.ll 
b/llvm/test/CodeGen/MSP430/shift-amount-threshold.ll
new file mode 100644
index ..19acb5f19739
--- /dev/null
+++ b/llvm/test/CodeGen/MSP430/shift-amount-threshold.ll
@@ -0,0 +1,189 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s
+target datalayout = "e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16"
+target triple = "msp430"
+
+define dso_local i16 @test000a(i16 %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test000a:
+; CHECK:   ; %bb.0: ; %entry
+; CHECK-NEXT:and #32, r12
+; CHECK-NEXT:clrc
+; CHECK-NEXT:rrc r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:ret
+entry:
+  %and = and i16 %a, 32
+  %cmp = icmp ne i16 %and, 0
+  %conv = zext i1 %cmp to i16
+  ret i16 %conv
+}
+
+define dso_local i16 @test000b(i16 %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test000b:
+; CHECK:   ; %bb.0: ; %entry
+; CHECK-NEXT:and #32, r12
+; CHECK-NEXT:clrc
+; CHECK-NEXT:rrc r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:ret
+entry:
+  %and = and i16 %a, 32
+  %cmp = icmp eq i16 %and, 32
+  %conv = zext i1 %cmp to i16
+  ret i16 %conv
+}
+
+define dso_local i16 @test000(i16 %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test000:
+; CHECK:   ; %bb.0: ; %entry
+; CHECK-NEXT:mov r12, r13
+; CHECK-NEXT:clr r12
+; CHECK-NEXT:bit #2048, r13
+; CHECK-NEXT:jeq .LBB2_2
+; CHECK-NEXT:  ; %bb.1: ; %entry
+; CHECK-NEXT:mov #3, r12
+; CHECK-NEXT:  .LBB2_2: ; %entry
+; CHECK-NEXT:ret
+entry:
+  %and = and i16 %a, 2048
+  %cmp = icmp eq i16 %and, 0
+  %cond = select i1 %cmp, i16 0, i16 3
+  ret i16 %cond
+}
+
+define dso_local i16 @test00(i16 %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test00:
+; CHECK:   ; %bb.0: ; %entry
+; CHECK-NEXT:inv r12
+; CHECK-NEXT:swpb r12
+; CHECK-NEXT:mov.b r12, r12
+; CHECK-NEXT:clrc
+; CHECK-NEXT:rrc r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:ret
+entry:
+  %cmp = icmp sgt i16 %a, -1
+  %cond = select i1 %cmp, i16 1, i16 0
+  ret i16 %cond
+}
+
+define dso_local i16 @test0(i16 %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test0:
+; CHECK:   ; %bb.0: ; %entry
+; CHECK-NEXT:swpb r12
+; CHECK-NEXT:sxt r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:ret
+entry:
+  %cmp = icmp slt i16 %a, 0
+  %cond = select i1 %cmp, i16 -1, i16 0
+  ret i16 %cond
+}
+
+define dso_local i16 @test1(i16 %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test1:
+; CHECK:   ; %bb.0: ; %entry
+; CHECK-NEXT:swpb r12
+; CHECK-NEXT:mov.b r12, r12
+; CHECK-NEXT:clrc
+; CHECK-NEXT:rrc r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:ret
+entry:
+  %cmp = icmp slt i16 %a, 0
+  %cond = select i1 %cmp, i16 1, i16 0
+  ret i16 %cond
+}
+
+define dso_local i16 @test2(i16 %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test2:
+; CHECK:   ; %bb.0: ; %entry
+; CHECK-NEXT:swpb r12
+; CHECK-NEXT:mov.b r12, r12
+; CHECK-NEXT:clrc
+; CHECK-NEXT:rrc r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:and #2, r12
+; CHECK-NEXT:ret
+entry:
+  %cmp = icmp slt i16 %a, 0
+  %cond = select i1 %cmp, i16 2, i16 0
+  ret i16 %cond
+}
+
+define dso_local i16 @test3(i16 %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test3:
+; CHECK:   ; %bb.0: ; %entry
+; CHECK-NEXT:swpb r12
+; CHECK-NEXT:sxt r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:rra r12
+; CHECK-NEXT:and #3, r12
+; CHECK-NEXT:ret
+entry:
+  %cmp = icmp slt i16 %a, 0
+  %cond = select i1 %cmp, i16 3, i16 0
+  ret i16 %cond
+}
+
+define dso_local i16 @test4(i16 %a, i16 %b) local_unnamed_addr #0 {
+; CHECK-LABEL: test4:
+; CHECK:   ; %bb.0: ; %ent

[llvm-branch-commits] [llvm] 8b0167f - Merging r374598:

2019-11-08 Thread Tom Stellard via llvm-branch-commits


Author: Simon Atanasyan
Date: 2019-11-08T12:17:54-08:00
New Revision: 8b0167fdee5f6556f18a4d912b679ef0af268e13

URL: 
https://github.com/llvm/llvm-project/commit/8b0167fdee5f6556f18a4d912b679ef0af268e13
DIFF: 
https://github.com/llvm/llvm-project/commit/8b0167fdee5f6556f18a4d912b679ef0af268e13.diff

LOG: Merging r374598:


r374598 | atanasyan | 2019-10-11 14:51:33 -0700 (Fri, 11 Oct 2019) | 12 lines

[mips] Store 64-bit `li.d' operand as a single 8-byte value

Now assembler generates two consecutive `.4byte` directives to store
64-bit `li.d' operand. The first directive stores high 4-byte of the
value. The second directive stores low 4-byte of the value. But on
64-bit system we load this value at once and get wrong result if the
system is little-endian.

This patch fixes the bug. It stores the `li.d' operand as a single
8-byte value.

Differential Revision: https://reviews.llvm.org/D68778


Added: 


Modified: 
llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/test/MC/Mips/macro-li.d.s

Removed: 




diff  --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp 
b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 56f47dc8b8dd..fd867acd234f 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -3426,8 +3426,8 @@ bool MipsAsmParser::expandLoadDoubleImmToGPR(MCInst 
&Inst, SMLoc IDLoc,
 
   getStreamer().SwitchSection(ReadOnlySection);
   getStreamer().EmitLabel(Sym, IDLoc);
-  getStreamer().EmitIntValue(HiImmOp64, 4);
-  getStreamer().EmitIntValue(LoImmOp64, 4);
+  getStreamer().EmitValueToAlignment(8);
+  getStreamer().EmitIntValue(ImmOp64, 8);
   getStreamer().SwitchSection(CS);
 
   if (emitPartialAddress(TOut, IDLoc, Sym))
@@ -3510,8 +3510,8 @@ bool MipsAsmParser::expandLoadDoubleImmToFPR(MCInst 
&Inst, bool Is64FPU,
 
   getStreamer().SwitchSection(ReadOnlySection);
   getStreamer().EmitLabel(Sym, IDLoc);
-  getStreamer().EmitIntValue(HiImmOp64, 4);
-  getStreamer().EmitIntValue(LoImmOp64, 4);
+  getStreamer().EmitValueToAlignment(8);
+  getStreamer().EmitIntValue(ImmOp64, 8);
   getStreamer().SwitchSection(CS);
 
   if (emitPartialAddress(TOut, IDLoc, Sym))

diff  --git a/llvm/test/MC/Mips/macro-li.d.s b/llvm/test/MC/Mips/macro-li.d.s
index 8af82ec608e0..6fc873e12dc5 100644
--- a/llvm/test/MC/Mips/macro-li.d.s
+++ b/llvm/test/MC/Mips/macro-li.d.s
@@ -17,11 +17,11 @@ li.d$4, 0.0
 # N32-N64: daddiu  $4, $zero, 0# encoding: 
[0x00,0x00,0x04,0x64]
 
 li.d   $4, 1.12345
-# ALL: .section.rodata,"a",@progbits
-# ALL:  [[LABEL:\$tmp[0-9]+]]:
-# ALL: .4byte  1072822694
-# ALL: .4byte  3037400872
-# ALL: .text
+# ALL:  .section  .rodata,"a",@progbits
+# ALL-NEXT:  [[LABEL:\$tmp[0-9]+]]:
+# ALL-NEXT:.p2align 3
+# ALL-NEXT:.8byte 4607738388174016296
+# ALL-NEXT:.text
 # O32-N32-NO-PIC:  lui $1, %hi([[LABEL]]) # encoding: 
[A,A,0x01,0x3c]
 # O32-N32-NO-PIC: #   fixup A - offset: 0, 
value: %hi([[LABEL]]), kind: fixup_Mips_HI16
 # O32-N32-NO-PIC:  addiu   $1, $1, %lo([[LABEL]]) # encoding: 
[A,A,0x21,0x24]
@@ -61,11 +61,11 @@ li.d$4, 1.0
 # N32-N64: dsll$4, $4, 46 # encoding: 
[0xbc,0x23,0x04,0x00]
 
 li.d   $4, 12345678910
-# ALL: .section.rodata,"a",@progbits
-# ALL:  [[LABEL:\$tmp[0-9]+]]:
-# ALL: .4byte  1107754720
-# ALL: .4byte  3790602240
-# ALL: .text
+# ALL:  .section  .rodata,"a",@progbits
+# ALL-NEXT:  [[LABEL:\$tmp[0-9]+]]:
+# ALL-NEXT:.p2align 3
+# ALL-NEXT:.8byte 4757770298180239360
+# ALL-NEXT:.text
 # O32-N32-NO-PIC:  lui $1, %hi([[LABEL]]) # encoding: 
[A,A,0x01,0x3c]
 # O32-N32-NO-PIC: #   fixup A - offset: 0, 
value: %hi([[LABEL]]), kind: fixup_Mips_HI16
 # O32-N32-NO-PIC:  addiu   $1, $1, %lo([[LABEL]]) # encoding: 
[A,A,0x21,0x24]
@@ -93,11 +93,11 @@ li.d$4, 12345678910
 # N32-N64: ld  $4, 0($1)  # encoding: 
[0x00,0x00,0x24,0xdc]
 
 li.d   $4, 12345678910.0
-# ALL: .section.rodata,"a",@progbits
-# ALL:  [[LABEL:\$tmp[0-9]+]]:
-# ALL: .4byte  1107754720
-# ALL: .4byte  3790602240
-# ALL: .text
+# ALL:  .section  .rodata,"a",@progbits
+# ALL-NEXT:  [[LABEL:\$tmp[0-9]+]]:
+# ALL-NEXT:.p2align 3
+# ALL-NEXT:.8byte 4757770298180239360
+# ALL-NEXT:.text
 # O32-N32-NO-PIC:  lui $1, %hi([[LABEL]]) # encoding: 
[A,A,0x01,0x3c]
 # O32-N32-NO-PIC: #   fixup A - offset: 0, 
value: %hi([[LABEL]]), kind: fixup_Mips_HI16
 # O32-N32-NO-PIC:  addiu   $1, $1, %lo([[LABEL]]) # encoding: 
[A,A,0x21,0x24]
@@ -125,11 +125,11 @@ li.d  $4, 12345678910.0
 # N32-N64: ld  $4,

[llvm-branch-commits] [compiler-rt] 4e858e4 - Merging r372038:

2019-11-08 Thread Tom Stellard via llvm-branch-commits


Author: Jian Cai
Date: 2019-11-08T12:33:21-08:00
New Revision: 4e858e4ac00b59f064da4e1f7e276916e7d296aa

URL: 
https://github.com/llvm/llvm-project/commit/4e858e4ac00b59f064da4e1f7e276916e7d296aa
DIFF: 
https://github.com/llvm/llvm-project/commit/4e858e4ac00b59f064da4e1f7e276916e7d296aa.diff

LOG: Merging r372038:


r372038 | jcai19 | 2019-09-16 14:47:47 -0700 (Mon, 16 Sep 2019) | 15 lines

[compiler-rt][crt]  make test case nontrivial in check_cxx_section_exists

Summary:
.init_array gets optimized away when building with -O2 and as a result,
check_cxx_section_exists failed to pass -DCOMPILER_RT_HAS_INITFINI_ARRAY
when building crtbegin.o and crtend.o, which causes binaries linked with
them encounter segmentation fault. See https://crbug.com/855759 for
details. This change prevents .init_array section to be optimized away
even with -O2 or higher optimization level.

Subscribers: dberris, mgorny, #sanitizers, llvm-commits

Tags: #sanitizers, #llvm

Differential Revision: https://reviews.llvm.org/D67628


Added: 


Modified: 
compiler-rt/lib/crt/CMakeLists.txt

Removed: 




diff  --git a/compiler-rt/lib/crt/CMakeLists.txt 
b/compiler-rt/lib/crt/CMakeLists.txt
index 03a07f475d7e..03e7b663ec40 100644
--- a/compiler-rt/lib/crt/CMakeLists.txt
+++ b/compiler-rt/lib/crt/CMakeLists.txt
@@ -69,7 +69,7 @@ function(check_cxx_section_exists section output)
 endfunction()
 
 check_cxx_section_exists(".init_array" COMPILER_RT_HAS_INITFINI_ARRAY
-  SOURCE "__attribute__((constructor)) void f() {}\nint main() { return 0; 
}\n")
+  SOURCE "volatile int x;\n__attribute__((constructor)) void f() {x = 0;}\nint 
main() { return 0; }\n")
 
 append_list_if(COMPILER_RT_HAS_STD_C11_FLAG -std=c11 CRT_CFLAGS)
 append_list_if(COMPILER_RT_HAS_INITFINI_ARRAY -DCRT_HAS_INITFINI_ARRAY 
CRT_CFLAGS)



___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] 1348294 - baseline

[llvm-branch-commits] [llvm] 8b0167f - Merging r374598:

[llvm-branch-commits] [compiler-rt] 4e858e4 - Merging r372038:

3 matches

Site Navigation

Mail list logo

Footer information