[llvm-branch-commits] [compiler-rt-branch] r293191 - Merging r293120:

[Hans Wennborg via llvm-branch-commits]

Author: hans
Date: Thu Jan 26 11:13:15 2017
New Revision: 293191

URL: http://llvm.org/viewvc/llvm-project?rev=293191&view=rev
Log:
Merging r293120:

r293120 | compnerd | 2017-01-25 16:37:55 -0800 (Wed, 25 Jan 2017) | 3 lines

builtins: remove an errant ':'

Thanks to Dave Lee for pointing this out!


Modified:
compiler-rt/branches/release_40/   (props changed)
compiler-rt/branches/release_40/lib/builtins/arm/comparesf2.S

Propchange: compiler-rt/branches/release_40/
--
svn:mergeinfo = /compiler-rt/trunk:293120

Modified: compiler-rt/branches/release_40/lib/builtins/arm/comparesf2.S
URL: 
http://llvm.org/viewvc/llvm-project/compiler-rt/branches/release_40/lib/builtins/arm/comparesf2.S?rev=293191&r1=293190&r2=293191&view=diff
==
--- compiler-rt/branches/release_40/lib/builtins/arm/comparesf2.S (original)
+++ compiler-rt/branches/release_40/lib/builtins/arm/comparesf2.S Thu Jan 26 
11:13:15 2017
@@ -283,7 +283,7 @@ DEFINE_COMPILERRT_FUNCTION(__unordsf2)
 END_COMPILERRT_FUNCTION(__unordsf2)
 
 #if defined(COMPILER_RT_ARMHF_TARGET)
-DEFINE_COMPILERRT_FUNCTION(__aeabi_fcmpum):
+DEFINE_COMPILERRT_FUNCTION(__aeabi_fcmpum)
vmov s0, r0
vmov s1, r1
b SYMBOL_NAME(__unordsf2)


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[llvm-branch-commits] [llvm-branch] r293240 - Merging r293000:

[Tom Stellard via llvm-branch-commits]

Author: tstellar
Date: Thu Jan 26 18:45:06 2017
New Revision: 293240

URL: http://llvm.org/viewvc/llvm-project?rev=293240&view=rev
Log:
Merging r293000:


r293000 | thomas.stellard | 2017-01-24 17:25:13 -0800 (Tue, 24 Jan 2017) | 15 
lines

AMDGPU add support for spilling to a user sgpr pointed buffers

Summary:
This lets you select which sort of spilling you want, either s[0:1] or 64-bit 
loads from s[0:1].

Patch By: Dave Airlie

Reviewers: nhaehnle, arsenm, tstellarAMD

Reviewed By: arsenm

Subscribers: mareko, llvm-commits, kzhuravl, wdng, yaxunl, tony-tye

Differential Revision: https://reviews.llvm.org/D25428



Modified:
llvm/branches/release_40/include/llvm/IR/IntrinsicsAMDGPU.td
llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUSubtarget.h
llvm/branches/release_40/lib/Target/AMDGPU/R600ISelLowering.cpp
llvm/branches/release_40/lib/Target/AMDGPU/SIFrameLowering.cpp
llvm/branches/release_40/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/branches/release_40/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
llvm/branches/release_40/lib/Target/AMDGPU/SIMachineFunctionInfo.h
llvm/branches/release_40/lib/Target/AMDGPU/SIRegisterInfo.cpp

Modified: llvm/branches/release_40/include/llvm/IR/IntrinsicsAMDGPU.td
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/include/llvm/IR/IntrinsicsAMDGPU.td?rev=293240&r1=293239&r2=293240&view=diff
==
--- llvm/branches/release_40/include/llvm/IR/IntrinsicsAMDGPU.td (original)
+++ llvm/branches/release_40/include/llvm/IR/IntrinsicsAMDGPU.td Thu Jan 26 
18:45:06 2017
@@ -100,6 +100,10 @@ def int_amdgcn_dispatch_id :
   GCCBuiltin<"__builtin_amdgcn_dispatch_id">,
   Intrinsic<[llvm_i64_ty], [], [IntrNoMem]>;
 
+def int_amdgcn_implicit_buffer_ptr :
+  GCCBuiltin<"__builtin_amdgcn_implicit_buffer_ptr">,
+  Intrinsic<[LLVMQualPointerType], [], [IntrNoMem]>;
+
 
//===--===//
 // Instruction Intrinsics
 
//===--===//

Modified: llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp?rev=293240&r1=293239&r2=293240&view=diff
==
--- llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp (original)
+++ llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp Thu Jan 26 
18:45:06 2017
@@ -140,7 +140,7 @@ bool AMDGPUAsmPrinter::isBlockOnlyReacha
 void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
   const AMDGPUSubtarget &STM = MF->getSubtarget();
   SIProgramInfo KernelInfo;
-  if (STM.isAmdCodeObjectV2()) {
+  if (STM.isAmdCodeObjectV2(*MF)) {
 getSIProgramInfo(KernelInfo, *MF);
 EmitAmdKernelCodeT(*MF, KernelInfo);
   }
@@ -149,7 +149,7 @@ void AMDGPUAsmPrinter::EmitFunctionBodyS
 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
   const SIMachineFunctionInfo *MFI = MF->getInfo();
   const AMDGPUSubtarget &STM = MF->getSubtarget();
-  if (MFI->isKernel() && STM.isAmdCodeObjectV2()) {
+  if (MFI->isKernel() && STM.isAmdCodeObjectV2(*MF)) {
 AMDGPUTargetStreamer *TS =
 static_cast(OutStreamer->getTargetStreamer());
 SmallString<128> SymbolName;
@@ -779,7 +779,7 @@ void AMDGPUAsmPrinter::EmitAmdKernelCode
 
   // FIXME: Should use getKernArgSize
   header.kernarg_segment_byte_size =
-  STM.getKernArgSegmentSize(MFI->getABIArgOffset());
+STM.getKernArgSegmentSize(MF, MFI->getABIArgOffset());
   header.wavefront_sgpr_count = KernelInfo.NumSGPR;
   header.workitem_vgpr_count = KernelInfo.NumVGPR;
   header.workitem_private_segment_byte_size = KernelInfo.ScratchSize;

Modified: llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUSubtarget.cpp?rev=293240&r1=293239&r2=293240&view=diff
==
--- llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUSubtarget.cpp (original)
+++ llvm/branches/release_40/lib/Target/AMDGPU/AMDGPUSubtarget.cpp Thu Jan 26 
18:45:06 2017
@@ -297,8 +297,9 @@ bool SISubtarget::isVGPRSpillingEnabled(
   return EnableVGPRSpilling || !AMDGPU::isShader(F.getCallingConv());
 }
 
-unsigned SISubtarget::getKernArgSegmentSize(unsigned ExplicitArgBytes) const {
-  unsigned ImplicitBytes = getImplicitArgNumBytes();
+unsigned SISubtarget::getKernArgSegmentSize(const MachineFunction &MF,
+   unsigned ExplicitArgBytes) cons