[llvm-branch-commits] [llvm-branch] r277440 - Merging r276701 and r277439
Author: rengolin
Date: Tue Aug 2 05:26:08 2016
New Revision: 277440
URL: http://llvm.org/viewvc/llvm-project?rev=277440&view=rev
Log:
Merging r276701 and r277439
The saturation instructions appeared in v6T2 / DSP extensions, but they
were being accepted / generated on any, with the new introduction of the
saturation detection in the back-end. This commit restricts the usage to
v6T2 / DSP-enable only cores.
Fixes PR28607.
Added:
llvm/branches/release_39/test/CodeGen/ARM/ssat-v4t.ll
llvm/branches/release_39/test/CodeGen/ARM/usat-v4t.ll
Modified:
llvm/branches/release_39/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/release_39/lib/Target/ARM/ARMInstrInfo.td
llvm/branches/release_39/lib/Target/ARM/ARMInstrThumb2.td
llvm/branches/release_39/test/CodeGen/ARM/ssat.ll
llvm/branches/release_39/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt
Modified: llvm/branches/release_39/lib/Target/ARM/ARMISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/ARM/ARMISelLowering.cpp?rev=277440&r1=277439&r2=277440&view=diff
==
--- llvm/branches/release_39/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/release_39/lib/Target/ARM/ARMISelLowering.cpp Tue Aug 2
05:26:08 2016
@@ -3857,7 +3857,8 @@ SDValue ARMTargetLowering::LowerSELECT_C
// Try to convert two saturating conditional selects into a single SSAT
SDValue SatValue;
uint64_t SatConstant;
- if (isSaturatingConditional(Op, SatValue, SatConstant))
+ if (((!Subtarget->isThumb() && Subtarget->hasV6Ops()) ||
Subtarget->isThumb2()) &&
+ isSaturatingConditional(Op, SatValue, SatConstant))
return DAG.getNode(ARMISD::SSAT, dl, VT, SatValue,
DAG.getConstant(countTrailingOnes(SatConstant), dl,
VT));
Modified: llvm/branches/release_39/lib/Target/ARM/ARMInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/ARM/ARMInstrInfo.td?rev=277440&r1=277439&r2=277440&view=diff
==
--- llvm/branches/release_39/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/release_39/lib/Target/ARM/ARMInstrInfo.td Tue Aug 2 05:26:08
2016
@@ -3650,7 +3650,8 @@ def USADA8 : AI<(outs GPR:$Rd), (ins GPR
def SSAT : AI<(outs GPRnopc:$Rd),
(ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
- SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
+ SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>,
+ Requires<[IsARM,HasV6]>{
bits<4> Rd;
bits<5> sat_imm;
bits<4> Rn;
@@ -3666,7 +3667,8 @@ def SSAT : AI<(outs GPRnopc:$Rd),
def SSAT16 : AI<(outs GPRnopc:$Rd),
(ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
-NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
+NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
+Requires<[IsARM,HasV6]>{
bits<4> Rd;
bits<4> sat_imm;
bits<4> Rn;
@@ -3679,7 +3681,8 @@ def SSAT16 : AI<(outs GPRnopc:$Rd),
def USAT : AI<(outs GPRnopc:$Rd),
(ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
- SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
+ SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>,
+ Requires<[IsARM,HasV6]> {
bits<4> Rd;
bits<5> sat_imm;
bits<4> Rn;
@@ -3695,7 +3698,8 @@ def USAT : AI<(outs GPRnopc:$Rd),
def USAT16 : AI<(outs GPRnopc:$Rd),
(ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
-NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
+NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>,
+Requires<[IsARM,HasV6]>{
bits<4> Rd;
bits<4> sat_imm;
bits<4> Rn;
Modified: llvm/branches/release_39/lib/Target/ARM/ARMInstrThumb2.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/ARM/ARMInstrThumb2.td?rev=277440&r1=277439&r2=277440&view=diff
==
--- llvm/branches/release_39/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/branches/release_39/lib/Target/ARM/ARMInstrThumb2.td Tue Aug 2
05:26:08 2016
@@ -2240,7 +2240,8 @@ class T2SatI {
+ NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>,
+ Requires<[IsThumb2]> {
let Inst{31-27} = 0b0;
let Inst{25-22} = 0b1100;
let Inst{20} = 0;
@@ -2251,7 +2252,7 @@ def t2SSAT: T2SatI<
def t2SSAT16: T2SatI<
(outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
"ssat16", "\t$Rd, $sat_imm, $Rn", []>,
- Requires<[IsThumb2, HasDSP]> {
+Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b0;
let Inst{25-22} = 0b1100;
let Inst{20} = 0;
@@ -2265,7 +2266,8 @@ def t2SSAT16: T2SatI<
def
[llvm-branch-commits] [llvm-branch] r277508 - Merging r276648:
Author: hans
Date: Tue Aug 2 14:41:53 2016
New Revision: 277508
URL: http://llvm.org/viewvc/llvm-project?rev=277508&view=rev
Log:
Merging r276648:
r276648 | delena | 2016-07-25 09:51:00 -0700 (Mon, 25 Jul 2016) | 6 lines
AVX-512: Fixed [US]INT_TO_FP selection for i1 vectors.
It failed with assertion before this patch.
Differential Revision: https://reviews.llvm.org/D22735
Modified:
llvm/branches/release_39/ (props changed)
llvm/branches/release_39/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/release_39/test/CodeGen/X86/avx512-cvt.ll
Propchange: llvm/branches/release_39/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Aug 2 14:41:53 2016
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,275868-275870,275879,275898,275928,275935,275946,275978,275981,276015,276077,276109,276119,276181,276209,276236-276237,276358,276364,276368,276389,276435,276438,276479,276510,276740,276956,276980,277114,277135
+/llvm/trunk:155241,275868-275870,275879,275898,275928,275935,275946,275978,275981,276015,276077,276109,276119,276181,276209,276236-276237,276358,276364,276368,276389,276435,276438,276479,276510,276648,276740,276956,276980,277114,277135
Modified: llvm/branches/release_39/lib/Target/X86/X86ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/X86/X86ISelLowering.cpp?rev=277508&r1=277507&r2=277508&view=diff
==
--- llvm/branches/release_39/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_39/lib/Target/X86/X86ISelLowering.cpp Tue Aug 2
14:41:53 2016
@@ -1187,6 +1187,14 @@ X86TargetLowering::X86TargetLowering(con
setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
+setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
+setOperationAction(ISD::UINT_TO_FP, MVT::v16i1, Custom);
+setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
+setOperationAction(ISD::UINT_TO_FP, MVT::v8i1, Custom);
+setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
+setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
+setOperationAction(ISD::SINT_TO_FP, MVT::v2i1, Custom);
+setOperationAction(ISD::UINT_TO_FP, MVT::v2i1, Custom);
setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
@@ -13373,6 +13381,7 @@ SDValue X86TargetLowering::LowerSINT_TO_
MVT VT = Op.getSimpleValueType();
SDLoc dl(Op);
+ const TargetLowering &TLI = DAG.getTargetLoweringInfo();
if (SrcVT.isVector()) {
if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
@@ -13380,6 +13389,9 @@ SDValue X86TargetLowering::LowerSINT_TO_
DAG.getUNDEF(SrcVT)));
}
if (SrcVT.getVectorElementType() == MVT::i1) {
+ if (SrcVT == MVT::v2i1 && TLI.isTypeLegal(SrcVT))
+return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
+ DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v2i64, Src));
MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
@@ -13694,6 +13706,15 @@ SDValue X86TargetLowering::lowerUINT_TO_
MVT SVT = N0.getSimpleValueType();
SDLoc dl(Op);
+ if (SVT.getVectorElementType() == MVT::i1) {
+if (SVT == MVT::v2i1)
+ return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
+ DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64, N0));
+MVT IntegerVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
+return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
+ DAG.getNode(ISD::ZERO_EXTEND, dl, IntegerVT, N0));
+ }
+
switch (SVT.SimpleTy) {
default:
llvm_unreachable("Custom UINT_TO_FP is not supported!");
Modified: llvm/branches/release_39/test/CodeGen/X86/avx512-cvt.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/test/CodeGen/X86/avx512-cvt.ll?rev=277508&r1=277507&r2=277508&view=diff
==
--- llvm/branches/release_39/test/CodeGen/X86/avx512-cvt.ll (original)
+++ llvm/branches/release_39/test/CodeGen/X86/avx512-cvt.ll Tue Aug 2 14:41:53
2016
@@ -744,6 +744,36 @@ define <8 x double> @sitofp_8i8_double(<
r
[llvm-branch-commits] [llvm-branch] r277509 - Merging r277371:
Author: hans
Date: Tue Aug 2 14:54:53 2016
New Revision: 277509
URL: http://llvm.org/viewvc/llvm-project?rev=277509&view=rev
Log:
Merging r277371:
r277371 | mkuper | 2016-08-01 12:39:49 -0700 (Mon, 01 Aug 2016) | 9 lines
[DAGCombine] Make sext(setcc) combine respect getBooleanContents
We used to combine "sext(setcc x, y, cc) -> (select (setcc x, y, cc), -1, 0)"
Instead, we should combine to (select (setcc x, y, cc), T, 0) where the value
of T is 1 or -1, depending on the type of the setcc, and getBooleanContents()
for the type if it is not i1.
This fixes PR28504.
Added:
llvm/branches/release_39/test/CodeGen/X86/pr28504.ll
- copied unchanged from r277371, llvm/trunk/test/CodeGen/X86/pr28504.ll
Modified:
llvm/branches/release_39/ (props changed)
llvm/branches/release_39/include/llvm/Target/TargetLowering.h
llvm/branches/release_39/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/branches/release_39/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Propchange: llvm/branches/release_39/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Aug 2 14:54:53 2016
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,275868-275870,275879,275898,275928,275935,275946,275978,275981,276015,276077,276109,276119,276181,276209,276236-276237,276358,276364,276368,276389,276435,276438,276479,276510,276648,276740,276956,276980,277114,277135
+/llvm/trunk:155241,275868-275870,275879,275898,275928,275935,275946,275978,275981,276015,276077,276109,276119,276181,276209,276236-276237,276358,276364,276368,276389,276435,276438,276479,276510,276648,276740,276956,276980,277114,277135,277371
Modified: llvm/branches/release_39/include/llvm/Target/TargetLowering.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/include/llvm/Target/TargetLowering.h?rev=277509&r1=277508&r2=277509&view=diff
==
--- llvm/branches/release_39/include/llvm/Target/TargetLowering.h (original)
+++ llvm/branches/release_39/include/llvm/Target/TargetLowering.h Tue Aug 2
14:54:53 2016
@@ -2349,6 +2349,10 @@ public:
/// from getBooleanContents().
bool isConstFalseVal(const SDNode *N) const;
+ /// Return a constant of type VT that contains a true value that respects
+ /// getBooleanContents()
+ SDValue getConstTrueVal(SelectionDAG &DAG, EVT VT, const SDLoc &DL) const;
+
/// Return if \p N is a True value when extended to \p VT.
bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool Signed) const;
Modified: llvm/branches/release_39/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=277509&r1=277508&r2=277509&view=diff
==
--- llvm/branches/release_39/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/branches/release_39/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Aug
2 14:54:53 2016
@@ -6198,13 +6198,27 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SD
}
}
-// sext(setcc x, y, cc) -> (select (setcc x, y, cc), -1, 0)
-unsigned ElementWidth = VT.getScalarType().getSizeInBits();
+// sext(setcc x, y, cc) -> (select (setcc x, y, cc), T, 0)
+// Here, T can be 1 or -1, depending on the type of the setcc and
+// getBooleanContents().
+unsigned SetCCWidth = N0.getValueType().getScalarSizeInBits();
+
SDLoc DL(N);
-SDValue NegOne =
- DAG.getConstant(APInt::getAllOnesValue(ElementWidth), DL, VT);
+// To determine the "true" side of the select, we need to know the high bit
+// of the value returned by the setcc if it evaluates to true.
+// If the type of the setcc is i1, then the true case of the select is just
+// sext(i1 1), that is, -1.
+// If the type of the setcc is larger (say, i8) then the value of the high
+// bit depends on getBooleanContents(). So, ask TLI for a real "true" value
+// of the appropriate width.
+SDValue ExtTrueVal =
+(SetCCWidth == 1)
+? DAG.getConstant(APInt::getAllOnesValue(VT.getScalarSizeInBits()),
+ DL, VT)
+: TLI.getConstTrueVal(DAG, VT, DL);
+
if (SDValue SCC = SimplifySelectCC(
-DL, N0.getOperand(0), N0.getOperand(1), NegOne,
+DL, N0.getOperand(0), N0.getOperand(1), ExtTrueVal,
DAG.getConstant(0, DL, VT),
cast(N0.getOperand(2))->get(), true))
return SCC;
@@ -6215,10 +6229,10 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SD
TLI.isOperationLegal(ISD::SETCC, N0.getOperand(0).getValueType())) {
SDLoc DL(N);
I
[llvm-branch-commits] [cfe-branch] r277525 - Merging r277095:
Author: hans
Date: Tue Aug 2 16:29:54 2016
New Revision: 277525
URL: http://llvm.org/viewvc/llvm-project?rev=277525&view=rev
Log:
Merging r277095:
r277095 | epilk | 2016-07-28 17:55:40 -0700 (Thu, 28 Jul 2016) | 5 lines
[Parser] Fix bug where delayed typo in conditional expression was corrected
twice
Patch by David Tarditi!
Differential revision: https://reviews.llvm.org/D22930
Modified:
cfe/branches/release_39/ (props changed)
cfe/branches/release_39/lib/Parse/ParseExpr.cpp
cfe/branches/release_39/test/Sema/typo-correction.c
Propchange: cfe/branches/release_39/
--
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Aug 2 16:29:54 2016
@@ -1,4 +1,4 @@
/cfe/branches/type-system-rewrite:134693-134817
-/cfe/trunk:275880,275967,276102,276350,276361,276473,276653,276716,276887,276891,276979,276983,277138,277141,277221,277307
+/cfe/trunk:275880,275967,276102,276350,276361,276473,276653,276716,276887,276891,276979,276983,277095,277138,277141,277221,277307
/cfe/trunk/test:170344
/cfe/trunk/test/SemaTemplate:126920
Modified: cfe/branches/release_39/lib/Parse/ParseExpr.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_39/lib/Parse/ParseExpr.cpp?rev=277525&r1=277524&r2=277525&view=diff
==
--- cfe/branches/release_39/lib/Parse/ParseExpr.cpp (original)
+++ cfe/branches/release_39/lib/Parse/ParseExpr.cpp Tue Aug 2 16:29:54 2016
@@ -447,14 +447,15 @@ Parser::ParseRHSOfBinaryExpression(ExprR
LHS = Actions.ActOnBinOp(getCurScope(), OpToken.getLocation(),
OpToken.getKind(), LHS.get(), RHS.get());
-// In this case, ActOnBinOp performed the CorrectDelayedTyposInExpr
check.
-if (!getLangOpts().CPlusPlus)
- continue;
} else {
LHS = Actions.ActOnConditionalOp(OpToken.getLocation(), ColonLoc,
LHS.get(), TernaryMiddle.get(),
RHS.get());
}
+ // In this case, ActOnBinOp or ActOnConditionalOp performed the
+ // CorrectDelayedTyposInExpr check.
+ if (!getLangOpts().CPlusPlus)
+continue;
}
// Ensure potential typos aren't left undiagnosed.
if (LHS.isInvalid()) {
Modified: cfe/branches/release_39/test/Sema/typo-correction.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_39/test/Sema/typo-correction.c?rev=277525&r1=277524&r2=277525&view=diff
==
--- cfe/branches/release_39/test/Sema/typo-correction.c (original)
+++ cfe/branches/release_39/test/Sema/typo-correction.c Tue Aug 2 16:29:54 2016
@@ -65,3 +65,18 @@ int fn_with_rs(int r) { r = TYPO + r * T
void fn_with_unknown(int a, int b) {
fn_with_unknown(unknown, unknown | unknown); // expected-error 3 {{use of
undeclared identifier}}
}
+
+// Two typos in a parenthesized expression or argument list with a conditional
+// expression caused a crash in C mode.
+//
+// r272587 fixed a similar bug for binary operations. The same fix was needed
for
+// conditional expressions.
+
+int g(int x, int y) {
+ return x + y;
+}
+
+int h() {
+ g(x, 5 ? z : 0); // expected-error 2 {{use of undeclared identifier}}
+ (x, 5 ? z : 0); // expected-error 2 {{use of undeclared identifier}}
+}
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