[llvm-branch-commits] [llvm-branch] r271217 - Merging r266438:
Author: tstellar
Date: Mon May 30 12:38:43 2016
New Revision: 271217
URL: http://llvm.org/viewvc/llvm-project?rev=271217&view=rev
Log:
Merging r266438:
r266438 | niravd | 2016-04-15 08:01:38 -0700 (Fri, 15 Apr 2016) | 15 lines
Fix typing on generated LXV2DX/STXV2DX instructions
[PPC] Previously when casting generic loads to LXV2DX/ST instructions we
would leave the original load return type in place allowing for an
assertion failure when we merge two equivalent LXV2DX nodes with
different types.
This fixes PR27350.
Reviewers: nemanjai
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D19133
Added:
llvm/branches/release_38/test/CodeGen/PowerPC/pr27350.ll
Modified:
llvm/branches/release_38/lib/Target/PowerPC/PPCISelLowering.cpp
Modified: llvm/branches/release_38/lib/Target/PowerPC/PPCISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/PowerPC/PPCISelLowering.cpp?rev=271217&r1=271216&r2=271217&view=diff
==
--- llvm/branches/release_38/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/branches/release_38/lib/Target/PowerPC/PPCISelLowering.cpp Mon May 30
12:38:43 2016
@@ -10109,13 +10109,24 @@ SDValue PPCTargetLowering::expandVSXLoad
MVT VecTy = N->getValueType(0).getSimpleVT();
SDValue LoadOps[] = { Chain, Base };
SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
- DAG.getVTList(VecTy, MVT::Other),
- LoadOps, VecTy, MMO);
+ DAG.getVTList(MVT::v2f64, MVT::Other),
+ LoadOps, MVT::v2f64, MMO);
+
DCI.AddToWorklist(Load.getNode());
Chain = Load.getValue(1);
- SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
- DAG.getVTList(VecTy, MVT::Other), Chain, Load);
+ SDValue Swap = DAG.getNode(
+ PPCISD::XXSWAPD, dl, DAG.getVTList(MVT::v2f64, MVT::Other), Chain, Load);
DCI.AddToWorklist(Swap.getNode());
+
+ // Add a bitcast if the resulting load type doesn't match v2f64.
+ if (VecTy != MVT::v2f64) {
+SDValue N = DAG.getNode(ISD::BITCAST, dl, VecTy, Swap);
+DCI.AddToWorklist(N.getNode());
+// Package {bitcast value, swap's chain} to match Load's shape.
+return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VecTy, MVT::Other),
+ N, Swap.getValue(1));
+ }
+
return Swap;
}
@@ -10159,8 +10170,15 @@ SDValue PPCTargetLowering::expandVSXStor
SDValue Src = N->getOperand(SrcOpnd);
MVT VecTy = Src.getValueType().getSimpleVT();
+
+ // All stores are done as v2f64 and possible bit cast.
+ if (VecTy != MVT::v2f64) {
+Src = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Src);
+DCI.AddToWorklist(Src.getNode());
+ }
+
SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
- DAG.getVTList(VecTy, MVT::Other), Chain, Src);
+ DAG.getVTList(MVT::v2f64, MVT::Other), Chain,
Src);
DCI.AddToWorklist(Swap.getNode());
Chain = Swap.getValue(1);
SDValue StoreOps[] = { Chain, Swap, Base };
Added: llvm/branches/release_38/test/CodeGen/PowerPC/pr27350.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/PowerPC/pr27350.ll?rev=271217&view=auto
==
--- llvm/branches/release_38/test/CodeGen/PowerPC/pr27350.ll (added)
+++ llvm/branches/release_38/test/CodeGen/PowerPC/pr27350.ll Mon May 30
12:38:43 2016
@@ -0,0 +1,26 @@
+; RUN: llc -mcpu=ppc64le -mtriple=powerpc64le-unknown-linux-gnu < %s
+
+; Function Attrs: argmemonly nounwind
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly,
i64, i32, i1) #0
+
+; Function Attrs: nounwind
+define internal fastcc void @foo() unnamed_addr #1 align 2 {
+entry:
+ call void @llvm.memcpy.p0i8.p0i8.i64(i8* undef, i8* null, i64 16, i32 8, i1
false)
+ %0 = load <2 x i64>, <2 x i64>* null, align 8
+ %1 = extractelement <2 x i64> %0, i32 1
+ %.fca.1.insert159.i = insertvalue [2 x i64] undef, i64 %1, 1
+ tail call fastcc void @bar([2 x i64] undef, [2 x i64] %.fca.1.insert159.i) #2
+ unreachable
+}
+
+; Function Attrs: nounwind
+declare fastcc void @bar([2 x i64], [2 x i64]) unnamed_addr #1 align 2
+
+attributes #0 = { argmemonly nounwind }
+attributes #1 = { nounwind "disable-tail-calls"="false"
"less-precise-fpmad"="false" "no-frame-pointer-elim"="true"
"no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false"
"no-jump-tables"="false" "no-nans-fp-math"="false"
"stack-protector-buffer-size"="8" "target-cpu"="ppc64le"
"target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-qpx"
"unsafe-fp-math"="false" "use-so
[llvm-branch-commits] [llvm-branch] r271216 - Merging r266217:
Author: tstellar
Date: Mon May 30 12:38:42 2016
New Revision: 271216
URL: http://llvm.org/viewvc/llvm-project?rev=271216&view=rev
Log:
Merging r266217:
r266217 | niravd | 2016-04-13 10:27:26 -0700 (Wed, 13 Apr 2016) | 12 lines
Cleanup Store Merging in UseAA case
This patch fixes a bug (PR26827) when using anti-aliasing in store
merging. This sets the chain users of the component stores to point to
the new store instead of the component stores chain parent.
Reviewers: jyknight
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D18909
Modified:
llvm/branches/release_38/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/branches/release_38/test/CodeGen/AArch64/merge-store.ll
Modified: llvm/branches/release_38/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=271216&r1=271215&r2=271216&view=diff
==
--- llvm/branches/release_38/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/branches/release_38/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon May
30 12:38:42 2016
@@ -11185,26 +11185,34 @@ bool DAGCombiner::MergeStoresOfConstants
false, false,
FirstInChain->getAlignment());
- // Replace the last store with the new store
- CombineTo(LatestOp, NewStore);
- // Erase all other stores.
- for (unsigned i = 0; i < NumStores; ++i) {
-if (StoreNodes[i].MemNode == LatestOp)
- continue;
-StoreSDNode *St = cast(StoreNodes[i].MemNode);
-// ReplaceAllUsesWith will replace all uses that existed when it was
-// called, but graph optimizations may cause new ones to appear. For
-// example, the case in pr14333 looks like
-//
-// St's chain -> St -> another store -> X
-//
-// And the only difference from St to the other store is the chain.
-// When we change it's chain to be St's chain they become identical,
-// get CSEed and the net result is that X is now a use of St.
-// Since we know that St is redundant, just iterate.
-while (!St->use_empty())
- DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain());
-deleteAndRecombine(St);
+ bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA
+ : DAG.getSubtarget().useAA();
+ if (UseAA) {
+// Replace all merged stores with the new store.
+for (unsigned i = 0; i < NumStores; ++i)
+ CombineTo(StoreNodes[i].MemNode, NewStore);
+ } else {
+// Replace the last store with the new store.
+CombineTo(LatestOp, NewStore);
+// Erase all other stores.
+for (unsigned i = 0; i < NumStores; ++i) {
+ if (StoreNodes[i].MemNode == LatestOp)
+continue;
+ StoreSDNode *St = cast(StoreNodes[i].MemNode);
+ // ReplaceAllUsesWith will replace all uses that existed when it was
+ // called, but graph optimizations may cause new ones to appear. For
+ // example, the case in pr14333 looks like
+ //
+ // St's chain -> St -> another store -> X
+ //
+ // And the only difference from St to the other store is the chain.
+ // When we change it's chain to be St's chain they become identical,
+ // get CSEed and the net result is that X is now a use of St.
+ // Since we know that St is redundant, just iterate.
+ while (!St->use_empty())
+DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain());
+ deleteAndRecombine(St);
+}
}
return true;
@@ -11708,16 +11716,24 @@ bool DAGCombiner::MergeConsecutiveStores
SDValue(NewLoad.getNode(), 1));
}
- // Replace the last store with the new store.
- CombineTo(LatestOp, NewStore);
- // Erase all other stores.
- for (unsigned i = 0; i < NumElem ; ++i) {
-// Remove all Store nodes.
-if (StoreNodes[i].MemNode == LatestOp)
- continue;
-StoreSDNode *St = cast(StoreNodes[i].MemNode);
-DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain());
-deleteAndRecombine(St);
+ bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA
+: DAG.getSubtarget().useAA();
+ if (UseAA) {
+// Replace the all stores with the new store.
+for (unsigned i = 0; i < NumElem; ++i)
+ CombineTo(StoreNodes[i].MemNode, NewStore);
+ } else {
+// Replace the last store with the new store.
+CombineTo(LatestOp, NewStore);
+// Erase all other stores.
+for (unsigned i = 0; i < NumElem; ++i) {
+ // Remove all Store nodes.
+ if (StoreNodes[i].MemNode == LatestOp)
+continue;
+ StoreSDNode *St = cast(StoreNodes[i].MemNode);
+ DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain());
+ deleteAndRecombine
[llvm-branch-commits] [llvm-branch] r271230 - Merging r261139:
Author: tstellar
Date: Mon May 30 15:42:50 2016
New Revision: 271230
URL: http://llvm.org/viewvc/llvm-project?rev=271230&view=rev
Log:
Merging r261139:
r261139 | deadalnix | 2016-02-17 11:21:28 -0800 (Wed, 17 Feb 2016) | 10 lines
Fix load alignement when unpacking aggregates structs
Summary: Store and loads unpacked by instcombine do not always have the
right alignement. This explicitely compute the alignement and set it.
Reviewers: dblaikie, majnemer, reames, hfinkel, joker.eph
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D17326
Modified:
llvm/branches/release_38/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
llvm/branches/release_38/test/Transforms/InstCombine/unpack-fca.ll
Modified:
llvm/branches/release_38/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp?rev=271230&r1=271229&r2=271230&view=diff
==
---
llvm/branches/release_38/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
(original)
+++
llvm/branches/release_38/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
Mon May 30 15:42:50 2016
@@ -523,16 +523,17 @@ static Instruction *unpackLoadToAggregat
if (!T->isAggregateType())
return nullptr;
+ auto Name = LI.getName();
assert(LI.getAlignment() && "Alignment must be set at this point");
if (auto *ST = dyn_cast(T)) {
// If the struct only have one element, we unpack.
-unsigned Count = ST->getNumElements();
-if (Count == 1) {
+auto NumElements = ST->getNumElements();
+if (NumElements == 1) {
LoadInst *NewLoad = combineLoadToNewType(IC, LI, ST->getTypeAtIndex(0U),
".unpack");
return IC.ReplaceInstUsesWith(LI, IC.Builder->CreateInsertValue(
-UndefValue::get(T), NewLoad, 0, LI.getName()));
+UndefValue::get(T), NewLoad, 0, Name));
}
// We don't want to break loads with padding here as we'd loose
@@ -542,23 +543,29 @@ static Instruction *unpackLoadToAggregat
if (SL->hasPadding())
return nullptr;
-auto Name = LI.getName();
+auto Align = LI.getAlignment();
+if (!Align)
+ Align = DL.getABITypeAlignment(ST);
+
SmallString<16> LoadName = Name;
LoadName += ".unpack";
SmallString<16> EltName = Name;
EltName += ".elt";
+
auto *Addr = LI.getPointerOperand();
-Value *V = UndefValue::get(T);
-auto *IdxType = Type::getInt32Ty(ST->getContext());
+auto *IdxType = Type::getInt32Ty(T->getContext());
auto *Zero = ConstantInt::get(IdxType, 0);
-for (unsigned i = 0; i < Count; i++) {
+
+Value *V = UndefValue::get(T);
+for (unsigned i = 0; i < NumElements; i++) {
Value *Indices[2] = {
Zero,
ConstantInt::get(IdxType, i),
};
- auto *Ptr = IC.Builder->CreateInBoundsGEP(ST, Addr,
makeArrayRef(Indices), EltName);
- auto *L = IC.Builder->CreateAlignedLoad(Ptr, LI.getAlignment(),
- LoadName);
+ auto *Ptr = IC.Builder->CreateInBoundsGEP(ST, Addr,
+makeArrayRef(Indices), EltName);
+ auto EltAlign = MinAlign(Align, SL->getElementOffset(i));
+ auto *L = IC.Builder->CreateAlignedLoad(Ptr, EltAlign, LoadName);
V = IC.Builder->CreateInsertValue(V, L, i);
}
@@ -950,11 +957,16 @@ static bool unpackStoreToAggregate(InstC
if (SL->hasPadding())
return false;
+auto Align = SI.getAlignment();
+if (!Align)
+ Align = DL.getABITypeAlignment(ST);
+
SmallString<16> EltName = V->getName();
EltName += ".elt";
auto *Addr = SI.getPointerOperand();
SmallString<16> AddrName = Addr->getName();
AddrName += ".repack";
+
auto *IdxType = Type::getInt32Ty(ST->getContext());
auto *Zero = ConstantInt::get(IdxType, 0);
for (unsigned i = 0; i < Count; i++) {
@@ -962,9 +974,11 @@ static bool unpackStoreToAggregate(InstC
Zero,
ConstantInt::get(IdxType, i),
};
- auto *Ptr = IC.Builder->CreateInBoundsGEP(ST, Addr,
makeArrayRef(Indices), AddrName);
+ auto *Ptr = IC.Builder->CreateInBoundsGEP(ST, Addr,
+makeArrayRef(Indices), AddrName);
auto *Val = IC.Builder->CreateExtractValue(V, i, EltName);
- IC.Builder->CreateStore(Val, Ptr);
+ auto EltAlign = MinAlign(Align, SL->getElementOffset(i));
+ IC.Builder->CreateAlignedStore(Val, Ptr, EltAlign);
}
return true;
Modified: llvm/branches/release_38/test/Transforms/InstCombine/unpack-fca.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test
