[llvm-branch-commits] [llvm-branch] r271119 - Merging r266833:
Author: dsanders
Date: Sat May 28 10:56:22 2016
New Revision: 271119
URL: http://llvm.org/viewvc/llvm-project?rev=271119&view=rev
Log:
Merging r266833:
r266833 | koriakin | 2016-04-20 00:46:59 +0100 (Wed, 20 Apr 2016) | 5 lines
[Mips] [MSan] VarArgMIPS64Helper: Use target's endian, not host's.
Ugh.
Differential Revision: http://reviews.llvm.org/D19292
Modified:
llvm/branches/release_38/lib/Transforms/Instrumentation/MemorySanitizer.cpp
Modified:
llvm/branches/release_38/lib/Transforms/Instrumentation/MemorySanitizer.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Transforms/Instrumentation/MemorySanitizer.cpp?rev=271119&r1=271118&r2=271119&view=diff
==
--- llvm/branches/release_38/lib/Transforms/Instrumentation/MemorySanitizer.cpp
(original)
+++ llvm/branches/release_38/lib/Transforms/Instrumentation/MemorySanitizer.cpp
Sat May 28 10:56:22 2016
@@ -2954,15 +2954,16 @@ struct VarArgMIPS64Helper : public VarAr
const DataLayout &DL = F.getParent()->getDataLayout();
for (CallSite::arg_iterator ArgIt = CS.arg_begin() + 1, End = CS.arg_end();
ArgIt != End; ++ArgIt) {
+ llvm::Triple TargetTriple(F.getParent()->getTargetTriple());
Value *A = *ArgIt;
Value *Base;
uint64_t ArgSize = DL.getTypeAllocSize(A->getType());
-#if defined(__MIPSEB__) || defined(MIPSEB)
- // Adjusting the shadow for argument with size < 8 to match the placement
- // of bits in big endian system
- if (ArgSize < 8)
-VAArgOffset += (8 - ArgSize);
-#endif
+ if (TargetTriple.getArch() == llvm::Triple::mips64) {
+// Adjusting the shadow for argument with size < 8 to match the
placement
+// of bits in big endian system
+if (ArgSize < 8)
+ VAArgOffset += (8 - ArgSize);
+ }
Base = getShadowPtrForVAArgument(A->getType(), IRB, VAArgOffset);
VAArgOffset += ArgSize;
VAArgOffset = RoundUpToAlignment(VAArgOffset, 8);
___
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[llvm-branch-commits] [llvm-branch] r271120 - Merging r268531:
Author: dsanders
Date: Sat May 28 10:57:13 2016
New Revision: 271120
URL: http://llvm.org/viewvc/llvm-project?rev=271120&view=rev
Log:
Merging r268531:
r268531 | koriakin | 2016-05-04 19:39:14 +0100 (Wed, 04 May 2016) | 3 lines
[MSan] [Mips64] Add tests for vararg handling.
Differential Revision: http://reviews.llvm.org/D19919
Added:
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll
Added:
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll?rev=271120&view=auto
==
---
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll
(added)
+++
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll
Sat May 28 10:57:13 2016
@@ -0,0 +1,43 @@
+; RUN: opt < %s -msan -S | FileCheck %s
+
+target datalayout = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"
+target triple = "mips64--linux"
+
+define i32 @foo(i32 %guard, ...) {
+ %vl = alloca i8*, align 8
+ %1 = bitcast i8** %vl to i8*
+ call void @llvm.lifetime.start(i64 32, i8* %1)
+ call void @llvm.va_start(i8* %1)
+ call void @llvm.va_end(i8* %1)
+ call void @llvm.lifetime.end(i64 32, i8* %1)
+ ret i32 0
+}
+
+; First, check allocation of the save area.
+
+; CHECK-LABEL: @foo
+; CHECK: [[A:%.*]] = load {{.*}} @__msan_va_arg_overflow_size_tls
+; CHECK: [[B:%.*]] = add i64 0, [[A]]
+; CHECK: [[C:%.*]] = alloca {{.*}} [[B]]
+
+; CHECK: [[STACK:%.*]] = bitcast {{.*}} @__msan_va_arg_tls to i8*
+; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[C]], i8* [[STACK]], i64
[[B]], i32 8, i1 false)
+
+declare void @llvm.lifetime.start(i64, i8* nocapture) #1
+declare void @llvm.va_start(i8*) #2
+declare void @llvm.va_end(i8*) #2
+declare void @llvm.lifetime.end(i64, i8* nocapture) #1
+
+define i32 @bar() {
+ %1 = call i32 (i32, ...) @foo(i32 0, i32 1, i64 2, double 3.00e+00)
+ ret i32 %1
+}
+
+; Save the incoming shadow value from the arguments in the __msan_va_arg_tls
+; array. The first argument is stored at position 4, since it's right
+; justified.
+; CHECK-LABEL: @bar
+; CHECK: store i32 0, i32* inttoptr (i64 add (i64 ptrtoint ([100 x i64]*
@__msan_va_arg_tls to i64), i64 4) to i32*), align 8
+; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]*
@__msan_va_arg_tls to i64), i64 8) to i64*), align 8
+; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]*
@__msan_va_arg_tls to i64), i64 16) to i64*), align 8
+; CHECK: store {{.*}} 24, {{.*}} @__msan_va_arg_overflow_size_tls
Added:
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll?rev=271120&view=auto
==
---
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll
(added)
+++
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll
Sat May 28 10:57:13 2016
@@ -0,0 +1,42 @@
+; RUN: opt < %s -msan -S | FileCheck %s
+
+target datalayout = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"
+target triple = "mips64el--linux"
+
+define i32 @foo(i32 %guard, ...) {
+ %vl = alloca i8*, align 8
+ %1 = bitcast i8** %vl to i8*
+ call void @llvm.lifetime.start(i64 32, i8* %1)
+ call void @llvm.va_start(i8* %1)
+ call void @llvm.va_end(i8* %1)
+ call void @llvm.lifetime.end(i64 32, i8* %1)
+ ret i32 0
+}
+
+; First, check allocation of the save area.
+
+; CHECK-LABEL: @foo
+; CHECK: [[A:%.*]] = load {{.*}} @__msan_va_arg_overflow_size_tls
+; CHECK: [[B:%.*]] = add i64 0, [[A]]
+; CHECK: [[C:%.*]] = alloca {{.*}} [[B]]
+
+; CHECK: [[STACK:%.*]] = bitcast {{.*}} @__msan_va_arg_tls to i8*
+; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[C]], i8* [[STACK]], i64
[[B]], i32 8, i1 false)
+
+declare void @llvm.lifetime.start(i64, i8* nocapture) #1
+declare void @llvm.va_start(i8*) #2
+declare void @llvm.va_end(i8*) #2
+declare void @llvm.lifetime.end(i64, i8* nocapture) #1
+
+define i32 @bar() {
+ %1 = call i32 (i32, ...) @foo(i32 0, i32 1, i64 2, double 3.00e+00)
+ ret i32 %1
+}
+
+; Save the incoming shadow value from the arguments in the __msan_va_arg_tls
+; array.
+; CHECK-LABEL: @bar
+; CHECK: store i32 0, i32* bitcast ([100 x i64]* @__msan_va_arg_tls to i32*),
align 8
+; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]*
@__msa
[llvm-branch-commits] [llvm-branch] r271121 - Merging r268673:
Author: dsanders
Date: Sat May 28 10:58:03 2016
New Revision: 271121
URL: http://llvm.org/viewvc/llvm-project?rev=271121&view=rev
Log:
Merging r268673:
r268673 | koriakin | 2016-05-05 21:13:17 +0100 (Thu, 05 May 2016) | 5 lines
[MSan] [MIPS64] Fix vararg helper for >1 fixed argument.
This fixes http://llvm.org/PR27646 on Mips64.
Differential Revision: http://reviews.llvm.org/D19989
Modified:
llvm/branches/release_38/lib/Transforms/Instrumentation/MemorySanitizer.cpp
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll
Modified:
llvm/branches/release_38/lib/Transforms/Instrumentation/MemorySanitizer.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Transforms/Instrumentation/MemorySanitizer.cpp?rev=271121&r1=271120&r2=271121&view=diff
==
--- llvm/branches/release_38/lib/Transforms/Instrumentation/MemorySanitizer.cpp
(original)
+++ llvm/branches/release_38/lib/Transforms/Instrumentation/MemorySanitizer.cpp
Sat May 28 10:58:03 2016
@@ -2952,7 +2952,8 @@ struct VarArgMIPS64Helper : public VarAr
void visitCallSite(CallSite &CS, IRBuilder<> &IRB) override {
unsigned VAArgOffset = 0;
const DataLayout &DL = F.getParent()->getDataLayout();
-for (CallSite::arg_iterator ArgIt = CS.arg_begin() + 1, End = CS.arg_end();
+for (CallSite::arg_iterator ArgIt = CS.arg_begin() +
+ CS.getFunctionType()->getNumParams(), End = CS.arg_end();
ArgIt != End; ++ArgIt) {
llvm::Triple TargetTriple(F.getParent()->getTargetTriple());
Value *A = *ArgIt;
Modified:
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll?rev=271121&r1=271120&r2=271121&view=diff
==
---
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll
(original)
+++
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll
Sat May 28 10:58:03 2016
@@ -41,3 +41,15 @@ define i32 @bar() {
; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]*
@__msan_va_arg_tls to i64), i64 8) to i64*), align 8
; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]*
@__msan_va_arg_tls to i64), i64 16) to i64*), align 8
; CHECK: store {{.*}} 24, {{.*}} @__msan_va_arg_overflow_size_tls
+
+; Check multiple fixed arguments.
+declare i32 @foo2(i32 %g1, i32 %g2, ...)
+define i32 @bar2() {
+ %1 = call i32 (i32, i32, ...) @foo2(i32 0, i32 1, i64 2, double 3.00e+00)
+ ret i32 %1
+}
+
+; CHECK-LABEL: @bar2
+; CHECK: store i64 0, i64* getelementptr inbounds ([100 x i64], [100 x i64]*
@__msan_va_arg_tls, i32 0, i32 0), align 8
+; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]*
@__msan_va_arg_tls to i64), i64 8) to i64*), align 8
+; CHECK: store {{.*}} 16, {{.*}} @__msan_va_arg_overflow_size_tls
Modified:
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll?rev=271121&r1=271120&r2=271121&view=diff
==
---
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll
(original)
+++
llvm/branches/release_38/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll
Sat May 28 10:58:03 2016
@@ -40,3 +40,15 @@ define i32 @bar() {
; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]*
@__msan_va_arg_tls to i64), i64 8) to i64*), align 8
; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]*
@__msan_va_arg_tls to i64), i64 16) to i64*), align 8
; CHECK: store {{.*}} 24, {{.*}} @__msan_va_arg_overflow_size_tls
+
+; Check multiple fixed arguments.
+declare i32 @foo2(i32 %g1, i32 %g2, ...)
+define i32 @bar2() {
+ %1 = call i32 (i32, i32, ...) @foo2(i32 0, i32 1, i64 2, double 3.00e+00)
+ ret i32 %1
+}
+
+; CHECK-LABEL: @bar2
+; CHECK: store i64 0, i64* getelementptr inbounds ([100 x i64], [100 x i64]*
@__msan_va_arg_tls, i32 0, i32 0), align 8
+; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]*
@__msan_va_arg_tls to i64), i64 8) to i64*), align 8
+; CHECK: store {{.*}} 16, {{.*}} @__msan_va_arg_overflow_size_tls
___
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[llvm-branch-commits] [llvm-branch] r271122 - Merging r259039:
Author: dsanders
Date: Sat May 28 11:08:13 2016
New Revision: 271122
URL: http://llvm.org/viewvc/llvm-project?rev=271122&view=rev
Log:
Merging r259039:
r259039 | zjovanovic | 2016-01-28 11:08:03 + (Thu, 28 Jan 2016) | 9 lines
[mips][microMIPS] Disable FastISel for microMIPS
Author: milena.vujosevic.janicic
Reviewers: dsanders
FastIsel is not supported for microMIPS, thus it needs to be disabled.
Test micromips-zero-mat-uses.ll is deleted since the tested sequence of
instructions is not generated for microMIPS without FastISel.
Differential Revision: http://reviews.llvm.org/D15892
Removed:
llvm/branches/release_38/test/CodeGen/Mips/micromips-zero-mat-uses.ll
Modified:
llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp
llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll
Modified: llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp?rev=271122&r1=271121&r2=271122&view=diff
==
--- llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp (original)
+++ llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp Sat May 28
11:08:13 2016
@@ -192,7 +192,8 @@ public:
TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
MFI = funcInfo.MF->getInfo();
Context = &funcInfo.Fn->getContext();
-bool ISASupported = !Subtarget->hasMips32r6() && Subtarget->hasMips32();
+bool ISASupported = !Subtarget->hasMips32r6() &&
+!Subtarget->inMicroMipsMode() &&
Subtarget->hasMips32();
TargetSupported =
ISASupported && (TM.getRelocationModel() == Reloc::PIC_) &&
(static_cast(TM).getABI().IsO32());
Modified:
llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll?rev=271122&r1=271121&r2=271122&view=diff
==
---
llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll
(original)
+++
llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll
Sat May 28 11:08:13 2016
@@ -7,6 +7,8 @@
; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \
; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
+; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -O0
-relocation-model=pic \
+; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
; RUN: llc -march=mips -mcpu=mips64 -O0 -relocation-model=pic \
; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s
Removed: llvm/branches/release_38/test/CodeGen/Mips/micromips-zero-mat-uses.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/Mips/micromips-zero-mat-uses.ll?rev=271121&view=auto
==
--- llvm/branches/release_38/test/CodeGen/Mips/micromips-zero-mat-uses.ll
(original)
+++ llvm/branches/release_38/test/CodeGen/Mips/micromips-zero-mat-uses.ll
(removed)
@@ -1,8 +0,0 @@
-; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips,+nooddspreg -O0 < %s |
FileCheck %s
-
-; CHECK: addiu$[[R0:[0-9]+]], $zero, 0
-; CHECK: subu16 $2, $[[R0]], ${{[0-9]+}}
-define i32 @foo() {
- %1 = sub i32 0, undef
- ret i32 %1
-}
___
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[llvm-branch-commits] [llvm-branch] r271123 - Merging r268053:
Author: dsanders
Date: Sat May 28 11:09:06 2016
New Revision: 271123
URL: http://llvm.org/viewvc/llvm-project?rev=271123&view=rev
Log:
Merging r268053:
r268053 | sdardis | 2016-04-29 17:07:47 +0100 (Fri, 29 Apr 2016) | 9 lines
[mips][FastISel] A store is not a load.
Correct trivial error. One of the failing tests from PR/27458.
Reviewers: dsanders, vkalintiris, mcrosier
Differential Review: http://reviews.llvm.org/D19726
Modified:
llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp
llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/fastalloca.ll
Modified: llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp?rev=271123&r1=271122&r2=271123&view=diff
==
--- llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp (original)
+++ llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp Sat May 28
11:09:06 2016
@@ -803,7 +803,7 @@ bool MipsFastISel::emitStore(MVT VT, uns
unsigned Offset = Addr.getOffset();
MachineFrameInfo &MFI = *MF->getFrameInfo();
MachineMemOperand *MMO = MF->getMachineMemOperand(
-MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
+MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
MFI.getObjectSize(FI), Align);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
.addReg(SrcReg)
Modified: llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/fastalloca.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/fastalloca.ll?rev=271123&r1=271122&r2=271123&view=diff
==
--- llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/fastalloca.ll
(original)
+++ llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/fastalloca.ll Sat May
28 11:09:06 2016
@@ -1,5 +1,5 @@
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1
-mcpu=mips32r2 \
-; RUN: < %s | FileCheck %s
+; RUN: < %s -verify-machineinstrs | FileCheck %s
%struct.x = type { i32 }
___
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[llvm-branch-commits] [llvm-branch] r271124 - Merging r268386:
Author: dsanders
Date: Sat May 28 11:10:01 2016
New Revision: 271124
URL: http://llvm.org/viewvc/llvm-project?rev=271124&view=rev
Log:
Merging r268386:
r268386 | dsanders | 2016-05-03 15:19:26 +0100 (Tue, 03 May 2016) | 11 lines
[mips][fastisel] ADJCALLSTACKUP has a second immediate operand.
Summary:
It's always zero for SelectionDAG and is never read by the MIPS backend so
do the same for FastISel.
Reviewers: sdardis
Subscribers: dsanders, llvm-commits, sdardis
Differential Revision: http://reviews.llvm.org/D19863
Modified:
llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp
llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/callabi.ll
llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/memtest1.ll
Modified: llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp?rev=271124&r1=271123&r2=271124&view=diff
==
--- llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp (original)
+++ llvm/branches/release_38/lib/Target/Mips/MipsFastISel.cpp Sat May 28
11:10:01 2016
@@ -1208,7 +1208,7 @@ bool MipsFastISel::processCallArgs(CallL
bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
unsigned NumBytes) {
CallingConv::ID CC = CLI.CallConv;
- emitInst(Mips::ADJCALLSTACKUP).addImm(16);
+ emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0);
if (RetVT != MVT::isVoid) {
SmallVector RVLocs;
CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
Modified: llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/callabi.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/callabi.ll?rev=271124&r1=271123&r2=271124&view=diff
==
--- llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/callabi.ll (original)
+++ llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/callabi.ll Sat May 28
11:10:01 2016
@@ -1,8 +1,8 @@
-; RUN: llc -march=mipsel -mcpu=mips32 -O0 \
-; RUN: -relocation-model=pic -fast-isel-abort=1 < %s | \
+; RUN: llc -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
+; RUN: -fast-isel-abort=1 -verify-machineinstrs < %s | \
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1
-; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 \
-; RUN: -relocation-model=pic -fast-isel-abort=1 < %s | \
+; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
+; RUN: -fast-isel-abort=1 -verify-machineinstrs < %s | \
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2
declare void @xb(i8)
Modified: llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/memtest1.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/memtest1.ll?rev=271124&r1=271123&r2=271124&view=diff
==
--- llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/memtest1.ll (original)
+++ llvm/branches/release_38/test/CodeGen/Mips/Fast-ISel/memtest1.ll Sat May 28
11:10:01 2016
@@ -1,8 +1,8 @@
; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
-; RUN: -fast-isel-abort=1 | FileCheck %s \
+; RUN: -fast-isel-abort=1 -verify-machineinstrs | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=32R1
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
-; RUN: -fast-isel-abort=1 | FileCheck %s \
+; RUN: -fast-isel-abort=1 -verify-machineinstrs | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=32R2
@str = private unnamed_addr constant [12 x i8] c"hello there\00", align 1
___
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[llvm-branch-commits] [llvm-branch] r271126 - Merging r262230:
Author: dsanders
Date: Sat May 28 11:11:08 2016
New Revision: 271126
URL: http://llvm.org/viewvc/llvm-project?rev=271126&view=rev
Log:
Merging r262230:
r262230 | vkalintiris | 2016-02-29 15:58:12 + (Mon, 29 Feb 2016) | 7 lines
[mips] Do not use SLL for ANY_EXTEND nodes as the high bits are undefined.
Reviewers: dsanders
Subscribers: dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D15420
Modified:
llvm/branches/release_38/lib/Target/Mips/Mips64InstrInfo.td
llvm/branches/release_38/test/CodeGen/Mips/cconv/return-struct.ll
llvm/branches/release_38/test/CodeGen/Mips/fcopysign-f32-f64.ll
Modified: llvm/branches/release_38/lib/Target/Mips/Mips64InstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/Mips/Mips64InstrInfo.td?rev=271126&r1=271125&r2=271126&view=diff
==
--- llvm/branches/release_38/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/branches/release_38/lib/Target/Mips/Mips64InstrInfo.td Sat May 28
11:11:08 2016
@@ -518,7 +518,8 @@ def : MipsPat<(rotr GPR64:$rt, (i32 (tru
(DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
// 32-to-64-bit extension
-def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
+def : MipsPat<(i64 (anyext GPR32:$src)),
+ (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
Modified: llvm/branches/release_38/test/CodeGen/Mips/cconv/return-struct.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/Mips/cconv/return-struct.ll?rev=271126&r1=271125&r2=271126&view=diff
==
--- llvm/branches/release_38/test/CodeGen/Mips/cconv/return-struct.ll (original)
+++ llvm/branches/release_38/test/CodeGen/Mips/cconv/return-struct.ll Sat May
28 11:11:08 2016
@@ -158,9 +158,6 @@ entry:
; sret pointer is already in $4
; N32-DAG:lui [[PTR_HI:\$[0-9]+]], %hi(struct_128xi16)
; N32-DAG:addiu [[PTR:\$[0-9]+]], [[PTR_HI]], %lo(struct_128xi16)
-; FIXME: This signext isn't necessary. Like integers, pointers are
-;but unlike integers, pointers cannot have the signext attribute.
-; N32-DAG:sll $5, [[PTR]], 0
; N32:jal memcpy
; sret pointer is already in $4
Modified: llvm/branches/release_38/test/CodeGen/Mips/fcopysign-f32-f64.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/Mips/fcopysign-f32-f64.ll?rev=271126&r1=271125&r2=271126&view=diff
==
--- llvm/branches/release_38/test/CodeGen/Mips/fcopysign-f32-f64.ll (original)
+++ llvm/branches/release_38/test/CodeGen/Mips/fcopysign-f32-f64.ll Sat May 28
11:11:08 2016
@@ -1,6 +1,9 @@
-; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s
-check-prefix=64
-; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s
-check-prefix=64
-; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s
-check-prefix=64R2
+; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | \
+; RUN:FileCheck %s -check-prefix=ALL -check-prefix=64
+; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | \
+; RUN:FileCheck %s -check-prefix=ALL -check-prefix=64
+; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | \
+; RUN:FileCheck %s -check-prefix=ALL -check-prefix=64R2
declare double @copysign(double, double) nounwind readnone
@@ -8,7 +11,8 @@ declare float @copysignf(float, float) n
define float @func2(float %d, double %f) nounwind readnone {
entry:
-; 64: func2
+; ALL-LABEL: func2:
+
; 64-DAG: lui $[[T0:[0-9]+]], 32767
; 64-DAG: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
; 64-DAG: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
@@ -30,17 +34,18 @@ entry:
define double @func3(double %d, float %f) nounwind readnone {
entry:
+; ALL-LABEL: func3:
-; 64: func3
-; 64-DAG: daddiu $[[T0:[0-9]+]], $zero, 1
-; 64-DAG: dsll $[[T1:[0-9]+]], $[[T0]], 63
-; 64-DAG: daddiu $[[MSK0:[0-9]+]], $[[T1]], -1
-; 64-DAG: and$[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
-; 64-DAG: srl$[[SRL:[0-9]+]], ${{[0-9]+}}, 31
-; 64-DAG: sll$[[SLL:[0-9]+]], $[[SRL]], 0
-; 64-DAG: dsll $[[DSLL:[0-9]+]], $[[SLL]], 63
-; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
-; 64: dmtc1 $[[OR]], $f0
+; 64-DAG: mfc1$[[MFC:[0-9]+]], $f13
+; 64-DAG: srl $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31
+; 64: dsll$[[DSLL:[0-9]+]], $[[SRL]], 63
+; 64-DAG: daddiu $[[R1:[0-9]+]], $zero, 1
+; 64-DAG: dsll$[[R2:[0-9]+]], $[[R1]], 63
+
[llvm-branch-commits] [llvm-branch] r271127 - Merging r263428:
Author: dsanders
Date: Sat May 28 11:11:58 2016
New Revision: 271127
URL: http://llvm.org/viewvc/llvm-project?rev=271127&view=rev
Log:
Merging r263428:
r263428 | zbuljan | 2016-03-14 12:50:23 + (Mon, 14 Mar 2016) | 3 lines
[mips] Fix an issue with long double when function roundl is defined
Differential Revision: http://reviews.llvm.org/D17760
Added:
llvm/branches/release_38/test/CodeGen/Mips/cconv/roundl-call.ll
Modified:
llvm/branches/release_38/lib/Target/Mips/MipsCCState.cpp
Modified: llvm/branches/release_38/lib/Target/Mips/MipsCCState.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/Mips/MipsCCState.cpp?rev=271127&r1=271126&r2=271127&view=diff
==
--- llvm/branches/release_38/lib/Target/Mips/MipsCCState.cpp (original)
+++ llvm/branches/release_38/lib/Target/Mips/MipsCCState.cpp Sat May 28
11:11:58 2016
@@ -26,8 +26,8 @@ static bool isF128SoftLibCall(const char
"ceill", "copysignl","cosl", "exp2l",
"expl", "floorl", "fmal", "fmodl",
"log10l","log2l","logl", "nearbyintl",
- "powl", "rintl","sinl", "sqrtl",
- "truncl"};
+ "powl", "rintl","roundl","sinl",
+ "sqrtl", "truncl"};
// Check that LibCalls is sorted alphabetically.
auto Comp = [](const char *S1, const char *S2) { return strcmp(S1, S2) < 0;
};
Added: llvm/branches/release_38/test/CodeGen/Mips/cconv/roundl-call.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/Mips/cconv/roundl-call.ll?rev=271127&view=auto
==
--- llvm/branches/release_38/test/CodeGen/Mips/cconv/roundl-call.ll (added)
+++ llvm/branches/release_38/test/CodeGen/Mips/cconv/roundl-call.ll Sat May 28
11:11:58 2016
@@ -0,0 +1,44 @@
+; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n32 < %s | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=N32 -check-prefix=HARD-FLOAT
+; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n32 < %s | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=N32 -check-prefix=HARD-FLOAT
+
+; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n64 < %s | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=N64 -check-prefix=HARD-FLOAT
+; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 < %s | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=N64 -check-prefix=HARD-FLOAT
+
+; RUN: llc -march=mips64 -mcpu=mips64 -mattr=+soft-float -target-abi=n32 < %s \
+; RUN: | FileCheck %s -check-prefix=ALL -check-prefix=N32 \
+; RUN:-check-prefix=SOFT-FLOAT
+; RUN: llc -march=mips64el -mcpu=mips64 -mattr=+soft-float -target-abi=n32 < \
+; RUN: %s | FileCheck %s -check-prefix=ALL -check-prefix=N32 \
+; RUN: -check-prefix=SOFT-FLOAT
+
+; RUN: llc -march=mips64 -mcpu=mips64 -mattr=+soft-float -target-abi=n64 < %s \
+; RUN: | FileCheck %s -check-prefix=ALL -check-prefix=N64 \
+; RUN:-check-prefix=SOFT-FLOAT
+; RUN: llc -march=mips64el -mcpu=mips64 -mattr=+soft-float -target-abi=n64 < \
+; RUN: %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 \
+; RUN: -check-prefix=SOFT-FLOAT
+
+@fp128 = global fp128 zeroinitializer
+
+define void @roundl_call(fp128 %value) {
+entry:
+; ALL-LABEL: roundl_call:
+; N32: lw $25, %call16(roundl)($gp)
+; N64: ld $25, %call16(roundl)($gp)
+
+; SOFT-FLOAT: sd $4, 8(${{[0-9]+}})
+; SOFT-FLOAT: sd $2, 0(${{[0-9]+}})
+
+; HARD-FLOAT: sdc1$f2, 8(${{[0-9]+}})
+; HARD-FLOAT: sdc1$f0, 0(${{[0-9]+}})
+
+ %call = call fp128 @roundl(fp128 %value)
+ store fp128 %call, fp128* @fp128
+ ret void
+}
+
+declare fp128 @roundl(fp128) nounwind readnone
___
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