[Lldb-commits] [PATCH] D62732: [RISCV] Add SystemV ABI

[Simon Cook via Phabricator via lldb-commits]

simoncook added a comment.
Herald added a subscriber: JDevlieghere.

Thanks for looking at this @luismarques We had planned to put more effort into 
this patch, but time got in the way for quite a lot, but I'm glad it's working; 
thanks for the rebase I'll update this to match shortly. And it's good that it 
looks like it's mostly working. I'm curious about your backtrace showing one 
frame, is that something without debug information, since the example I was 
using when writing this did show a backtrace back to main? It would be good to 
understand why that disn't produce the expected output.

As for next steps, if we're happy with the state then I think this should land 
(assuming qemu is sufficient given it is public), and then we can flesh out 
other bits which give a better experience. I'm not sure how to connect this to 
any automated testing, or where to document any way of checking this manually, 
the state of that isn't quite clear, so any clarity there helps.

Beyond this I think the next stage is implementing the parts for calling 
functions within a target, which if you could help with that would be great. I 
see that as a follow up patch to this, I don't see the two necessarily having 
to land together, since this part enables a useful debugging experience already.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62732/new/

https://reviews.llvm.org/D62732

___
lldb-commits mailing list
lldb-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [PATCH] D62732: [RISCV] Add SystemV ABI

[Simon Cook via Phabricator via lldb-commits]

simoncook updated this revision to Diff 286749.
simoncook added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62732/new/

https://reviews.llvm.org/D62732

Files:
  lldb/include/lldb/Utility/ArchSpec.h
  lldb/source/Plugins/ABI/CMakeLists.txt
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
  lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
  lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
  lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
  lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  lldb/source/Target/Platform.cpp
  lldb/source/Utility/ArchSpec.cpp

Index: lldb/source/Utility/ArchSpec.cpp
===
--- lldb/source/Utility/ArchSpec.cpp
+++ lldb/source/Utility/ArchSpec.cpp
@@ -212,6 +212,11 @@
 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
  ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"},
 
+{eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32,
+ ArchSpec::eCore_riscv32, "riscv32"},
+{eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64,
+ ArchSpec::eCore_riscv64, "riscv64"},
+
 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch,
  ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
@@ -452,6 +457,10 @@
  0xu, 0xu}, // ARC
 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE,
  0xu, 0xu}, // AVR
+{ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV, LLDB_INVALID_CPUTYPE,
+ 0xu, 0xu}, // riscv32
+{ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV, LLDB_INVALID_CPUTYPE,
+ 0xu, 0xu}, // riscv64
 };
 
 static const ArchDefinition g_elf_arch_def = {
Index: lldb/source/Target/Platform.cpp
===
--- lldb/source/Target/Platform.cpp
+++ lldb/source/Target/Platform.cpp
@@ -1951,6 +1951,20 @@
 trap_opcode_size = sizeof(g_i386_opcode);
   } break;
 
+  case llvm::Triple::riscv32:
+  case llvm::Triple::riscv64: {
+static const uint8_t g_riscv_c_opcode[] = {0x02, 0x90}; // c_ebreak
+static const uint8_t g_riscv_opcode[] = {0x73, 0x00, 0x10, 0x00}; // ebreak
+if (arch.GetFlags() & ArchSpec::eRISCV_arch_c) {
+  trap_opcode = g_riscv_c_opcode;
+  trap_opcode_size = sizeof(g_riscv_c_opcode);
+} else {
+  trap_opcode = g_riscv_opcode;
+  trap_opcode_size = sizeof(g_riscv_opcode);
+}
+break;
+  }
+
   default:
 return 0;
   }
Index: lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===
--- lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -1364,6 +1364,18 @@
   arch_spec.SetFlags(ArchSpec::eARM_abi_hard_float);
   }
 
+  if (arch_spec.GetMachine() == llvm::Triple::riscv32 ||
+  arch_spec.GetMachine() == llvm::Triple::riscv64) {
+if (header.e_flags & llvm::ELF::EF_RISCV_RVC)
+  arch_spec.SetFlags(ArchSpec::eRISCV_arch_c);
+if ((header.e_flags & llvm::ELF::EF_RISCV_FLOAT_ABI) ==
+llvm::ELF::EF_RISCV_FLOAT_ABI_SINGLE)
+  arch_spec.SetFlags(ArchSpec::eRISCV_abi_f);
+if ((header.e_flags & llvm::ELF::EF_RISCV_FLOAT_ABI) ==
+llvm::ELF::EF_RISCV_FLOAT_ABI_DOUBLE)
+  arch_spec.SetFlags(ArchSpec::eRISCV_abi_d);
+  }
+
   // If there are no section headers we are done.
   if (header.e_shnum == 0)
 return 0;
Index: lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
===
--- lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
+++ lldb/source/Plugins/Disassembler/LLVMC/DisassemblerLLVMC.cpp
@@ -1149,6 +1149,11 @@
 cpu = "apple-latest";
   }
 
+  // For RISC-V, enable all standard extensions so these can be disassembled.
+  if (triple.getArch() == llvm::Triple::riscv32 ||
+  triple.getArch() == llvm::Triple::riscv64)
+features_str += "+a,+c,+d,+f,+m";
+
   // We use m_disasm_up.get() to tell whether we are valid or not, so if this
   // isn't good for some reason, we won't be valid and FindPlugin will fail and
   // we won't get used.
Index: lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/CMakeLists.txt
@@ -0,0 +1,10 @@
+add_lldb_library(lldbPluginABISysV_riscv PLUGIN
+  ABISysV_riscv.cpp
+
+  LINK_LIBS
+lldbCore
+lldbSymbol
+lldbTarget
+  LINK_COMPONENTS
+Support
+  )
Index: lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
===
--- /dev/null
+++ lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.h
@@ -0,0 +1,116 @@
+//===-- ABISysV_riscv.h -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with 

[Lldb-commits] [PATCH] D62732: [WIP][RISCV] Initial port of LLDB for RISC-V

[Simon Cook via Phabricator via lldb-commits]

simoncook updated this revision to Diff 205287.
simoncook added a comment.

- Refactored register tables to match style used in i386/x86_64
- Add enum for RISC-V DWARF numbers
- Add F registers (assuming 32-bit, at runtime this seems to be overwritten to 
64-bit if D extension is provided)
- Add default unwind plan for first frame


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62732/new/

https://reviews.llvm.org/D62732

Files:
  lldb/include/lldb/Utility/ArchSpec.h
  lldb/source/API/SystemInitializerFull.cpp
  lldb/source/Plugins/ABI/CMakeLists.txt
  lldb/source/Plugins/ABI/SysV-riscv/ABISysV_riscv.cpp
  lldb/source/Plugins/ABI/SysV-riscv/ABISysV_riscv.h
  lldb/source/Plugins/ABI/SysV-riscv/CMakeLists.txt
  lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
  lldb/source/Target/Platform.cpp
  lldb/source/Target/Thread.cpp
  lldb/source/Utility/ArchSpec.cpp

Index: lldb/source/Utility/ArchSpec.cpp
===
--- lldb/source/Utility/ArchSpec.cpp
+++ lldb/source/Utility/ArchSpec.cpp
@@ -210,6 +210,11 @@
 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
  ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"},
 
+{eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32,
+ ArchSpec::eCore_riscv32, "riscv32"},
+{eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64,
+ ArchSpec::eCore_riscv64, "riscv64"},
+
 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch,
  ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
@@ -446,6 +451,10 @@
  ArchSpec::eMIPSSubType_mips64r6el, 0xu, 0xu}, // mips64r6el
 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON,
  LLDB_INVALID_CPUTYPE, 0xu, 0xu}, // HEXAGON
+{ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV, LLDB_INVALID_CPUTYPE,
+ 0xu, 0xu}, // riscv32
+{ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV, LLDB_INVALID_CPUTYPE,
+ 0xu, 0xu}, // riscv64
 };
 
 static const ArchDefinition g_elf_arch_def = {
Index: lldb/source/Target/Thread.cpp
===
--- lldb/source/Target/Thread.cpp
+++ lldb/source/Target/Thread.cpp
@@ -2070,6 +2070,8 @@
 case llvm::Triple::ppc:
 case llvm::Triple::ppc64:
 case llvm::Triple::ppc64le:
+case llvm::Triple::riscv32:
+case llvm::Triple::riscv64:
 case llvm::Triple::systemz:
 case llvm::Triple::hexagon:
   m_unwinder_up.reset(new UnwindLLDB(*this));
Index: lldb/source/Target/Platform.cpp
===
--- lldb/source/Target/Platform.cpp
+++ lldb/source/Target/Platform.cpp
@@ -1911,6 +1911,15 @@
 trap_opcode_size = sizeof(g_i386_opcode);
   } break;
 
+  case llvm::Triple::riscv32:
+  case llvm::Triple::riscv64: {
+// TODO: Use ebreak when c_ebreak is not available.
+static const uint8_t g_riscv_c_opcode[] = {0x02, 0x90}; // c_ebreak
+trap_opcode = g_riscv_c_opcode;
+trap_opcode_size = sizeof(g_riscv_c_opcode);
+break;
+  }
+
   default:
 llvm_unreachable(
 "Unhandled architecture in Platform::GetSoftwareBreakpointTrapOpcode");
Index: lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
===
--- lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
+++ lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
@@ -1198,6 +1198,11 @@
 cpu = "apple-latest";
   }
 
+  // For RISC-V, enable all standard extensions so these can be disassembled.
+  if (triple.getArch() == llvm::Triple::riscv32 ||
+  triple.getArch() == llvm::Triple::riscv64)
+features_str += "+a,+c,+d,+f,+m";
+
   // We use m_disasm_up.get() to tell whether we are valid or not, so if this
   // isn't good for some reason, we won't be valid and FindPlugin will fail and
   // we won't get used.
Index: lldb/source/Plugins/ABI/SysV-riscv/CMakeLists.txt
===
--- /dev/null
+++ lldb/source/Plugins/ABI/SysV-riscv/CMakeLists.txt
@@ -0,0 +1,10 @@
+add_lldb_library(lldbPluginABISysV_riscv PLUGIN
+  ABISysV_riscv.cpp
+
+  LINK_LIBS
+lldbCore
+lldbSymbol
+lldbTarget
+  LINK_COMPONENTS
+Support
+  )
Index: lldb/source/Plugins/ABI/SysV-riscv/ABISysV_riscv.h
===
--- /dev/null
+++ lldb/source/Plugins/ABI/SysV-riscv/ABISysV_riscv.h
@@ -0,0 +1,108 @@
+//===-- ABISysV_riscv.h -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef lib

[Lldb-commits] [PATCH] D62732: [RISCV] Add SystemV ABI

[Simon Cook via Phabricator via lldb-commits]

simoncook updated this revision to Diff 225998.
simoncook retitled this revision from "[WIP][RISCV] Initial port of LLDB for 
RISC-V" to "[RISCV] Add SystemV ABI".
simoncook edited the summary of this revision.
simoncook added a comment.
Herald added subscribers: pzheng, s.egerton, lenary, arichardson, emaste.
Herald added a reviewer: espindola.

Rebase, implement all hooks that aren't PrepareTrivialCall/function calling 
related. If its possible to commit these two separately, I think it would be 
best to have that as a separate patch whereby preparing arguments for the 
various RISC-V hard-float ABIs can be done independently of 
breakpoints/unwinding/etc.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62732/new/

https://reviews.llvm.org/D62732

Files:
  lldb/include/lldb/Utility/ArchSpec.h
  lldb/source/API/SystemInitializerFull.cpp
  lldb/source/Plugins/ABI/CMakeLists.txt
  lldb/source/Plugins/ABI/SysV-riscv/ABISysV_riscv.cpp
  lldb/source/Plugins/ABI/SysV-riscv/ABISysV_riscv.h
  lldb/source/Plugins/ABI/SysV-riscv/CMakeLists.txt
  lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
  lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
  lldb/source/Target/Platform.cpp
  lldb/source/Target/Thread.cpp
  lldb/source/Utility/ArchSpec.cpp

Index: lldb/source/Utility/ArchSpec.cpp
===
--- lldb/source/Utility/ArchSpec.cpp
+++ lldb/source/Utility/ArchSpec.cpp
@@ -212,6 +212,11 @@
 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
  ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"},
 
+{eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32,
+ ArchSpec::eCore_riscv32, "riscv32"},
+{eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64,
+ ArchSpec::eCore_riscv64, "riscv64"},
+
 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch,
  ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
@@ -445,6 +450,10 @@
  LLDB_INVALID_CPUTYPE, 0xu, 0xu}, // HEXAGON
 {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE,
  0xu, 0xu }, // ARC
+{ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV, LLDB_INVALID_CPUTYPE,
+ 0xu, 0xu}, // riscv32
+{ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV, LLDB_INVALID_CPUTYPE,
+ 0xu, 0xu}, // riscv64
 };
 
 static const ArchDefinition g_elf_arch_def = {
Index: lldb/source/Target/Thread.cpp
===
--- lldb/source/Target/Thread.cpp
+++ lldb/source/Target/Thread.cpp
@@ -2059,6 +2059,8 @@
 case llvm::Triple::ppc:
 case llvm::Triple::ppc64:
 case llvm::Triple::ppc64le:
+case llvm::Triple::riscv32:
+case llvm::Triple::riscv64:
 case llvm::Triple::systemz:
 case llvm::Triple::hexagon:
 case llvm::Triple::arc:
Index: lldb/source/Target/Platform.cpp
===
--- lldb/source/Target/Platform.cpp
+++ lldb/source/Target/Platform.cpp
@@ -1901,6 +1901,20 @@
 trap_opcode_size = sizeof(g_i386_opcode);
   } break;
 
+  case llvm::Triple::riscv32:
+  case llvm::Triple::riscv64: {
+static const uint8_t g_riscv_c_opcode[] = {0x02, 0x90}; // c_ebreak
+static const uint8_t g_riscv_opcode[] = {0x73, 0x00, 0x10, 0x00}; // ebreak
+if (arch.GetFlags() & ArchSpec::eRISCV_supports_rvc) {
+  trap_opcode = g_riscv_c_opcode;
+  trap_opcode_size = sizeof(g_riscv_c_opcode);
+} else {
+  trap_opcode = g_riscv_opcode;
+  trap_opcode_size = sizeof(g_riscv_opcode);
+}
+break;
+  }
+
   default:
 llvm_unreachable(
 "Unhandled architecture in Platform::GetSoftwareBreakpointTrapOpcode");
Index: lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===
--- lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -1360,6 +1360,18 @@
   arch_spec.SetFlags(ArchSpec::eARM_abi_hard_float);
   }
 
+  if (arch_spec.GetMachine() == llvm::Triple::riscv32 ||
+  arch_spec.GetMachine() == llvm::Triple::riscv64) {
+if (header.e_flags & llvm::ELF::EF_RISCV_RVC)
+  arch_spec.SetFlags(ArchSpec::eRISCV_supports_rvc);
+if ((header.e_flags & llvm::ELF::EF_RISCV_FLOAT_ABI) ==
+llvm::ELF::EF_RISCV_FLOAT_ABI_SINGLE)
+  arch_spec.SetFlags(ArchSpec::eRISCV_abi_single_float);
+if ((header.e_flags & llvm::ELF::EF_RISCV_FLOAT_ABI) ==
+llvm::ELF::EF_RISCV_FLOAT_ABI_DOUBLE)
+  arch_spec.SetFlags(ArchSpec::eRISCV_abi_double_float);
+  }
+
   // If there are no section headers we are done.
   if (header.e_shnum == 0)
 return 0;
Index: lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
===
--- lldb/source/Plugins/Disassembler/llv

[Lldb-commits] [PATCH] D62732: [WIP][RISCV] Initial port of LLDB for RISC-V

[Simon Cook via Phabricator via lldb-commits]

simoncook created this revision.
simoncook added reviewers: asb, lewis-revill.
Herald added subscribers: benna, psnobl, jocewei, PkmX, rkruppe, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, 
kito-cheng, niosHD, sabuasal, apazos, johnrusso, rbar, mgorny.
Herald added a project: LLDB.

This is the start of a LLDB port for both 32 and 64-bit RISC-V, implementing 
the components needed in order to get basic functionality working with our 
embedded debug server.

Currently the following things are working:

- RV32I/RV64I base registers
- breakpoints (assumes C extension is enabled)
- frame unwinding (if binary has CFI information)
- continue/step
- disassembly

Currently calling functions via the command line and disassembly based frame 
unwind is not yet implemented. I haven't yet looked at what tests should be 
implemented alongside this patch.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D62732

Files:
  lldb/include/lldb/Utility/ArchSpec.h
  lldb/source/API/SystemInitializerFull.cpp
  lldb/source/Plugins/ABI/CMakeLists.txt
  lldb/source/Plugins/ABI/SysV-riscv/ABISysV_riscv.cpp
  lldb/source/Plugins/ABI/SysV-riscv/ABISysV_riscv.h
  lldb/source/Plugins/ABI/SysV-riscv/CMakeLists.txt
  lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
  lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
  lldb/source/Target/Platform.cpp
  lldb/source/Target/Thread.cpp
  lldb/source/Utility/ArchSpec.cpp

Index: lldb/source/Utility/ArchSpec.cpp
===
--- lldb/source/Utility/ArchSpec.cpp
+++ lldb/source/Utility/ArchSpec.cpp
@@ -210,6 +210,11 @@
 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
  ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"},
 
+{eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32,
+ ArchSpec::eCore_riscv32, "riscv32"},
+{eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64,
+ ArchSpec::eCore_riscv64, "riscv64"},
+
 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch,
  ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
@@ -446,6 +451,10 @@
  ArchSpec::eMIPSSubType_mips64r6el, 0xu, 0xu}, // mips64r6el
 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON,
  LLDB_INVALID_CPUTYPE, 0xu, 0xu}, // HEXAGON
+{ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV, LLDB_INVALID_CPUTYPE,
+ 0xu, 0xu}, // riscv32
+{ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV, LLDB_INVALID_CPUTYPE,
+ 0xu, 0xu}, // riscv64
 };
 
 static const ArchDefinition g_elf_arch_def = {
Index: lldb/source/Target/Thread.cpp
===
--- lldb/source/Target/Thread.cpp
+++ lldb/source/Target/Thread.cpp
@@ -2070,6 +2070,8 @@
 case llvm::Triple::ppc:
 case llvm::Triple::ppc64:
 case llvm::Triple::ppc64le:
+case llvm::Triple::riscv32:
+case llvm::Triple::riscv64:
 case llvm::Triple::systemz:
 case llvm::Triple::hexagon:
   m_unwinder_up.reset(new UnwindLLDB(*this));
Index: lldb/source/Target/Platform.cpp
===
--- lldb/source/Target/Platform.cpp
+++ lldb/source/Target/Platform.cpp
@@ -1911,6 +1911,15 @@
 trap_opcode_size = sizeof(g_i386_opcode);
   } break;
 
+  case llvm::Triple::riscv32:
+  case llvm::Triple::riscv64: {
+// FIXME: Use ebreak when c_ebreak is not available.
+static const uint8_t g_riscv_c_opcode[] = {0x02, 0x90}; // c_ebreak
+trap_opcode = g_riscv_c_opcode;
+trap_opcode_size = sizeof(g_riscv_c_opcode);
+break;
+  }
+
   default:
 llvm_unreachable(
 "Unhandled architecture in Platform::GetSoftwareBreakpointTrapOpcode");
Index: lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
===
--- lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
+++ lldb/source/Plugins/Process/Utility/DynamicRegisterInfo.cpp
@@ -621,6 +621,18 @@
   }
   break;
 
+case llvm::Triple::riscv32:
+case llvm::Triple::riscv64:
+  for (auto ® : m_regs) {
+if (strcmp(reg.name, "x1") == 0)
+  reg.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA;
+else if (strcmp(reg.name, "x2") == 0)
+  reg.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP;
+else if (strcmp(reg.name, "pc") == 0)
+  reg.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC;
+  }
+  break;
+
 default:
   break;
 }
Index: lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
===
--- lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
+++ lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
@@ -1198,6 +1198,11 @@
 cpu = "apple-latest";
   }
 
+  // For RISC-V, ena