[Lldb-commits] [lldb] r249020 - [LLDB][MIPS] Fix gp register value for o32 applications on 64-bit target

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Thu Oct  1 10:05:31 2015
New Revision: 249020

URL: http://llvm.org/viewvc/llvm-project?rev=249020&view=rev
Log:
[LLDB][MIPS] Fix gp register value for o32 applications on 64-bit target

GP registers for o32 applications were always giving zero value because 
SetType() on the RegisterValue was causing the accessor functions to pickup the 
value from m_scalar of RegisterValue which is zero.
In this patch byte size and byte order of register value is set at the time of 
setting the value of the register.


Modified:
lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp

Modified: lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp?rev=249020&r1=249019&r2=249020&view=diff
==
--- lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp (original)
+++ lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp Thu Oct  1 
10:05:31 2015
@@ -2206,6 +2206,8 @@ ObjectFileELF::ParseSymbols (Symtab *sym
 mangled.SetDemangledName( ConstString((demangled_name + 
suffix).str()) );
 }
 
+printf("Symbol: name=%s, Type:%d value=%08lx\n", symbol_name, 
symbol_type, symbol.st_value);
+
 Symbol dc_symbol(
 i + start_id,   // ID is the original symbol table index.
 mangled,

Modified: 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp?rev=249020&r1=249019&r2=249020&view=diff
==
--- 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp 
(original)
+++ 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp 
Thu Oct  1 10:05:31 2015
@@ -623,13 +623,6 @@ NativeRegisterContextLinux_mips64::ReadR
 else
 {
 error = ReadRegisterRaw(reg, reg_value);
-if (error.Success())
-{
-// If our return byte size was greater than the return value reg 
size, then
-// use the type specified by reg_info rather than the uint64_t 
default
-if (reg_value.GetByteSize() > reg_info->byte_size)
-reg_value.SetType(reg_info);
-}
 }
 
 return error;
@@ -1387,7 +1380,7 @@ NativeRegisterContextLinux_mips64::DoRea
 {
 lldb_private::ArchSpec arch;
 if (m_thread.GetProcess()->GetArchitecture(arch))
-value.SetBytes((void *)(((unsigned char *)(®s)) + offset), 8, 
arch.GetByteOrder());
+value.SetBytes((void *)(((unsigned char *)®s) + offset + 4 * 
(arch.GetMachine() == llvm::Triple::mips)), arch.GetAddressByteSize(), 
arch.GetByteOrder());
 else
 error.SetErrorString("failed to get architecture");
 }


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[Lldb-commits] [lldb] r249021 - Romove accidentially added statement in r249020

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Thu Oct  1 10:15:42 2015
New Revision: 249021

URL: http://llvm.org/viewvc/llvm-project?rev=249021&view=rev
Log:
Romove accidentially added statement in r249020

Modified:
lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp

Modified: lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp?rev=249021&r1=249020&r2=249021&view=diff
==
--- lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp (original)
+++ lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp Thu Oct  1 
10:15:42 2015
@@ -2206,8 +2206,6 @@ ObjectFileELF::ParseSymbols (Symtab *sym
 mangled.SetDemangledName( ConstString((demangled_name + 
suffix).str()) );
 }
 
-printf("Symbol: name=%s, Type:%d value=%08lx\n", symbol_name, 
symbol_type, symbol.st_value);
-
 Symbol dc_symbol(
 i + start_id,   // ID is the original symbol table index.
 mangled,


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[Lldb-commits] [lldb] r250696 - [LLDB][MIPS] Use the correct ptrace buffer for writing register value for o32 applications

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Mon Oct 19 06:21:20 2015
New Revision: 250696

URL: http://llvm.org/viewvc/llvm-project?rev=250696&view=rev
Log:
[LLDB][MIPS] Use the correct ptrace buffer for writing register value for o32 
applications

For o32 applications on mips we were getting segmentation fault while launching 
lldb-server because of overwritting stack when using elf_gregset_t in 
DoWriteRegisterValue.
We are now using the GPR_mips_linux buffer in DoWriteRegisterValue as done in 
DoReadRegisterValue also, which solves the above issue.


Modified:

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp

Modified: 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp?rev=250696&r1=250695&r2=250696&view=diff
==
--- 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp 
(original)
+++ 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp 
Mon Oct 19 06:21:20 2015
@@ -927,7 +927,7 @@ GetWatchHi (struct pt_watch_regs *regs,
 return regs->mips32.watchhi[index];
 else if (regs->style == pt_watch_style_mips64)
 return regs->mips64.watchhi[index];
-else
+if(log)
 log->Printf("Invalid watch register style");
 return 0;
 }
@@ -940,7 +940,7 @@ SetWatchHi (struct pt_watch_regs *regs,
 regs->mips32.watchhi[index] = value;
 else if (regs->style == pt_watch_style_mips64)
 regs->mips64.watchhi[index] = value;
-else
+if(log)
 log->Printf("Invalid watch register style");
 return;
 }
@@ -953,7 +953,7 @@ GetWatchLo (struct pt_watch_regs *regs,
 return regs->mips32.watchlo[index];
 else if (regs->style == pt_watch_style_mips64)
 return regs->mips64.watchlo[index];
-else
+if(log)
 log->Printf("Invalid watch register style");
 return LLDB_INVALID_ADDRESS;
 }
@@ -966,7 +966,7 @@ SetWatchLo (struct pt_watch_regs *regs,
 regs->mips32.watchlo[index] = (uint32_t) value;
 else if (regs->style == pt_watch_style_mips64)
 regs->mips64.watchlo[index] = value;
-else
+if(log)
 log->Printf("Invalid watch register style");
 return;
 }
@@ -979,7 +979,7 @@ GetIRWMask (struct pt_watch_regs *regs,
 return regs->mips32.watch_masks[index] & IRW;
 else if (regs->style == pt_watch_style_mips64)
 return regs->mips64.watch_masks[index] & IRW;
-else
+if(log)
 log->Printf("Invalid watch register style");
 return 0;
 }
@@ -992,7 +992,7 @@ GetRegMask (struct pt_watch_regs *regs,
 return regs->mips32.watch_masks[index] & ~IRW;
 else if (regs->style == pt_watch_style_mips64)
 return regs->mips64.watch_masks[index] & ~IRW;
-else
+if(log)
 log->Printf("Invalid watch register style");
 return 0;
 }
@@ -1361,7 +1361,8 @@ NativeRegisterContextLinux_mips64::NumSu
 num_valid = regs.mips64.num_valid;
 return num_valid;
 default:
-log->Printf("NativeRegisterContextLinux_mips64::%s Error: 
Unrecognized watch register style", __FUNCTION__);
+if(log)
+log->Printf("NativeRegisterContextLinux_mips64::%s Error: 
Unrecognized watch register style", __FUNCTION__);
 }
 return 0;
 }
@@ -1392,7 +1393,7 @@ NativeRegisterContextLinux_mips64::DoWri
 const char* reg_name,
 const RegisterValue 
&value)
 {
-elf_gregset_t regs;
+GPR_linux_mips regs;
 Error error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGS, 
m_thread.GetID(), NULL, ®s, sizeof regs);
 if (error.Success())
 {


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[Lldb-commits] [PATCH] D14633: [LLDB][MIPS] Clear bug 25194 - LLDB-Server Assertion raised when single stepping on MIPS

[Sagar Thakur via lldb-commits]

sagar created this revision.
sagar added reviewers: clayborg, tberghammer.
sagar added subscribers: nitesh.jain, jaydeep, bhushan, mohit.bhakkad, 
lldb-commits.
sagar set the repository for this revision to rL LLVM.
Herald added a subscriber: dsanders.

This patch will clear bug 25194 - LLDB-Server Assertion raised when single 
stepping on MIPS. The problem was that while emulating instructions, old and 
new pc values would have garbage value in their upper 32 bits. Therefore 
checking if pc was changed (old_pc == new_pc) would always return false, 
because of which pc was not getting updated.

>/* If we haven't changed the PC, change it here */
>if (old_pc == new_pc)
>{
>new_pc += 4;
>Context context;
>if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, 
> >dwarf_pc_mips, new_pc))
>return false;
>}


Repository:
  rL LLVM

http://reviews.llvm.org/D14633

Files:
  source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
  source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h

Index: source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
===
--- source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
+++ source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
@@ -80,6 +80,12 @@
 return SupportsEmulatingInstructionsOfTypeStatic (inst_type);
 }
 
+uint32_t
+ReadRegisterUnsigned (lldb::RegisterKind reg_kind,
+  uint32_t reg_num,
+  uint32_t fail_value, 
+  bool *success_ptr);
+
 bool
 ReadInstruction () override;
 
Index: source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
===
--- source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
+++ source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
@@ -760,6 +760,20 @@
 return false;
 }
 
+uint32_t
+EmulateInstructionMIPS::ReadRegisterUnsigned (lldb::RegisterKind reg_kind,
+  uint32_t reg_num,
+  uint32_t fail_value, 
+  bool *success_ptr)
+{
+RegisterValue reg_value;
+if (ReadRegister (reg_kind, reg_num, reg_value))
+return reg_value.GetAsUInt32(fail_value, success_ptr);
+if (success_ptr)
+*success_ptr = false;
+return fail_value;
+}
+
 bool 
 EmulateInstructionMIPS::ReadInstruction ()
 {
@@ -817,7 +831,7 @@
 if (opcode_data == NULL)
 return false;
 
-uint64_t old_pc = 0, new_pc = 0;
+uint32_t old_pc = 0, new_pc = 0;
 const bool auto_advance_pc = evaluate_options & 
eEmulateInstructionOptionAutoAdvancePC;
 
 if (auto_advance_pc)


Index: source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
===
--- source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
+++ source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h
@@ -80,6 +80,12 @@
 return SupportsEmulatingInstructionsOfTypeStatic (inst_type);
 }
 
+uint32_t
+ReadRegisterUnsigned (lldb::RegisterKind reg_kind,
+  uint32_t reg_num,
+  uint32_t fail_value, 
+  bool *success_ptr);
+
 bool
 ReadInstruction () override;
 
Index: source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
===
--- source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
+++ source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
@@ -760,6 +760,20 @@
 return false;
 }
 
+uint32_t
+EmulateInstructionMIPS::ReadRegisterUnsigned (lldb::RegisterKind reg_kind,
+  uint32_t reg_num,
+  uint32_t fail_value, 
+  bool *success_ptr)
+{
+RegisterValue reg_value;
+if (ReadRegister (reg_kind, reg_num, reg_value))
+return reg_value.GetAsUInt32(fail_value, success_ptr);
+if (success_ptr)
+*success_ptr = false;
+return fail_value;
+}
+
 bool 
 EmulateInstructionMIPS::ReadInstruction ()
 {
@@ -817,7 +831,7 @@
 if (opcode_data == NULL)
 return false;
 
-uint64_t old_pc = 0, new_pc = 0;
+uint32_t old_pc = 0, new_pc = 0;
 const bool auto_advance_pc = evaluate_options & eEmulateInstructionOptionAutoAdvancePC;
 
 if (auto_advance_pc)
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Re: [Lldb-commits] [PATCH] D14633: [LLDB][MIPS] Clear bug 25194 - LLDB-Server Assertion raised when single stepping on MIPS

[Sagar Thakur via lldb-commits]

sagar updated this revision to Diff 40256.
sagar added a comment.

Addressed review comments.


Repository:
  rL LLVM

http://reviews.llvm.org/D14633

Files:
  source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp

Index: source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
===
--- source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
+++ source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
@@ -1375,7 +1375,11 @@
RegisterValue &value)
 {
 GPR_linux_mips regs;
+lldb_private::ArchSpec arch;
 ::memset(®s, 0, sizeof(GPR_linux_mips));
+
+// Clear all bits in RegisterValue before writing actual value read from 
ptrace to avoid garbage value in 32-bit MSB 
+value.SetBytes((void *)(((unsigned char *)®s) + offset), 8, 
arch.GetByteOrder());
 Error error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGS, 
m_thread.GetID(), NULL, ®s, sizeof regs);
 if (error.Success())
 {


Index: source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
===
--- source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
+++ source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
@@ -1375,7 +1375,11 @@
RegisterValue &value)
 {
 GPR_linux_mips regs;
+lldb_private::ArchSpec arch;
 ::memset(®s, 0, sizeof(GPR_linux_mips));
+
+// Clear all bits in RegisterValue before writing actual value read from ptrace to avoid garbage value in 32-bit MSB 
+value.SetBytes((void *)(((unsigned char *)®s) + offset), 8, arch.GetByteOrder());
 Error error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGS, m_thread.GetID(), NULL, ®s, sizeof regs);
 if (error.Success())
 {
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Re: [Lldb-commits] [PATCH] D14633: [LLDB][MIPS] Clear bug 25194 - LLDB-Server Assertion raised when single stepping on MIPS

[Sagar Thakur via lldb-commits]

sagar added a comment.

> Admittedly it's a bit unintuitive for an unsigned 32-bit value from a MIPS32 
> binary to be represented in a 64-bit register as, for example, 
> 0x8000 but the debugger shouldn't normally admit to the existence 
> of the extra bits when debugging 32-bit code so the user won't normally see 
> this.


In case of MIPS32 the 0x value in 32 MSB will always be truncated out 
of RegisterValue, since SetBytes() will only write lower 4 bytes of the value 
into RegisterValue. The problem here is that RegisterValue initially contains 
garbage value. Therefore clearing all bits in RegisterValue before writing 
actual 32-bit value solves the problem.


Repository:
  rL LLVM

http://reviews.llvm.org/D14633



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Re: [Lldb-commits] [PATCH] D14633: [LLDB][MIPS] Clear bug 25194 - LLDB-Server Assertion raised when single stepping on MIPS

[Sagar Thakur via lldb-commits]

sagar added a comment.

Hi @tberghammer,

I tried using RegisterValue::SetUInt() instead of RegisterValue::SetBytes(). 
When using RegisterValue::SetUInt() all register values we get are zero in case 
of mips32 big endian machine. The 
GDBRemoteCommunicationServerLLGS::SendStopReplyPacketForThread() and 
GDBRemoteCommunicationServerLLGS::Handle_p() function implementations retrieve 
a pointer to register value by calling RegisterValue::GetBytes() which in turn 
retrieves a pointer to value from Scalar::GetBytes() in cases if type of 
RegisterValue is eTypeUInt*. But Scalar::GetBytes() does not seem to handle 
endianness correctly. As a workaround I made RegisterValue::GetBytes() retrieve 
the pointer to register value from its bytes buffer for all cases and also 
called SetBytes from RegisterValue::SetUInt() like this :

> diff --git a/source/Core/RegisterValue.cpp b/source/Core/RegisterValue.cpp

> index d4ba998..ec8bfb8 100644

> --- a/source/Core/RegisterValue.cpp

> +++ b/source/Core/RegisterValue.cpp

> @@ -822,7 +822,7 @@ RegisterValue::GetBytes () const

>  case eTypeUInt128:

>  case eTypeFloat:

>  case eTypeDouble:

> -case eTypeLongDouble:   return m_scalar.GetBytes();

> +case eTypeLongDouble:

>  case eTypeBytes:return buffer.bytes;

>  }

>  return NULL;

> @@ -841,7 +841,7 @@ RegisterValue::GetBytes ()

>  case eTypeUInt128:

>  case eTypeFloat:

>  case eTypeDouble:

> -case eTypeLongDouble:   return m_scalar.GetBytes();

> +case eTypeLongDouble:

>  case eTypeBytes:return buffer.bytes;

>  }

>  return NULL;

> @@ -896,6 +896,7 @@ RegisterValue::SetUInt (uint64_t uint, uint32_t byte_size)

>  }

>  else

>  return false;

> +SetBytes (&uint, byte_size, GetByteOrder());

>  return true;

>  }


If this looks good I will submit a separate patch for the same.
Should we use the above mentioned workaround or use RegisterValue::SetBytes as 
before? Kindly let me know if you have any other suggestions.

Regards,
Sagar


Repository:
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http://reviews.llvm.org/D14633



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[Lldb-commits] [lldb] r253444 - [MIPS][LLDB]Fix TestBreakpointCondition.py for MIPS

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Wed Nov 18 02:12:34 2015
New Revision: 253444

URL: http://llvm.org/viewvc/llvm-project?rev=253444&view=rev
Log:
[MIPS][LLDB]Fix TestBreakpointCondition.py for MIPS

Patch by Nitesh Jain

Summary: The self.getArchitecture() returns the architecture based on the value 
of -A flag passed to dotest.py script.
There are many possible values for MIPS to this option (like mips32r2, 
mips32r6, mips64, mips64r2, ).
This patch uses re.match(mips,arch) to check if architecture string starts with 
mips.

Subscribers: lldb-commits, mohit.bhakkad, sagar, bhushan, jaydeep
Reviewers: clayborg, ovyalov
Differential: http://reviews.llvm.org/D14493

Modified:

lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_conditions/TestBreakpointConditions.py

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_conditions/TestBreakpointConditions.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_conditions/TestBreakpointConditions.py?rev=253444&r1=253443&r2=253444&view=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_conditions/TestBreakpointConditions.py
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/breakpoint/breakpoint_conditions/TestBreakpointConditions.py
 Wed Nov 18 02:12:34 2015
@@ -103,12 +103,15 @@ class BreakpointConditionsTestCase(TestB
 self.runCmd("breakpoint disable")
 
 self.runCmd("breakpoint set -p Loop")
-if self.getArchitecture() in ['x86_64', 'i386']:
+arch = self.getArchitecture()
+if arch in ['x86_64', 'i386']:
 self.runCmd("breakpoint modify -c ($eax&&i)")
-elif self.getArchitecture() in ['aarch64']:
+elif arch in ['aarch64']:
 self.runCmd("breakpoint modify -c ($x1&&i)")
-elif self.getArchitecture() in ['arm']:
+elif arch in ['arm']:
 self.runCmd("breakpoint modify -c ($r0&&i)")
+elif re.match("mips",arch):
+self.runCmd("breakpoint modify -c ($r2&&i)")
 self.runCmd("run")
 
 self.expect("process status", PROCESS_STOPPED,


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Re: [Lldb-commits] [PATCH] D14493: [MIPS][LLDB]Fix TestBreakpointCondition.py for MIPS

[Sagar Thakur via lldb-commits]

sagar closed this revision.
sagar added a comment.

Committed in r253444 on behalf of @nitesh.jain


Repository:
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[Lldb-commits] [lldb] r253445 - [LLDB][MIPS] Fix TestDisassembleBreakpoint.py for MIPS

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Wed Nov 18 02:18:03 2015
New Revision: 253445

URL: http://llvm.org/viewvc/llvm-project?rev=253445&view=rev
Log:
[LLDB][MIPS] Fix TestDisassembleBreakpoint.py for MIPS

Patch by Nitesh Jain

Summary: The break is opcode for breakpoint instruction.

Subscribers: lldb-commits, mohit.bhakkad, sagar, bhushan
Reviewers: clayborg, ovyalov, jaydeep
Differential: http://reviews.llvm.org/D14634

Modified:

lldb/trunk/packages/Python/lldbsuite/test/functionalities/disassembly/TestDisassembleBreakpoint.py

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/disassembly/TestDisassembleBreakpoint.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/disassembly/TestDisassembleBreakpoint.py?rev=253445&r1=253444&r2=253445&view=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/disassembly/TestDisassembleBreakpoint.py
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/disassembly/TestDisassembleBreakpoint.py
 Wed Nov 18 02:18:03 2015
@@ -32,12 +32,16 @@ class DisassemblyTestCase(TestBase):
 disassembly = self.res.GetOutput()
 
 # ARCH, if not specified, defaults to x86_64.
-if self.getArchitecture() in ["", 'x86_64', 'i386', 'i686']:
+arch = self.getArchitecture()
+if arch in ["", 'x86_64', 'i386', 'i686']:
 breakpoint_opcodes = ["int3"]
 instructions = [' mov', ' addl ', 'ret']
-elif self.getArchitecture() in ["arm", "aarch64"]:
+elif arch in ["arm", "aarch64"]:
 breakpoint_opcodes = ["brk", "udf"]
 instructions = [' add ', ' ldr ', ' str ']
+elif re.match("mips" , arch):
+breakpoint_opcodes = ["break"]
+instructions = ['lw', 'sw', 'jr']
 else:
 # TODO please add your arch here
 self.fail('unimplemented for arch = 
"{arch}"'.format(arch=self.getArchitecture()))


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Re: [Lldb-commits] [PATCH] D14634: [LLDB][MIPS] Fix TestDisassembleBreakpoint.py for MIPS

[Sagar Thakur via lldb-commits]

sagar added a comment.

Committed in r253445 on behalf of @nitesh.jain


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http://reviews.llvm.org/D14634



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Re: [Lldb-commits] [PATCH] D14633: [LLDB][MIPS] Clear bug 25194 - LLDB-Server Assertion raised when single stepping on MIPS

[Sagar Thakur via lldb-commits]

sagar added a comment.

Hi,

@tberghammer : For both mips32 and mips64 big endian 'T' packet response 
contains the register values in target byte order only. But for mips32 big 
endian when we set the value of the register in RegisterValue using 
RegisterValue::SetUInt() the upper half of the container in RegisterValue 
contains zero value and the lower half contains the actual value. And when we 
fetch a pointer to the container in RegisterValue using 
RegisterValue::GetBytes() we get the start address of upper half of the 
container. Therefore while constructing 'T' packet response the function 
AppendHexValue() in GDBRemoteCommunicationServerLLGS.cpp called from 
WriteRegisterValueInHexFixedWidth() will read only the next 4 bytes it sees 
which are all zero. Therefore we get zero values for all registers at the 
client side:

> <   5> send packet: $?#3f

> < 680> read packet:

> $T17thread:774d;name:step_32eb.elf;threads:774d;jstopinfo:5b7b226e616d65223a22737465705f333265622e656c66222c22726561736f6e223a227369676e616c222c227369676e616c223a32332c22746964223a33303534317d5d;

> 00:;01:;02:;03:;04:;05:;06:;07:;08:;09:;

> 0a:;0b:;0c:;0d:;0e:;0f:;10:;11:;12:;13:;

> 14:;15:;16:;17:;18:;19:;1a:;1b:;1c:;1d:;

> 1e:;1f:;20:;21:;22:;23:;24:;25:;26:;reason:signal;#47


@clayborg: After this change will submit a separate patch to read all GPRs in a 
single call for once and then extract the register value as needed in the MIPS 
register context.

Regards,
Sagar


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[Lldb-commits] [lldb] r253555 - [LLDB][MIPS] Fix lldbplatformutil.py Failure

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Thu Nov 19 05:01:21 2015
New Revision: 253555

URL: http://llvm.org/viewvc/llvm-project?rev=253555&view=rev
Log:
[LLDB][MIPS] Fix lldbplatformutil.py Failure

Patch by Nitesh Jain

Summary: This patch check whether first register is readable.

Subscribers: lldb-commits, mohit.bhakkad, sagar, bhushan
Reviewers: clayborg, ovyalov, jaydeep
Differential: http://reviews.llvm.org/D14635

Modified:
lldb/trunk/packages/Python/lldbsuite/test/lldbplatformutil.py

Modified: lldb/trunk/packages/Python/lldbsuite/test/lldbplatformutil.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/lldbplatformutil.py?rev=253555&r1=253554&r2=253555&view=diff
==
--- lldb/trunk/packages/Python/lldbsuite/test/lldbplatformutil.py (original)
+++ lldb/trunk/packages/Python/lldbsuite/test/lldbplatformutil.py Thu Nov 19 
05:01:21 2015
@@ -9,13 +9,19 @@ from __future__ import absolute_import
 
 # LLDB modules
 
+import re
+
 def check_first_register_readable(test_case):
-if test_case.getArchitecture() in ['x86_64', 'i386']:
+arch = test_case.getArchitecture()
+
+if arch in ['x86_64', 'i386']:
 test_case.expect("register read eax", substrs = ['eax = 0x'])
-elif test_case.getArchitecture() in ['arm']:
+elif arch in ['arm']:
test_case.expect("register read r0", substrs = ['r0 = 0x'])
-elif test_case.getArchitecture() in ['aarch64']:
+elif arch in ['aarch64']:
 test_case.expect("register read x0", substrs = ['x0 = 0x'])
+elif re.match("mips",arch):
+test_case.expect("register read zero", substrs = ['zero = 0x'])
 else:
 # TODO: Add check for other architectures
 test_case.fail("Unsupported architecture for test case (arch: %s)" % 
test_case.getArchitecture())


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Re: [Lldb-commits] [PATCH] D14635: [LLDB][MIPS] Fix lldbplatformutil.py Failure

[Sagar Thakur via lldb-commits]

sagar closed this revision.
sagar added a comment.

Committed in r253555 on behalf of @nitesh.jain


Repository:
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http://reviews.llvm.org/D14635



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Re: [Lldb-commits] [PATCH] D14633: [LLDB][MIPS] Clear bug 25194 - LLDB-Server Assertion raised when single stepping on MIPS

[Sagar Thakur via lldb-commits]

sagar added a comment.

Hi,

Could we use SetBytes for now for clearing the bug 25194? I have tried using 
SetBytes(), it does not cause any issue on MIPS for both endian. Once we have a 
new function to llvm::APInt to access actual data I will revert back to using 
SetUInt. Kindly let me know if you agree with this.

Regards,
Sagar


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http://reviews.llvm.org/D14633



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Re: [Lldb-commits] [PATCH] D14633: [LLDB][MIPS] Clear bug 25194 - LLDB-Server Assertion raised when single stepping on MIPS

[Sagar Thakur via lldb-commits]

sagar updated this revision to Diff 41232.
sagar added a comment.

Addressed review comments


Repository:
  rL LLVM

http://reviews.llvm.org/D14633

Files:
  source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp

Index: source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
===
--- source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
+++ source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
@@ -1376,6 +1376,9 @@
 {
 GPR_linux_mips regs;
 ::memset(®s, 0, sizeof(GPR_linux_mips));
+
+// Clear all bits in RegisterValue before writing actual value read from 
ptrace to avoid garbage value in 32-bit MSB 
+value.SetBytes((void *)(((unsigned char *)®s) + offset), 8, 
GetByteOrder());
 Error error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGS, 
m_thread.GetID(), NULL, ®s, sizeof regs);
 if (error.Success())
 {


Index: source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
===
--- source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
+++ source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
@@ -1376,6 +1376,9 @@
 {
 GPR_linux_mips regs;
 ::memset(®s, 0, sizeof(GPR_linux_mips));
+
+// Clear all bits in RegisterValue before writing actual value read from ptrace to avoid garbage value in 32-bit MSB 
+value.SetBytes((void *)(((unsigned char *)®s) + offset), 8, GetByteOrder());
 Error error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGS, m_thread.GetID(), NULL, ®s, sizeof regs);
 if (error.Success())
 {
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[Lldb-commits] [lldb] r254379 - [LLDB][MIPS] Clear bug 25194 - LLDB-Server Assertion raised when single stepping on MIPS

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Mon Nov 30 23:44:18 2015
New Revision: 254379

URL: http://llvm.org/viewvc/llvm-project?rev=254379&view=rev
Log:
[LLDB][MIPS] Clear bug 25194 - LLDB-Server Assertion raised when single 
stepping on MIPS

This patch will clear bug 25194 - LLDB-Server Assertion raised when single 
stepping on MIPS. The problem was that while emulating instructions, old and 
new pc values would have garbage value in their upper 32 bits. Therefore 
checking if pc was changed (old_pc == new_pc) would always return false, 
because of which pc was not getting updated.

/* If we haven't changed the PC, change it here */
if (old_pc == new_pc)
{
new_pc += 4;
Context context;
return false;
}

Reviewers: tberghammer, clayborg
Subscribers: dsanders, lldb-commits, mohit.bhakkad, bhushan, jaydeep, 
nitesh.jain
Differential: http://reviews.llvm.org/D14633

Modified:

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp

Modified: 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp?rev=254379&r1=254378&r2=254379&view=diff
==
--- 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp 
(original)
+++ 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp 
Mon Nov 30 23:44:18 2015
@@ -1376,6 +1376,9 @@ NativeRegisterContextLinux_mips64::DoRea
 {
 GPR_linux_mips regs;
 ::memset(®s, 0, sizeof(GPR_linux_mips));
+
+// Clear all bits in RegisterValue before writing actual value read from 
ptrace to avoid garbage value in 32-bit MSB 
+value.SetBytes((void *)(((unsigned char *)®s) + offset), 8, 
GetByteOrder());
 Error error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGS, 
m_thread.GetID(), NULL, ®s, sizeof regs);
 if (error.Success())
 {


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Re: [Lldb-commits] [PATCH] D14633: [LLDB][MIPS] Clear bug 25194 - LLDB-Server Assertion raised when single stepping on MIPS

[Sagar Thakur via lldb-commits]

sagar closed this revision.
sagar added a comment.

Committed in revision 254379


Repository:
  rL LLVM

http://reviews.llvm.org/D14633



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[Lldb-commits] [lldb] r254850 - [LLDB][MIPS] Fix TestConstVariables.py

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Sat Dec  5 06:01:48 2015
New Revision: 254850

URL: http://llvm.org/viewvc/llvm-project?rev=254850&view=rev
Log:
[LLDB][MIPS] Fix TestConstVariables.py

Patch by Nitesh Jain.

Summary: There is no debug information generated for variable index with –O3 
optimization flag. The DW_AT_location tag in DWARF debug_info section is empty.

Reviewers: ovyalov, clayborg
Subscribers: lldb-commits, mohit.bhakkad, sagar, bhushan, jaydeep
Differential: http://reviews.llvm.org/D15224

Modified:

lldb/trunk/packages/Python/lldbsuite/test/lang/c/const_variables/TestConstVariables.py

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/lang/c/const_variables/TestConstVariables.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/lang/c/const_variables/TestConstVariables.py?rev=254850&r1=254849&r2=254850&view=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/lang/c/const_variables/TestConstVariables.py
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/lang/c/const_variables/TestConstVariables.py
 Sat Dec  5 06:01:48 2015
@@ -23,6 +23,7 @@ class ConstVariableTestCase(TestBase):
 oslist=["freebsd", "linux"],
 compiler="clang", compiler_version=["=", "3.8"])
 @expectedFailureAll(oslist=["freebsd", "linux"], compiler="icc")
+@expectedFailureAll(archs=['mips', 'mipsel', 'mips64', 'mips64el'])
 @expectedFailureWindows("llvm.org/pr24489: Name lookup not working 
correctly on Windows")
 @expectedFailureWindows("llvm.org/pr24490: We shouldn't be using 
platform-specific names like `getpid` in tests")
 def test_and_run_command(self):


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Re: [Lldb-commits] [PATCH] D15224: [LLDB][MIPS] Fix TestConstVariables.py

[Sagar Thakur via lldb-commits]

sagar closed this revision.
sagar added a comment.

Committed in revision 254850 on behalf of Nitesh Jain.


Repository:
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http://reviews.llvm.org/D15224



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[Lldb-commits] [lldb] r255108 - [LLDB][MIPS] Adding call to IsMSAAvailable() while creating RegisterInfoInterface

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Wed Dec  9 06:31:01 2015
New Revision: 255108

URL: http://llvm.org/viewvc/llvm-project?rev=255108&view=rev
Log:
[LLDB][MIPS] Adding call to IsMSAAvailable() while creating 
RegisterInfoInterface

This patch will fix the test case 
test_p_returns_correct_data_size_for_each_qRegisterInfo_attach_llgs_* of 
TestLldbGdbServer.py on mips. The test fails because we were sending 
RegisterInfo for msa registers to client even when msa registers are not 
available. With this commit server will send E45(end of resigters) response if 
msa registers are not available.


Modified:

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h

Modified: 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp?rev=255108&r1=255107&r2=255108&view=diff
==
--- 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp 
(original)
+++ 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp 
Wed Dec  9 06:31:01 2015
@@ -20,6 +20,7 @@
 #include "lldb/Core/Log.h"
 #include "lldb/Core/DataBufferHeap.h"
 #include "lldb/Host/HostInfo.h"
+#include "lldb/Host/Host.h"
 #include "lldb/Core/EmulateInstruction.h"
 #include "lldb/lldb-enumerations.h"
 #include "lldb/lldb-private-enumerations.h"
@@ -416,14 +417,14 @@ CreateRegisterInfoInterface(const ArchSp
 if (HostInfo::GetArchitecture().GetAddressByteSize() == 4)
 {
 // 32-bit hosts run with a RegisterContextLinux_mips context.
-return new RegisterContextLinux_mips(target_arch);
+return new RegisterContextLinux_mips(target_arch, 
NativeRegisterContextLinux_mips64::IsMSAAvailable());
 }
 else
 {
 assert((HostInfo::GetArchitecture().GetAddressByteSize() == 8) &&
"Register setting path assumes this is a 64-bit host");
 // mips64 hosts know how to work with 64-bit and 32-bit EXEs using the 
mips64 register context.
-return new RegisterContextLinux_mips64 (target_arch);
+return new RegisterContextLinux_mips64 (target_arch, 
NativeRegisterContextLinux_mips64::IsMSAAvailable());
 }
 }
 
@@ -1104,9 +1105,12 @@ NativeRegisterContextLinux_mips64::IsMSA
 bool
 NativeRegisterContextLinux_mips64::IsMSAAvailable()
 {
-Error error = NativeRegisterContextLinux::ReadRegisterSet(&m_msa, 
sizeof(MSA_linux_mips), NT_MIPS_MSA);
+MSA_linux_mips msa_buf;
+unsigned int regset = NT_MIPS_MSA;
 
-if (error.Success() && m_msa.mir)
+Error error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGSET, 
Host::GetCurrentProcessID(), static_cast(®set), &msa_buf, 
sizeof(MSA_linux_mips));
+
+if (error.Success() && msa_buf.mir)
 {
 return true;
 }

Modified: 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h?rev=255108&r1=255107&r2=255108&view=diff
==
--- lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h 
(original)
+++ lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h 
Wed Dec  9 06:31:01 2015
@@ -89,6 +89,9 @@ namespace process_linux {
 uint32_t
 NumSupportedHardwareWatchpoints () override;
 
+static bool
+IsMSAAvailable();
+
 protected:
 Error
 DoReadRegisterValue(uint32_t offset,
@@ -119,9 +122,6 @@ namespace process_linux {
 bool
 IsMSA(uint32_t reg_index) const;
 
-bool
-IsMSAAvailable();
-
 void*
 GetGPRBuffer() override { return &m_gpr; }
 


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[Lldb-commits] [lldb] r269181 - [LLDB][MIPS] Setting appropriate ArchSpec::m_flags based on ABI

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Wed May 11 08:08:29 2016
New Revision: 269181

URL: http://llvm.org/viewvc/llvm-project?rev=269181&view=rev
Log:
[LLDB][MIPS] Setting appropriate ArchSpec::m_flags based on ABI

Patch by Nitesh Jain.

Summary: The ArchSpec::m_flags will be set based on ELF flag ABI.

Reviewers: ovyalov, clayborg
Subscribers: lldb-commits, mohit.bhakkad, sagar, jaydeep, bhushan
Differential: D18858

Modified:
lldb/trunk/include/lldb/Core/ArchSpec.h
lldb/trunk/source/Core/ArchSpec.cpp
lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp

Modified: lldb/trunk/include/lldb/Core/ArchSpec.h
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/Core/ArchSpec.h?rev=269181&r1=269180&r2=269181&view=diff
==
--- lldb/trunk/include/lldb/Core/ArchSpec.h (original)
+++ lldb/trunk/include/lldb/Core/ArchSpec.h Wed May 11 08:08:29 2016
@@ -69,6 +69,9 @@ public:
 eMIPSABI_O32= 0x2000,
 eMIPSABI_N32= 0x4000,
 eMIPSABI_N64= 0x8000,
+eMIPSABI_O64= 0x0002,
+eMIPSABI_EABI32 = 0x0004,
+eMIPSABI_EABI64 = 0x0008,
 eMIPSABI_mask   = 0x000ff000
 };
 
@@ -289,6 +292,14 @@ public:
 const char *
 GetArchitectureName () const;
 
+//-
+/// if MIPS architecture return true.
+///
+///  @return a boolean value.
+//-
+bool
+IsMIPS() const;
+
 //--
 /// Returns a string representing current architecture as a target CPU
 /// for tools like compiler, disassembler etc.

Modified: lldb/trunk/source/Core/ArchSpec.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Core/ArchSpec.cpp?rev=269181&r1=269180&r2=269181&view=diff
==
--- lldb/trunk/source/Core/ArchSpec.cpp (original)
+++ lldb/trunk/source/Core/ArchSpec.cpp Wed May 11 08:08:29 2016
@@ -507,6 +507,18 @@ ArchSpec::GetArchitectureName () const
 return "unknown";
 }
 
+bool 
+ArchSpec::IsMIPS() const
+{
+const llvm::Triple::ArchType machine = GetMachine();
+if(machine == llvm::Triple::mips ||
+   machine == llvm::Triple::mipsel ||
+   machine == llvm::Triple::mips64 ||
+   machine == llvm::Triple::mips64el)
+   return true;
+return false;
+}
+
 std::string
 ArchSpec::GetClangTargetCPU ()
 {

Modified: lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp?rev=269181&r1=269180&r2=269181&view=diff
==
--- lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp (original)
+++ lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp Wed May 11 
08:08:29 2016
@@ -1697,8 +1697,7 @@ ObjectFileELF::GetSectionHeaderInfo(Sect
 
 I->section_name = name;
 
-if (arch_spec.GetMachine() == llvm::Triple::mips || 
arch_spec.GetMachine() == llvm::Triple::mipsel
-|| arch_spec.GetMachine() == llvm::Triple::mips64 || 
arch_spec.GetMachine() == llvm::Triple::mips64el)
+if (arch_spec.IsMIPS())
 {
 uint32_t arch_flags = arch_spec.GetFlags ();
 DataExtractor data;
@@ -1712,13 +1711,27 @@ ObjectFileELF::GetSectionHeaderInfo(Sect
 }
 }
 // Settings appropriate ArchSpec ABI Flags
-if (header.e_flags & llvm::ELF::EF_MIPS_ABI2)
+switch(header.e_flags & llvm::ELF::EF_MIPS_ABI)
 {
-arch_flags |= lldb_private::ArchSpec::eMIPSABI_N32;
-}
-else if (header.e_flags & llvm::ELF::EF_MIPS_ABI_O32)
-{
- arch_flags |= lldb_private::ArchSpec::eMIPSABI_O32;
+case llvm::ELF::EF_MIPS_ABI_O32:
+arch_flags |= lldb_private::ArchSpec::eMIPSABI_O32;
+break;
+case EF_MIPS_ABI_O64:
+arch_flags |= lldb_private::ArchSpec::eMIPSABI_O64;
+break;
+case EF_MIPS_ABI_EABI32:
+arch_flags |= 
lldb_private::ArchSpec::eMIPSABI_EABI32;
+break;
+case EF_MIPS_ABI_EABI64:
+arch_flags |= 
lldb_private::ArchSpec::eMIPSABI_EABI64;
+break;
+default:
+// ABI Mask doesn't cover N32 and 

[Lldb-commits] [lldb] r269407 - [LLDB][MIPS] Provide ABI string to compiler for appropriate code generation for MIPS

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Fri May 13 06:04:47 2016
New Revision: 269407

URL: http://llvm.org/viewvc/llvm-project?rev=269407&view=rev
Log:
[LLDB][MIPS] Provide ABI string to compiler for appropriate code generation for 
MIPS

Patch by Nitesh Jain.

Summary: These patch will set clang::TargetOptions::ABI and accordingly code 
will be generated for MIPS target.

Reviewers: ovyalov, clayborg
Subscribers: lldb-commits, mohit.bhakkad, sagar, jaydeep, bhushan
Differential: D18638

Modified:
lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.h

Modified: 
lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp?rev=269407&r1=269406&r2=269407&view=diff
==
--- lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp 
(original)
+++ lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp 
Fri May 13 06:04:47 2016
@@ -286,7 +286,8 @@ ClangExpressionParser::ClangExpressionPa
 lldb::LanguageType frame_lang = expr.Language(); // defaults to 
lldb::eLanguageTypeUnknown
 bool overridden_target_opts = false;
 lldb_private::LanguageRuntime *lang_rt = nullptr;
-
+
+std::string abi;
 ArchSpec target_arch;
 target_arch = target_sp->GetArchitecture();
 
@@ -350,6 +351,11 @@ ClangExpressionParser::ClangExpressionPa
 // This will be empty for any CPU that doesn't really need to make a 
special CPU string.
 m_compiler->getTargetOpts().CPU = target_arch.GetClangTargetCPU();
 
+// Set the target ABI
+abi = GetClangTargetABI(target_arch);
+if (!abi.empty())
+m_compiler->getTargetOpts().ABI = abi;
+
 // 3. Now allow the runtime to provide custom configuration options for 
the target.
 // In this case, a specialized language runtime is available and we can 
query it for extra options.
 // For 99% of use cases, this will not be needed and should be provided 
when basic platform detection is not enough.
@@ -658,6 +664,29 @@ ClangExpressionParser::Parse(DiagnosticM
 return num_errors;
 }
 
+std::string
+ClangExpressionParser::GetClangTargetABI (const ArchSpec &target_arch)
+{
+std::string abi;
+const llvm::Triple::ArchType machine = target_arch.GetMachine();
+
+if(target_arch.IsMIPS())
+{
+   switch (target_arch.GetFlags () & ArchSpec::eMIPSABI_mask)
+   {
+   case ArchSpec::eMIPSABI_N64:
+abi = "n64"; break;
+   case ArchSpec::eMIPSABI_N32:
+abi = "n32"; break;
+   case ArchSpec::eMIPSABI_O32:
+abi = "o32"; break;
+   default:
+  break;
+   }
+}
+return abi;
+}
+
 bool
 ClangExpressionParser::RewriteExpression(DiagnosticManager &diagnostic_manager)
 {

Modified: 
lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.h
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.h?rev=269407&r1=269406&r2=269407&view=diff
==
--- lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.h 
(original)
+++ lldb/trunk/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.h 
Fri May 13 06:04:47 2016
@@ -137,7 +137,19 @@ public:
 Error
 RunStaticInitializers (lldb::IRExecutionUnitSP &execution_unit_sp,
ExecutionContext &exe_ctx);
-
+
+//--
+/// Returns a string representing current ABI.
+///
+/// @param[in] target_arch
+/// The target architecture.
+///
+/// @return
+/// A string representing target ABI for the current architecture.
+//---
+std::string
+GetClangTargetABI (const ArchSpec &target_arch);
+ 
 private:
 std::unique_ptr   m_llvm_context; ///< The 
LLVM context to generate IR into
 std::unique_ptr  m_file_manager; ///< The 
Clang file manager object used by the compiler


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[Lldb-commits] [lldb] r270207 - [LLDB][MIPS] Fix floating point handling in case of thread step-out

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Fri May 20 07:07:27 2016
New Revision: 270207

URL: http://llvm.org/viewvc/llvm-project?rev=270207&view=rev
Log:
[LLDB][MIPS] Fix floating point handling in case of thread step-out

Patch by Nitesh Jain.

Summary: These patch fix thread step-out for hard and soft float.

Reviewers: clayborg, bhushan, jaydeep
Subscribers: mohit.bhakkad, sagar, sdardis
Differential: D20416

Modified:
lldb/trunk/include/lldb/Core/ArchSpec.h
lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.h
lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.h
lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp

Modified: lldb/trunk/include/lldb/Core/ArchSpec.h
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/Core/ArchSpec.h?rev=270207&r1=270206&r2=270207&view=diff
==
--- lldb/trunk/include/lldb/Core/ArchSpec.h (original)
+++ lldb/trunk/include/lldb/Core/ArchSpec.h Fri May 20 07:07:27 2016
@@ -75,6 +75,20 @@ public:
 eMIPSABI_mask   = 0x000ff000
 };
 
+// MIPS Floating point ABI Values
+enum MIPS_ABI_FP
+{
+eMIPS_ABI_FP_ANY = 0x,
+eMIPS_ABI_FP_DOUBLE  = 0x0010,  // hard float / -mdouble-float
+eMIPS_ABI_FP_SINGLE  = 0x0020,  // hard float / -msingle-float
+eMIPS_ABI_FP_SOFT= 0x0030,  // soft float
+eMIPS_ABI_FP_OLD_64  = 0x0040,  // -mips32r2 -mfp64
+eMIPS_ABI_FP_XX  = 0x0050,  // -mfpxx
+eMIPS_ABI_FP_64  = 0x0060,  // -mips32r2 -mfp64
+eMIPS_ABI_FP_64A = 0x0070,  // -mips32r2 -mfp64 -mno-odd-spreg
+eMIPS_ABI_FP_mask= 0x0070
+};
+
 // ARM specific e_flags
 enum ARMeflags
 {

Modified: lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp?rev=270207&r1=270206&r2=270207&view=diff
==
--- lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp (original)
+++ lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp Fri May 20 
07:07:27 2016
@@ -397,7 +397,11 @@ ABISysV_mips::GetReturnValueObjectImpl (
 if (exe_ctx.GetTargetPtr() == nullptr || exe_ctx.GetProcessPtr() == 
nullptr)
 return return_valobj_sp;
 
+Target *target = exe_ctx.GetTargetPtr();
+const ArchSpec target_arch = target->GetArchitecture();
+ByteOrder target_byte_order = target_arch.GetByteOrder();
 value.SetCompilerType(return_compiler_type);
+uint32_t fp_flag = target_arch.GetFlags() & 
lldb_private::ArchSpec::eMIPS_ABI_FP_mask;
 
 RegisterContext *reg_ctx = thread.GetRegisterContext().get();
 if (!reg_ctx)
@@ -409,8 +413,7 @@ ABISysV_mips::GetReturnValueObjectImpl (
 
 // In MIPS register "r2" (v0) holds the integer function return values
 const RegisterInfo *r2_reg_info = reg_ctx->GetRegisterInfoByName("r2", 0);
-size_t bit_width = return_compiler_type.GetBitSize(&thread);
-
+size_t bit_width = return_compiler_type.GetBitSize(&thread); 
 if (return_compiler_type.IsIntegerType (is_signed))
 {
 switch (bit_width)
@@ -467,37 +470,107 @@ ABISysV_mips::GetReturnValueObjectImpl (
 }
 else if (return_compiler_type.IsFloatingPointType (count, is_complex))
 {
-const RegisterInfo *f0_info = reg_ctx->GetRegisterInfoByName("f0", 0);
-const RegisterInfo *f1_info = reg_ctx->GetRegisterInfoByName("f1", 0);
-
-if (count == 1 && !is_complex)
+if (IsSoftFloat (fp_flag))
 {
+uint64_t raw_value = reg_ctx->ReadRegisterAsUnsigned(r2_reg_info, 
0);
+if (count != 1 && is_complex)
+return return_valobj_sp;
 switch (bit_width)
 {
 default:
 return return_valobj_sp;
-case 64:
-{
-static_assert(sizeof(double) == sizeof(uint64_t), "");
-uint64_t raw_value;
-raw_value = reg_ctx->ReadRegisterAsUnsigned(f0_info, 0) & 
UINT32_MAX;
-raw_value |= 
((uint64_t)(reg_ctx->ReadRegisterAsUnsigned(f1_info, 0) & UINT32_MAX)) << 32;
-value.GetScalar() = *reinterpret_cast(&raw_value);
-break;
-}
 case 32:
-{
 static_assert(sizeof(float) == sizeof(uint32_t), "");
-uint32_t raw_value = 
reg_ctx->ReadRegisterAsUnsigned(f0_info, 0) & UINT32_MAX;
-value.GetScalar() = *reinterpret_cast(&raw_value);
+value.GetScalar() = *((float *)(&raw_value));
+break;
+case 64:
+ 

[Lldb-commits] [lldb] r270208 - [LLDB][MIPS] Fix Floating point Registers Encoding

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Fri May 20 07:11:52 2016
New Revision: 270208

URL: http://llvm.org/viewvc/llvm-project?rev=270208&view=rev
Log:
[LLDB][MIPS] Fix Floating point Registers Encoding

Patch by Nitesh Jain.

Summary: Currently floating point regsiters has eEncodingUint encoding. Hence 
register write  '1.25' will failed. This patch add eEncodingIEEE754 encoding 
for floating point registers( - ). This patch will fix test_fp_register_write 
in TestRegisters.py

Reviewers: clayborg, sagar
Subscribers: mohit.bhakkad, jaydeep, bhushan, sdardis, lldb-commits
Differential: D18853

Modified:
lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_mips.h
lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_mips64.h

Modified: lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_mips.h
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_mips.h?rev=270208&r1=270207&r2=270208&view=diff
==
--- lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_mips.h (original)
+++ lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_mips.h Fri May 20 
07:11:52 2016
@@ -39,8 +39,12 @@
   eFormatHex, { kind1, kind2, kind3, kind4, gpr_##reg##_mips }, NULL, NULL 
}
 
 #define DEFINE_FPR(reg, alt, kind1, kind2, kind3, kind4)   \
-{ #reg, alt, sizeof(((FPR_linux_mips*)NULL)->reg), FPR_OFFSET(reg), 
eEncodingUint,   \
-  eFormatHex, { kind1, kind2, kind3, kind4, fpr_##reg##_mips }, NULL, NULL 
}
+{ #reg, alt, sizeof(((FPR_linux_mips*)NULL)->reg), FPR_OFFSET(reg), 
eEncodingIEEE754,   \
+  eFormatFloat, { kind1, kind2, kind3, kind4, fpr_##reg##_mips }, NULL, 
NULL }
+
+#define DEFINE_FPR_INFO(reg, alt, kind1, kind2, kind3, kind4)  \
+   { #reg, alt, sizeof(((FPR_linux_mips*)NULL)->reg), FPR_OFFSET(reg), 
eEncodingUint,   \
+ eFormatHex, { kind1, kind2, kind3, kind4, fpr_##reg##_mips }, NULL, NULL }
 
 #define DEFINE_MSA(reg, alt, kind1, kind2, kind3, kind4)\
 { #reg, alt, sizeof(((MSA_linux_mips*)0)->reg), MSA_OFFSET(reg), 
eEncodingVector,   \
@@ -126,9 +130,9 @@ g_register_infos_mips[] =
 DEFINE_FPR (f29,   nullptr,dwarf_f29_mips,  dwarf_f29_mips,  
LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM),
 DEFINE_FPR (f30,   nullptr,dwarf_f30_mips,  dwarf_f30_mips,  
LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM),
 DEFINE_FPR (f31,   nullptr,dwarf_f31_mips,  dwarf_f31_mips,  
LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM),
-DEFINE_FPR (fcsr,  nullptr,dwarf_fcsr_mips, dwarf_fcsr_mips, 
LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM),
-DEFINE_FPR (fir,   nullptr,dwarf_fir_mips,  dwarf_fir_mips,  
LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM),
-DEFINE_FPR (config5,   nullptr,dwarf_config5_mips,  
dwarf_config5_mips,  LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM),
+DEFINE_FPR_INFO (fcsr,  nullptr,dwarf_fcsr_mips, dwarf_fcsr_mips, 
LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM),
+DEFINE_FPR_INFO (fir,   nullptr,dwarf_fir_mips,  dwarf_fir_mips,  
LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM),
+DEFINE_FPR_INFO (config5,   nullptr,dwarf_config5_mips,  
dwarf_config5_mips,  LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM),
 DEFINE_MSA (w0,nullptr,dwarf_w0_mips,   dwarf_w0_mips,   
LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM),
 DEFINE_MSA (w1,nullptr,dwarf_w1_mips,   dwarf_w1_mips,   
LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM),
 DEFINE_MSA (w2,nullptr,dwarf_w2_mips,   dwarf_w2_mips,   
LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM),
@@ -176,6 +180,7 @@ static_assert((sizeof(g_register_infos_m
 #undef MSA_OFFSET
 #undef DEFINE_GPR
 #undef DEFINE_FPR
+#undef DEFINE_FPR_INFO
 #undef DEFINE_MSA
 #undef DEFINE_MSA_INFO
 

Modified: lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_mips64.h
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_mips64.h?rev=270208&r1=270207&r2=270208&view=diff
==
--- lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_mips64.h (original)
+++ lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_mips64.h Fri May 20 
07:11:52 2016
@@ -56,6 +56,10 @@
   eFormatHex, { kind1, kind2, kind3, kind4, gpr_##reg##_mips64 }, NULL, 
NULL }
 
 #define DEFINE_FPR(reg, alt, kind1, kind2, kind3, kind4)\
+{ #reg, alt, sizeof(((FPR_linux_mips*)0)->reg), FPR_OFFSET(reg), 
eEncodingIEEE754,  \
+  eFormatFloat, { kind1, kind2, kind3, kind4, fpr_##reg##_mips64 }, NULL, 
NULL }
+
+#define DEFINE_FPR_INFO(reg, alt, kind1, kind2, kind3, kind4)\
 { #reg, alt, sizeof(((FPR_linux_mips*)0)->reg), FPR_OFFSET(reg), 
eEncodingUint,   \
   eFormatHex, { kind1, kind2, kind3, kind4, fpr_##reg##_mips64 }, NULL, 
NULL }
 
@@ -184,9 +188,9 @@ g_register_infos_mips64[] =
 DEFINE_FPR (f29

[Lldb-commits] [lldb] r270564 - [LLDB][MIPS] Fix floating point handling in case of thread step-out

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Tue May 24 09:52:50 2016
New Revision: 270564

URL: http://llvm.org/viewvc/llvm-project?rev=270564&view=rev
Log:
[LLDB][MIPS] Fix floating point handling in case of thread step-out

Patch by Nitesh Jain.

Summary: These patch fix thread step-out for hard and soft float.

Reviewers: jaydeep, bhushan, clayborg
Differential Revision: http://reviews.llvm.org/D20416

Modified:
lldb/trunk/include/lldb/Core/ArchSpec.h
lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.h
lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.h
lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp

Modified: lldb/trunk/include/lldb/Core/ArchSpec.h
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/include/lldb/Core/ArchSpec.h?rev=270564&r1=270563&r2=270564&view=diff
==
--- lldb/trunk/include/lldb/Core/ArchSpec.h (original)
+++ lldb/trunk/include/lldb/Core/ArchSpec.h Tue May 24 09:52:50 2016
@@ -75,6 +75,20 @@ public:
 eMIPSABI_mask   = 0x000ff000
 };
 
+// MIPS Floating point ABI Values
+enum MIPS_ABI_FP
+{
+eMIPS_ABI_FP_ANY = 0x,
+eMIPS_ABI_FP_DOUBLE  = 0x0010,  // hard float / -mdouble-float
+eMIPS_ABI_FP_SINGLE  = 0x0020,  // hard float / -msingle-float
+eMIPS_ABI_FP_SOFT= 0x0030,  // soft float
+eMIPS_ABI_FP_OLD_64  = 0x0040,  // -mips32r2 -mfp64
+eMIPS_ABI_FP_XX  = 0x0050,  // -mfpxx
+eMIPS_ABI_FP_64  = 0x0060,  // -mips32r2 -mfp64
+eMIPS_ABI_FP_64A = 0x0070,  // -mips32r2 -mfp64 -mno-odd-spreg
+eMIPS_ABI_FP_mask= 0x0070
+};
+
 // ARM specific e_flags
 enum ARMeflags
 {

Modified: lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp?rev=270564&r1=270563&r2=270564&view=diff
==
--- lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp (original)
+++ lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp Tue May 24 
09:52:50 2016
@@ -397,7 +397,11 @@ ABISysV_mips::GetReturnValueObjectImpl (
 if (exe_ctx.GetTargetPtr() == nullptr || exe_ctx.GetProcessPtr() == 
nullptr)
 return return_valobj_sp;
 
+Target *target = exe_ctx.GetTargetPtr();
+const ArchSpec target_arch = target->GetArchitecture();
+ByteOrder target_byte_order = target_arch.GetByteOrder();
 value.SetCompilerType(return_compiler_type);
+uint32_t fp_flag = target_arch.GetFlags() & 
lldb_private::ArchSpec::eMIPS_ABI_FP_mask;
 
 RegisterContext *reg_ctx = thread.GetRegisterContext().get();
 if (!reg_ctx)
@@ -409,8 +413,7 @@ ABISysV_mips::GetReturnValueObjectImpl (
 
 // In MIPS register "r2" (v0) holds the integer function return values
 const RegisterInfo *r2_reg_info = reg_ctx->GetRegisterInfoByName("r2", 0);
-size_t bit_width = return_compiler_type.GetBitSize(&thread);
-
+size_t bit_width = return_compiler_type.GetBitSize(&thread); 
 if (return_compiler_type.IsIntegerType (is_signed))
 {
 switch (bit_width)
@@ -467,37 +470,107 @@ ABISysV_mips::GetReturnValueObjectImpl (
 }
 else if (return_compiler_type.IsFloatingPointType (count, is_complex))
 {
-const RegisterInfo *f0_info = reg_ctx->GetRegisterInfoByName("f0", 0);
-const RegisterInfo *f1_info = reg_ctx->GetRegisterInfoByName("f1", 0);
-
-if (count == 1 && !is_complex)
+if (IsSoftFloat (fp_flag))
 {
+uint64_t raw_value = reg_ctx->ReadRegisterAsUnsigned(r2_reg_info, 
0);
+if (count != 1 && is_complex)
+return return_valobj_sp;
 switch (bit_width)
 {
 default:
 return return_valobj_sp;
-case 64:
-{
-static_assert(sizeof(double) == sizeof(uint64_t), "");
-uint64_t raw_value;
-raw_value = reg_ctx->ReadRegisterAsUnsigned(f0_info, 0) & 
UINT32_MAX;
-raw_value |= 
((uint64_t)(reg_ctx->ReadRegisterAsUnsigned(f1_info, 0) & UINT32_MAX)) << 32;
-value.GetScalar() = *reinterpret_cast(&raw_value);
-break;
-}
 case 32:
-{
 static_assert(sizeof(float) == sizeof(uint32_t), "");
-uint32_t raw_value = 
reg_ctx->ReadRegisterAsUnsigned(f0_info, 0) & UINT32_MAX;
-value.GetScalar() = *reinterpret_cast(&raw_value);
+value.GetScalar() = *((float *)(&raw_value));
+break;
+case 64:
+sta

Re: [Lldb-commits] [PATCH] D20416: [LLDB][MIPS] Fix floating point handling in case of thread step-out

[Sagar Thakur via lldb-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL270564: [LLDB][MIPS] Fix floating point handling in case of 
thread step-out (authored by slthakur).

Changed prior to commit:
  http://reviews.llvm.org/D20416?vs=57739&id=58236#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D20416

Files:
  lldb/trunk/include/lldb/Core/ArchSpec.h
  lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
  lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.h
  lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.cpp
  lldb/trunk/source/Plugins/ABI/SysV-mips64/ABISysV_mips64.h
  lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp

Index: lldb/trunk/include/lldb/Core/ArchSpec.h
===
--- lldb/trunk/include/lldb/Core/ArchSpec.h
+++ lldb/trunk/include/lldb/Core/ArchSpec.h
@@ -75,6 +75,20 @@
 eMIPSABI_mask   = 0x000ff000
 };
 
+// MIPS Floating point ABI Values
+enum MIPS_ABI_FP
+{
+eMIPS_ABI_FP_ANY = 0x,
+eMIPS_ABI_FP_DOUBLE  = 0x0010,  // hard float / -mdouble-float
+eMIPS_ABI_FP_SINGLE  = 0x0020,  // hard float / -msingle-float
+eMIPS_ABI_FP_SOFT= 0x0030,  // soft float
+eMIPS_ABI_FP_OLD_64  = 0x0040,  // -mips32r2 -mfp64
+eMIPS_ABI_FP_XX  = 0x0050,  // -mfpxx
+eMIPS_ABI_FP_64  = 0x0060,  // -mips32r2 -mfp64
+eMIPS_ABI_FP_64A = 0x0070,  // -mips32r2 -mfp64 -mno-odd-spreg
+eMIPS_ABI_FP_mask= 0x0070
+};
+
 // ARM specific e_flags
 enum ARMeflags
 {
Index: lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.h
===
--- lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.h
+++ lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.h
@@ -54,6 +54,9 @@
 RegisterIsVolatile(const lldb_private::RegisterInfo *reg_info) override;
 
 bool
+IsSoftFloat(uint32_t fp_flag) const;
+
+bool
 CallFrameAddressIsValid(lldb::addr_t cfa) override
 {
 // Make sure the stack call frame addresses are 8 byte aligned
Index: lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
===
--- lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
+++ lldb/trunk/source/Plugins/ABI/SysV-mips/ABISysV_mips.cpp
@@ -397,7 +397,11 @@
 if (exe_ctx.GetTargetPtr() == nullptr || exe_ctx.GetProcessPtr() == nullptr)
 return return_valobj_sp;
 
+Target *target = exe_ctx.GetTargetPtr();
+const ArchSpec target_arch = target->GetArchitecture();
+ByteOrder target_byte_order = target_arch.GetByteOrder();
 value.SetCompilerType(return_compiler_type);
+uint32_t fp_flag = target_arch.GetFlags() & lldb_private::ArchSpec::eMIPS_ABI_FP_mask;
 
 RegisterContext *reg_ctx = thread.GetRegisterContext().get();
 if (!reg_ctx)
@@ -409,8 +413,7 @@
 
 // In MIPS register "r2" (v0) holds the integer function return values
 const RegisterInfo *r2_reg_info = reg_ctx->GetRegisterInfoByName("r2", 0);
-size_t bit_width = return_compiler_type.GetBitSize(&thread);
-
+size_t bit_width = return_compiler_type.GetBitSize(&thread); 
 if (return_compiler_type.IsIntegerType (is_signed))
 {
 switch (bit_width)
@@ -467,37 +470,107 @@
 }
 else if (return_compiler_type.IsFloatingPointType (count, is_complex))
 {
-const RegisterInfo *f0_info = reg_ctx->GetRegisterInfoByName("f0", 0);
-const RegisterInfo *f1_info = reg_ctx->GetRegisterInfoByName("f1", 0);
-
-if (count == 1 && !is_complex)
+if (IsSoftFloat (fp_flag))
 {
+uint64_t raw_value = reg_ctx->ReadRegisterAsUnsigned(r2_reg_info, 0);
+if (count != 1 && is_complex)
+return return_valobj_sp;
 switch (bit_width)
 {
 default:
 return return_valobj_sp;
-case 64:
-{
-static_assert(sizeof(double) == sizeof(uint64_t), "");
-uint64_t raw_value;
-raw_value = reg_ctx->ReadRegisterAsUnsigned(f0_info, 0) & UINT32_MAX;
-raw_value |= ((uint64_t)(reg_ctx->ReadRegisterAsUnsigned(f1_info, 0) & UINT32_MAX)) << 32;
-value.GetScalar() = *reinterpret_cast(&raw_value);
-break;
-}
 case 32:
-{
 static_assert(sizeof(float) == sizeof(uint32_t), "");
-uint32_t raw_value = reg_ctx->ReadRegisterAsUnsigned(f0_info, 0) & UINT32_MAX;
-value.GetScalar() = *reinterpret_cast(&raw_value);
+value.GetScalar() = *((float *)(&raw_value));
+break;
+case 64:
+static_assert(sizeof(double) == 

[Lldb-commits] [lldb] r273535 - [LLDB][MIPS] Fix Emulation of Compact branch and ADDIU instructions

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Thu Jun 23 01:40:37 2016
New Revision: 273535

URL: http://llvm.org/viewvc/llvm-project?rev=273535&view=rev
Log:
[LLDB][MIPS] Fix Emulation of Compact branch and ADDIU instructions

Patch by Nitesh Jain.

This patch contains 2 changes:

  - Corrected target address calculation of compact branch instructions to 
reflect changes in disassembler (http://reviews.llvm.org/D17540).
  - Added emulation for (missing) 'Addiu' instruction.

Reviewers :jaydeep, bhushan, clayborg
Differential: http://reviews.llvm.org/D21064

Modified:
lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp

Modified: lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp?rev=273535&r1=273534&r2=273535&view=diff
==
--- lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp 
(original)
+++ lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp Thu 
Jun 23 01:40:37 2016
@@ -1482,56 +1482,56 @@ EmulateInstructionMIPS::Emulate_BXX_3ops
 if (!strcasecmp (op_name, "BEQC"))
 {
 if (rs_val == rt_val)
-target = pc + 4 + offset;
+target = pc + offset;
 else
 target = pc + 4;
 }
 else if (!strcasecmp (op_name, "BNEC"))
 {
 if (rs_val != rt_val)
-target = pc + 4 + offset;
+target = pc + offset;
 else
 target = pc + 4;
 }
 else if (!strcasecmp (op_name, "BLTC"))
 {
 if (rs_val < rt_val)
-target = pc + 4 + offset;
+target = pc + offset;
 else
 target = pc + 4;
 }
 else if (!strcasecmp (op_name, "BGEC"))
 {
 if (rs_val >= rt_val)
-target = pc + 4 + offset;
+target = pc  + offset;
 else
 target = pc + 4;
 }
 else if (!strcasecmp (op_name, "BLTUC"))
 {
 if (rs_val < rt_val)
-target = pc + 4 + offset;
+target = pc + offset;
 else
 target = pc + 4;
 }
 else if (!strcasecmp (op_name, "BGEUC"))
 {
 if ((uint32_t)rs_val >= (uint32_t)rt_val)
-target = pc + 4 + offset;
+target = pc + offset;
 else
 target = pc + 4;
 }
 else if (!strcasecmp (op_name, "BOVC"))
 {
 if (IsAdd64bitOverflow (rs_val, rt_val))
-target = pc + 4 + offset;
+target = pc + offset;
 else
 target = pc + 4;
 }
 else if (!strcasecmp (op_name, "BNVC"))
 {
 if (!IsAdd64bitOverflow (rs_val, rt_val))
-target = pc + 4 + offset;
+target = pc + offset;
 else
 target = pc + 4;
 }
@@ -1773,42 +1773,42 @@ EmulateInstructionMIPS::Emulate_BXX_2ops
 if (!strcasecmp (op_name, "BLTZC"))
 {
 if (rs_val < 0)
-target = pc + 4 + offset;
+target = pc + offset;
 else
 target = pc + 4;
 }
 else if (!strcasecmp (op_name, "BLEZC"))
 {
 if (rs_val <= 0)
-target = pc + 4 + offset;
+target = pc + offset;
 else
 target = pc + 4;
 }
 else if (!strcasecmp (op_name, "BGEZC"))
 {
 if (rs_val >= 0)
-target = pc + 4 + offset;
+target = pc + offset;
 else
 target = pc + 4;
 }
 else if (!strcasecmp (op_name, "BGTZC"))
 {
 if (rs_val > 0)
-target = pc + 4 + offset;
+target = pc + offset;
 else
 target = pc + 4;
 }
 else if (!strcasecmp (op_name, "BEQZC"))
 {
 if (rs_val == 0)
-target = pc + 4 + offset;
+target = pc + offset;
 else
 target = pc + 4;
 }
 else if (!strcasecmp (op_name, "BNEZC"))
 {
 if (rs_val != 0)
-target = pc + 4 + offset;
+target = pc + offset;
 else
 target = pc + 4;
 }
@@ -2129,7 +2129,7 @@ EmulateInstructionMIPS::Emulate_BALC (ll
 if (!success)
 return false;
 
-target = pc + 4 + offset;
+target = pc + offset;
 
 Context context;
 
@@ -2159,7 +2159,7 @@ EmulateInstructionMIPS::Emulate_BC (llvm
 if (!success)
 return false;
 
-target = pc + 4 + offset;
+target = pc + offset;
 
 Context context;
 

Modified: 
lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp?rev=273535&r1=273534&r2=273535&view=diff
==
--- lldb/trunk/source/Plug

Re: [Lldb-commits] [PATCH] D21064: [LLDB][MIPS] Fix Emulation of Compact branch and ADDIU instructions

[Sagar Thakur via lldb-commits]

slthakur closed this revision.
slthakur added a comment.

Committed in http://reviews.llvm.org/rL273535


Repository:
  rL LLVM

http://reviews.llvm.org/D21064



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[Lldb-commits] [lldb] r274121 - [LLDB][MIPS] Check if libatomic needs to be specified explicitly

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Wed Jun 29 07:30:18 2016
New Revision: 274121

URL: http://llvm.org/viewvc/llvm-project?rev=274121&view=rev
Log:
[LLDB][MIPS] Check if libatomic needs to be specified explicitly

Patch by Nitesh Jain.

Summary : The problem appears while linking liblldb.so. The class Address 
contain atomic variable m_offset. The loading and storing of variable is access 
via atomic_load_8 and atomic_store_8 functions. Some target fail to implicitly 
link libatomic, which cause undefine reference to atomic_store_8/atomic_load_8. 
This patch uses http://reviews.llvm.org/D20896 to check if libatomic need to be 
explicitly link.

Reviewed by labath.
Differential: D20464

Modified:
lldb/trunk/cmake/LLDBDependencies.cmake

Modified: lldb/trunk/cmake/LLDBDependencies.cmake
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/cmake/LLDBDependencies.cmake?rev=274121&r1=274120&r2=274121&view=diff
==
--- lldb/trunk/cmake/LLDBDependencies.cmake (original)
+++ lldb/trunk/cmake/LLDBDependencies.cmake Wed Jun 29 07:30:18 2016
@@ -157,6 +157,11 @@ if (NOT CMAKE_SYSTEM_NAME MATCHES "Windo
 endif()
   endif()
 endif()
+
+if (NOT HAVE_CXX_ATOMICS64_WITHOUT_LIB )
+list(APPEND LLDB_SYSTEM_LIBS atomic)
+endif()
+
 # On FreeBSD/NetBSD backtrace() is provided by libexecinfo, not libc.
 if (CMAKE_SYSTEM_NAME MATCHES "FreeBSD" OR CMAKE_SYSTEM_NAME MATCHES "NetBSD")
   list(APPEND LLDB_SYSTEM_LIBS execinfo)


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[Lldb-commits] [lldb] r255619 - [LLDB][MIPS] Added support for MIPS1, MIPS2, MIPS3, MIPS4 and MIPS5 instruction sets

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Mon Dec 14 23:50:55 2015
New Revision: 255619

URL: http://llvm.org/viewvc/llvm-project?rev=255619&view=rev
Log:
[LLDB][MIPS] Added support for MIPS1, MIPS2, MIPS3, MIPS4 and MIPS5 instruction 
sets

Patch by Nitesh Jain.

Summary: This Patch will allowed LLDB to debug respective instruction sets 
binaries.

Reviewers: jaydeep, clayborg
Subscribers: lldb-commits, mohit.bhakkad, sagar, bhushan
Differential: http://reviews.llvm.org/D15487

Modified:
lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp

Modified: lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp?rev=255619&r1=255618&r2=255619&view=diff
==
--- lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp (original)
+++ lldb/trunk/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp Mon Dec 14 
23:50:55 2015
@@ -328,6 +328,11 @@ mipsVariantFromElfFlags(const elf::elf_w
 
 switch (mips_arch)
 {
+case llvm::ELF::EF_MIPS_ARCH_1:
+case llvm::ELF::EF_MIPS_ARCH_2:
+case llvm::ELF::EF_MIPS_ARCH_3:
+case llvm::ELF::EF_MIPS_ARCH_4:
+case llvm::ELF::EF_MIPS_ARCH_5:
 case llvm::ELF::EF_MIPS_ARCH_32:
 return (endian == ELFDATA2LSB) ? ArchSpec::eMIPSSubType_mips32el : 
ArchSpec::eMIPSSubType_mips32;
 case llvm::ELF::EF_MIPS_ARCH_32R2:


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Re: [Lldb-commits] [PATCH] D15487: [LLDB][MIPS] Added support for MIPS1, MIPS2, MIPS3, MIPS4 and MIPS5 instruction sets

[Sagar Thakur via lldb-commits]

sagar closed this revision.
sagar added a comment.

Committed in revision 255619 on behalf of Nitesh Jain.


Repository:
  rL LLVM

http://reviews.llvm.org/D15487



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[Lldb-commits] [PATCH] D15884: [LLDB][MIPS] Make register read/write to set/get the size of register according to abi.

[Sagar Thakur via lldb-commits]

sagar created this revision.
sagar added reviewers: clayborg, tberghammer.
sagar added subscribers: jaydeep, bhushan, mohit.bhakkad, nitesh.jain, 
lldb-commits.
sagar set the repository for this revision to rL LLVM.

For O32 abi register size should be 4 bytes.
For N32 and N64 abi register size should be 8 bytes.
This patch will make register read/write to set/get the size of register 
according to abi.



Repository:
  rL LLVM

http://reviews.llvm.org/D15884

Files:
  source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp

Index: source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
===
--- source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
+++ source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
@@ -1388,7 +1388,7 @@
 {
 lldb_private::ArchSpec arch;
 if (m_thread.GetProcess()->GetArchitecture(arch))
-value.SetBytes((void *)(((unsigned char *)®s) + offset + 4 * 
(arch.GetMachine() == llvm::Triple::mips)), arch.GetAddressByteSize(), 
arch.GetByteOrder());
+value.SetBytes((void *)(((unsigned char *)®s) + offset + 4 * 
(arch.GetMachine() == llvm::Triple::mips)), 4 + (!(arch.GetFlags() & 
lldb_private::ArchSpec::eMIPSABI_O32) * 4), arch.GetByteOrder());
 else
 error.SetErrorString("failed to get architecture");
 }
@@ -1404,8 +1404,14 @@
 Error error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGS, 
m_thread.GetID(), NULL, ®s, sizeof regs);
 if (error.Success())
 {
-::memcpy((void *)(((unsigned char *)(®s)) + offset), 
value.GetBytes(), 8);
-error = NativeProcessLinux::PtraceWrapper(PTRACE_SETREGS, 
m_thread.GetID(), NULL, ®s, sizeof regs);
+lldb_private::ArchSpec arch;
+if (m_thread.GetProcess()->GetArchitecture(arch))
+{
+::memcpy((void *)(((unsigned char *)(®s)) + offset), 
value.GetBytes(), 4 + (!(arch.GetFlags() & 
lldb_private::ArchSpec::eMIPSABI_O32) * 4));
+error = NativeProcessLinux::PtraceWrapper(PTRACE_SETREGS, 
m_thread.GetID(), NULL, ®s, sizeof regs);
+}
+else
+error.SetErrorString("failed to get architecture");
 }
 return error;
 }


Index: source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
===
--- source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
+++ source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
@@ -1388,7 +1388,7 @@
 {
 lldb_private::ArchSpec arch;
 if (m_thread.GetProcess()->GetArchitecture(arch))
-value.SetBytes((void *)(((unsigned char *)®s) + offset + 4 * (arch.GetMachine() == llvm::Triple::mips)), arch.GetAddressByteSize(), arch.GetByteOrder());
+value.SetBytes((void *)(((unsigned char *)®s) + offset + 4 * (arch.GetMachine() == llvm::Triple::mips)), 4 + (!(arch.GetFlags() & lldb_private::ArchSpec::eMIPSABI_O32) * 4), arch.GetByteOrder());
 else
 error.SetErrorString("failed to get architecture");
 }
@@ -1404,8 +1404,14 @@
 Error error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGS, m_thread.GetID(), NULL, ®s, sizeof regs);
 if (error.Success())
 {
-::memcpy((void *)(((unsigned char *)(®s)) + offset), value.GetBytes(), 8);
-error = NativeProcessLinux::PtraceWrapper(PTRACE_SETREGS, m_thread.GetID(), NULL, ®s, sizeof regs);
+lldb_private::ArchSpec arch;
+if (m_thread.GetProcess()->GetArchitecture(arch))
+{
+::memcpy((void *)(((unsigned char *)(®s)) + offset), value.GetBytes(), 4 + (!(arch.GetFlags() & lldb_private::ArchSpec::eMIPSABI_O32) * 4));
+error = NativeProcessLinux::PtraceWrapper(PTRACE_SETREGS, m_thread.GetID(), NULL, ®s, sizeof regs);
+}
+else
+error.SetErrorString("failed to get architecture");
 }
 return error;
 }
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[Lldb-commits] [lldb] r256834 - [LLDB][MIPS] Make register read/write to set/get the size of register according to abi.

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Tue Jan  5 08:03:45 2016
New Revision: 256834

URL: http://llvm.org/viewvc/llvm-project?rev=256834&view=rev
Log:
[LLDB][MIPS] Make register read/write to set/get the size of register according 
to abi.

Summary:
For O32 abi register size should be 4 bytes.
For N32 and N64 abi register size should be 8 bytes.
This patch will make register read/write to set/get the size of register 
according to abi.

Reviewers: clayborg, tberghammer
Subscribers: lldb-commits, nitesh.jain, mohit.bhakkad, bhushan, jaydeep
Differential: http://reviews.llvm.org/D15884

Modified:

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp

Modified: 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp?rev=256834&r1=256833&r2=256834&view=diff
==
--- 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp 
(original)
+++ 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp 
Tue Jan  5 08:03:45 2016
@@ -1388,7 +1388,7 @@ NativeRegisterContextLinux_mips64::DoRea
 {
 lldb_private::ArchSpec arch;
 if (m_thread.GetProcess()->GetArchitecture(arch))
-value.SetBytes((void *)(((unsigned char *)®s) + offset + 4 * 
(arch.GetMachine() == llvm::Triple::mips)), arch.GetAddressByteSize(), 
arch.GetByteOrder());
+value.SetBytes((void *)(((unsigned char *)®s) + offset + 4 * 
(arch.GetMachine() == llvm::Triple::mips)), arch.GetFlags() & 
lldb_private::ArchSpec::eMIPSABI_O32 ? 4 : 8, arch.GetByteOrder());
 else
 error.SetErrorString("failed to get architecture");
 }
@@ -1404,8 +1404,14 @@ NativeRegisterContextLinux_mips64::DoWri
 Error error = NativeProcessLinux::PtraceWrapper(PTRACE_GETREGS, 
m_thread.GetID(), NULL, ®s, sizeof regs);
 if (error.Success())
 {
-::memcpy((void *)(((unsigned char *)(®s)) + offset), 
value.GetBytes(), 8);
-error = NativeProcessLinux::PtraceWrapper(PTRACE_SETREGS, 
m_thread.GetID(), NULL, ®s, sizeof regs);
+lldb_private::ArchSpec arch;
+if (m_thread.GetProcess()->GetArchitecture(arch))
+{
+::memcpy((void *)(((unsigned char *)(®s)) + offset), 
value.GetBytes(), arch.GetFlags() & lldb_private::ArchSpec::eMIPSABI_O32 ? 4 : 
8);
+error = NativeProcessLinux::PtraceWrapper(PTRACE_SETREGS, 
m_thread.GetID(), NULL, ®s, sizeof regs);
+}
+else
+error.SetErrorString("failed to get architecture");
 }
 return error;
 }


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Re: [Lldb-commits] [PATCH] D15884: [LLDB][MIPS] Make register read/write to set/get the size of register according to abi.

[Sagar Thakur via lldb-commits]

sagar closed this revision.
sagar marked an inline comment as done.
sagar added a comment.

Committed in revision 256834


Repository:
  rL LLVM

http://reviews.llvm.org/D15884



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[Lldb-commits] [lldb] r257587 - [LLDB][MIPS] Fix TestDisassembleRawData.py

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Wed Jan 13 05:22:56 2016
New Revision: 257587

URL: http://llvm.org/viewvc/llvm-project?rev=257587&view=rev
Log:
[LLDB][MIPS] Fix TestDisassembleRawData.py

Patch by Nitesh Jain.

Summary: This patch adds check for the correctness of disassembling instruction 
for MIPS target.

Reviewers: emaste, clayborg, ovyalov
Subscribers: lldb-commits, mohit.bhakkad, sagar, bhushan, jaydeep
Differential: http://reviews.llvm.org/D15915

Modified:

lldb/trunk/packages/Python/lldbsuite/test/python_api/disassemble-raw-data/TestDisassembleRawData.py

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/python_api/disassemble-raw-data/TestDisassembleRawData.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/python_api/disassemble-raw-data/TestDisassembleRawData.py?rev=257587&r1=257586&r2=257587&view=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/python_api/disassemble-raw-data/TestDisassembleRawData.py
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/python_api/disassemble-raw-data/TestDisassembleRawData.py
 Wed Jan 13 05:22:56 2016
@@ -21,11 +21,18 @@ class DisassembleRawDataTestCase(TestBas
 def test_disassemble_raw_data(self):
 """Test disassembling raw bytes with the API."""
 # Create a target from the debugger.
-target = self.dbg.CreateTargetWithFileAndTargetTriple ("", "x86_64")
+arch = self.getArchitecture()
+if re.match("mips*el",arch):
+target = self.dbg.CreateTargetWithFileAndTargetTriple ("", 
"mipsel")
+raw_bytes = bytearray([0x21,0xf0, 0xa0, 0x03])
+elif re.match("mips",arch):
+target = self.dbg.CreateTargetWithFileAndTargetTriple ("", "mips")
+raw_bytes = bytearray([0x03,0xa0, 0xf0, 0x21])
+else:
+target = self.dbg.CreateTargetWithFileAndTargetTriple ("", 
"x86_64")
+raw_bytes = bytearray([0x48, 0x89, 0xe5])
+
 self.assertTrue(target, VALID_TARGET)
-
-raw_bytes = bytearray([0x48, 0x89, 0xe5])
-
 insts = target.GetInstructions(lldb.SBAddress(0, target), raw_bytes)
 
 inst = insts.GetInstructionAtIndex(0)
@@ -34,6 +41,9 @@ class DisassembleRawDataTestCase(TestBas
 print()
 print("Raw bytes:", [hex(x) for x in raw_bytes])
 print("Disassembled%s" % str(inst))
- 
-self.assertTrue (inst.GetMnemonic(target) == "movq")
-self.assertTrue (inst.GetOperands(target) == '%' + "rsp, " + '%' + 
"rbp")
+if re.match("mips",arch):
+self.assertTrue (inst.GetMnemonic(target) == "move")
+self.assertTrue (inst.GetOperands(target) == '$' + "fp, " + '$' + 
"sp")
+else:
+self.assertTrue (inst.GetMnemonic(target) == "movq")
+self.assertTrue (inst.GetOperands(target) == '%' + "rsp, " + '%' + 
"rbp")


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Re: [Lldb-commits] [PATCH] D15915: [LLDB][MIPS] Fix TestDisassembleRawData.py

[Sagar Thakur via lldb-commits]

sagar closed this revision.
sagar added a comment.

Committed in revision 257587 on behalf of Nitesh Jain.


Repository:
  rL LLVM

http://reviews.llvm.org/D15915



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[Lldb-commits] [lldb] r258684 - [LLDB][MIPS] Fix TestExprsChar.py

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Mon Jan 25 06:27:46 2016
New Revision: 258684

URL: http://llvm.org/viewvc/llvm-project?rev=258684&view=rev
Log:
[LLDB][MIPS] Fix TestExprsChar.py

Patch by Nitesh Jain.

Summary: When incorrect type used for 'char' then (at least) one of the 
expression evaluates to incorrect value. Please refer to bug llvm.org/pr23069

Reviewers: ovyalov, clayborg
Subscribers: lldb-commits, mohit.bhakkad, sagar, bhushan, jaydeep
Differential: reviews.llvm.org/D16132

Modified:

lldb/trunk/packages/Python/lldbsuite/test/expression_command/char/TestExprsChar.py

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/expression_command/char/TestExprsChar.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/expression_command/char/TestExprsChar.py?rev=258684&r1=258683&r2=258684&view=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/expression_command/char/TestExprsChar.py
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/expression_command/char/TestExprsChar.py
 Mon Jan 25 06:27:46 2016
@@ -65,5 +65,6 @@ class ExprCharTestCase(TestBase):
 @expectedFailurei386("llvm.org/pr23069")
 @expectedFailurex86_64("llvm.org/pr23069")
 @expectedFailureWindows("llvm.org/pr21765")
+@expectedFailureAll(bugnumber="llvm.org/pr23069", triple = 'mips*')
 def test_unsigned_char(self):
 self.do_test(dictionary={'CFLAGS_EXTRAS': '-funsigned-char'})


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Re: [Lldb-commits] [PATCH] D16132: [LLDB][MIPS] Fix TestExprsChar.py

[Sagar Thakur via lldb-commits]

sagar closed this revision.
sagar added a comment.

Committed in revision 258684


Repository:
  rL LLVM

http://reviews.llvm.org/D16132



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[Lldb-commits] [lldb] r258685 - [LLDB][MIPS] Fix TestPrintStackTraces.py

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Mon Jan 25 06:33:03 2016
New Revision: 258685

URL: http://llvm.org/viewvc/llvm-project?rev=258685&view=rev
Log:
[LLDB][MIPS] Fix TestPrintStackTraces.py

Patch by Nitesh Jain.

Summary: The thread_start function in libc doesn't contain any epilogue and 
prologue instructions. Hence unwinding fail when we are stopped in thread_start.

Reviewers: ovyalov, clayborg
Subscribers: lldb-commits, mohit.bhakkad, sagar, bhushan, jaydeep
Differential: reviews.llvm.org/D16136

Modified:

lldb/trunk/packages/Python/lldbsuite/test/python_api/lldbutil/process/TestPrintStackTraces.py

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/python_api/lldbutil/process/TestPrintStackTraces.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/python_api/lldbutil/process/TestPrintStackTraces.py?rev=258685&r1=258684&r2=258685&view=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/python_api/lldbutil/process/TestPrintStackTraces.py
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/python_api/lldbutil/process/TestPrintStackTraces.py
 Mon Jan 25 06:33:03 2016
@@ -22,6 +22,10 @@ class ThreadsStackTracesTestCase(TestBas
 self.line = line_number('main.cpp', '// Set break point at this line.')
 
 @expectedFailureAll("llvm.org/pr23043", ["linux"], archs=["i386"]) # We 
are unable to produce a backtrace of the main thread when the thread is blocked 
in fgets
+
+#The __thread_start function in libc doesn't contain any epilogue and 
prologue instructions 
+#hence unwinding fail when we are stopped in __thread_start
+@expectedFailureAll(triple = 'mips*')
 @expectedFailureWindows("llvm.org/pr24778")
 @add_test_categories(['pyapi'])
 def test_stack_traces(self):


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Re: [Lldb-commits] [PATCH] D16136: [LLDB][MIPS] Fix TestPrintStackTraces.py

[Sagar Thakur via lldb-commits]

sagar closed this revision.
sagar added a comment.

Committed in revision 258685.


Repository:
  rL LLVM

http://reviews.llvm.org/D16136



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[Lldb-commits] [lldb] r262011 - [LLDB][MIPS] Fix TestInferiorAssert.py for MIPS

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Fri Feb 26 07:30:34 2016
New Revision: 262011

URL: http://llvm.org/viewvc/llvm-project?rev=262011&view=rev
Log:
[LLDB][MIPS] Fix TestInferiorAssert.py for MIPS

Patch by Nitesh Jain.

Summary: The debug version of libc.so is require for backtracing which may not 
be available on all platforms.

Reviewers: ovyalov, clayborg
Subscribers: zturner, lldb-commits, mohit.bhakkad, sagar, bhushan, jaydeep
Differential: http://reviews.llvm.org/D17131

Modified:

lldb/trunk/packages/Python/lldbsuite/test/functionalities/inferior-assert/TestInferiorAssert.py

Modified: 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/inferior-assert/TestInferiorAssert.py
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/packages/Python/lldbsuite/test/functionalities/inferior-assert/TestInferiorAssert.py?rev=262011&r1=262010&r2=262011&view=diff
==
--- 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/inferior-assert/TestInferiorAssert.py
 (original)
+++ 
lldb/trunk/packages/Python/lldbsuite/test/functionalities/inferior-assert/TestInferiorAssert.py
 Fri Feb 26 07:30:34 2016
@@ -17,6 +17,7 @@ class AssertingInferiorTestCase(TestBase
 
 @expectedFailureAll(oslist=["windows"], bugnumber="llvm.org/pr21793: need 
to implement support for detecting assertion / abort on Windows")
 @expectedFailureAll(oslist=["linux"], archs=["arm"], 
bugnumber="llvm.org/pr25338")
+@expectedFailureAll(bugnumber="llvm.org/pr26592", triple = '^mips')
 def test_inferior_asserting(self):
 """Test that lldb reliably catches the inferior asserting (command)."""
 self.build()
@@ -31,6 +32,7 @@ class AssertingInferiorTestCase(TestBase
 
 @expectedFailureAll(oslist=["windows"], bugnumber="llvm.org/pr21793: need 
to implement support for detecting assertion / abort on Windows")
 @expectedFailureAll(oslist=["linux"], archs=["aarch64", "arm"], 
bugnumber="llvm.org/pr25338")
+@expectedFailureAll(bugnumber="llvm.org/pr26592", triple = '^mips')
 def test_inferior_asserting_disassemble(self):
 """Test that lldb reliably disassembles frames after asserting 
(command)."""
 self.build()
@@ -45,6 +47,7 @@ class AssertingInferiorTestCase(TestBase
 
 @expectedFailureAll(oslist=["windows"], bugnumber="llvm.org/pr21793: need 
to implement support for detecting assertion / abort on Windows")
 @expectedFailureAll(oslist=["linux"], archs=["aarch64", "arm"], 
bugnumber="llvm.org/pr25338")
+@expectedFailureAll(bugnumber="llvm.org/pr26592", triple = '^mips')
 def test_inferior_asserting_expr(self):
 """Test that the lldb expression interpreter can read from the 
inferior after asserting (command)."""
 self.build()
@@ -52,6 +55,7 @@ class AssertingInferiorTestCase(TestBase
 
 @expectedFailureAll(oslist=["windows"], bugnumber="llvm.org/pr21793: need 
to implement support for detecting assertion / abort on Windows")
 @expectedFailureAll(oslist=["linux"], archs=["aarch64", "arm"], 
bugnumber="llvm.org/pr25338")
+@expectedFailureAll(bugnumber="llvm.org/pr26592", triple = '^mips')
 def test_inferior_asserting_step(self):
 """Test that lldb functions correctly after stepping through a call to 
assert()."""
 self.build()


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Re: [Lldb-commits] [PATCH] D17131: [LLDB][MIPS] Fix TestInferiorAssert.py for MIPS

[Sagar Thakur via lldb-commits]

sagar closed this revision.
sagar added a comment.

Committed in revision 262011.


Repository:
  rL LLVM

http://reviews.llvm.org/D17131



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Re: [Lldb-commits] [PATCH] D18853: [LLDB][MIPS] Fix Floating point Registers Encoding

[Sagar Thakur via lldb-commits]

sagar accepted this revision.
sagar added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
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http://reviews.llvm.org/D18853



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Re: [Lldb-commits] [PATCH] D12100: [LLDB] Use llvm::APInt and llvm::APFloat in Scalar and RegisterValue

[Sagar Thakur via lldb-commits]

sagar added a comment.

Hi,

I have corrected the patch for Scalar which was reverted in r245222 and 
addressed all concerns raised (http://reviews.llvm.org/rL245216) by Pavel 
Labath.
Could you please review it?


Repository:
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http://reviews.llvm.org/D12100



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Re: [Lldb-commits] [PATCH] D12100: [LLDB] Use llvm::APInt and llvm::APFloat in Scalar and RegisterValue

[Sagar Thakur via lldb-commits]

sagar added inline comments.


Comment at: include/lldb/Core/RegisterValue.h:185
@@ -190,1 +184,3 @@
+llvm::APInt
+GetAsUInt128 (llvm::APInt& fail_value, bool *success_ptr = NULL) const;
 

ovyalov wrote:
> Could you pass fail_value as a const reference?
Yes, I have changed fail_value to const reference.


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[Lldb-commits] [lldb] r245927 - Fix build on mips

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Tue Aug 25 04:52:59 2015
New Revision: 245927

URL: http://llvm.org/viewvc/llvm-project?rev=245927&view=rev
Log:
Fix build on mips

Setting and getting register values as bytes instead of depending on the 128 
bit integer support in register value.
This patch will fix the build failure in the release branch.

Reviewers: tberghammer, clayborg, hans
Subscribers: bhushan, nitesh.jain, jaydeep, lldb-commits
Differential: http://reviews.llvm.org/D12275

Modified:

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp

Modified: 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp?rev=245927&r1=245926&r2=245927&view=diff
==
--- 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp 
(original)
+++ 
lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp 
Tue Aug 25 04:52:59 2015
@@ -584,7 +584,6 @@ NativeRegisterContextLinux_mips64::ReadR
 if (IsMSA(reg) || IsFPR(reg))
 {
 uint8_t *src;
-type128 int128;
 
 error = ReadCP1();
 
@@ -604,9 +603,6 @@ NativeRegisterContextLinux_mips64::ReadR
 assert (reg_info->byte_offset < sizeof(UserArea));
 src = (uint8_t *)&m_msa + reg_info->byte_offset - (sizeof(m_gpr) + 
sizeof(m_fpr));
 }
-int128.x[0] = *(uint64_t *)src;
-int128.x[1] = *(uint64_t *)(src + 8);
-llvm::APInt rhs = llvm::APInt(128, 2, int128.x);
 switch (reg_info->byte_size)
 {
 case 4:
@@ -616,7 +612,7 @@ NativeRegisterContextLinux_mips64::ReadR
 reg_value.SetUInt64(*(uint64_t *)src);
 break;
 case 16:
-reg_value.SetUInt128(rhs);
+reg_value.SetBytes((const void *)src, 16, GetByteOrder());
 break;
 default:
 assert(false && "Unhandled data size.");
@@ -660,7 +656,7 @@ NativeRegisterContextLinux_mips64::Write
 if (IsFPR(reg_index) || IsMSA(reg_index))
 {
 uint8_t *dst;
-const uint64_t *src;
+uint64_t *src;
 
 // Initialise the FP and MSA buffers by reading all co-processor 1 
registers
 ReadCP1();
@@ -675,8 +671,6 @@ NativeRegisterContextLinux_mips64::Write
 assert (reg_info->byte_offset < sizeof(UserArea));
 dst = (uint8_t *)&m_msa + reg_info->byte_offset - (sizeof(m_gpr) + 
sizeof(m_fpr));
 }
-llvm::APInt lhs;
-llvm::APInt fail_value = llvm::APInt::getMaxValue(128);
 switch (reg_info->byte_size)
 {
 case 4:
@@ -686,8 +680,7 @@ NativeRegisterContextLinux_mips64::Write
 *(uint64_t *)dst = reg_value.GetAsUInt64();
 break;
 case 16:
-lhs = reg_value.GetAsUInt128(fail_value);
-src = lhs.getRawData();
+src = (uint64_t *)reg_value.GetBytes();
 *(uint64_t *)dst = *src;
 *(uint64_t *)(dst + 8) = *(src + 1);
 break;


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Re: [Lldb-commits] [PATCH] D12275: Fix build on mips

[Sagar Thakur via lldb-commits]

sagar added a comment.

Hi Hans,

I have committed it to the trunk in revision 245927.  You can now merge it to 
the release branch.

Thanks,
Sagar


Repository:
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[Lldb-commits] [PATCH] D12356: [MIPS64] Emulate MSA branch instructions

[Sagar Thakur via lldb-commits]

sagar created this revision.
sagar added reviewers: jaydeep, clayborg.
sagar added subscribers: bhushan, mohit.bhakkad, nitesh.jain, lldb-commits.
sagar set the repository for this revision to rL LLVM.

This patch adds MSA branch instruction emulation for MIPS64.

Repository:
  rL LLVM

http://reviews.llvm.org/D12356

Files:
  source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
  source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h

Index: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
===
--- source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
+++ source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
@@ -302,6 +302,36 @@
 Emulate_BC1ANY4T  (llvm::MCInst& insn);
 
 bool
+Emulate_BNZB  (llvm::MCInst& insn);
+
+bool
+Emulate_BNZH  (llvm::MCInst& insn);
+
+bool
+Emulate_BNZW  (llvm::MCInst& insn);
+
+bool
+Emulate_BNZD  (llvm::MCInst& insn);
+
+bool
+Emulate_BZB  (llvm::MCInst& insn);
+
+bool
+Emulate_BZH  (llvm::MCInst& insn);
+
+bool
+Emulate_BZW  (llvm::MCInst& insn); 
+
+bool
+Emulate_BZD  (llvm::MCInst& insn); 
+
+bool
+Emulate_BNZV  (llvm::MCInst& insn);
+
+ bool
+Emulate_BZV  (llvm::MCInst& insn);
+
+bool
 nonvolatile_reg_p (uint64_t regnum);
 
 const char *
Index: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
===
--- source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
+++ source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
@@ -256,6 +256,38 @@
 case gcc_dwarf_f29_mips64: return "f29";
 case gcc_dwarf_f30_mips64: return "f30";
 case gcc_dwarf_f31_mips64: return "f31";
+case gcc_dwarf_w0_mips64:  return "w0";
+case gcc_dwarf_w1_mips64:  return "w1";
+case gcc_dwarf_w2_mips64:  return "w2";
+case gcc_dwarf_w3_mips64:  return "w3";
+case gcc_dwarf_w4_mips64:  return "w4";
+case gcc_dwarf_w5_mips64:  return "w5";
+case gcc_dwarf_w6_mips64:  return "w6";
+case gcc_dwarf_w7_mips64:  return "w7";
+case gcc_dwarf_w8_mips64:  return "w8";
+case gcc_dwarf_w9_mips64:  return "w9";
+case gcc_dwarf_w10_mips64: return "w10";
+case gcc_dwarf_w11_mips64: return "w11";
+case gcc_dwarf_w12_mips64: return "w12";
+case gcc_dwarf_w13_mips64: return "w13";
+case gcc_dwarf_w14_mips64: return "w14";
+case gcc_dwarf_w15_mips64: return "w15";
+case gcc_dwarf_w16_mips64: return "w16";
+case gcc_dwarf_w17_mips64: return "w17";
+case gcc_dwarf_w18_mips64: return "w18";
+case gcc_dwarf_w19_mips64: return "w19";
+case gcc_dwarf_w20_mips64: return "w20";
+case gcc_dwarf_w21_mips64: return "w21";
+case gcc_dwarf_w22_mips64: return "w22";
+case gcc_dwarf_w23_mips64: return "w23";
+case gcc_dwarf_w24_mips64: return "w24";
+case gcc_dwarf_w25_mips64: return "w25";
+case gcc_dwarf_w26_mips64: return "w26";
+case gcc_dwarf_w27_mips64: return "w27";
+case gcc_dwarf_w28_mips64: return "w28";
+case gcc_dwarf_w29_mips64: return "w29";
+case gcc_dwarf_w30_mips64: return "w30";
+case gcc_dwarf_w31_mips64: return "w31";
 default:
 break;
 }
@@ -336,6 +368,41 @@
 case gcc_dwarf_f31_mips64:  return "f31";
 case gcc_dwarf_fcsr_mips64: return "fcsr";
 case gcc_dwarf_fir_mips64:  return "fir";
+case gcc_dwarf_w0_mips64:   return "w0";
+case gcc_dwarf_w1_mips64:   return "w1";
+case gcc_dwarf_w2_mips64:   return "w2";
+case gcc_dwarf_w3_mips64:   return "w3";
+case gcc_dwarf_w4_mips64:   return "w4";
+case gcc_dwarf_w5_mips64:   return "w5";
+case gcc_dwarf_w6_mips64:   return "w6";
+case gcc_dwarf_w7_mips64:   return "w7";
+case gcc_dwarf_w8_mips64:   return "w8";
+case gcc_dwarf_w9_mips64:   return "w9";
+case gcc_dwarf_w10_mips64:  return "w10";
+case gcc_dwarf_w11_mips64:  return "w11";
+case gcc_dwarf_w12_mips64:  return "w12";
+case gcc_dwarf_w13_mips64:  return "w13";
+case gcc_dwarf_w14_mips64:  return "w14";
+case gcc_dwarf_w15_mips64:  return "w15";
+case gcc_dwarf_w16_mips64:  return "w16";
+case gcc_dwarf_w17_mips64:  return "w17";
+case gcc_dwarf_w18_mips64:  return "w18";
+case gcc_dwarf_w19_mips64:  return "w19";
+case gcc_dwarf_w20_mips64:  return "w20";
+case gcc_dwarf_w21_mips64:  return

Re: [Lldb-commits] [PATCH] D12356: [MIPS64] Emulate MSA branch instructions

[Sagar Thakur via lldb-commits]

sagar updated this revision to Diff 33323.
sagar added a comment.

Addressed review comments


Repository:
  rL LLVM

http://reviews.llvm.org/D12356

Files:
  source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
  source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h

Index: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
===
--- source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
+++ source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
@@ -302,6 +302,42 @@
 Emulate_BC1ANY4T  (llvm::MCInst& insn);
 
 bool
+Emulate_BNZB  (llvm::MCInst& insn);
+
+bool
+Emulate_BNZH  (llvm::MCInst& insn);
+
+bool
+Emulate_BNZW  (llvm::MCInst& insn);
+
+bool
+Emulate_BNZD  (llvm::MCInst& insn);
+
+bool
+Emulate_BZB  (llvm::MCInst& insn);
+
+bool
+Emulate_BZH  (llvm::MCInst& insn);
+
+bool
+Emulate_BZW  (llvm::MCInst& insn);
+
+bool
+Emulate_BZD  (llvm::MCInst& insn);
+
+bool
+Emulate_MSA_Branch_DF (llvm::MCInst& insn, int element_byte_size, bool bnz);
+
+bool
+Emulate_BNZV  (llvm::MCInst& insn);
+
+bool
+Emulate_BZV  (llvm::MCInst& insn);
+
+bool
+Emulate_MSA_Branch_V (llvm::MCInst& insn, bool bnz);
+
+bool
 nonvolatile_reg_p (uint64_t regnum);
 
 const char *
Index: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
===
--- source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
+++ source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
@@ -256,6 +256,41 @@
 case gcc_dwarf_f29_mips64: return "f29";
 case gcc_dwarf_f30_mips64: return "f30";
 case gcc_dwarf_f31_mips64: return "f31";
+case gcc_dwarf_w0_mips64:  return "w0";
+case gcc_dwarf_w1_mips64:  return "w1";
+case gcc_dwarf_w2_mips64:  return "w2";
+case gcc_dwarf_w3_mips64:  return "w3";
+case gcc_dwarf_w4_mips64:  return "w4";
+case gcc_dwarf_w5_mips64:  return "w5";
+case gcc_dwarf_w6_mips64:  return "w6";
+case gcc_dwarf_w7_mips64:  return "w7";
+case gcc_dwarf_w8_mips64:  return "w8";
+case gcc_dwarf_w9_mips64:  return "w9";
+case gcc_dwarf_w10_mips64: return "w10";
+case gcc_dwarf_w11_mips64: return "w11";
+case gcc_dwarf_w12_mips64: return "w12";
+case gcc_dwarf_w13_mips64: return "w13";
+case gcc_dwarf_w14_mips64: return "w14";
+case gcc_dwarf_w15_mips64: return "w15";
+case gcc_dwarf_w16_mips64: return "w16";
+case gcc_dwarf_w17_mips64: return "w17";
+case gcc_dwarf_w18_mips64: return "w18";
+case gcc_dwarf_w19_mips64: return "w19";
+case gcc_dwarf_w20_mips64: return "w20";
+case gcc_dwarf_w21_mips64: return "w21";
+case gcc_dwarf_w22_mips64: return "w22";
+case gcc_dwarf_w23_mips64: return "w23";
+case gcc_dwarf_w24_mips64: return "w24";
+case gcc_dwarf_w25_mips64: return "w25";
+case gcc_dwarf_w26_mips64: return "w26";
+case gcc_dwarf_w27_mips64: return "w27";
+case gcc_dwarf_w28_mips64: return "w28";
+case gcc_dwarf_w29_mips64: return "w29";
+case gcc_dwarf_w30_mips64: return "w30";
+case gcc_dwarf_w31_mips64: return "w31";
+case gcc_dwarf_mir_mips64: return "mir";
+case gcc_dwarf_mcsr_mips64: return "mcsr";
+case gcc_dwarf_config5_mips64: return "config5";
 default:
 break;
 }
@@ -336,6 +371,41 @@
 case gcc_dwarf_f31_mips64:  return "f31";
 case gcc_dwarf_fcsr_mips64: return "fcsr";
 case gcc_dwarf_fir_mips64:  return "fir";
+case gcc_dwarf_w0_mips64:   return "w0";
+case gcc_dwarf_w1_mips64:   return "w1";
+case gcc_dwarf_w2_mips64:   return "w2";
+case gcc_dwarf_w3_mips64:   return "w3";
+case gcc_dwarf_w4_mips64:   return "w4";
+case gcc_dwarf_w5_mips64:   return "w5";
+case gcc_dwarf_w6_mips64:   return "w6";
+case gcc_dwarf_w7_mips64:   return "w7";
+case gcc_dwarf_w8_mips64:   return "w8";
+case gcc_dwarf_w9_mips64:   return "w9";
+case gcc_dwarf_w10_mips64:  return "w10";
+case gcc_dwarf_w11_mips64:  return "w11";
+case gcc_dwarf_w12_mips64:  return "w12";
+case gcc_dwarf_w13_mips64:  return "w13";
+case gcc_dwarf_w14_mips64:  return "w14";
+case gcc_dwarf_w15_mips64:  return "w15";
+case gcc_dwarf_w16_mips64:  return "w16";
+case gcc_dwarf_w17_mips64:  return "w17";
+case gcc_dwarf_w18_mips64:  return "

Re: [Lldb-commits] [PATCH] D12356: [MIPS64] Emulate MSA branch instructions

[Sagar Thakur via lldb-commits]

sagar updated this revision to Diff 33567.
sagar added a comment.

Addressed review commenst


Repository:
  rL LLVM

http://reviews.llvm.org/D12356

Files:
  source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
  source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h

Index: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
===
--- source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
+++ source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
@@ -302,6 +302,42 @@
 Emulate_BC1ANY4T  (llvm::MCInst& insn);
 
 bool
+Emulate_BNZB  (llvm::MCInst& insn);
+
+bool
+Emulate_BNZH  (llvm::MCInst& insn);
+
+bool
+Emulate_BNZW  (llvm::MCInst& insn);
+
+bool
+Emulate_BNZD  (llvm::MCInst& insn);
+
+bool
+Emulate_BZB  (llvm::MCInst& insn);
+
+bool
+Emulate_BZH  (llvm::MCInst& insn);
+
+bool
+Emulate_BZW  (llvm::MCInst& insn);
+
+bool
+Emulate_BZD  (llvm::MCInst& insn);
+
+bool
+Emulate_MSA_Branch_DF (llvm::MCInst& insn, int element_byte_size, bool bnz);
+
+bool
+Emulate_BNZV  (llvm::MCInst& insn);
+
+bool
+Emulate_BZV  (llvm::MCInst& insn);
+
+bool
+Emulate_MSA_Branch_V (llvm::MCInst& insn, bool bnz);
+
+bool
 nonvolatile_reg_p (uint64_t regnum);
 
 const char *
Index: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
===
--- source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
+++ source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
@@ -256,6 +256,41 @@
 case gcc_dwarf_f29_mips64: return "f29";
 case gcc_dwarf_f30_mips64: return "f30";
 case gcc_dwarf_f31_mips64: return "f31";
+case gcc_dwarf_w0_mips64:  return "w0";
+case gcc_dwarf_w1_mips64:  return "w1";
+case gcc_dwarf_w2_mips64:  return "w2";
+case gcc_dwarf_w3_mips64:  return "w3";
+case gcc_dwarf_w4_mips64:  return "w4";
+case gcc_dwarf_w5_mips64:  return "w5";
+case gcc_dwarf_w6_mips64:  return "w6";
+case gcc_dwarf_w7_mips64:  return "w7";
+case gcc_dwarf_w8_mips64:  return "w8";
+case gcc_dwarf_w9_mips64:  return "w9";
+case gcc_dwarf_w10_mips64: return "w10";
+case gcc_dwarf_w11_mips64: return "w11";
+case gcc_dwarf_w12_mips64: return "w12";
+case gcc_dwarf_w13_mips64: return "w13";
+case gcc_dwarf_w14_mips64: return "w14";
+case gcc_dwarf_w15_mips64: return "w15";
+case gcc_dwarf_w16_mips64: return "w16";
+case gcc_dwarf_w17_mips64: return "w17";
+case gcc_dwarf_w18_mips64: return "w18";
+case gcc_dwarf_w19_mips64: return "w19";
+case gcc_dwarf_w20_mips64: return "w20";
+case gcc_dwarf_w21_mips64: return "w21";
+case gcc_dwarf_w22_mips64: return "w22";
+case gcc_dwarf_w23_mips64: return "w23";
+case gcc_dwarf_w24_mips64: return "w24";
+case gcc_dwarf_w25_mips64: return "w25";
+case gcc_dwarf_w26_mips64: return "w26";
+case gcc_dwarf_w27_mips64: return "w27";
+case gcc_dwarf_w28_mips64: return "w28";
+case gcc_dwarf_w29_mips64: return "w29";
+case gcc_dwarf_w30_mips64: return "w30";
+case gcc_dwarf_w31_mips64: return "w31";
+case gcc_dwarf_mir_mips64: return "mir";
+case gcc_dwarf_mcsr_mips64: return "mcsr";
+case gcc_dwarf_config5_mips64: return "config5";
 default:
 break;
 }
@@ -336,6 +371,41 @@
 case gcc_dwarf_f31_mips64:  return "f31";
 case gcc_dwarf_fcsr_mips64: return "fcsr";
 case gcc_dwarf_fir_mips64:  return "fir";
+case gcc_dwarf_w0_mips64:   return "w0";
+case gcc_dwarf_w1_mips64:   return "w1";
+case gcc_dwarf_w2_mips64:   return "w2";
+case gcc_dwarf_w3_mips64:   return "w3";
+case gcc_dwarf_w4_mips64:   return "w4";
+case gcc_dwarf_w5_mips64:   return "w5";
+case gcc_dwarf_w6_mips64:   return "w6";
+case gcc_dwarf_w7_mips64:   return "w7";
+case gcc_dwarf_w8_mips64:   return "w8";
+case gcc_dwarf_w9_mips64:   return "w9";
+case gcc_dwarf_w10_mips64:  return "w10";
+case gcc_dwarf_w11_mips64:  return "w11";
+case gcc_dwarf_w12_mips64:  return "w12";
+case gcc_dwarf_w13_mips64:  return "w13";
+case gcc_dwarf_w14_mips64:  return "w14";
+case gcc_dwarf_w15_mips64:  return "w15";
+case gcc_dwarf_w16_mips64:  return "w16";
+case gcc_dwarf_w17_mips64:  return "w17";
+case gcc_dwarf_w18_mips64:  return "

Re: [Lldb-commits] [PATCH] D12356: [MIPS64] Emulate MSA branch instructions

[Sagar Thakur via lldb-commits]

sagar marked 7 inline comments as done.


Comment at: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp:3160
@@ +3159,3 @@
+if((*ptr == 0 && bnz) || (*ptr != 0 && !bnz) )
+branch_hit = false;
+break;

The former one is more readable.


Comment at: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp:3187
@@ +3186,3 @@
+context.type = eContextRelativeBranchImmediate;
+
+if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, 
gcc_dwarf_pc_mips64, target))

I have set the type to eContextRelativeBranchImmediate for now we are using 
these instructions for single stepping only.


Comment at: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp:3230
@@ +3229,3 @@
+else
+target = pc + 8;
+

The former one is more readable.


Comment at: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp:3236
@@ +3235,3 @@
+if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, 
gcc_dwarf_pc_mips64, target))
+return false;
+

I have set the type to eContextRelativeBranchImmediate for now we are using 
these instructions for single stepping only.


Repository:
  rL LLVM

http://reviews.llvm.org/D12356



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Re: [Lldb-commits] [PATCH] D12356: [MIPS64] Emulate MSA branch instructions

[Sagar Thakur via lldb-commits]

sagar updated this revision to Diff 33668.
sagar marked 4 inline comments as done.
sagar added a comment.

Corrected code indent and initialized wr_val correctly.


Repository:
  rL LLVM

http://reviews.llvm.org/D12356

Files:
  source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
  source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h

Index: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
===
--- source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
+++ source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h
@@ -302,6 +302,42 @@
 Emulate_BC1ANY4T  (llvm::MCInst& insn);
 
 bool
+Emulate_BNZB  (llvm::MCInst& insn);
+
+bool
+Emulate_BNZH  (llvm::MCInst& insn);
+
+bool
+Emulate_BNZW  (llvm::MCInst& insn);
+
+bool
+Emulate_BNZD  (llvm::MCInst& insn);
+
+bool
+Emulate_BZB  (llvm::MCInst& insn);
+
+bool
+Emulate_BZH  (llvm::MCInst& insn);
+
+bool
+Emulate_BZW  (llvm::MCInst& insn);
+
+bool
+Emulate_BZD  (llvm::MCInst& insn);
+
+bool
+Emulate_MSA_Branch_DF (llvm::MCInst& insn, int element_byte_size, bool bnz);
+
+bool
+Emulate_BNZV  (llvm::MCInst& insn);
+
+bool
+Emulate_BZV  (llvm::MCInst& insn);
+
+bool
+Emulate_MSA_Branch_V (llvm::MCInst& insn, bool bnz);
+
+bool
 nonvolatile_reg_p (uint64_t regnum);
 
 const char *
Index: source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
===
--- source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
+++ source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
@@ -221,41 +221,76 @@
 {
 switch (reg_num)
 {
-case gcc_dwarf_sp_mips64:  return "r29"; 
-case gcc_dwarf_r30_mips64: return "r30"; 
-case gcc_dwarf_ra_mips64:  return "r31";
-case gcc_dwarf_f0_mips64:  return "f0";
-case gcc_dwarf_f1_mips64:  return "f1";
-case gcc_dwarf_f2_mips64:  return "f2";
-case gcc_dwarf_f3_mips64:  return "f3";
-case gcc_dwarf_f4_mips64:  return "f4";
-case gcc_dwarf_f5_mips64:  return "f5";
-case gcc_dwarf_f6_mips64:  return "f6";
-case gcc_dwarf_f7_mips64:  return "f7";
-case gcc_dwarf_f8_mips64:  return "f8";
-case gcc_dwarf_f9_mips64:  return "f9";
-case gcc_dwarf_f10_mips64: return "f10";
-case gcc_dwarf_f11_mips64: return "f11";
-case gcc_dwarf_f12_mips64: return "f12";
-case gcc_dwarf_f13_mips64: return "f13";
-case gcc_dwarf_f14_mips64: return "f14";
-case gcc_dwarf_f15_mips64: return "f15";
-case gcc_dwarf_f16_mips64: return "f16";
-case gcc_dwarf_f17_mips64: return "f17";
-case gcc_dwarf_f18_mips64: return "f18";
-case gcc_dwarf_f19_mips64: return "f19";
-case gcc_dwarf_f20_mips64: return "f20";
-case gcc_dwarf_f21_mips64: return "f21";
-case gcc_dwarf_f22_mips64: return "f22";
-case gcc_dwarf_f23_mips64: return "f23";
-case gcc_dwarf_f24_mips64: return "f24";
-case gcc_dwarf_f25_mips64: return "f25";
-case gcc_dwarf_f26_mips64: return "f26";
-case gcc_dwarf_f27_mips64: return "f27";
-case gcc_dwarf_f28_mips64: return "f28";
-case gcc_dwarf_f29_mips64: return "f29";
-case gcc_dwarf_f30_mips64: return "f30";
-case gcc_dwarf_f31_mips64: return "f31";
+case gcc_dwarf_sp_mips64:  return "r29"; 
+case gcc_dwarf_r30_mips64: return "r30"; 
+case gcc_dwarf_ra_mips64:  return "r31";
+case gcc_dwarf_f0_mips64:  return "f0";
+case gcc_dwarf_f1_mips64:  return "f1";
+case gcc_dwarf_f2_mips64:  return "f2";
+case gcc_dwarf_f3_mips64:  return "f3";
+case gcc_dwarf_f4_mips64:  return "f4";
+case gcc_dwarf_f5_mips64:  return "f5";
+case gcc_dwarf_f6_mips64:  return "f6";
+case gcc_dwarf_f7_mips64:  return "f7";
+case gcc_dwarf_f8_mips64:  return "f8";
+case gcc_dwarf_f9_mips64:  return "f9";
+case gcc_dwarf_f10_mips64: return "f10";
+case gcc_dwarf_f11_mips64: return "f11";
+case gcc_dwarf_f12_mips64: return "f12";
+case gcc_dwarf_f13_mips64: return "f13";
+case gcc_dwarf_f14_mips64: return "f14";
+case gcc_dwarf_f15_mips64: return "f15";
+case gcc_dwarf_f16_mips64: return "f16";
+case gcc_dwarf_f17_mips64: return "f17";
+case gcc_dwarf_f18_mips64: return "f18";
+case gcc_dwarf_f19_mips64: return "f19";
+ 

[Lldb-commits] [lldb] r246745 - [MIPS64] Emulate MSA branch instructions

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Wed Sep  2 22:57:44 2015
New Revision: 246745

URL: http://llvm.org/viewvc/llvm-project?rev=246745&view=rev
Log:
[MIPS64] Emulate MSA branch instructions

This patch adds MSA branch instruction emulation for MIPS64.

Reviewers: tberghammer, jaydeep
Subscribers: tberghammer, lldb-commits, nitesh.jain, mohit.bhakkad (Mohit 
Bhakkad), bhushan (Bhushan Attarde)
Differential: http://reviews.llvm.org/D12356

Modified:
lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h

Modified: 
lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp?rev=246745&r1=246744&r2=246745&view=diff
==
--- lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp 
(original)
+++ lldb/trunk/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp 
Wed Sep  2 22:57:44 2015
@@ -221,41 +221,76 @@ EmulateInstructionMIPS64::GetRegisterNam
 {
 switch (reg_num)
 {
-case gcc_dwarf_sp_mips64:  return "r29"; 
-case gcc_dwarf_r30_mips64: return "r30"; 
-case gcc_dwarf_ra_mips64:  return "r31";
-case gcc_dwarf_f0_mips64:  return "f0";
-case gcc_dwarf_f1_mips64:  return "f1";
-case gcc_dwarf_f2_mips64:  return "f2";
-case gcc_dwarf_f3_mips64:  return "f3";
-case gcc_dwarf_f4_mips64:  return "f4";
-case gcc_dwarf_f5_mips64:  return "f5";
-case gcc_dwarf_f6_mips64:  return "f6";
-case gcc_dwarf_f7_mips64:  return "f7";
-case gcc_dwarf_f8_mips64:  return "f8";
-case gcc_dwarf_f9_mips64:  return "f9";
-case gcc_dwarf_f10_mips64: return "f10";
-case gcc_dwarf_f11_mips64: return "f11";
-case gcc_dwarf_f12_mips64: return "f12";
-case gcc_dwarf_f13_mips64: return "f13";
-case gcc_dwarf_f14_mips64: return "f14";
-case gcc_dwarf_f15_mips64: return "f15";
-case gcc_dwarf_f16_mips64: return "f16";
-case gcc_dwarf_f17_mips64: return "f17";
-case gcc_dwarf_f18_mips64: return "f18";
-case gcc_dwarf_f19_mips64: return "f19";
-case gcc_dwarf_f20_mips64: return "f20";
-case gcc_dwarf_f21_mips64: return "f21";
-case gcc_dwarf_f22_mips64: return "f22";
-case gcc_dwarf_f23_mips64: return "f23";
-case gcc_dwarf_f24_mips64: return "f24";
-case gcc_dwarf_f25_mips64: return "f25";
-case gcc_dwarf_f26_mips64: return "f26";
-case gcc_dwarf_f27_mips64: return "f27";
-case gcc_dwarf_f28_mips64: return "f28";
-case gcc_dwarf_f29_mips64: return "f29";
-case gcc_dwarf_f30_mips64: return "f30";
-case gcc_dwarf_f31_mips64: return "f31";
+case gcc_dwarf_sp_mips64:  return "r29"; 
+case gcc_dwarf_r30_mips64: return "r30"; 
+case gcc_dwarf_ra_mips64:  return "r31";
+case gcc_dwarf_f0_mips64:  return "f0";
+case gcc_dwarf_f1_mips64:  return "f1";
+case gcc_dwarf_f2_mips64:  return "f2";
+case gcc_dwarf_f3_mips64:  return "f3";
+case gcc_dwarf_f4_mips64:  return "f4";
+case gcc_dwarf_f5_mips64:  return "f5";
+case gcc_dwarf_f6_mips64:  return "f6";
+case gcc_dwarf_f7_mips64:  return "f7";
+case gcc_dwarf_f8_mips64:  return "f8";
+case gcc_dwarf_f9_mips64:  return "f9";
+case gcc_dwarf_f10_mips64: return "f10";
+case gcc_dwarf_f11_mips64: return "f11";
+case gcc_dwarf_f12_mips64: return "f12";
+case gcc_dwarf_f13_mips64: return "f13";
+case gcc_dwarf_f14_mips64: return "f14";
+case gcc_dwarf_f15_mips64: return "f15";
+case gcc_dwarf_f16_mips64: return "f16";
+case gcc_dwarf_f17_mips64: return "f17";
+case gcc_dwarf_f18_mips64: return "f18";
+case gcc_dwarf_f19_mips64: return "f19";
+case gcc_dwarf_f20_mips64: return "f20";
+case gcc_dwarf_f21_mips64: return "f21";
+case gcc_dwarf_f22_mips64: return "f22";
+case gcc_dwarf_f23_mips64: return "f23";
+case gcc_dwarf_f24_mips64: return "f24";
+case gcc_dwarf_f25_mips64: return "f25";
+case gcc_dwarf_f26_mips64: return "f26";
+case gcc_dwarf_f27_mips64: return "f27";
+case gcc_dwarf_f28_mips64: return "f28";
+case gcc_dwarf_f29_mips64: return "f

Re: [Lldb-commits] [PATCH] D12356: [MIPS64] Emulate MSA branch instructions

[Sagar Thakur via lldb-commits]

sagar closed this revision.
sagar added a comment.

Committed in revision 246745


Repository:
  rL LLVM

http://reviews.llvm.org/D12356



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[Lldb-commits] [lldb] r248277 - [MIPS32] Emulate MSA instructions for MIPS32

[Sagar Thakur via lldb-commits]

Author: slthakur
Date: Tue Sep 22 08:57:11 2015
New Revision: 248277

URL: http://llvm.org/viewvc/llvm-project?rev=248277&view=rev
Log:
[MIPS32] Emulate MSA instructions for MIPS32

This patch adds MSA branch instruction emulation for MIPS32.

Reviewers: tberghammer, jaydeep
Subscribers: mohit.bhakkad, bhushan, nitesh.jain
Differential: http://reviews.llvm.org/D12898

Modified:
lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h

Modified: lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
URL: 
http://llvm.org/viewvc/llvm-project/lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp?rev=248277&r1=248276&r2=248277&view=diff
==
--- lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp 
(original)
+++ lldb/trunk/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp Tue 
Sep 22 08:57:11 2015
@@ -221,41 +221,76 @@ EmulateInstructionMIPS::GetRegisterName
 {
 switch (reg_num)
 {
-case dwarf_sp_mips:  return "r29"; 
-case dwarf_r30_mips: return "r30"; 
-case dwarf_ra_mips:  return "r31";
-case dwarf_f0_mips:  return "f0";
-case dwarf_f1_mips:  return "f1";
-case dwarf_f2_mips:  return "f2";
-case dwarf_f3_mips:  return "f3";
-case dwarf_f4_mips:  return "f4";
-case dwarf_f5_mips:  return "f5";
-case dwarf_f6_mips:  return "f6";
-case dwarf_f7_mips:  return "f7";
-case dwarf_f8_mips:  return "f8";
-case dwarf_f9_mips:  return "f9";
-case dwarf_f10_mips: return "f10";
-case dwarf_f11_mips: return "f11";
-case dwarf_f12_mips: return "f12";
-case dwarf_f13_mips: return "f13";
-case dwarf_f14_mips: return "f14";
-case dwarf_f15_mips: return "f15";
-case dwarf_f16_mips: return "f16";
-case dwarf_f17_mips: return "f17";
-case dwarf_f18_mips: return "f18";
-case dwarf_f19_mips: return "f19";
-case dwarf_f20_mips: return "f20";
-case dwarf_f21_mips: return "f21";
-case dwarf_f22_mips: return "f22";
-case dwarf_f23_mips: return "f23";
-case dwarf_f24_mips: return "f24";
-case dwarf_f25_mips: return "f25";
-case dwarf_f26_mips: return "f26";
-case dwarf_f27_mips: return "f27";
-case dwarf_f28_mips: return "f28";
-case dwarf_f29_mips: return "f29";
-case dwarf_f30_mips: return "f30";
-case dwarf_f31_mips: return "f31";
+case dwarf_sp_mips:  return "r29"; 
+case dwarf_r30_mips: return "r30"; 
+case dwarf_ra_mips:  return "r31";
+case dwarf_f0_mips:  return "f0";
+case dwarf_f1_mips:  return "f1";
+case dwarf_f2_mips:  return "f2";
+case dwarf_f3_mips:  return "f3";
+case dwarf_f4_mips:  return "f4";
+case dwarf_f5_mips:  return "f5";
+case dwarf_f6_mips:  return "f6";
+case dwarf_f7_mips:  return "f7";
+case dwarf_f8_mips:  return "f8";
+case dwarf_f9_mips:  return "f9";
+case dwarf_f10_mips: return "f10";
+case dwarf_f11_mips: return "f11";
+case dwarf_f12_mips: return "f12";
+case dwarf_f13_mips: return "f13";
+case dwarf_f14_mips: return "f14";
+case dwarf_f15_mips: return "f15";
+case dwarf_f16_mips: return "f16";
+case dwarf_f17_mips: return "f17";
+case dwarf_f18_mips: return "f18";
+case dwarf_f19_mips: return "f19";
+case dwarf_f20_mips: return "f20";
+case dwarf_f21_mips: return "f21";
+case dwarf_f22_mips: return "f22";
+case dwarf_f23_mips: return "f23";
+case dwarf_f24_mips: return "f24";
+case dwarf_f25_mips: return "f25";
+case dwarf_f26_mips: return "f26";
+case dwarf_f27_mips: return "f27";
+case dwarf_f28_mips: return "f28";
+case dwarf_f29_mips: return "f29";
+case dwarf_f30_mips: return "f30";
+case dwarf_f31_mips: return "f31";
+case gcc_dwarf_w0_mips:  return "w0";
+case gcc_dwarf_w1_mips:  return "w1";
+case gcc_dwarf_w2_mips:  return "w2";
+case gcc_dwarf_w3_mips:  return "w3";
+case gcc_d