[Lldb-commits] [mlir] [clang-tools-extra] [clang] [lldb] [llvm] [compiler-rt] [libc] [flang] [DAGCombiner] Combine frem into fdiv+ftrunc+fma (PR #67642)
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/67642
>From 2ff3a666e4347f9224c1a406126282d98e3c9633 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Thu, 28 Sep 2023 16:09:40 +0800
Subject: [PATCH 1/2] [DAGCombiner] Combine frem into fdiv+ftrunc+fma
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 12 ++
llvm/test/CodeGen/PowerPC/frem.ll | 142 +-
2 files changed, 49 insertions(+), 105 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 0d34ebb117667aa..2f5f295e199188a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -16958,6 +16958,18 @@ SDValue DAGCombiner::visitFREM(SDNode *N) {
if (SDValue NewSel = foldBinOpIntoSelect(N))
return NewSel;
+ // (frem x, y) -> (fma (fneg (ftrunc (fdiv x, y))), y, x)
+ if (Flags.hasApproximateFuncs() && Flags.hasNoSignedZeros() &&
+ Flags.hasNoInfs() && !TLI.isOperationLegalOrCustom(ISD::FREM, VT) &&
+ TLI.isOperationLegalOrCustom(ISD::FTRUNC, VT) &&
+ TLI.isOperationLegalOrCustom(ISD::FMA, VT)) {
+SDLoc Loc(N);
+SDValue Div = DAG.getNode(ISD::FDIV, Loc, VT, N0, N1);
+SDValue Trunc = DAG.getNode(ISD::FTRUNC, Loc, VT, Div);
+return DAG.getNode(ISD::FMA, Loc, VT,
+ DAG.getNode(ISD::FNEG, Loc, VT, Trunc), N1, N0);
+ }
+
return SDValue();
}
diff --git a/llvm/test/CodeGen/PowerPC/frem.ll
b/llvm/test/CodeGen/PowerPC/frem.ll
index 8cb68e60f7f9b71..dff9c796289e96e 100644
--- a/llvm/test/CodeGen/PowerPC/frem.ll
+++ b/llvm/test/CodeGen/PowerPC/frem.ll
@@ -4,16 +4,13 @@
define float @frem32(float %a, float %b) {
; CHECK-LABEL: frem32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT:mflr 0
-; CHECK-NEXT:stdu 1, -32(1)
-; CHECK-NEXT:std 0, 48(1)
-; CHECK-NEXT:.cfi_def_cfa_offset 32
-; CHECK-NEXT:.cfi_offset lr, 16
-; CHECK-NEXT:bl fmodf
-; CHECK-NEXT:nop
-; CHECK-NEXT:addi 1, 1, 32
-; CHECK-NEXT:ld 0, 16(1)
-; CHECK-NEXT:mtlr 0
+; CHECK-NEXT:xsresp 0, 2
+; CHECK-NEXT:fmr 4, 1
+; CHECK-NEXT:xsmulsp 3, 1, 0
+; CHECK-NEXT:xsnmsubasp 4, 2, 3
+; CHECK-NEXT:xsmaddasp 3, 0, 4
+; CHECK-NEXT:xsrdpiz 0, 3
+; CHECK-NEXT:xsnmsubasp 1, 0, 2
; CHECK-NEXT:blr
entry:
%rem = frem fast float %a, %b
@@ -23,16 +20,17 @@ entry:
define double @frem64(double %a, double %b) {
; CHECK-LABEL: frem64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT:mflr 0
-; CHECK-NEXT:stdu 1, -32(1)
-; CHECK-NEXT:std 0, 48(1)
-; CHECK-NEXT:.cfi_def_cfa_offset 32
-; CHECK-NEXT:.cfi_offset lr, 16
-; CHECK-NEXT:bl fmod
-; CHECK-NEXT:nop
-; CHECK-NEXT:addi 1, 1, 32
-; CHECK-NEXT:ld 0, 16(1)
-; CHECK-NEXT:mtlr 0
+; CHECK-NEXT:vspltisw 2, -1
+; CHECK-NEXT:xsredp 0, 2
+; CHECK-NEXT:fmr 4, 1
+; CHECK-NEXT:xvcvsxwdp 3, 34
+; CHECK-NEXT:xsmaddadp 3, 2, 0
+; CHECK-NEXT:xsnmsubadp 0, 0, 3
+; CHECK-NEXT:xsmuldp 3, 1, 0
+; CHECK-NEXT:xsnmsubadp 4, 2, 3
+; CHECK-NEXT:xsmaddadp 3, 0, 4
+; CHECK-NEXT:xsrdpiz 0, 3
+; CHECK-NEXT:xsnmsubadp 1, 0, 2
; CHECK-NEXT:blr
entry:
%rem = frem fast double %a, %b
@@ -42,59 +40,13 @@ entry:
define <4 x float> @frem4x32(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: frem4x32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT:mflr 0
-; CHECK-NEXT:stdu 1, -96(1)
-; CHECK-NEXT:std 0, 112(1)
-; CHECK-NEXT:.cfi_def_cfa_offset 96
-; CHECK-NEXT:.cfi_offset lr, 16
-; CHECK-NEXT:.cfi_offset v28, -64
-; CHECK-NEXT:.cfi_offset v29, -48
-; CHECK-NEXT:.cfi_offset v30, -32
-; CHECK-NEXT:.cfi_offset v31, -16
-; CHECK-NEXT:xxsldwi 0, 34, 34, 3
-; CHECK-NEXT:stxv 60, 32(1) # 16-byte Folded Spill
-; CHECK-NEXT:xscvspdpn 1, 0
-; CHECK-NEXT:xxsldwi 0, 35, 35, 3
-; CHECK-NEXT:stxv 61, 48(1) # 16-byte Folded Spill
-; CHECK-NEXT:stxv 62, 64(1) # 16-byte Folded Spill
-; CHECK-NEXT:stxv 63, 80(1) # 16-byte Folded Spill
-; CHECK-NEXT:xscvspdpn 2, 0
-; CHECK-NEXT:vmr 31, 3
-; CHECK-NEXT:vmr 30, 2
-; CHECK-NEXT:bl fmodf
-; CHECK-NEXT:nop
-; CHECK-NEXT:xxsldwi 0, 62, 62, 1
-; CHECK-NEXT:xscpsgndp 61, 1, 1
-; CHECK-NEXT:xscvspdpn 1, 0
-; CHECK-NEXT:xxsldwi 0, 63, 63, 1
-; CHECK-NEXT:xscvspdpn 2, 0
-; CHECK-NEXT:bl fmodf
-; CHECK-NEXT:nop
-; CHECK-NEXT:# kill: def $f1 killed $f1 def $vsl1
-; CHECK-NEXT:xxmrghd 0, 1, 61
-; CHECK-NEXT:xscvspdpn 1, 62
-; CHECK-NEXT:xscvspdpn 2, 63
-; CHECK-NEXT:xvcvdpsp 60, 0
-; CHECK-NEXT:bl fmodf
-; CHECK-NEXT:nop
-; CHECK-NEXT:xxswapd 0, 62
-; CHECK-NEXT:xscpsgndp 61, 1, 1
-; CHECK-NEXT:xscvspdpn 1, 0
-; CHECK-NEXT:xxswapd 0, 63
-; CHECK-NEXT:xscvspdpn 2, 0
-; CHECK-NEXT:bl fmodf
-; CHECK-NEXT:nop
-; CHECK-NEXT:# kill: def $f1 killed $f1 def $vsl1
-; CHECK-NEXT:xxmrghd 0, 61, 1
-; CHE
[Lldb-commits] [lldb] [clang] [libc] [libcxxabi] [libunwind] [llvm] [flang] [libcxx] [lld] [clang-tools-extra] [compiler-rt] [PowerPC] Combine sub within setcc back to sext (PR #66978)
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/66978
>From 2a7b9be6cd0705590c85c51b35ea99fe053aaf47 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 6 Sep 2023 16:16:34 +0800
Subject: [PATCH 1/4] [PowerPC] Combine sub within setcc back to sext
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 37 +-
llvm/test/CodeGen/PowerPC/setcc-to-sub.ll | 42 +
2 files changed, 69 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index f4e3531980d165f..4659ebef35ecf62 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -14407,15 +14407,18 @@ SDValue
PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
ShiftCst);
}
-SDValue PPCTargetLowering::combineSetCC(SDNode *N,
-DAGCombinerInfo &DCI) const {
- assert(N->getOpcode() == ISD::SETCC &&
- "Should be called with a SETCC node");
+SDValue PPCTargetLowering::combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const
{
+ assert(N->getOpcode() == ISD::SETCC && "Should be called with a SETCC node");
ISD::CondCode CC = cast(N->getOperand(2))->get();
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ SDLoc DL(N);
+ SelectionDAG &DAG = DCI.DAG;
+ EVT VT = N->getValueType(0);
+ EVT OpVT = LHS.getValueType();
+
if (CC == ISD::SETNE || CC == ISD::SETEQ) {
-SDValue LHS = N->getOperand(0);
-SDValue RHS = N->getOperand(1);
// If there is a '0 - y' pattern, canonicalize the pattern to the RHS.
if (LHS.getOpcode() == ISD::SUB && isNullConstant(LHS.getOperand(0)) &&
@@ -14426,15 +14429,29 @@ SDValue PPCTargetLowering::combineSetCC(SDNode *N,
// x != 0-y --> x+y != 0
if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
RHS.hasOneUse()) {
- SDLoc DL(N);
- SelectionDAG &DAG = DCI.DAG;
- EVT VT = N->getValueType(0);
- EVT OpVT = LHS.getValueType();
SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LHS, RHS.getOperand(1));
return DAG.getSetCC(DL, VT, Add, DAG.getConstant(0, DL, OpVT), CC);
}
}
+ // Combine (a-2^(M-1)) => sext(trunc(a, M), 64)
+ if (CC == ISD::SETULT && LHS.getOpcode() == ISD::ADD && OpVT == MVT::i64 &&
+ isa(RHS) && isa(LHS.getOperand(1))) {
+uint64_t ShiftVal =
+~(cast(LHS.getOperand(1))->getZExtValue()) + 1;
+uint64_t CmpVal = ~(cast(RHS)->getZExtValue()) + 1;
+if (isPowerOf2_64(ShiftVal) && ShiftVal << 1 == CmpVal) {
+ unsigned DestBits = Log2_64(CmpVal);
+ if (DestBits == 8 || DestBits == 16 || DestBits == 32) {
+SDValue Conv =
+DAG.getSExtOrTrunc(DAG.getSExtOrTrunc(LHS.getOperand(0), DL,
+ MVT::getIntegerVT(DestBits)),
+ DL, OpVT);
+return DAG.getSetCC(DL, VT, LHS.getOperand(0), Conv, ISD::SETNE);
+ }
+}
+ }
+
return DAGCombineTruncBoolExt(N, DCI);
}
diff --git a/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll
b/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll
index 13c629b6349450c..ce75b77eed29666 100644
--- a/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll
+++ b/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll
@@ -89,6 +89,48 @@ entry:
ret i1 %cmp.i5
}
+define zeroext i1 @test5(i64 %a) {
+; CHECK-LABEL: test5:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:extsw 4, 3
+; CHECK-NEXT:xor 3, 3, 4
+; CHECK-NEXT:addic 4, 3, -1
+; CHECK-NEXT:subfe 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+ %0 = add i64 %a, -2147483648
+ %cmp = icmp ult i64 %0, -4294967296
+ ret i1 %cmp
+}
+
+define zeroext i1 @test6(i64 %a) {
+; CHECK-LABEL: test6:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:extsh 4, 3
+; CHECK-NEXT:xor 3, 3, 4
+; CHECK-NEXT:addic 4, 3, -1
+; CHECK-NEXT:subfe 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+ %0 = add i64 %a, -32768
+ %cmp = icmp ult i64 %0, -65536
+ ret i1 %cmp
+}
+
+define zeroext i1 @test7(i64 %a) {
+; CHECK-LABEL: test7:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:extsb 4, 3
+; CHECK-NEXT:xor 3, 3, 4
+; CHECK-NEXT:addic 4, 3, -1
+; CHECK-NEXT:subfe 3, 4, 3
+; CHECK-NEXT:blr
+entry:
+ %0 = add i64 %a, -128
+ %cmp = icmp ult i64 %0, -256
+ ret i1 %cmp
+}
+
!1 = !{!2, !2, i64 0}
!2 = !{!"int", !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0}
>From fbb7e6362d6223f8e0ee6014e000c1cc5ae6e777 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 6 Sep 2023 16:16:34 +0800
Subject: [PATCH 2/4] [PowerPC] Combine sub within setcc back to sext
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 37 +-
llvm/test/CodeGen/PowerPC/setcc-to-sub.ll | 42 +
2 files changed, 69 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index f4e3531980d165f..4659
[Lldb-commits] [clang-tools-extra] [libc] [compiler-rt] [lldb] [flang] [clang] [llvm] [mlir] [DAGCombiner] Combine frem into fdiv+ftrunc+fma (PR #67642)
ecnelises wrote: I tested with a number of random floating values. In most of the cases, the expanded result is exactly the same as libcall result. But when `fmod(a,b)` is very close to `b` (smaller than `1e-10`, for example, `fmod(521862.045173469, 31.048432006988875)`), the result would be totally wrong.. I'm thinking about a solution. https://github.com/llvm/llvm-project/pull/67642 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang-tools-extra] [clang] [libcxx] [lld] [libc] [llvm] [flang] [lldb] [compiler-rt] [Legalizer] Expand fmaximum and fminimum (PR #67301)
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/67301
>From 92abb76631594dfc2ca586c46c38031610be0548 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Mon, 25 Sep 2023 17:08:59 +0800
Subject: [PATCH 1/5] [Legalizer] Expand fmaximum and fminimum
According to langref, llvm.maximum/minimum has -0.0 < +0.0 semantics and
propagates NaN.
Expand the nodes on targets not supporting the operation, by adding
extra check for NaN and using is_fpclass to check zero signs.
---
llvm/include/llvm/CodeGen/TargetLowering.h| 3 +
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 6 +
.../SelectionDAG/LegalizeVectorOps.cpp| 7 +
.../CodeGen/SelectionDAG/TargetLowering.cpp | 58 ++
llvm/lib/Target/ARM/ARMISelLowering.cpp | 14 +-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 10 +-
.../CodeGen/ARM/minnum-maxnum-intrinsics.ll | 28 +-
.../CodeGen/PowerPC/fminimum-fmaximum-f128.ll | 97 ++
.../test/CodeGen/PowerPC/fminimum-fmaximum.ll | 847 ++
9 files changed, 1039 insertions(+), 31 deletions(-)
create mode 100644 llvm/test/CodeGen/PowerPC/fminimum-fmaximum-f128.ll
create mode 100644 llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h
b/llvm/include/llvm/CodeGen/TargetLowering.h
index c6a7aa17146dd4..429cfd72af2e6e 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -5089,6 +5089,9 @@ class TargetLowering : public TargetLoweringBase {
/// Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted
inputs.
SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const;
+ /// Expand fminimum/fmaximum into multiple comparison with selects.
+ SDValue expandFMINIMUM_FMAXIMUM(SDNode *N, SelectionDAG &DAG) const;
+
/// Expand FP_TO_[US]INT_SAT into FP_TO_[US]INT and selects or min/max.
/// \param N Node to expand
/// \returns The expansion result
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index f19beea3a3ed8b..33f6354d558454 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3540,6 +3540,12 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
Results.push_back(Expanded);
break;
}
+ case ISD::FMINIMUM:
+ case ISD::FMAXIMUM: {
+if (SDValue Expanded = TLI.expandFMINIMUM_FMAXIMUM(Node, DAG))
+ Results.push_back(Expanded);
+break;
+ }
case ISD::FSIN:
case ISD::FCOS: {
EVT VT = Node->getValueType(0);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index dec81475f3a88f..db132035adcf29 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -949,6 +949,13 @@ void VectorLegalizer::Expand(SDNode *Node,
SmallVectorImpl &Results) {
return;
}
break;
+ case ISD::FMINIMUM:
+ case ISD::FMAXIMUM:
+if (SDValue Expanded = TLI.expandFMINIMUM_FMAXIMUM(Node, DAG)) {
+ Results.push_back(Expanded);
+ return;
+}
+break;
case ISD::SMIN:
case ISD::SMAX:
case ISD::UMIN:
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 39489e0bf142eb..23de9829b5e9ff 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -8177,6 +8177,64 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode
*Node,
return SDValue();
}
+SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
+SelectionDAG &DAG) const {
+ SDLoc DL(N);
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ unsigned Opc = N->getOpcode();
+ EVT VT = N->getValueType(0);
+ EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
+ bool NoNaN = (N->getFlags().hasNoNaNs() ||
+(DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)));
+ bool NoZeroSign =
+ (N->getFlags().hasNoSignedZeros() || DAG.isKnownNeverZeroFloat(LHS) ||
+ DAG.isKnownNeverZeroFloat(RHS));
+ bool IsMax = Opc == ISD::FMAXIMUM;
+
+ if (VT.isVector() &&
+ isOperationLegalOrCustomOrPromote(Opc, VT.getScalarType()))
+return SDValue();
+
+ SDValue MinMax;
+ if (isOperationLegalOrCustom(IsMax ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE,
+ VT))
+MinMax = DAG.getNode(IsMax ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE, DL, VT,
+ LHS, RHS);
+ else if (isOperationLegalOrCustom(IsMax ? ISD::FMAXNUM : ISD::FMINNUM, VT))
+MinMax = DAG.getNode(IsMax ? ISD::FMAXNUM : ISD::FMINNUM, DL, VT, LHS,
RHS);
+ else
+MinMax = DAG.getSelect(
+DL, VT,
+DAG.getSetCC(DL, CCVT, LHS, RHS, IsMax ? ISD::SETGT : ISD::SETLT), LHS,
+RHS);
+
+ // Propagate
[Lldb-commits] [clang-tools-extra] [clang] [libcxx] [lld] [libc] [llvm] [flang] [lldb] [compiler-rt] [Legalizer] Expand fmaximum and fminimum (PR #67301)
@@ -8262,6 +8262,64 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode
*Node,
return SDValue();
}
+SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
+SelectionDAG &DAG) const {
+ SDLoc DL(N);
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ unsigned Opc = N->getOpcode();
+ EVT VT = N->getValueType(0);
+ EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
+ bool IsMax = Opc == ISD::FMAXIMUM;
+
+ if (VT.isVector() &&
+ isOperationLegalOrCustomOrPromote(Opc, VT.getScalarType()))
+return SDValue();
+
+ // First, implement comparison not propagating NaN. If no native fmin or fmax
+ // available, use plain select with setcc instead.
+ SDValue MinMax;
+ if (isOperationLegalOrCustom(IsMax ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE,
+ VT)) {
+MinMax = DAG.getNode(IsMax ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE, DL, VT,
+ LHS, RHS);
+ } else if (isOperationLegalOrCustom(IsMax ? ISD::FMAXNUM : ISD::FMINNUM,
+ VT)) {
+MinMax = DAG.getNode(IsMax ? ISD::FMAXNUM : ISD::FMINNUM, DL, VT, LHS,
RHS);
+ } else {
+SDValue Compare =
+DAG.getSetCC(DL, CCVT, LHS, RHS, IsMax ? ISD::SETGT : ISD::SETLT);
+MinMax = DAG.getSelect(DL, VT, Compare, LHS, RHS);
+ }
+
+ // Propagate any NaN of both operands
+ if (!N->getFlags().hasNoNaNs() &&
+ (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) {
+ConstantFP *FPNaN = ConstantFP::get(
+*DAG.getContext(), APFloat::getNaN(DAG.EVTToAPFloatSemantics(VT)));
+MinMax = DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, LHS, RHS,
ISD::SETUO),
+ DAG.getConstantFP(*FPNaN, DL, VT), MinMax);
+ }
+
+ // fminimum/fmaximum requires -0.0 less than +0.0
+ if (!N->getFlags().hasNoSignedZeros() && !DAG.isKnownNeverZeroFloat(LHS) &&
+ !DAG.isKnownNeverZeroFloat(RHS)) {
+SDValue IsZero = DAG.getSetCC(DL, CCVT, MinMax,
+ DAG.getConstantFP(0.0, DL, VT), ISD::SETEQ);
+SDValue TestZero =
+DAG.getTargetConstant(IsMax ? fcPosZero : fcNegZero, DL, MVT::i32);
+SDValue LCmp = DAG.getSelect(
+DL, VT, DAG.getNode(ISD::IS_FPCLASS, DL, CCVT, LHS, TestZero), LHS,
+MinMax);
+SDValue RCmp = DAG.getSelect(
+DL, VT, DAG.getNode(ISD::IS_FPCLASS, DL, CCVT, RHS, TestZero), RHS,
+LCmp);
+MinMax = DAG.getSelect(DL, VT, IsZero, RCmp, MinMax);
ecnelises wrote:
We still need isfpclass to know which is negative/positive zero and whether
both are zeros, I think.
https://github.com/llvm/llvm-project/pull/67301
___
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lldb-commits@lists.llvm.org
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[Lldb-commits] [clang-tools-extra] [clang] [libcxx] [lld] [libc] [llvm] [flang] [lldb] [compiler-rt] [Legalizer] Expand fmaximum and fminimum (PR #67301)
@@ -8262,6 +8262,64 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode
*Node,
return SDValue();
}
+SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
+SelectionDAG &DAG) const {
+ SDLoc DL(N);
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ unsigned Opc = N->getOpcode();
+ EVT VT = N->getValueType(0);
+ EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
+ bool IsMax = Opc == ISD::FMAXIMUM;
+
+ if (VT.isVector() &&
+ isOperationLegalOrCustomOrPromote(Opc, VT.getScalarType()))
+return SDValue();
+
+ // First, implement comparison not propagating NaN. If no native fmin or fmax
+ // available, use plain select with setcc instead.
+ SDValue MinMax;
+ if (isOperationLegalOrCustom(IsMax ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE,
+ VT)) {
+MinMax = DAG.getNode(IsMax ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE, DL, VT,
+ LHS, RHS);
+ } else if (isOperationLegalOrCustom(IsMax ? ISD::FMAXNUM : ISD::FMINNUM,
+ VT)) {
+MinMax = DAG.getNode(IsMax ? ISD::FMAXNUM : ISD::FMINNUM, DL, VT, LHS,
RHS);
+ } else {
+SDValue Compare =
+DAG.getSetCC(DL, CCVT, LHS, RHS, IsMax ? ISD::SETGT : ISD::SETLT);
ecnelises wrote:
Yes here it assumes no NaN exists (if either operand is NaN, it will be
propagated in following code)
https://github.com/llvm/llvm-project/pull/67301
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[Lldb-commits] [libcxx] [clang-tools-extra] [libc] [lldb] [flang] [lld] [clang] [llvm] [compiler-rt] [Legalizer] Expand fmaximum and fminimum (PR #67301)
ecnelises wrote: > Is there any existing vector test coverage? Yes, there are vector tests in PowerPC's fminimum-fmaximum.ll. https://github.com/llvm/llvm-project/pull/67301 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [libunwind] [clang-tools-extra] [lld] [llvm] [lldb] [compiler-rt] [libclc] [libc] [clang] [libcxxabi] [flang] [libcxx] [Legalizer] Soften EXTRACT_ELEMENT on ppcf128 (PR #77412)
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/77412
>From 87e1d4acdd87d45f265e590ad135e21f352dc5ad Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Tue, 9 Jan 2024 13:33:56 +0800
Subject: [PATCH 1/2] [Legalizer] Soften EXTRACT_ELEMENT on ppcf128
ppc_fp128 values are always split into two f64. Implement soften
operation in soft-float mode to handle output f64 correctly.
---
.../CodeGen/SelectionDAG/LegalizeFloatTypes.cpp| 14 +-
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 +
llvm/test/CodeGen/PowerPC/ppcsoftops.ll| 10 ++
3 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 6e0e1e23419bec..69759a7d6471f6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -60,7 +60,9 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned
ResNo) {
#endif
report_fatal_error("Do not know how to soften the result of this "
"operator!");
-
+case ISD::EXTRACT_ELEMENT:
+ R = SoftenFloatRes_EXTRACT_ELEMENT(N);
+ break;
case ISD::ARITH_FENCE: R = SoftenFloatRes_ARITH_FENCE(N); break;
case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break;
case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break;
@@ -262,6 +264,16 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(SDNode
*N) {
}
}
+SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_ELEMENT(SDNode *N) {
+ SDValue Src = N->getOperand(0);
+ assert(Src.getValueType() == MVT::ppcf128 &&
+ Src.getOperand(0)->getOpcode() == ISD::BUILD_PAIR &&
+ "In floats only ppcf128 can be extracted by element!");
+ EVT DestVT = EVT::getIntegerVT(*DAG.getContext(), N->getValueSizeInBits(0));
+ return DAG.getNode(ISD::EXTRACT_ELEMENT, SDLoc(N), DestVT,
+ Src.getOperand(0), N->getOperand(1));
+}
+
SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N,
unsigned ResNo) {
SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0));
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 09f0bca8b8611e..efe8ac536b63bd 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -541,6 +541,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue SoftenFloatRes_BITCAST(SDNode *N);
SDValue SoftenFloatRes_BUILD_PAIR(SDNode *N);
SDValue SoftenFloatRes_ConstantFP(SDNode *N);
+ SDValue SoftenFloatRes_EXTRACT_ELEMENT(SDNode *N);
SDValue SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo);
SDValue SoftenFloatRes_FABS(SDNode *N);
SDValue SoftenFloatRes_FMINNUM(SDNode *N);
diff --git a/llvm/test/CodeGen/PowerPC/ppcsoftops.ll
b/llvm/test/CodeGen/PowerPC/ppcsoftops.ll
index 0ee30f67c30f24..4c74798cf0ea5b 100644
--- a/llvm/test/CodeGen/PowerPC/ppcsoftops.ll
+++ b/llvm/test/CodeGen/PowerPC/ppcsoftops.ll
@@ -68,8 +68,18 @@ define dso_local zeroext i32 @func(double noundef %0, double
noundef %1) #0 {
; CHECK-LABEL: __adddf3
}
+; To check ppc_fp128 soften without crash
+define zeroext i1 @ppcf128_soften(ppc_fp128 %a) #0 {
+entry:
+ %0 = tail call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %a, i32 100)
+ ret i1 %0
+
+ ; CHECK-LABEL: ppcf128_soften
+}
+
; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn
memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #1
+declare i1 @llvm.is.fpclass.ppcf128(ppc_fp128, i32 immarg) #1
attributes #0 = {"use-soft-float"="true" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn
memory(none) }
>From 2a222d9adcd086b9b25724ed31ae1478100e334a Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 10 Jan 2024 10:46:32 +0800
Subject: [PATCH 2/2] Use changeTypeToInteger
---
llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp | 5 ++---
llvm/test/CodeGen/PowerPC/ppcsoftops.ll | 4 ++--
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index ecbf3ce94a3807..fac2a85e77b7b9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -267,10 +267,9 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(SDNode
*N) {
SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_ELEMENT(SDNode *N) {
SDValue Src = N->getOperand(0);
assert(Src.getValueType() == MVT::ppcf128 &&
- Src.getOperand(0)->getOpcode() == ISD::BUILD_PAIR &&
"In floats only ppcf128 can be extracted by element!");
- EVT DestVT = EVT::getIntegerVT(*DAG.getContext(), N->getValueSizeInBits(0));
- ret
[Lldb-commits] [llvm] [flang] [lld] [clang-tools-extra] [libcxx] [clang] [libc] [compiler-rt] [lldb] [Legalizer] Expand fmaximum and fminimum (PR #67301)
@@ -8262,6 +8262,64 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode
*Node,
return SDValue();
}
+SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
+SelectionDAG &DAG) const {
+ SDLoc DL(N);
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ unsigned Opc = N->getOpcode();
+ EVT VT = N->getValueType(0);
+ EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
+ bool IsMax = Opc == ISD::FMAXIMUM;
+
+ if (VT.isVector() &&
+ isOperationLegalOrCustomOrPromote(Opc, VT.getScalarType()))
+return SDValue();
+
+ // First, implement comparison not propagating NaN. If no native fmin or fmax
+ // available, use plain select with setcc instead.
+ SDValue MinMax;
+ if (isOperationLegalOrCustom(IsMax ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE,
+ VT)) {
+MinMax = DAG.getNode(IsMax ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE, DL, VT,
+ LHS, RHS);
+ } else if (isOperationLegalOrCustom(IsMax ? ISD::FMAXNUM : ISD::FMINNUM,
+ VT)) {
+MinMax = DAG.getNode(IsMax ? ISD::FMAXNUM : ISD::FMINNUM, DL, VT, LHS,
RHS);
+ } else {
+SDValue Compare =
+DAG.getSetCC(DL, CCVT, LHS, RHS, IsMax ? ISD::SETGT : ISD::SETLT);
+MinMax = DAG.getSelect(DL, VT, Compare, LHS, RHS);
+ }
+
+ // Propagate any NaN of both operands
+ if (!N->getFlags().hasNoNaNs() &&
+ (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) {
+ConstantFP *FPNaN = ConstantFP::get(
+*DAG.getContext(), APFloat::getNaN(DAG.EVTToAPFloatSemantics(VT)));
+MinMax = DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, LHS, RHS,
ISD::SETUO),
+ DAG.getConstantFP(*FPNaN, DL, VT), MinMax);
+ }
+
+ // fminimum/fmaximum requires -0.0 less than +0.0
+ if (!N->getFlags().hasNoSignedZeros() && !DAG.isKnownNeverZeroFloat(LHS) &&
+ !DAG.isKnownNeverZeroFloat(RHS)) {
+SDValue IsZero = DAG.getSetCC(DL, CCVT, MinMax,
+ DAG.getConstantFP(0.0, DL, VT), ISD::SETEQ);
+SDValue TestZero =
+DAG.getTargetConstant(IsMax ? fcPosZero : fcNegZero, DL, MVT::i32);
+SDValue LCmp = DAG.getSelect(
+DL, VT, DAG.getNode(ISD::IS_FPCLASS, DL, CCVT, LHS, TestZero), LHS,
+MinMax);
+SDValue RCmp = DAG.getSelect(
+DL, VT, DAG.getNode(ISD::IS_FPCLASS, DL, CCVT, RHS, TestZero), RHS,
+LCmp);
+MinMax = DAG.getSelect(DL, VT, IsZero, RCmp, MinMax);
ecnelises wrote:
PowerPC implements `fmaxnum_ieee` into `xsmaxdp` which repsects zero signs. I
did not see AMDGPU backend implements it.
While LoongArch (using `fmax.d`) ISA just says _following the specification of
maxNum(x,y) operation in the IEEE 754-2008 standard_. I think it's unspecified.
(maybe @llvm/pr-subscribers-loongarch )
https://github.com/llvm/llvm-project/pull/67301
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[Lldb-commits] [clang-tools-extra] [lld] [flang] [libcxx] [clang] [lldb] [libc] [llvm] [compiler-rt] [Legalizer] Expand fmaximum and fminimum (PR #67301)
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/67301
>From 92abb76631594dfc2ca586c46c38031610be0548 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Mon, 25 Sep 2023 17:08:59 +0800
Subject: [PATCH 1/6] [Legalizer] Expand fmaximum and fminimum
According to langref, llvm.maximum/minimum has -0.0 < +0.0 semantics and
propagates NaN.
Expand the nodes on targets not supporting the operation, by adding
extra check for NaN and using is_fpclass to check zero signs.
---
llvm/include/llvm/CodeGen/TargetLowering.h| 3 +
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 6 +
.../SelectionDAG/LegalizeVectorOps.cpp| 7 +
.../CodeGen/SelectionDAG/TargetLowering.cpp | 58 ++
llvm/lib/Target/ARM/ARMISelLowering.cpp | 14 +-
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 10 +-
.../CodeGen/ARM/minnum-maxnum-intrinsics.ll | 28 +-
.../CodeGen/PowerPC/fminimum-fmaximum-f128.ll | 97 ++
.../test/CodeGen/PowerPC/fminimum-fmaximum.ll | 847 ++
9 files changed, 1039 insertions(+), 31 deletions(-)
create mode 100644 llvm/test/CodeGen/PowerPC/fminimum-fmaximum-f128.ll
create mode 100644 llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h
b/llvm/include/llvm/CodeGen/TargetLowering.h
index c6a7aa17146dd4..429cfd72af2e6e 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -5089,6 +5089,9 @@ class TargetLowering : public TargetLoweringBase {
/// Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted
inputs.
SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const;
+ /// Expand fminimum/fmaximum into multiple comparison with selects.
+ SDValue expandFMINIMUM_FMAXIMUM(SDNode *N, SelectionDAG &DAG) const;
+
/// Expand FP_TO_[US]INT_SAT into FP_TO_[US]INT and selects or min/max.
/// \param N Node to expand
/// \returns The expansion result
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index f19beea3a3ed8b..33f6354d558454 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3540,6 +3540,12 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
Results.push_back(Expanded);
break;
}
+ case ISD::FMINIMUM:
+ case ISD::FMAXIMUM: {
+if (SDValue Expanded = TLI.expandFMINIMUM_FMAXIMUM(Node, DAG))
+ Results.push_back(Expanded);
+break;
+ }
case ISD::FSIN:
case ISD::FCOS: {
EVT VT = Node->getValueType(0);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index dec81475f3a88f..db132035adcf29 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -949,6 +949,13 @@ void VectorLegalizer::Expand(SDNode *Node,
SmallVectorImpl &Results) {
return;
}
break;
+ case ISD::FMINIMUM:
+ case ISD::FMAXIMUM:
+if (SDValue Expanded = TLI.expandFMINIMUM_FMAXIMUM(Node, DAG)) {
+ Results.push_back(Expanded);
+ return;
+}
+break;
case ISD::SMIN:
case ISD::SMAX:
case ISD::UMIN:
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 39489e0bf142eb..23de9829b5e9ff 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -8177,6 +8177,64 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode
*Node,
return SDValue();
}
+SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
+SelectionDAG &DAG) const {
+ SDLoc DL(N);
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ unsigned Opc = N->getOpcode();
+ EVT VT = N->getValueType(0);
+ EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
+ bool NoNaN = (N->getFlags().hasNoNaNs() ||
+(DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)));
+ bool NoZeroSign =
+ (N->getFlags().hasNoSignedZeros() || DAG.isKnownNeverZeroFloat(LHS) ||
+ DAG.isKnownNeverZeroFloat(RHS));
+ bool IsMax = Opc == ISD::FMAXIMUM;
+
+ if (VT.isVector() &&
+ isOperationLegalOrCustomOrPromote(Opc, VT.getScalarType()))
+return SDValue();
+
+ SDValue MinMax;
+ if (isOperationLegalOrCustom(IsMax ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE,
+ VT))
+MinMax = DAG.getNode(IsMax ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE, DL, VT,
+ LHS, RHS);
+ else if (isOperationLegalOrCustom(IsMax ? ISD::FMAXNUM : ISD::FMINNUM, VT))
+MinMax = DAG.getNode(IsMax ? ISD::FMAXNUM : ISD::FMINNUM, DL, VT, LHS,
RHS);
+ else
+MinMax = DAG.getSelect(
+DL, VT,
+DAG.getSetCC(DL, CCVT, LHS, RHS, IsMax ? ISD::SETGT : ISD::SETLT), LHS,
+RHS);
+
+ // Propagate
[Lldb-commits] [clang-tools-extra] [libclc] [lld] [flang] [libcxx] [libunwind] [clang] [libcxxabi] [lldb] [libc] [llvm] [compiler-rt] [Legalizer] Soften EXTRACT_ELEMENT on ppcf128 (PR #77412)
https://github.com/ecnelises updated
https://github.com/llvm/llvm-project/pull/77412
>From 87e1d4acdd87d45f265e590ad135e21f352dc5ad Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Tue, 9 Jan 2024 13:33:56 +0800
Subject: [PATCH 1/3] [Legalizer] Soften EXTRACT_ELEMENT on ppcf128
ppc_fp128 values are always split into two f64. Implement soften
operation in soft-float mode to handle output f64 correctly.
---
.../CodeGen/SelectionDAG/LegalizeFloatTypes.cpp| 14 +-
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 +
llvm/test/CodeGen/PowerPC/ppcsoftops.ll| 10 ++
3 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 6e0e1e23419bec..69759a7d6471f6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -60,7 +60,9 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned
ResNo) {
#endif
report_fatal_error("Do not know how to soften the result of this "
"operator!");
-
+case ISD::EXTRACT_ELEMENT:
+ R = SoftenFloatRes_EXTRACT_ELEMENT(N);
+ break;
case ISD::ARITH_FENCE: R = SoftenFloatRes_ARITH_FENCE(N); break;
case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break;
case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break;
@@ -262,6 +264,16 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(SDNode
*N) {
}
}
+SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_ELEMENT(SDNode *N) {
+ SDValue Src = N->getOperand(0);
+ assert(Src.getValueType() == MVT::ppcf128 &&
+ Src.getOperand(0)->getOpcode() == ISD::BUILD_PAIR &&
+ "In floats only ppcf128 can be extracted by element!");
+ EVT DestVT = EVT::getIntegerVT(*DAG.getContext(), N->getValueSizeInBits(0));
+ return DAG.getNode(ISD::EXTRACT_ELEMENT, SDLoc(N), DestVT,
+ Src.getOperand(0), N->getOperand(1));
+}
+
SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N,
unsigned ResNo) {
SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0));
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 09f0bca8b8611e..efe8ac536b63bd 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -541,6 +541,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue SoftenFloatRes_BITCAST(SDNode *N);
SDValue SoftenFloatRes_BUILD_PAIR(SDNode *N);
SDValue SoftenFloatRes_ConstantFP(SDNode *N);
+ SDValue SoftenFloatRes_EXTRACT_ELEMENT(SDNode *N);
SDValue SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo);
SDValue SoftenFloatRes_FABS(SDNode *N);
SDValue SoftenFloatRes_FMINNUM(SDNode *N);
diff --git a/llvm/test/CodeGen/PowerPC/ppcsoftops.ll
b/llvm/test/CodeGen/PowerPC/ppcsoftops.ll
index 0ee30f67c30f24..4c74798cf0ea5b 100644
--- a/llvm/test/CodeGen/PowerPC/ppcsoftops.ll
+++ b/llvm/test/CodeGen/PowerPC/ppcsoftops.ll
@@ -68,8 +68,18 @@ define dso_local zeroext i32 @func(double noundef %0, double
noundef %1) #0 {
; CHECK-LABEL: __adddf3
}
+; To check ppc_fp128 soften without crash
+define zeroext i1 @ppcf128_soften(ppc_fp128 %a) #0 {
+entry:
+ %0 = tail call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %a, i32 100)
+ ret i1 %0
+
+ ; CHECK-LABEL: ppcf128_soften
+}
+
; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn
memory(none)
declare double @llvm.fmuladd.f64(double, double, double) #1
+declare i1 @llvm.is.fpclass.ppcf128(ppc_fp128, i32 immarg) #1
attributes #0 = {"use-soft-float"="true" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn
memory(none) }
>From 2a222d9adcd086b9b25724ed31ae1478100e334a Mon Sep 17 00:00:00 2001
From: Qiu Chaofan
Date: Wed, 10 Jan 2024 10:46:32 +0800
Subject: [PATCH 2/3] Use changeTypeToInteger
---
llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp | 5 ++---
llvm/test/CodeGen/PowerPC/ppcsoftops.ll | 4 ++--
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index ecbf3ce94a3807..fac2a85e77b7b9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -267,10 +267,9 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(SDNode
*N) {
SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_ELEMENT(SDNode *N) {
SDValue Src = N->getOperand(0);
assert(Src.getValueType() == MVT::ppcf128 &&
- Src.getOperand(0)->getOpcode() == ISD::BUILD_PAIR &&
"In floats only ppcf128 can be extracted by element!");
- EVT DestVT = EVT::getIntegerVT(*DAG.getContext(), N->getValueSizeInBits(0));
- ret
[Lldb-commits] [compiler-rt] [libcxx] [libcxxabi] [lldb] [libc] [llvm] [flang] [clang] [lld] [clang-tools-extra] [libunwind] [PowerPC] Combine sub within setcc back to sext (PR #66978)
@@ -14428,15 +14431,52 @@ SDValue PPCTargetLowering::combineSetCC(SDNode *N,
// x != 0-y --> x+y != 0
if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
RHS.hasOneUse()) {
- SDLoc DL(N);
- SelectionDAG &DAG = DCI.DAG;
- EVT VT = N->getValueType(0);
- EVT OpVT = LHS.getValueType();
SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LHS, RHS.getOperand(1));
return DAG.getSetCC(DL, VT, Add, DAG.getConstant(0, DL, OpVT), CC);
}
}
+ if (CC == ISD::SETULT && isa(RHS)) {
+uint64_t RHSVal = cast(RHS)->getZExtValue();
+if (LHS.getOpcode() == ISD::ADD && isa(LHS.getOperand(1)))
{
+ uint64_t Addend =
cast(LHS.getOperand(1))->getZExtValue();
+ if (OpVT == MVT::i64) {
+uint64_t ShiftVal = ~Addend + 1;
ecnelises wrote:
negating an unsigned variable is UB?
https://github.com/llvm/llvm-project/pull/66978
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[Lldb-commits] [compiler-rt] [libcxx] [libcxxabi] [lldb] [libc] [llvm] [flang] [clang] [lld] [clang-tools-extra] [libunwind] [PowerPC] Combine sub within setcc back to sext (PR #66978)
https://github.com/ecnelises edited https://github.com/llvm/llvm-project/pull/66978 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] 00c0ce0 - [NFC] [Clang] Remove pre-computed complex float types
Author: Qiu Chaofan
Date: 2021-10-08T15:52:16+08:00
New Revision: 00c0ce0655da804c2ffb1a2a807052298032acc6
URL:
https://github.com/llvm/llvm-project/commit/00c0ce0655da804c2ffb1a2a807052298032acc6
DIFF:
https://github.com/llvm/llvm-project/commit/00c0ce0655da804c2ffb1a2a807052298032acc6.diff
LOG: [NFC] [Clang] Remove pre-computed complex float types
As discussed in D109948, pre-computing all complex float types is not
necessary and brings extra overhead. This patch removes these defined
types, and construct them in-place when needed.
Reviewed By: teemperor
Differential Revision: https://reviews.llvm.org/D111387
Added:
Modified:
clang/include/clang/AST/ASTContext.h
clang/lib/AST/ASTContext.cpp
lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
lldb/unittests/Symbol/TestTypeSystemClang.cpp
Removed:
diff --git a/clang/include/clang/AST/ASTContext.h
b/clang/include/clang/AST/ASTContext.h
index 582134e586e0d..d4e813c5ed9d7 100644
--- a/clang/include/clang/AST/ASTContext.h
+++ b/clang/include/clang/AST/ASTContext.h
@@ -1091,8 +1091,6 @@ class ASTContext : public RefCountedBase {
CanQualType HalfTy; // [OpenCL 6.1.1.1], ARM NEON
CanQualType BFloat16Ty;
CanQualType Float16Ty; // C11 extension ISO/IEC TS 18661-3
- CanQualType FloatComplexTy, DoubleComplexTy, LongDoubleComplexTy;
- CanQualType Float128ComplexTy;
CanQualType VoidPtrTy, NullPtrTy;
CanQualType DependentTy, OverloadTy, BoundMemberTy, UnknownAnyTy;
CanQualType BuiltinFnTy;
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index d1fd3ce061415..4085477bc45ad 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -1411,12 +1411,6 @@ void ASTContext::InitBuiltinTypes(const TargetInfo
&Target,
if (LangOpts.MatrixTypes)
InitBuiltinType(IncompleteMatrixIdxTy, BuiltinType::IncompleteMatrixIdx);
- // C99 6.2.5p11.
- FloatComplexTy = getComplexType(FloatTy);
- DoubleComplexTy = getComplexType(DoubleTy);
- LongDoubleComplexTy = getComplexType(LongDoubleTy);
- Float128ComplexTy = getComplexType(Float128Ty);
-
// Builtin types for 'id', 'Class', and 'SEL'.
InitBuiltinType(ObjCBuiltinIdTy, BuiltinType::ObjCId);
InitBuiltinType(ObjCBuiltinClassTy, BuiltinType::ObjCClass);
@@ -6341,10 +6335,10 @@ QualType
ASTContext::getFloatingTypeOfSizeWithinDomain(QualType Size,
case Float16Rank:
case HalfRank: llvm_unreachable("Complex half is not supported");
case Ibm128Rank: llvm_unreachable("Complex __ibm128 is not supported");
-case FloatRank: return FloatComplexTy;
-case DoubleRank: return DoubleComplexTy;
-case LongDoubleRank: return LongDoubleComplexTy;
-case Float128Rank: return Float128ComplexTy;
+case FloatRank: return getComplexType(FloatTy);
+case DoubleRank: return getComplexType(DoubleTy);
+case LongDoubleRank: return getComplexType(LongDoubleTy);
+case Float128Rank: return getComplexType(Float128Ty);
}
}
diff --git a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
index 99ed2a906635c..152b570a6f913 100644
--- a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
+++ b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
@@ -981,21 +981,25 @@ CompilerType
TypeSystemClang::GetBuiltinTypeForDWARFEncodingAndBitSize(
}
break;
- case DW_ATE_complex_float:
-if (QualTypeMatchesBitSize(bit_size, ast, ast.FloatComplexTy))
- return GetType(ast.FloatComplexTy);
-else if (QualTypeMatchesBitSize(bit_size, ast, ast.DoubleComplexTy))
- return GetType(ast.DoubleComplexTy);
-else if (QualTypeMatchesBitSize(bit_size, ast, ast.LongDoubleComplexTy))
- return GetType(ast.LongDoubleComplexTy);
-else {
- CompilerType complex_float_clang_type =
- GetBuiltinTypeForDWARFEncodingAndBitSize("float", DW_ATE_float,
- bit_size / 2);
- return GetType(
-
ast.getComplexType(ClangUtil::GetQualType(complex_float_clang_type)));
-}
-break;
+ case DW_ATE_complex_float: {
+CanQualType FloatComplexTy = ast.getComplexType(ast.FloatTy);
+if (QualTypeMatchesBitSize(bit_size, ast, FloatComplexTy))
+ return GetType(FloatComplexTy);
+
+CanQualType DoubleComplexTy = ast.getComplexType(ast.DoubleTy);
+if (QualTypeMatchesBitSize(bit_size, ast, DoubleComplexTy))
+ return GetType(DoubleComplexTy);
+
+CanQualType LongDoubleComplexTy = ast.getComplexType(ast.LongDoubleTy);
+if (QualTypeMatchesBitSize(bit_size, ast, LongDoubleComplexTy))
+ return GetType(LongDoubleComplexTy);
+
+CompilerType complex_float_clang_type =
+GetBuiltinTypeForDWARFEncodingAndBitSize("float", DW_ATE_float,
+ bit_size / 2);
+re
[Lldb-commits] [lldb] da0b62d - Revert a LIT typo fix in a RUN line
Author: Qiu Chaofan Date: 2021-10-09T11:29:44+08:00 New Revision: da0b62dfb3ca597f618b1f88226b440bc7ca3960 URL: https://github.com/llvm/llvm-project/commit/da0b62dfb3ca597f618b1f88226b440bc7ca3960 DIFF: https://github.com/llvm/llvm-project/commit/da0b62dfb3ca597f618b1f88226b440bc7ca3960.diff LOG: Revert a LIT typo fix in a RUN line Commit 573531f changes the behavior of the test, revert it back. Added: Modified: lldb/test/Shell/ScriptInterpreter/Python/command_relative_import.test Removed: diff --git a/lldb/test/Shell/ScriptInterpreter/Python/command_relative_import.test b/lldb/test/Shell/ScriptInterpreter/Python/command_relative_import.test index 4b378cc921975..aa2cbcafc9283 100644 --- a/lldb/test/Shell/ScriptInterpreter/Python/command_relative_import.test +++ b/lldb/test/Shell/ScriptInterpreter/Python/command_relative_import.test @@ -8,9 +8,9 @@ # RUN:-o 'command source %t/foo/magritte.in' \ # RUN:-o 'command source %t/foo/zip.in' \ # RUN:-o 'command source %t/foo/magritte.in' \ -# RUN:-o 'zip' \ +# RUN;-o 'zip' \ # RUN:-o 'hello' -# RUN:-o 'magritte' 2>&1 | FileCheck %s +# RUN -o 'magritte' 2>&1 | FileCheck %s # The first time importing 'magritte' fails because we didn't pass -c. # CHECK: ModuleNotFoundError: No module named 'magritte' ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [flang] [clang-tools-extra] [compiler-rt] [libc] [llvm] [lldb] [clang] [libcxx] [PowerPC] Support mcmodel=large for AIX (PR #70652)
@@ -5723,16 +5723,14 @@ void Clang::ConstructJob(Compilation &C, const
JobAction &JA,
if (Arg *A = Args.getLastArg(options::OPT_mcmodel_EQ)) {
StringRef CM = A->getValue();
bool Ok = false;
-if (Triple.isOSAIX() && CM == "medium") {
+if (Triple.isOSAIX() && CM == "medium")
CM = "large";
- Ok = true;
-}
if (Triple.isAArch64(64)) {
Ok = CM == "tiny" || CM == "small" || CM == "large";
if (CM == "large" && RelocationModel != llvm::Reloc::Static)
D.Diag(diag::err_drv_argument_only_allowed_with)
<< A->getAsString(Args) << "-fno-pic";
-} else if (Triple.isPPC64()) {
+} else if (Triple.isPPC64() || Triple.isOSAIX()) {
ecnelises wrote:
CC @chmeeedalf
https://github.com/llvm/llvm-project/pull/70652
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[Lldb-commits] [clang-tools-extra] [libc] [clang] [lldb] [libcxx] [flang] [compiler-rt] [llvm] [PowerPC] Support mcmodel=small/large for AIX (PR #70652)
https://github.com/ecnelises edited https://github.com/llvm/llvm-project/pull/70652 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang-tools-extra] [libc] [clang] [lldb] [libcxx] [flang] [compiler-rt] [llvm] [PowerPC] Support mcmodel=small/large for AIX (PR #70652)
https://github.com/ecnelises closed https://github.com/llvm/llvm-project/pull/70652 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [clang-tools-extra] [libc] [clang] [lldb] [libcxx] [flang] [compiler-rt] [llvm] [PowerPC] Support mcmodel=small/large for AIX (PR #70652)
ecnelises wrote: https://github.com/llvm/llvm-project/issues/71356 to track SPE issue https://github.com/llvm/llvm-project/pull/70652 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
