[Lldb-commits] [lldb] [LoongArch64]: Add support for LoongArch64 in elf-core for lldb (PR #112296)
@@ -0,0 +1,62 @@ +//===-- RegisterContextPOSIXCore_loongarch64.h --*- C++ +//-*-===// SixWeining wrote: ditto https://github.com/llvm/llvm-project/pull/112296 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [LoongArch64]: Add support for LoongArch64 in elf-core for lldb (PR #112296)
@@ -0,0 +1,87 @@ +//===-- RegisterContextPOSIXCore_loongarch64.cpp +//--===// SixWeining wrote: format https://github.com/llvm/llvm-project/pull/112296 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [LoongArch64]: Add support for LoongArch64 in elf-core for lldb (PR #112296)
https://github.com/SixWeining edited https://github.com/llvm/llvm-project/pull/112296 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [LoongArch64]: Add support for LoongArch64 in elf-core for lldb (PR #112296)
https://github.com/SixWeining commented: @wangleiat may take a look. https://github.com/llvm/llvm-project/pull/112296 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][LoongArch64] Add support for LoongArch64 in elf-core for lldb (PR #112296)
@@ -0,0 +1,62 @@
+//===-- RegisterContextPOSIXCore_loongarch64.h --*- C++
+//-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#ifndef
LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_LOONGARCH64_H
+#define
LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_LOONGARCH64_H
+
+#include "Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.h"
+
+#include "Plugins/Process/elf-core/RegisterUtilities.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/DataExtractor.h"
+#include "lldb/Utility/RegisterValue.h"
+
+#include
+
+class RegisterContextCorePOSIX_loongarch64
+: public RegisterContextPOSIX_loongarch64 {
+public:
+ static std::unique_ptr
+ Create(lldb_private::Thread &thread, const lldb_private::ArchSpec &arch,
+ const lldb_private::DataExtractor &gpregset,
+ llvm::ArrayRef notes);
+
+ ~RegisterContextCorePOSIX_loongarch64() override;
+
+ bool ReadRegister(const lldb_private::RegisterInfo *reg_info,
+lldb_private::RegisterValue &value) override;
+
+ bool WriteRegister(const lldb_private::RegisterInfo *reg_info,
+ const lldb_private::RegisterValue &value) override;
+
+protected:
+ RegisterContextCorePOSIX_loongarch64(
+ lldb_private::Thread &thread,
+ std::unique_ptr register_info,
+ const lldb_private::DataExtractor &gpregset,
+ llvm::ArrayRef notes);
+
+ bool ReadGPR() override;
+
+ bool ReadFPR() override;
+
+ bool WriteGPR() override;
+
+ bool WriteFPR() override;
+
+private:
+ lldb::DataBufferSP m_gpr_buffer;
SixWeining wrote:
Seems we only need to define them as local variables before using it. No need
to be class-member-variables.
https://github.com/llvm/llvm-project/pull/112296
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[Lldb-commits] [lldb] [LoongArch64]: Add support for LoongArch64 in elf-core for lldb (PR #112296)
SixWeining wrote: > When using the lldb command 'target create -- core' on the LoongArch64 > architecture, this part of the code is required. Do you mean `--core` but not `-- core`? https://github.com/llvm/llvm-project/pull/112296 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [LoongArch64]: Add support for LoongArch64 in elf-core for lldb (PR #112296)
https://github.com/SixWeining edited https://github.com/llvm/llvm-project/pull/112296 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][LoongArch64] Add support for LoongArch64 in elf-core for lldb (PR #112296)
SixWeining wrote: Seems we the same `GetRegisterSetCount` misprint issue as #93297. https://github.com/llvm/llvm-project/pull/112296 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][LoongArch64] Add support for LoongArch64 in elf-core for lldb (PR #112296)
https://github.com/SixWeining edited https://github.com/llvm/llvm-project/pull/112296 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][LoongArch64] Add support for LoongArch64 in elf-core for lldb (PR #112296)
@@ -833,6 +845,107 @@ def test_riscv64_regs_gpr_only(self):
substrs=["registers were unavailable"],
)
+@skipIfLLVMTargetMissing("LoongArch")
+def test_loongarch64_regs(self):
+# check registers using 64 bit LoongArch core file containing GP and
FP registers
+target = self.dbg.CreateTarget(None)
+self.assertTrue(target, VALID_TARGET)
+process = target.LoadCore("linux-loongarch64.core")
+
+values = {}
+values["r0"] = "0x"
+values["r1"] = "0x0001216c"
+values["r2"] = "0x"
+values["r3"] = "0x7b8249e0"
+values["r4"] = "0x"
+values["r5"] = "0x0001210c"
+values["r6"] = "0x"
+values["r7"] = "0x"
+values["r8"] = "0x"
+values["r9"] = "0x"
+values["r10"] = "0x"
+values["r11"] = "0x00dd"
+values["r12"] = "0x"
+values["r13"] = "0x002f"
+values["r14"] = "0x"
+values["r15"] = "0x"
+values["r16"] = "0x"
+values["r17"] = "0x"
+values["r18"] = "0x"
+values["r19"] = "0x"
+values["r20"] = "0x"
+values["r21"] = "0x"
+values["r22"] = "0x7b824a10"
+values["r23"] = "0x"
+values["r24"] = "0x"
+values["r25"] = "0x"
+values["r26"] = "0x"
+values["r27"] = "0x"
+values["r28"] = "0x"
+values["r29"] = "0x"
+values["r30"] = "0x"
+values["r31"] = "0x"
+values["orig_a0"] = "0x56b62d50"
+values["pc"] = "0x0001212c"
+
+fpr_values = {}
+fpr_values["f0"] = "0xff05"
+fpr_values["f1"] = "0x2525252525252525"
+fpr_values["f2"] = "0x2525252525560005"
+fpr_values["f3"] = "0x"
+fpr_values["f4"] = "0x"
+fpr_values["f5"] = "0x0008"
+fpr_values["f6"] = "0x0f0e0d0c0b0a0908"
+fpr_values["f7"] = "0x"
+fpr_values["f8"] = "0x6261747563657845"
+fpr_values["f9"] = "0x766173206562206c"
+fpr_values["f10"] = "0x"
+fpr_values["f11"] = "0x"
+fpr_values["f12"] = "0x"
+fpr_values["f13"] = "0x"
+fpr_values["f14"] = "0x"
+fpr_values["f15"] = "0x"
+fpr_values["f16"] = "0x"
+fpr_values["f17"] = "0x"
+fpr_values["f18"] = "0x"
+fpr_values["f19"] = "0x"
+fpr_values["f20"] = "0x"
+fpr_values["f21"] = "0x"
+fpr_values["f22"] = "0x"
+fpr_values["f23"] = "0x"
+fpr_values["f24"] = "0x"
+fpr_values["f25"] = "0x"
+fpr_values["f26"] = "0x"
+fpr_values["f27"] = "0x"
+fpr_values["f28"] = "0x"
+fpr_values["f29"] = "0x"
+fpr_values["f30"] = "0x"
+fpr_values["f31"] = "0x"
+fpr_values["fcc0"] = "0x01"
+fpr_values["fcc1"] = "0x00"
+fpr_values["fcc2"] = "0x01"
+fpr_values["fcc3"] = "0x01"
+fpr_values["fcc4"] = "0x01"
+fpr_values["fcc5"] = "0x01"
+fpr_values["fcc6"] = "0x00"
+fpr_values["fcc7"] = "0x01"
+fpr_values["fcsr"] = "0x"
SixWeining wrote:
(lldb) register read fcsr
fcsr = 0x
https://github.com/llvm/llvm-project/pull/112296
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[Lldb-commits] [lldb] [lldb][LoongArch64] Add support for LoongArch64 in elf-core for lldb (PR #112296)
https://github.com/SixWeining commented: Looks good to me once the `code_formatter` CI fail and fcsr format issues are addressed. https://github.com/llvm/llvm-project/pull/112296 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][LoongArch64] Add support for LoongArch64 in elf-core for lldb (PR #112296)
https://github.com/SixWeining approved this pull request. LGTM and thanks! https://github.com/llvm/llvm-project/pull/112296 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][LoongArch64] Add support for LoongArch64 in elf-core for lldb (PR #112296)
@@ -833,6 +845,107 @@ def test_riscv64_regs_gpr_only(self):
substrs=["registers were unavailable"],
)
+@skipIfLLVMTargetMissing("LoongArch")
+def test_loongarch64_regs(self):
+# check registers using 64 bit LoongArch64 core file containing
GP-registers only
+target = self.dbg.CreateTarget(None)
+self.assertTrue(target, VALID_TARGET)
+process = target.LoadCore("linux-loongarch64.core")
+
+values = {}
+values["r0"] = "0x0"
+values["r1"] = "0x0001216c"
+values["r2"] = "0x0"
+values["r3"] = "0x7b8249e0"
+values["r4"] = "0x0"
+values["r5"] = "0x0001210c"
+values["r6"] = "0x0"
+values["r7"] = "0x0"
+values["r8"] = "0x0"
+values["r9"] = "0x0"
+values["r10"] = "0x0"
+values["r11"] = "0x00dd"
+values["r12"] = "0x0"
+values["r13"] = "0x002f"
+values["r14"] = "0x0"
+values["r15"] = "0x0"
+values["r16"] = "0x0"
+values["r17"] = "0x0"
+values["r18"] = "0x0"
+values["r19"] = "0x0"
+values["r20"] = "0x0"
+values["r21"] = "0x0"
+values["r22"] = "0x7b824a10"
+values["r23"] = "0x0"
+values["r24"] = "0x0"
+values["r25"] = "0x0"
+values["r26"] = "0x0"
+values["r27"] = "0x0"
+values["r28"] = "0x0"
+values["r29"] = "0x0"
+values["r30"] = "0x0"
+values["r31"] = "0x0"
+values["orig_a0"] = "0x56b62d50"
+values["pc"] = "0x0001212c"
+
+fpr_values = {}
+fpr_values["f0"] = "0xff05"
+fpr_values["f1"] = "0x2525252525252525"
+fpr_values["f2"] = "0x2525252525560005"
+fpr_values["f3"] = "0x"
+fpr_values["f4"] = "0x0"
+fpr_values["f5"] = "0x0008"
+fpr_values["f6"] = "0x0f0e0d0c0b0a0908"
+fpr_values["f7"] = "0x"
+fpr_values["f8"] = "0x6261747563657845"
+fpr_values["f9"] = "0x766173206562206c"
+fpr_values["f10"] = "0x"
+fpr_values["f11"] = "0x"
+fpr_values["f12"] = "0x"
+fpr_values["f13"] = "0x"
+fpr_values["f14"] = "0x"
+fpr_values["f15"] = "0x"
+fpr_values["f16"] = "0x"
+fpr_values["f17"] = "0x"
+fpr_values["f18"] = "0x"
+fpr_values["f19"] = "0x"
+fpr_values["f20"] = "0x"
+fpr_values["f21"] = "0x"
+fpr_values["f22"] = "0x"
+fpr_values["f23"] = "0x"
+fpr_values["f24"] = "0x"
+fpr_values["f25"] = "0x"
+fpr_values["f26"] = "0x"
+fpr_values["f27"] = "0x"
+fpr_values["f28"] = "0x"
+fpr_values["f29"] = "0x"
+fpr_values["f30"] = "0x"
+fpr_values["f31"] = "0x"
+fpr_values["fcc0"] = "0x01"
+fpr_values["fcc1"] = "0x0"
SixWeining wrote:
Should it be `0x00`? Otherwise `0x01` can also match the expect.
https://github.com/llvm/llvm-project/pull/112296
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[Lldb-commits] [lldb] [lldb][LoongArch64] Add support for LoongArch64 in elf-core for lldb (PR #112296)
@@ -833,6 +845,107 @@ def test_riscv64_regs_gpr_only(self):
substrs=["registers were unavailable"],
)
+@skipIfLLVMTargetMissing("LoongArch")
+def test_loongarch64_regs(self):
+# check registers using 64 bit LoongArch64 core file containing
GP-registers only
+target = self.dbg.CreateTarget(None)
+self.assertTrue(target, VALID_TARGET)
+process = target.LoadCore("linux-loongarch64.core")
+
+values = {}
+values["r0"] = "0x0"
+values["r1"] = "0x0001216c"
+values["r2"] = "0x0"
+values["r3"] = "0x7b8249e0"
+values["r4"] = "0x0"
+values["r5"] = "0x0001210c"
+values["r6"] = "0x0"
+values["r7"] = "0x0"
+values["r8"] = "0x0"
+values["r9"] = "0x0"
+values["r10"] = "0x0"
+values["r11"] = "0x00dd"
+values["r12"] = "0x0"
+values["r13"] = "0x002f"
+values["r14"] = "0x0"
SixWeining wrote:
Should we use full encoding (i.e. 8bytes)?
https://github.com/llvm/llvm-project/pull/112296
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[Lldb-commits] [lldb] [lldb][LoongArch64] Add support for LoongArch64 in elf-core for lldb (PR #112296)
@@ -833,6 +845,107 @@ def test_riscv64_regs_gpr_only(self):
substrs=["registers were unavailable"],
)
+@skipIfLLVMTargetMissing("LoongArch")
+def test_loongarch64_regs(self):
+# check registers using 64 bit LoongArch64 core file containing
GP-registers only
+target = self.dbg.CreateTarget(None)
+self.assertTrue(target, VALID_TARGET)
+process = target.LoadCore("linux-loongarch64.core")
+
+values = {}
+values["r0"] = "0x0"
+values["r1"] = "0x0001216c"
+values["r2"] = "0x0"
+values["r3"] = "0x7b8249e0"
+values["r4"] = "0x0"
+values["r5"] = "0x0001210c"
+values["r6"] = "0x0"
+values["r7"] = "0x0"
+values["r8"] = "0x0"
+values["r9"] = "0x0"
+values["r10"] = "0x0"
+values["r11"] = "0x00dd"
+values["r12"] = "0x0"
+values["r13"] = "0x002f"
+values["r14"] = "0x0"
+values["r15"] = "0x0"
+values["r16"] = "0x0"
+values["r17"] = "0x0"
+values["r18"] = "0x0"
+values["r19"] = "0x0"
+values["r20"] = "0x0"
+values["r21"] = "0x0"
+values["r22"] = "0x7b824a10"
+values["r23"] = "0x0"
+values["r24"] = "0x0"
+values["r25"] = "0x0"
+values["r26"] = "0x0"
+values["r27"] = "0x0"
+values["r28"] = "0x0"
+values["r29"] = "0x0"
+values["r30"] = "0x0"
+values["r31"] = "0x0"
+values["orig_a0"] = "0x56b62d50"
+values["pc"] = "0x0001212c"
+
+fpr_values = {}
+fpr_values["f0"] = "0xff05"
+fpr_values["f1"] = "0x2525252525252525"
+fpr_values["f2"] = "0x2525252525560005"
+fpr_values["f3"] = "0x"
+fpr_values["f4"] = "0x0"
+fpr_values["f5"] = "0x0008"
+fpr_values["f6"] = "0x0f0e0d0c0b0a0908"
+fpr_values["f7"] = "0x"
+fpr_values["f8"] = "0x6261747563657845"
+fpr_values["f9"] = "0x766173206562206c"
+fpr_values["f10"] = "0x"
+fpr_values["f11"] = "0x"
+fpr_values["f12"] = "0x"
+fpr_values["f13"] = "0x"
+fpr_values["f14"] = "0x"
+fpr_values["f15"] = "0x"
+fpr_values["f16"] = "0x"
+fpr_values["f17"] = "0x"
+fpr_values["f18"] = "0x"
+fpr_values["f19"] = "0x"
+fpr_values["f20"] = "0x"
+fpr_values["f21"] = "0x"
+fpr_values["f22"] = "0x"
+fpr_values["f23"] = "0x"
+fpr_values["f24"] = "0x"
+fpr_values["f25"] = "0x"
+fpr_values["f26"] = "0x"
+fpr_values["f27"] = "0x"
+fpr_values["f28"] = "0x"
+fpr_values["f29"] = "0x"
+fpr_values["f30"] = "0x"
+fpr_values["f31"] = "0x"
+fpr_values["fcc0"] = "0x01"
+fpr_values["fcc1"] = "0x0"
+fpr_values["fcc2"] = "0x01"
+fpr_values["fcc3"] = "0x01"
+fpr_values["fcc4"] = "0x01"
+fpr_values["fcc5"] = "0x01"
+fpr_values["fcc6"] = "0x0"
+fpr_values["fcc7"] = "0x01"
+fpr_values["fcsr"] = "0x0"
SixWeining wrote:
0x
https://github.com/llvm/llvm-project/pull/112296
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[Lldb-commits] [lldb] [lldb][LoongArch64] Add support for LoongArch64 in elf-core for lldb (PR #112296)
@@ -833,6 +845,107 @@ def test_riscv64_regs_gpr_only(self):
substrs=["registers were unavailable"],
)
+@skipIfLLVMTargetMissing("LoongArch")
+def test_loongarch64_regs(self):
+# check registers using 64 bit LoongArch64 core file containing
GP-registers only
+target = self.dbg.CreateTarget(None)
+self.assertTrue(target, VALID_TARGET)
+process = target.LoadCore("linux-loongarch64.core")
+
+values = {}
+values["r0"] = "0x0"
+values["r1"] = "0x0001216c"
+values["r2"] = "0x0"
+values["r3"] = "0x7b8249e0"
+values["r4"] = "0x0"
+values["r5"] = "0x0001210c"
+values["r6"] = "0x0"
+values["r7"] = "0x0"
+values["r8"] = "0x0"
+values["r9"] = "0x0"
+values["r10"] = "0x0"
+values["r11"] = "0x00dd"
+values["r12"] = "0x0"
+values["r13"] = "0x002f"
+values["r14"] = "0x0"
+values["r15"] = "0x0"
+values["r16"] = "0x0"
+values["r17"] = "0x0"
+values["r18"] = "0x0"
+values["r19"] = "0x0"
+values["r20"] = "0x0"
+values["r21"] = "0x0"
+values["r22"] = "0x7b824a10"
+values["r23"] = "0x0"
+values["r24"] = "0x0"
+values["r25"] = "0x0"
+values["r26"] = "0x0"
+values["r27"] = "0x0"
+values["r28"] = "0x0"
+values["r29"] = "0x0"
+values["r30"] = "0x0"
+values["r31"] = "0x0"
+values["orig_a0"] = "0x56b62d50"
+values["pc"] = "0x0001212c"
+
+fpr_values = {}
+fpr_values["f0"] = "0xff05"
+fpr_values["f1"] = "0x2525252525252525"
+fpr_values["f2"] = "0x2525252525560005"
+fpr_values["f3"] = "0x"
+fpr_values["f4"] = "0x0"
+fpr_values["f5"] = "0x0008"
+fpr_values["f6"] = "0x0f0e0d0c0b0a0908"
+fpr_values["f7"] = "0x"
+fpr_values["f8"] = "0x6261747563657845"
+fpr_values["f9"] = "0x766173206562206c"
+fpr_values["f10"] = "0x"
+fpr_values["f11"] = "0x"
+fpr_values["f12"] = "0x"
+fpr_values["f13"] = "0x"
+fpr_values["f14"] = "0x"
+fpr_values["f15"] = "0x"
+fpr_values["f16"] = "0x"
+fpr_values["f17"] = "0x"
+fpr_values["f18"] = "0x"
+fpr_values["f19"] = "0x"
+fpr_values["f20"] = "0x"
+fpr_values["f21"] = "0x"
+fpr_values["f22"] = "0x"
+fpr_values["f23"] = "0x"
+fpr_values["f24"] = "0x"
+fpr_values["f25"] = "0x"
+fpr_values["f26"] = "0x"
+fpr_values["f27"] = "0x"
+fpr_values["f28"] = "0x"
+fpr_values["f29"] = "0x"
+fpr_values["f30"] = "0x"
+fpr_values["f31"] = "0x"
+fpr_values["fcc0"] = "0x01"
+fpr_values["fcc1"] = "0x0"
+fpr_values["fcc2"] = "0x01"
+fpr_values["fcc3"] = "0x01"
+fpr_values["fcc4"] = "0x01"
+fpr_values["fcc5"] = "0x01"
+fpr_values["fcc6"] = "0x0"
SixWeining wrote:
Ditto.
https://github.com/llvm/llvm-project/pull/112296
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[Lldb-commits] [lldb] [lldb][LoongArch64] Add support for LoongArch64 in elf-core for lldb (PR #112296)
@@ -0,0 +1,84 @@ +//===-- RegisterContextPOSIXCore_loongarch64.cpp --===// SixWeining wrote: Generally one line has 80 characters at most. https://github.com/llvm/llvm-project/pull/112296 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][LoongArch64] Add support for LoongArch64 in elf-core for lldb (PR #112296)
@@ -833,6 +845,107 @@ def test_riscv64_regs_gpr_only(self):
substrs=["registers were unavailable"],
)
+@skipIfLLVMTargetMissing("LoongArch")
+def test_loongarch64_regs(self):
+# check registers using 64 bit LoongArch64 core file containing
GP-registers only
+target = self.dbg.CreateTarget(None)
+self.assertTrue(target, VALID_TARGET)
+process = target.LoadCore("linux-loongarch64.core")
+
+values = {}
+values["r0"] = "0x"
+values["r1"] = "0x0001216c"
+values["r2"] = "0x"
+values["r3"] = "0x7b8249e0"
+values["r4"] = "0x"
+values["r5"] = "0x0001210c"
+values["r6"] = "0x"
+values["r7"] = "0x"
+values["r8"] = "0x"
+values["r9"] = "0x"
+values["r10"] = "0x"
+values["r11"] = "0x00dd"
+values["r12"] = "0x"
+values["r13"] = "0x002f"
+values["r14"] = "0x"
+values["r15"] = "0x"
+values["r16"] = "0x"
+values["r17"] = "0x"
+values["r18"] = "0x"
+values["r19"] = "0x"
+values["r20"] = "0x"
+values["r21"] = "0x"
+values["r22"] = "0x7b824a10"
+values["r23"] = "0x"
+values["r24"] = "0x"
+values["r25"] = "0x"
+values["r26"] = "0x"
+values["r27"] = "0x"
+values["r28"] = "0x"
+values["r29"] = "0x"
+values["r30"] = "0x"
+values["r31"] = "0x"
+values["orig_a0"] = "0x56b62d50"
+values["pc"] = "0x0001212c"
+
+fpr_values = {}
+fpr_values["f0"] = "0xff05"
+fpr_values["f1"] = "0x2525252525252525"
+fpr_values["f2"] = "0x2525252525560005"
+fpr_values["f3"] = "0x"
+fpr_values["f4"] = "0x"
+fpr_values["f5"] = "0x0008"
+fpr_values["f6"] = "0x0f0e0d0c0b0a0908"
+fpr_values["f7"] = "0x"
+fpr_values["f8"] = "0x6261747563657845"
+fpr_values["f9"] = "0x766173206562206c"
+fpr_values["f10"] = "0x"
+fpr_values["f11"] = "0x"
+fpr_values["f12"] = "0x"
+fpr_values["f13"] = "0x"
+fpr_values["f14"] = "0x"
+fpr_values["f15"] = "0x"
+fpr_values["f16"] = "0x"
+fpr_values["f17"] = "0x"
+fpr_values["f18"] = "0x"
+fpr_values["f19"] = "0x"
+fpr_values["f20"] = "0x"
+fpr_values["f21"] = "0x"
+fpr_values["f22"] = "0x"
+fpr_values["f23"] = "0x"
+fpr_values["f24"] = "0x"
+fpr_values["f25"] = "0x"
+fpr_values["f26"] = "0x"
+fpr_values["f27"] = "0x"
+fpr_values["f28"] = "0x"
+fpr_values["f29"] = "0x"
+fpr_values["f30"] = "0x"
+fpr_values["f31"] = "0x"
+fpr_values["fcc0"] = "0x01"
+fpr_values["fcc1"] = "0x00"
+fpr_values["fcc2"] = "0x01"
+fpr_values["fcc3"] = "0x01"
+fpr_values["fcc4"] = "0x01"
+fpr_values["fcc5"] = "0x01"
+fpr_values["fcc6"] = "0x00"
+fpr_values["fcc7"] = "0x01"
+fpr_values["fcsr"] = "0x00"
SixWeining wrote:
Not like fcc registers, fcsr is 32bit.
```
(lldb) register read fcsr
fcsr = 0x
```
https://github.com/llvm/llvm-project/pull/112296
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[Lldb-commits] [lldb] [lldb][LoongArch64] Add support for LoongArch64 in elf-core for lldb (PR #112296)
SixWeining wrote: > I'm not aware of the current status of LoongArch in LLDB @DavidSpickett General debugging commands can be used on LoongArch with some known issues to be addressed. Here is a summary #109394. For this PR, I have checked locally. I can confirm core dump file could be debugged with this change. https://github.com/llvm/llvm-project/pull/112296 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][LoongArch64] Add support for LoongArch64 in elf-core for lldb (PR #112296)
SixWeining wrote: > For RISC-V I have been using #55383 as the tracking issue for overall > support. If you want to, you could open a similar issue and write out what > currently works, and I'll link to it from the [main lldb > page](https://lldb.llvm.org/#platform-support). Not a requirement, just if > you have the time. Thanks. I just filed #112693. https://github.com/llvm/llvm-project/pull/112296 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][Process/Linux] Introduce LoongArch64 hw break/watchpoint support (PR #118043)
@@ -337,4 +354,471 @@
NativeRegisterContextLinux_loongarch64::GetExpeditedRegisters(
return expedited_reg_nums;
}
+uint32_t
+NativeRegisterContextLinux_loongarch64::NumSupportedHardwareBreakpoints() {
+ Log *log = GetLog(LLDBLog::Breakpoints);
+
+ // Read hardware breakpoint and watchpoint information.
+ Status error = ReadHardwareDebugInfo();
+
+ if (error.Fail()) {
+LLDB_LOG(log, "failed to read debug registers");
+return 0;
+ }
+
+ LLDB_LOG(log, "{0}", m_max_hbp_supported);
SixWeining wrote:
Could we make the log message more readable? For example `Supported hardware
breakpoints: {0}`
https://github.com/llvm/llvm-project/pull/118043
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[Lldb-commits] [lldb] [lldb][Process/Linux] Introduce LoongArch64 hw break/watchpoint support (PR #118043)
@@ -337,4 +354,471 @@
NativeRegisterContextLinux_loongarch64::GetExpeditedRegisters(
return expedited_reg_nums;
}
+uint32_t
+NativeRegisterContextLinux_loongarch64::NumSupportedHardwareBreakpoints() {
+ Log *log = GetLog(LLDBLog::Breakpoints);
+
+ // Read hardware breakpoint and watchpoint information.
+ Status error = ReadHardwareDebugInfo();
+
+ if (error.Fail()) {
+LLDB_LOG(log, "failed to read debug registers");
+return 0;
+ }
+
+ LLDB_LOG(log, "{0}", m_max_hbp_supported);
+ return m_max_hbp_supported;
+}
+
+uint32_t
+NativeRegisterContextLinux_loongarch64::SetHardwareBreakpoint(lldb::addr_t
addr,
+ size_t size) {
+ Log *log = GetLog(LLDBLog::Breakpoints);
+ LLDB_LOG(log, "addr: {0:x}, size: {1:x}", addr, size);
SixWeining wrote:
Ditto.
https://github.com/llvm/llvm-project/pull/118043
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[Lldb-commits] [lldb] [lldb][Process/Linux] Introduce LoongArch64 hw break/watchpoint support (PR #118043)
@@ -337,4 +354,471 @@
NativeRegisterContextLinux_loongarch64::GetExpeditedRegisters(
return expedited_reg_nums;
}
+uint32_t
+NativeRegisterContextLinux_loongarch64::NumSupportedHardwareBreakpoints() {
+ Log *log = GetLog(LLDBLog::Breakpoints);
+
+ // Read hardware breakpoint and watchpoint information.
+ Status error = ReadHardwareDebugInfo();
+
+ if (error.Fail()) {
+LLDB_LOG(log, "failed to read debug registers");
+return 0;
+ }
+
+ LLDB_LOG(log, "{0}", m_max_hbp_supported);
+ return m_max_hbp_supported;
+}
+
+uint32_t
+NativeRegisterContextLinux_loongarch64::SetHardwareBreakpoint(lldb::addr_t
addr,
+ size_t size) {
+ Log *log = GetLog(LLDBLog::Breakpoints);
+ LLDB_LOG(log, "addr: {0:x}, size: {1:x}", addr, size);
+
+ // Read hardware breakpoint and watchpoint information.
+ Status error = ReadHardwareDebugInfo();
+ if (error.Fail()) {
+LLDB_LOG(log, "unable to set breakpoint: failed to read debug registers");
+return LLDB_INVALID_INDEX32;
+ }
+
+ uint32_t bp_index = 0;
+
+ // Check if size has a valid hardware breakpoint length.
+ if (size != 4)
+return LLDB_INVALID_INDEX32; // Invalid size for a LoongArch hardware
+ // breakpoint
+
+ // Check 4-byte alignment for hardware breakpoint target address.
+ if (addr & 0x03)
+return LLDB_INVALID_INDEX32; // Invalid address, should be 4-byte aligned.
+
+ // Iterate over stored breakpoints and find a free bp_index
+ bp_index = LLDB_INVALID_INDEX32;
+ for (uint32_t i = 0; i < m_max_hbp_supported; i++) {
+if (!BreakpointIsEnabled(i))
+ bp_index = i; // Mark last free slot
+else if (m_hbp_regs[i].address == addr)
+ return LLDB_INVALID_INDEX32; // We do not support duplicate breakpoints.
+ }
+
+ if (bp_index == LLDB_INVALID_INDEX32)
+return LLDB_INVALID_INDEX32;
+
+ // Update breakpoint in local cache
+ m_hbp_regs[bp_index].address = addr;
+ m_hbp_regs[bp_index].control = g_enable_bit;
+
+ // PTRACE call to set corresponding hardware breakpoint register.
+ error = WriteHardwareDebugRegs(eDREGTypeBREAK);
+
+ if (error.Fail()) {
+m_hbp_regs[bp_index].address = 0;
+m_hbp_regs[bp_index].control = 0;
+
+LLDB_LOG(log, "unable to set breakpoint: failed to write debug registers");
+return LLDB_INVALID_INDEX32;
+ }
+
+ return bp_index;
+}
+bool NativeRegisterContextLinux_loongarch64::ClearHardwareBreakpoint(
+uint32_t hw_idx) {
+ Log *log = GetLog(LLDBLog::Breakpoints);
+ LLDB_LOG(log, "hw_idx: {0}", hw_idx);
+
+ // Read hardware breakpoint and watchpoint information.
+ Status error = ReadHardwareDebugInfo();
+ if (error.Fail()) {
+LLDB_LOG(log, "unable to clear breakpoint: failed to read debug
registers");
+return false;
+ }
+
+ if (hw_idx >= m_max_hbp_supported)
+return false;
+
+ // Create a backup we can revert to in case of failure.
+ lldb::addr_t tempAddr = m_hbp_regs[hw_idx].address;
+ uint32_t tempControl = m_hbp_regs[hw_idx].control;
+
+ m_hbp_regs[hw_idx].control = 0;
+ m_hbp_regs[hw_idx].address = 0;
+
+ // PTRACE call to clear corresponding hardware breakpoint register.
+ error = WriteHardwareDebugRegs(eDREGTypeBREAK);
+
+ if (error.Fail()) {
+m_hbp_regs[hw_idx].control = tempControl;
+m_hbp_regs[hw_idx].address = tempAddr;
+
+LLDB_LOG(log,
+ "unable to clear breakpoint: failed to write debug registers");
+return false;
+ }
+
+ return true;
+}
+Status NativeRegisterContextLinux_loongarch64::GetHardwareBreakHitIndex(
+uint32_t &bp_index, lldb::addr_t trap_addr) {
+ Log *log = GetLog(LLDBLog::Breakpoints);
+
+ LLDB_LOGF(log, "NativeRegisterContextLinux_loongarch64::%s()", __FUNCTION__);
+
+ lldb::addr_t break_addr;
+
+ for (bp_index = 0; bp_index < m_max_hbp_supported; ++bp_index) {
+break_addr = m_hbp_regs[bp_index].address;
+
+if (BreakpointIsEnabled(bp_index) && trap_addr == break_addr) {
+ m_hbp_regs[bp_index].hit_addr = trap_addr;
+ return Status();
+}
+ }
+
+ bp_index = LLDB_INVALID_INDEX32;
+ return Status();
+}
+Status NativeRegisterContextLinux_loongarch64::ClearAllHardwareBreakpoints() {
+ Log *log = GetLog(LLDBLog::Breakpoints);
+
+ LLDB_LOGF(log, "NativeRegisterContextLinux_loongarch64::%s()", __FUNCTION__);
+
+ // Read hardware breakpoint and watchpoint information.
+ Status error = ReadHardwareDebugInfo();
+ if (error.Fail())
+return error;
+
+ for (uint32_t i = 0; i < m_max_hbp_supported; i++) {
+if (!BreakpointIsEnabled(i))
+ continue;
+// Create a backup we can revert to in case of failure.
+lldb::addr_t tempAddr = m_hbp_regs[i].address;
+uint32_t tempControl = m_hbp_regs[i].control;
+
+// Clear watchpoints in local cache
+m_hbp_regs[i].control = 0;
+m_hbp_regs[i].address = 0;
+
+// Ptrace call to update hardware debug registers
+error = WriteHardwareDebugRegs(eDREGTypeBREAK);
+
+if (error.Fai
[Lldb-commits] [lldb] [LLDB][LoongArch] Fix build errors and extend watchpoint numbers (PR #126020)
@@ -36,9 +36,30 @@
0xa03 /* LoongArch Advanced SIMD eXtension registers */
#endif
+#ifndef NT_LOONGARCH_HW_BREAK
+#define NT_LOONGARCH_HW_BREAK 0xa05 /* LoongArch hardware breakpoint
registers */
+#endif
+
+#ifndef NT_LOONGARCH_HW_WATCH
+#define NT_LOONGARCH_HW_WATCH 0xa06 /* LoongArch hardware watchpoint
registers */
+#endif
+
#define REG_CONTEXT_SIZE
\
(GetGPRSize() + GetFPRSize() + sizeof(m_lsx) + sizeof(m_lasx))
+// In order to avoid undefined or redefined error, just add a new struct
+// loongarch_user_watch_state in LLDB which is same with the uapi struct
+// user_watch_state_v2.
+struct loongarch_user_watch_state {
SixWeining wrote:
Seems the code indent is inappropriate.
https://github.com/llvm/llvm-project/pull/126020
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[Lldb-commits] [lldb] [LLDB][LoongArch] Fix build errors and extend watchpoint numbers (PR #126020)
https://github.com/SixWeining commented: LGTM with a nit. LLVM uses squash merge. If you'd to keep the 2 commits, please summit 2 PRs. https://github.com/llvm/llvm-project/pull/126020 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [LLDB][LoongArch] Fix build errors and extend watchpoint numbers (PR #126020)
https://github.com/SixWeining edited https://github.com/llvm/llvm-project/pull/126020 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [LLDB][LoongArch] Extend the maximum number of watchpoints (PR #126204)
https://github.com/SixWeining approved this pull request. https://github.com/llvm/llvm-project/pull/126204 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [LLDB][LoongArch] Extend the maximum number of watchpoints (PR #126204)
https://github.com/SixWeining closed https://github.com/llvm/llvm-project/pull/126204 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [LLDB][LoongArch] Fix build errors about NT_LOONGARCH_HW_{BREAK, WATCH} (PR #126020)
https://github.com/SixWeining approved this pull request. https://github.com/llvm/llvm-project/pull/126020 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [LLDB][LoongArch] Fix build errors about NT_LOONGARCH_HW_{BREAK, WATCH} (PR #126020)
https://github.com/SixWeining closed https://github.com/llvm/llvm-project/pull/126020 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][LoongArch] Fix the incorrect floating-point register dwarf number (PR #120391)
https://github.com/SixWeining approved this pull request. https://github.com/llvm/llvm-project/pull/120391 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [LLDB][LoongArch] Add LSX and LASX register definitions and operations (PR #120664)
https://github.com/SixWeining commented: Could you add some tests in `lldb/test/Shell/Register/` ? https://github.com/llvm/llvm-project/pull/120664 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [LLDB][LoongArch] Add LSX and LASX register definitions and operations (PR #120664)
@@ -27,6 +27,14 @@ // struct iovec definition #include +#ifndef NT_LARCH_LSX SixWeining wrote: Why not use the `NT_LOONGARCH_LSX` defined in elf.h? https://github.com/llvm/llvm-project/pull/120664 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [LLDB][LoongArch] Add LSX and LASX register definitions and operations (PR #120664)
https://github.com/SixWeining edited https://github.com/llvm/llvm-project/pull/120664 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [lldb] [lldb][LoongArch] Complete register alias name in `AugmentRegisterInfo` (PR #124059)
https://github.com/SixWeining approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/124059 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
