[Lldb-commits] [clang-tools-extra] [compiler-rt] [lldb] [llvm] [libc] [flang] [clang] [GlobalIsel] Combine select of binops (PR #76763)

[Kai Luo via lldb-commits]

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bzEq wrote:

It's also exhausting memory when `llvm-lit 
llvm-project/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll`.
See https://lab.llvm.org/buildbot/#/builders/249/builds/13786.

https://github.com/llvm/llvm-project/pull/76763
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[Lldb-commits] [llvm] [libcxxabi] [libcxx] [clang-tools-extra] [libunwind] [compiler-rt] [lld] [libc] [clang] [flang] [lldb] [PowerPC] Combine sub within setcc back to sext (PR #66978)

[Kai Luo via lldb-commits]

bzEq wrote:

Please provide more description in PR summary.

https://github.com/llvm/llvm-project/pull/66978
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[Lldb-commits] [clang-tools-extra] [libunwind] [libcxx] [compiler-rt] [clang] [llvm] [lld] [libcxxabi] [lldb] [libc] [flang] [PowerPC] Combine sub within setcc back to sext (PR #66978)

[Kai Luo via lldb-commits]

@@ -14428,15 +14431,52 @@ SDValue PPCTargetLowering::combineSetCC(SDNode *N,
 // x != 0-y --> x+y != 0
 if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
 RHS.hasOneUse()) {
-  SDLoc DL(N);
-  SelectionDAG &DAG = DCI.DAG;
-  EVT VT = N->getValueType(0);
-  EVT OpVT = LHS.getValueType();
   SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LHS, RHS.getOperand(1));
   return DAG.getSetCC(DL, VT, Add, DAG.getConstant(0, DL, OpVT), CC);
 }
   }
 
+  if (CC == ISD::SETULT && isa(RHS)) {
+uint64_t RHSVal = cast(RHS)->getZExtValue();
+if (LHS.getOpcode() == ISD::ADD && isa(LHS.getOperand(1))) 
{
+  uint64_t Addend = 
cast(LHS.getOperand(1))->getZExtValue();
+  if (OpVT == MVT::i64) {
+uint64_t ShiftVal = ~Addend + 1;

bzEq wrote:

```suggestion
uint64_t ShiftVal = -Addend;
```

https://github.com/llvm/llvm-project/pull/66978
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[Lldb-commits] [libcxx] [lldb] [compiler-rt] [clang-tools-extra] [flang] [clang] [libcxxabi] [libc] [libunwind] [lld] [llvm] [PowerPC] Combine sub within setcc back to sext (PR #66978)

[Kai Luo via lldb-commits]

@@ -14428,15 +14431,52 @@ SDValue PPCTargetLowering::combineSetCC(SDNode *N,
 // x != 0-y --> x+y != 0
 if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
 RHS.hasOneUse()) {
-  SDLoc DL(N);
-  SelectionDAG &DAG = DCI.DAG;
-  EVT VT = N->getValueType(0);
-  EVT OpVT = LHS.getValueType();
   SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LHS, RHS.getOperand(1));
   return DAG.getSetCC(DL, VT, Add, DAG.getConstant(0, DL, OpVT), CC);
 }
   }
 
+  if (CC == ISD::SETULT && isa(RHS)) {
+uint64_t RHSVal = cast(RHS)->getZExtValue();
+if (LHS.getOpcode() == ISD::ADD && isa(LHS.getOperand(1))) 
{
+  uint64_t Addend = 
cast(LHS.getOperand(1))->getZExtValue();
+  if (OpVT == MVT::i64) {
+uint64_t ShiftVal = ~Addend + 1;
+uint64_t CmpVal = ~RHSVal + 1;

bzEq wrote:

```suggestion
uint64_t CmpVal = -RHSVal;
```

https://github.com/llvm/llvm-project/pull/66978
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[Lldb-commits] [libunwind] [clang-tools-extra] [lld] [flang] [libc] [compiler-rt] [libcxx] [clang] [libcxxabi] [lldb] [llvm] [PowerPC] Combine sub within setcc back to sext (PR #66978)

[Kai Luo via lldb-commits]

@@ -14428,15 +14431,52 @@ SDValue PPCTargetLowering::combineSetCC(SDNode *N,
 // x != 0-y --> x+y != 0
 if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
 RHS.hasOneUse()) {
-  SDLoc DL(N);
-  SelectionDAG &DAG = DCI.DAG;
-  EVT VT = N->getValueType(0);
-  EVT OpVT = LHS.getValueType();
   SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LHS, RHS.getOperand(1));
   return DAG.getSetCC(DL, VT, Add, DAG.getConstant(0, DL, OpVT), CC);
 }
   }
 
+  if (CC == ISD::SETULT && isa(RHS)) {
+uint64_t RHSVal = cast(RHS)->getZExtValue();
+if (LHS.getOpcode() == ISD::ADD && isa(LHS.getOperand(1))) 
{
+  uint64_t Addend = 
cast(LHS.getOperand(1))->getZExtValue();
+  if (OpVT == MVT::i64) {
+uint64_t ShiftVal = ~Addend + 1;
+uint64_t CmpVal = ~RHSVal + 1;
+if (isPowerOf2_64(ShiftVal) && ShiftVal << 1 == CmpVal) {

bzEq wrote:

Add comment for the DAG pattern found. Better provide alive2 prove in the PR 
summary.

https://github.com/llvm/llvm-project/pull/66978
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