Jianhui-Li wrote:
> > At some point it would be nice to have some design document or
> > documentation somewhere explaining how all these MLIR runners works,
> > including this one.
>
> The idea is to eventually consolidate all runners into one. This PR is just
> another piece of the puzzle.
>
> Once we're all happy with how the runners work, we should common them up
> using command line options to select the "type" and CMake options to enable
> particular runner types (depending on the runtimes and hardware available).
>
> > Globally this PR add a SYCL runner, but it is very specific for Intel Level
> > 0. It would be nice to have in the future some generalization, like SYCL
> > using OpenCL interoperability interface to run the SPIR-V kernels or even
> > native kernels.
>
> Agreed! The SYCL runtime here is just being used to abstract the LevelZero
> calls, but this work will be helpful when adding a full SYCL runner (actual
> language extensions and libraries) to other CPUs/GPUs later.
Agree. The key point of this PR is not to create yet another runner, but just
enable the existing mlir-cpu-runner to runs llvm + device kernel on SYCL
platform. The current implementation uses L0 but could be extended.
I won't call this as adding a "SYCL runner", it is add SYCL backend to
mlir-cpu-runner. The term "xxx runner" in MLIR is a bit overused.
mlir-cpu-runner doesn't mean it runs only on CPU, instead it runs both the host
and device kernel. mlir-cpu-runner currently does that but the name is a bit
misleading. We really just need a "mlir-runner" with target-platform as
command parameters.
https://github.com/llvm/llvm-project/pull/65539
___
lldb-commits mailing list
lldb-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
