[Lldb-commits] [clang] [libcxx] [llvm] [libunwind] [libc] [lldb] [compiler-rt] [lld] [clang-tools-extra] [flang] [AMDGPU] Fix predicates for V_DOT instructions. (PR #78198)

[Ivan Kosarev via lldb-commits]

https://github.com/kosarev updated 
https://github.com/llvm/llvm-project/pull/78198

>From 0dc06c5ab3b1ff5f2441ff0ee26f5a6dfbbb7753 Mon Sep 17 00:00:00 2001
From: Ivan Kosarev 
Date: Mon, 15 Jan 2024 17:20:34 +
Subject: [PATCH] [AMDGPU] Fix predicates for V_DOT instructions.

Resolves AsmParser ambiguities, e.g., between V_DOT4C_I32_I8_dpp_vi and
V_DOT4C_I32_I8_dpp_gfx10. The latter is predicated with isGFX10Only while
the first has no subtarget generation predicates.

Part of .
---
 llvm/lib/Target/AMDGPU/VOP2Instructions.td | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td 
b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index 48d4e259bc1cec..bbb2ac0bdb861d 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -2512,6 +2512,7 @@ defm V_FMAAK_F32: VOP2_Real_MADK_gfx940 <0x18>;
 }
 
 multiclass VOP2_Real_DOT_ACC_gfx9 op> : Base_VOP2_Real_e32e64_vi {
+  let SubtargetPredicate = isGFX9Only in
   def _dpp_vi : VOP2_DPP(NAME#"_dpp")>;
 }
 
@@ -2520,22 +2521,22 @@ multiclass VOP2_Real_DOT_ACC_gfx10 op> :
   VOP2_Real_dpp_gfx10,
   VOP2_Real_dpp8_gfx10;
 
-let SubtargetPredicate = HasDot5Insts in {
+let OtherPredicates = [HasDot5Insts] in {
   defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx9<0x37>;
   // NB: Opcode conflicts with V_DOT8C_I32_I4
   // This opcode exists in gfx 10.1* only
   defm V_DOT2C_F32_F16 : VOP2_Real_DOT_ACC_gfx10<0x02>;
 }
 
-let SubtargetPredicate = HasDot6Insts in {
+let OtherPredicates = [HasDot6Insts] in {
   defm V_DOT4C_I32_I8  : VOP2_Real_DOT_ACC_gfx9<0x39>;
   defm V_DOT4C_I32_I8  : VOP2_Real_DOT_ACC_gfx10<0x0d>;
 }
 
-let SubtargetPredicate = HasDot4Insts in {
+let OtherPredicates = [HasDot4Insts] in {
   defm V_DOT2C_I32_I16 : VOP2_Real_DOT_ACC_gfx9<0x38>;
 }
-let SubtargetPredicate = HasDot3Insts in {
+let OtherPredicates = [HasDot3Insts] in {
   defm V_DOT8C_I32_I4  : VOP2_Real_DOT_ACC_gfx9<0x3a>;
 }
 

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[Lldb-commits] [clang-tools-extra] [libcxx] [clang] [lldb] [lld] [llvm] [flang] [libc] [compiler-rt] [AMDGPU][GFX12] VOP encoding and codegen - add support for v_cvt fp8/… (PR #78414)

[Ivan Kosarev via lldb-commits]

kosarev wrote:

> Correct, some of these instructions use opsel[1] which in LLVM in stored in 
> src1_modifiers so a dummy src1 is used.

Why can't we just use `SRCMODS.OP_SEL_1` with src0?

https://github.com/llvm/llvm-project/pull/78414
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[Lldb-commits] [libcxx] [lld] [libc] [lldb] [clang] [flang] [compiler-rt] [clang-tools-extra] [llvm] [AMDGPU][GFX12] VOP encoding and codegen - add support for v_cvt fp8/… (PR #78414)

[Ivan Kosarev via lldb-commits]

@@ -626,11 +629,82 @@ class Cvt_PK_F32_F8_Pat;
 
-foreach Index = [0, -1] in {
-  def : Cvt_PK_F32_F8_Pat;
-  def : Cvt_PK_F32_F8_Pat;
+let SubtargetPredicate = isGFX9Only in {
+  foreach Index = [0, -1] in {
+def : Cvt_PK_F32_F8_Pat;
+def : Cvt_PK_F32_F8_Pat;
+  }
+}
+
+
+// Similar to VOPProfile_Base_CVT_F32_F8, but for VOP3 instructions.
+def VOPProfile_Base_CVT_PK_F32_F8_OpSel : VOPProfileI2F  {
+  let InsVOP3OpSel = (ins Src0Mod:$src0_modifiers, Src0RC64:$src0,
+  clampmod:$clamp, omod:$omod, op_sel0:$op_sel);
+
+  let HasOpSel = 1;
+  let HasExtVOP3DPP = 0;
+}
+
+def VOPProfile_Base_CVT_F32_F8_OpSel : VOPProfile<[f32, i32, i32, untyped]> {
+  let InsVOP3OpSel = (ins Src0Mod:$src0_modifiers, Src0RC64:$src0,
+  Src1Mod:$src1_modifiers, Src1RC64:$src1,
+  clampmod:$clamp, omod:$omod, op_sel0:$op_sel);
+  let AsmVOP3OpSel = !subst(", $src1_modifiers", "", getAsmVOP3OpSel<2, 0, 0, 
1, 1, 0>.ret);
+
+  let HasOpSel = 1;
+  let HasExtDPP = 1;
+  let HasExtVOP3DPP = 1;
+
+  let Src1VOP3DPP = Src1RC64;
+  let AsmVOP3DPP8 = getAsmVOP3DPP8.ret;
+  let AsmVOP3DPP16 = getAsmVOP3DPP16.ret;
+}
+
+let SubtargetPredicate = isGFX12Plus, mayRaiseFPException = 0,
+SchedRW = [WriteFloatCvt] in {
+  defm V_CVT_F32_FP8_OP_SEL: VOP1Inst<"v_cvt_f32_fp8_op_sel", 
VOPProfile_Base_CVT_F32_F8_OpSel>;
+  defm V_CVT_F32_BF8_OP_SEL: VOP1Inst<"v_cvt_f32_bf8_op_sel", 
VOPProfile_Base_CVT_F32_F8_OpSel>;
+  defm V_CVT_PK_F32_FP8_OP_SEL : VOP1Inst<"v_cvt_pk_f32_fp8_op_sel", 
VOPProfile_Base_CVT_PK_F32_F8_OpSel>;
+  defm V_CVT_PK_F32_BF8_OP_SEL : VOP1Inst<"v_cvt_pk_f32_bf8_op_sel", 
VOPProfile_Base_CVT_PK_F32_F8_OpSel>;
+}
+
+class Cvt_F32_F8_Pat_OpSel index,
+VOP1_Pseudo inst_e32, VOP3_Pseudo inst_e64> : GCNPat<
+(f32 (node i32:$src, index)),
+!if (index,
+ (inst_e64 !if(index{0}, SRCMODS.OP_SEL_0, SRCMODS.OP_SEL_1), $src,
+   !if(index{1}, SRCMODS.OP_SEL_0, SRCMODS.OP_SEL_1), (i32 0),

kosarev wrote:

Why do we expect `SRCMODS.OP_SEL_1` for dropped index bits? Is there any test 
coverage for these cases?

https://github.com/llvm/llvm-project/pull/78414
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[Lldb-commits] [clang] [libcxx] [libc] [lld] [llvm] [flang] [clang-tools-extra] [lldb] [compiler-rt] [AMDGPU][GFX12] VOP encoding and codegen - add support for v_cvt fp8/… (PR #78414)

[Ivan Kosarev via lldb-commits]

Mirko =?utf-8?q?Brkušanin?= 
Message-ID:
In-Reply-To: 



@@ -305,6 +305,11 @@ class VOP3OpSel_gfx10 op, VOPProfile p> : 
VOP3e_gfx10 {
 
 class VOP3OpSel_gfx11_gfx12 op, VOPProfile p> : VOP3OpSel_gfx10;
 
+class VOP3FP8OpSel_gfx11_gfx12 op, VOPProfile p> : VOP3e_gfx10 
{
+  let Inst{11} = !if(p.HasSrc0, src0_modifiers{2}, 0);
+  let Inst{12} = !if(p.HasSrc0, src0_modifiers{3}, 0);

kosarev wrote:

Yes, thanks Mirko. Can we also avoid adding the other dummy operands in 
`cvtVOP3DPP()` and `cvtDPP()`?

https://github.com/llvm/llvm-project/pull/78414
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