[Lldb-commits] [flang] [lldb] [llvm] [clang-tools-extra] [compiler-rt] [mlir] [clang] [Profile] Add binary profile correlation for code coverage. (PR #69493)

2023-12-11 Thread David Li via lldb-commits 

david-xl wrote:

> @david-xl , Zequan posted an 
> [RFC](https://discourse.llvm.org/t/rfc-add-binary-profile-correlation-to-not-load-profile-metadata-sections-into-memory-at-runtime/74565/8)
>  for this. Is there a PGO tag, or something we can use to increase visibility 
> for PGO reviewers? I think most of the complexity for this new mode is in the 
> PGO code, so I think the best person to review it would be someone with an 
> interest in PGO.
> 
> I'll tag some folks, but let me know if there is a better way: @kparzysz 
> @snehasish

I am aware of this patch and it mostly look good to me. Since there is a long 
list of reviewers attached to this PR, better give more time for them to chime 
in.  I am quite busy early part of this week, but will try to give it another 
round by the end of the week if no one else beats me to it.

https://github.com/llvm/llvm-project/pull/69493
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[Lldb-commits] [lldb] [llvm] [clang-tools-extra] [compiler-rt] [mlir] [clang] [flang] [Profile] Add binary profile correlation for code coverage. (PR #69493)

2023-12-12 Thread David Li via lldb-commits 


@@ -0,0 +1,9 @@
+// RUN: %clang_cc1  -fprofile-instrument=clang -fcoverage-mapping -emit-llvm 
-o - %s | FileCheck %s
+// RUN: %clang_cc1 -mllvm -profile-correlate=binary -fprofile-instrument=clang 
-fcoverage-mapping -emit-llvm -o - %s | FileCheck %s 
--check-prefix=BIN-CORRELATE
+
+// CHECK: @__llvm_profile_raw_version = {{.*}} i64 9

david-xl wrote:

why is it 9?

https://github.com/llvm/llvm-project/pull/69493
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[Lldb-commits] [clang] [llvm] [flang] [mlir] [compiler-rt] [lldb] [clang-tools-extra] [Profile] Add binary profile correlation for code coverage. (PR #69493)

2023-12-12 Thread David Li via lldb-commits 

https://github.com/david-xl approved this pull request.

LGTM. Thanks for the new feature. (Wait a few days in case other reviewers have 
additional comments).

https://github.com/llvm/llvm-project/pull/69493
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[Lldb-commits] [flang] [clang] [lldb] [mlir] [compiler-rt] [clang-tools-extra] [llvm] [Profile] Add binary profile correlation for code coverage. (PR #69493)

2023-12-12 Thread David Li via lldb-commits 


@@ -1829,6 +1833,22 @@ void CoverageMappingModuleGen::emit() {
  llvm::GlobalValue::InternalLinkage, NamesArrVal,
  llvm::getCoverageUnusedNamesVarName());
   }
+  const StringRef VarName(INSTR_PROF_QUOTE(INSTR_PROF_RAW_VERSION_VAR));
+  llvm::Type *IntTy64 = llvm::Type::getInt64Ty(Ctx);
+  uint64_t ProfileVersion = INSTR_PROF_RAW_VERSION;
+  if (llvm::ProfileCorrelate == llvm::InstrProfCorrelator::BINARY)
+ProfileVersion |= VARIANT_MASK_BIN_CORRELATE;

david-xl wrote:

This might overwrite other modifier bits set else where.

https://github.com/llvm/llvm-project/pull/69493
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[Lldb-commits] [flang] [llvm] [compiler-rt] [clang] [lldb] [mlir] [clang-tools-extra] [Profile] Add binary profile correlation for code coverage. (PR #69493)

2023-12-12 Thread David Li via lldb-commits 

https://github.com/david-xl edited 
https://github.com/llvm/llvm-project/pull/69493
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[Lldb-commits] [mlir] [flang] [clang-tools-extra] [lldb] [compiler-rt] [clang] [llvm] [Profile] Add binary profile correlation for code coverage. (PR #69493)

2023-12-12 Thread David Li via lldb-commits 


@@ -1829,6 +1833,22 @@ void CoverageMappingModuleGen::emit() {
  llvm::GlobalValue::InternalLinkage, NamesArrVal,
  llvm::getCoverageUnusedNamesVarName());
   }
+  const StringRef VarName(INSTR_PROF_QUOTE(INSTR_PROF_RAW_VERSION_VAR));

david-xl wrote:

Add some comments for this segment.

https://github.com/llvm/llvm-project/pull/69493
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[Lldb-commits] [llvm] [lldb] [compiler-rt] [libunwind] [mlir] [libcxx] [clang] [libc] [flang] [clang-tools-extra] [lld] [IRPGO][ValueProfile] Instrument virtual table address that could be used to do

2023-12-19 Thread David Li via lldb-commits 

https://github.com/david-xl approved this pull request.

After this patch,  follow up with a patch documenting raw and index format. 
This has long being requested by many in the community.

https://github.com/llvm/llvm-project/pull/66825
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[Lldb-commits] [mlir] [lldb] [llvm] [clang] [compiler-rt] Enable Custom Lowering for fabs.v8f16 on AVX (PR #71730)

2023-11-13 Thread David Li via lldb-commits 

https://github.com/david-xl updated 
https://github.com/llvm/llvm-project/pull/71730

>From 6032b965f85482b39e841bd95842f4e17c92fefd Mon Sep 17 00:00:00 2001
From: David Li 
Date: Tue, 7 Nov 2023 23:29:44 -0800
Subject: [PATCH 1/6] Enable Custom Lowering for fabs.v8f16 on AVX

---
 llvm/lib/Target/X86/X86ISelLowering.cpp |  3 ++
 llvm/test/CodeGen/X86/vec_fabs.ll   | 41 +
 2 files changed, 44 insertions(+)

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp 
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 22fba5601ccfd38..8d9519b9f8c6b10 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2238,6 +2238,9 @@ X86TargetLowering::X86TargetLowering(const 
X86TargetMachine &TM,
 }
   }
 
+  if (Subtarget.hasAVX())
+setOperationAction(ISD::FABS, MVT::v8f16, Custom);
+
   if (!Subtarget.useSoftFloat() &&
   (Subtarget.hasAVXNECONVERT() || Subtarget.hasBF16())) {
 addRegisterClass(MVT::v8bf16, Subtarget.hasAVX512() ? &X86::VR128XRegClass
diff --git a/llvm/test/CodeGen/X86/vec_fabs.ll 
b/llvm/test/CodeGen/X86/vec_fabs.ll
index 982062d8907542a..08364449ab1a378 100644
--- a/llvm/test/CodeGen/X86/vec_fabs.ll
+++ b/llvm/test/CodeGen/X86/vec_fabs.ll
@@ -1,8 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s 
--check-prefix=X86 --check-prefix=X86-AVX
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s 
--check-prefix=X86 --check-prefix=X86-AVX2
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512vl | FileCheck %s 
--check-prefix=X86 --check-prefix=X86-AVX512VL
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512dq,+avx512vl | 
FileCheck %s --check-prefix=X86 --check-prefix=X86-AVX512VLDQ
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s 
--check-prefix=X64 --check-prefix=X64-AVX
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s 
--check-prefix=X64 --check-prefix=X64-AVX2
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl | FileCheck 
%s --check-prefix=X64 --check-prefix=X64-AVX512VL
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl | 
FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX512VLDQ
 
@@ -111,6 +113,45 @@ define <4 x double> @fabs_v4f64(<4 x double> %p) {
 }
 declare <4 x double> @llvm.fabs.v4f64(<4 x double> %p)
 
+define <8 x half> @fabs_v8f16(ptr %p) {
+; X86-AVX-LABEL: fabs_v8f16:
+; X86-AVX:   # %bb.0:
+; X86-AVX-NEXT:movl 4(%esp), [[ADDRREG:%.*]]
+; X86-AVX-NEXT:vmovaps ([[ADDRREG]]), %xmm0
+; X86-AVX-NEXT:vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
+; X86-AVX-NEXT:retl
+
+; X86-AVX2-LABEL: fabs_v8f16:
+; X86-AVX2:   # %bb.0:
+; X86-AVX2-NEXT:movl 4(%esp), [[REG:%.*]]
+; X86-AVX2-NEXT:vpbroadcastw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
+; X86-AVX2-NEXT:vpand ([[REG]]), %xmm0, %xmm0
+; X86-AVX2-NEXT:retl
+
+; X64-AVX512VL-LABEL: fabs_v8f16:
+; X64-AVX512VL:   # %bb.0:
+; X64-AVX512VL-NEXT:vpbroadcastw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-AVX512VL-NEXT:vpand (%rdi), %xmm0, %xmm0
+; X64-AVX512VL-NEXT:retq
+
+; X64-AVX-LABEL: fabs_v8f16:
+; X64-AVX:   # %bb.0:
+; X64-AVX-NEXT:vmovaps (%rdi), %xmm0
+; X64-AVX-NEXT:vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT:retq
+
+; X64-AVX2-LABEL: fabs_v8f16:
+; X64-AVX2:   # %bb.0:
+; X64-AVX2-NEXT:vpbroadcastw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X64-AVX2-NEXT:vpand (%rdi), %xmm0, %xmm0
+; X64-AVX2-NEXT:retq
+
+  %v = load <8 x half>, ptr %p, align 16
+  %nnv = call <8 x half> @llvm.fabs.v8f16(<8 x half> %v)
+  ret <8 x half> %nnv
+}
+declare <8 x half> @llvm.fabs.v8f16(<8 x half> %p)
+
 define <8 x float> @fabs_v8f32(<8 x float> %p) {
 ; X86-AVX-LABEL: fabs_v8f32:
 ; X86-AVX:   # %bb.0:

>From f2f3136667805cc7202ccba45e01393afe34ccc5 Mon Sep 17 00:00:00 2001
From: David Li 
Date: Tue, 7 Nov 2023 23:29:44 -0800
Subject: [PATCH 2/6] Enable Custom Lowering for fabs.v8f16 on AVX

---
 llvm/lib/Target/X86/X86ISelLowering.cpp |  3 ++
 llvm/test/CodeGen/X86/vec_fabs.ll   | 41 +
 2 files changed, 44 insertions(+)

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp 
b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 22fba5601ccfd38..8d9519b9f8c6b10 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2238,6 +2238,9 @@ X86TargetLowering::X86TargetLowering(const 
X86TargetMachine &TM,
 }
   }
 
+  if (Subtarget.hasAVX())
+setOperationAction(ISD::FABS, MVT::v8f16, Custom);
+
   if (!Subtarget.useSoftFloat() &&
   (Subtarget.hasAVXNECONVERT() || Subtarget.hasBF16())) {
 addRegisterClass(MVT::v8bf16, Subtarget.hasAVX512() ? &X86::VR128XRegClass
diff --git a/llvm/test/CodeGen/X86/vec_fabs.ll 
b/llvm/test/CodeGen/X86/vec_fabs.ll
index 98