[Lldb-commits] [PATCH] D41962: Fix TestYMMRegisters for older machines without AVX2

2018-01-11 Thread Craig Topper via Phabricator via lldb-commits 
craig.topper added a comment.

I don't know what platforms this needs to support. But __builtin_cpu_support 
only works when compiled with clang or gcc. And it requires compiler-rt or 
libgcc. I don't know if that's guaranteed to exist on Windows.


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https://reviews.llvm.org/D41962



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[Lldb-commits] [PATCH] D41962: Fix TestYMMRegisters for older machines without AVX2

2018-01-12 Thread Craig Topper via Phabricator via lldb-commits 
craig.topper added a comment.

__builtin_cpu_init was added to clang between 5.0 and 6.0


https://reviews.llvm.org/D41962



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[Lldb-commits] [PATCH] D128612: RISC-V big-endian support implementation

2022-06-28 Thread Craig Topper via Phabricator via lldb-commits 
craig.topper added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.h:111
 SizeType = UnsignedInt;
-resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128");
   }

Instead of creating new classes, could we have a branch on the Arch or 
isLittleEndian portion of the triple to decide what to pass to resetDataLayout? 
That's what PPC32TargetInfo does for example.



Comment at: lld/ELF/Arch/RISCV.cpp:160
+  if (config->is64) {
+if (config->isLE)
+  write64le(buf, mainPart->dynamic->getVA());

Is it possible to use write64 instead of write64le/be? It looks like it checks 
the endianness internally.



Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp:628
+  // For big endian cores, data fixup should be swapped.
+  bool swapValue = (Endian == support::big) && isDataFixup(Kind);
   for (unsigned i = 0; i != NumBytes; ++i) {

Capitalize `swapValue`



Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h:34
   const MCTargetOptions &Options)
-  : MCAsmBackend(support::little), STI(STI), OSABI(OSABI), 
Is64Bit(Is64Bit),
+  : MCAsmBackend(IsLittleEndian ? support::little : support::big), 
STI(STI), OSABI(OSABI), Is64Bit(Is64Bit),
 TargetOptions(Options) {

Is this longer than 80 columns?



Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp:24
+  if (TT.getArch() == Triple::riscv32be || TT.getArch() == Triple::riscv64be)
+IsLittleEndian = false;
+

Could we do IsLittleEndian = TT.isLittleEndian()?



Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:64
+  return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
+else
+  return "E-m:e-p:64:64-i64:64-i128:128-n64-S128";

No else after return


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[Lldb-commits] [PATCH] D130586: [cmake] Use `CMAKE_INSTALL_LIBDIR` too

2022-12-07 Thread Craig Topper via Phabricator via lldb-commits 
craig.topper added a comment.

I seem to be unable to pass `check-clang` after this. A lot of tests fail 
because they can't find headers they need.


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[Lldb-commits] [PATCH] D144366: [RISCV]Add more pattern for fma ins

2023-02-19 Thread Craig Topper via Phabricator via lldb-commits 
craig.topper added inline comments.
Herald added subscribers: Michael137, JDevlieghere.



Comment at: lldb/include/lldb/Target/Target.h:416
 
-  void SetResultIsInternal(bool b) { m_result_is_internal = b; }
 

Unrelated?


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[Lldb-commits] [PATCH] D144366: [RISCV]Add more pattern for fma ins

2023-02-19 Thread Craig Topper via Phabricator via lldb-commits 
craig.topper added a comment.

These transforms are not valid without the `contract` fast math flag


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[Lldb-commits] [PATCH] D144366: [RISCV]Add more pattern for fma ins

2023-02-20 Thread Craig Topper via Phabricator via lldb-commits 
craig.topper added a comment.

I posted https://reviews.llvm.org/D17 to get these in the frontend.


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[Lldb-commits] [PATCH] D150996: LLVM_FALLTHROUGH => [[fallthrough]]. NFC

2023-05-19 Thread Craig Topper via Phabricator via lldb-commits 
craig.topper created this revision.
craig.topper added a reviewer: MaskRay.
Herald added subscribers: ThomasRaoux, kbarton, hiraditya, nemanjai.
Herald added a project: All.
craig.topper requested review of this revision.
Herald added a reviewer: zuban32.
Herald added subscribers: lldb-commits, cfe-commits, pcwang-thead.
Herald added a reviewer: mpaszkowski.
Herald added projects: clang, LLDB, LLVM.

Repository:
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https://reviews.llvm.org/D150996

Files:
  clang/lib/AST/TemplateBase.cpp
  clang/lib/Basic/SourceManager.cpp
  clang/lib/Sema/SemaChecking.cpp
  lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
  llvm/lib/Analysis/MemoryLocation.cpp
  llvm/lib/Analysis/ScalarEvolution.cpp
  llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp
  llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
  llvm/lib/ProfileData/InstrProf.cpp
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.h
  llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Index: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
===
--- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -8487,7 +8487,7 @@
   Ops[1] = SafeRHS;
   return new VPWidenRecipe(*I, make_range(Ops.begin(), Ops.end()));
 }
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   }
   case Instruction::Add:
   case Instruction::And:
Index: llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
===
--- llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -55,7 +55,7 @@
   switch (Intrinsic) {
   case Intrinsic::spv_load:
 AlignIdx = 2;
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case Intrinsic::spv_store: {
 if (I.getNumOperands() >= AlignIdx + 1) {
   auto *AlignOp = cast(I.getOperand(AlignIdx));
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
===
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -183,7 +183,7 @@
   case 'f':
 if (RegName[1] == 'p')
   return RegName + 2;
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case 'r':
   case 'v':
 if (RegName[1] == 's') {
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10686,7 +10686,7 @@
   RetOps.push_back(Extract);
   return DAG.getMergeValues(RetOps, dl);
 }
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   }
   case Intrinsic::ppc_vsx_disassemble_pair: {
 int NumVecs = 2;
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -3994,7 +3994,7 @@
   if (SRLConst && SRLConst->getSExtValue() == 16)
 return false;
 }
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case ISD::ROTL:
   case ISD::SHL:
   case ISD::AND:
Index: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
===
--- llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -2523,7 +2523,7 @@
   return 2 * LT.first;
 if (!Ty->getScalarType()->isFP128Ty())
   return LT.first;
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case ISD::FMUL:
   case ISD::FDIV:
 // These nodes are marked as 'custom' just to lower them to SVE.
Index: llvm/lib/ProfileData/InstrProf.cpp
===
--- llvm/lib/ProfileData/InstrProf.cpp
+++ llvm/lib/ProfileData/InstrProf.cpp
@@ -1385,7 +1385,7 @@
   case 10ull:
 H.TemporalProfTracesOffset =
 read(Buffer, offsetOf(&Header::TemporalProfTracesOffset));
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case 9ull:
 H.BinaryIdOffset = read(Buffer, offsetOf(&Header::BinaryIdOffset));
 [[fallthrough]];
Index: llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
===
--- llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+++ llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
@@ -2420,7 +2420,7 @@
   case OMPScheduleType::BaseRuntimeSimd:
 assert(!ChunkSize &&
"schedule type does not support user-defined chunk sizes");
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case OMPScheduleType::BaseDynamicChunked:
   case OMPScheduleType::BaseGuidedChunked:
   case OMPScheduleType::BaseGuidedIterativeChunked:
Index: llvm/lib/DebugInfo/LogicalView/

[Lldb-commits] [PATCH] D150996: LLVM_FALLTHROUGH => [[fallthrough]]. NFC

2023-05-24 Thread Craig Topper via Phabricator via lldb-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rG6006d43e2d7d: LLVM_FALLTHROUGH => [[fallthrough]]. NFC 
(authored by craig.topper).

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Files:
  clang/lib/AST/TemplateBase.cpp
  clang/lib/Basic/SourceManager.cpp
  clang/lib/Sema/SemaChecking.cpp
  lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
  llvm/lib/Analysis/MemoryLocation.cpp
  llvm/lib/Analysis/ScalarEvolution.cpp
  llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp
  llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
  llvm/lib/ProfileData/InstrProf.cpp
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.h
  llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Index: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
===
--- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -8487,7 +8487,7 @@
   Ops[1] = SafeRHS;
   return new VPWidenRecipe(*I, make_range(Ops.begin(), Ops.end()));
 }
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   }
   case Instruction::Add:
   case Instruction::And:
Index: llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
===
--- llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -55,7 +55,7 @@
   switch (Intrinsic) {
   case Intrinsic::spv_load:
 AlignIdx = 2;
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case Intrinsic::spv_store: {
 if (I.getNumOperands() >= AlignIdx + 1) {
   auto *AlignOp = cast(I.getOperand(AlignIdx));
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
===
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -183,7 +183,7 @@
   case 'f':
 if (RegName[1] == 'p')
   return RegName + 2;
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case 'r':
   case 'v':
 if (RegName[1] == 's') {
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10686,7 +10686,7 @@
   RetOps.push_back(Extract);
   return DAG.getMergeValues(RetOps, dl);
 }
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   }
   case Intrinsic::ppc_vsx_disassemble_pair: {
 int NumVecs = 2;
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -3994,7 +3994,7 @@
   if (SRLConst && SRLConst->getSExtValue() == 16)
 return false;
 }
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case ISD::ROTL:
   case ISD::SHL:
   case ISD::AND:
Index: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
===
--- llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -2529,7 +2529,7 @@
   return 2 * LT.first;
 if (!Ty->getScalarType()->isFP128Ty())
   return LT.first;
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case ISD::FMUL:
   case ISD::FDIV:
 // These nodes are marked as 'custom' just to lower them to SVE.
Index: llvm/lib/ProfileData/InstrProf.cpp
===
--- llvm/lib/ProfileData/InstrProf.cpp
+++ llvm/lib/ProfileData/InstrProf.cpp
@@ -1385,7 +1385,7 @@
   case 10ull:
 H.TemporalProfTracesOffset =
 read(Buffer, offsetOf(&Header::TemporalProfTracesOffset));
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case 9ull:
 H.BinaryIdOffset = read(Buffer, offsetOf(&Header::BinaryIdOffset));
 [[fallthrough]];
Index: llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
===
--- llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+++ llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
@@ -2420,7 +2420,7 @@
   case OMPScheduleType::BaseRuntimeSimd:
 assert(!ChunkSize &&
"schedule type does not support user-defined chunk sizes");
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case OMPScheduleType::BaseDynamicChunked:
   case OMPScheduleType::BaseGuidedChunked:
   case OMPScheduleType::BaseGuidedIterativeChunked:
Index: llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp
===
--- llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp
++

[Lldb-commits] [PATCH] D109483: [APInt] Normalize naming on keep constructors / predicate methods.

2021-09-09 Thread Craig Topper via Phabricator via lldb-commits 
craig.topper added inline comments.



Comment at: llvm/include/llvm/ADT/APInt.h:384
   /// value for the APInt's bit width.
   bool isMaxValue() const { return isAllOnesValue(); }
 

isAllOnes()?


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[Lldb-commits] [PATCH] D109483: [APInt] Normalize naming on keep constructors / predicate methods.

2021-09-09 Thread Craig Topper via Phabricator via lldb-commits 
craig.topper added a comment.

I think I read this patch too closely. I'll leave it up to you how much of this 
you want to do.




Comment at: llvm/include/llvm/IR/Constants.h:206
   /// Determine if the value is all ones.
   bool isMinusOne() const { return Val.isAllOnesValue(); }
 

isAllOnes()



Comment at: llvm/include/llvm/Transforms/InstCombine/InstCombiner.h:171
   TrueIfSigned = true;
   return RHS.isAllOnesValue();
 case ICmpInst::ICMP_SGT: // True if LHS s> -1

isAllOnes since you're already in the area



Comment at: llvm/include/llvm/Transforms/InstCombine/InstCombiner.h:174
   TrueIfSigned = false;
   return RHS.isAllOnesValue();
 case ICmpInst::ICMP_SGE: // True if LHS s>= 0

isAllOnes



Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:3243
"Don't know how to expand this subtraction!");
-Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
-   DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
-   VT));
+Tmp1 = DAG.getNode(
+ISD::XOR, dl, VT, Node->getOperand(1),

This could use DAG.getNOT if you're willing to make that change.



Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp:965
+  DAG.getConstant(APInt::getAllOnes(BitTy.getSizeInBits()), DL, MaskTy);
   SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
 

I think this could also be DAG.getNOT but I'm less sure.



Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp:1212
+  DAG.getConstant(APInt::getAllOnes(VT.getScalarSizeInBits()), DL, VT);
   SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
 

This could be DAG.getNOT



Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:4021
   // (X & (C l>>/<< Y)) ==/!= 0  -->  ((X <> Y) & C) ==/!= 0
   if (C1.isNullValue())
 if (SDValue CC = optimizeSetCCByHoistingAndByConstFromLogicalShift(

isZero()



Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:4030
   // all bits set:   (X | (Y<<32)) == -1 --> (X & Y) == -1
   bool CmpZero = N1C->getAPIntValue().isNullValue();
+  bool CmpNegOne = N1C->getAPIntValue().isAllOnes();

isNullValue() -> isZero(). I was going to say you could use N1C->isZero() but I 
think it would have to be N1C->isNullValue() because that is the ConstantSDNode 
interface.



Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:12185
 else
-  OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
-VT);
+  OtherOp = DAG.getConstant(APInt::getAllOnes(VT.getSizeInBits()), dl, VT);
 return true;

I think we have DAG.getAllOnesConstant if you want to use it



Comment at: llvm/lib/Target/Lanai/LanaiISelLowering.cpp:1403
 else
-  OtherOp =
-  DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl, VT);
+  OtherOp = DAG.getConstant(APInt::getAllOnes(VT.getSizeInBits()), dl, VT);
 return true;

I think we have DAG.getAllOnesConstant if you want to use it



Comment at: llvm/lib/Target/M68k/M68kISelLowering.cpp:1983
   Carry = DAG.getNode(M68kISD::ADD, DL, DAG.getVTList(CarryVT, MVT::i32), 
Carry,
   DAG.getConstant(NegOne, DL, CarryVT));
 

This is also getAllOnesConstant



Comment at: llvm/unittests/ADT/APIntTest.cpp:29
 TEST(APIntTest, ShiftLeftByZero) {
-  APInt One = APInt::getNullValue(65) + 1;
+  APInt One = APInt::getZero(65) + 1;
   APInt Shl = One.shl(0);

That's a strange way to write APInt(64, 1) unless there was some specific bug.


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[Lldb-commits] [PATCH] D109483: [APInt] Normalize naming on keep constructors / predicate methods.

2021-09-10 Thread Craig Topper via Phabricator via lldb-commits 
craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[Lldb-commits] [PATCH] D78791: [lldb][NFC][CallSite] Remove CallSite use

2020-04-23 Thread Craig Topper via Phabricator via lldb-commits 
craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


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[Lldb-commits] [PATCH] D78882: [IR] Replace all uses of CallBase::getCalledValue() with getCalledOperand().

2020-04-27 Thread Craig Topper via Phabricator via lldb-commits 
craig.topper created this revision.
craig.topper added a reviewer: dblaikie.
Herald added subscribers: lldb-commits, cfe-commits, Kayjukh, frgossen, 
grosul1, dantrushin, Joonsoo, kerbowa, liufengdb, lucyrfox, mgester, 
arpith-jacob, csigg, nicolasvasilache, antiagainst, shauheen, jpienaar, 
rriddle, mehdi_amini, asbirlea, dexonsmith, steven_wu, george.burgess.iv, 
kbarton, aheejin, hiraditya, jgravelle-google, sbc100, nhaehnle, jvesely, 
nemanjai, dschuff, arsenm, jholewinski.
Herald added a reviewer: deadalnix.
Herald added a reviewer: ftynse.
Herald added projects: clang, LLDB, LLVM.

This method has been commented as deprecated for a while. Remove
it and replace all uses with the equivalent getCalledOperand().

I also made a few cleanups in here. For example, to removes use
of getElementType on a pointer when we could just use getFunctionType
from the call.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D78882

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/CodeGen/CGObjC.cpp
  clang/lib/CodeGen/CodeGenFunction.cpp
  lldb/source/Expression/IRInterpreter.cpp
  lldb/source/Plugins/ExpressionParser/Clang/IRDynamicChecks.cpp
  lldb/source/Plugins/ExpressionParser/Clang/IRForTarget.cpp
  llvm/include/llvm-c/Core.h
  llvm/include/llvm/CodeGen/FastISel.h
  llvm/include/llvm/IR/AbstractCallSite.h
  llvm/include/llvm/IR/InstrTypes.h
  llvm/lib/Analysis/AliasAnalysisEvaluator.cpp
  llvm/lib/Analysis/InstructionSimplify.cpp
  llvm/lib/Analysis/Lint.cpp
  llvm/lib/Analysis/MemorySSA.cpp
  llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
  llvm/lib/Analysis/StackSafetyAnalysis.cpp
  llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
  llvm/lib/CodeGen/CodeGenPrepare.cpp
  llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
  llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
  llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
  llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
  llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
  llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/CodeGen/WasmEHPrepare.cpp
  llvm/lib/CodeGen/WinEHPrepare.cpp
  llvm/lib/ExecutionEngine/Interpreter/Execution.cpp
  llvm/lib/IR/AsmWriter.cpp
  llvm/lib/IR/Core.cpp
  llvm/lib/IR/Instructions.cpp
  llvm/lib/IR/Verifier.cpp
  llvm/lib/Target/AArch64/AArch64PromoteConstant.cpp
  llvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp
  llvm/lib/Target/AMDGPU/AMDGPUFixFunctionBitcasts.cpp
  llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/ARM/ARMFastISel.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
  llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86WinEHState.cpp
  llvm/lib/Transforms/Coroutines/CoroSplit.cpp
  llvm/lib/Transforms/IPO/CalledValuePropagation.cpp
  llvm/lib/Transforms/IPO/GlobalOpt.cpp
  llvm/lib/Transforms/IPO/PruneEH.cpp
  llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
  llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
  llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
  llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
  llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
  llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
  llvm/lib/Transforms/Instrumentation/ValueProfilePlugins.inc
  llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
  llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
  llvm/lib/Transforms/Utils/Evaluator.cpp
  llvm/lib/Transforms/Utils/InlineFunction.cpp
  llvm/lib/Transforms/Utils/Local.cpp
  llvm/lib/Transforms/Utils/LowerInvoke.cpp
  llvm/lib/Transforms/Utils/SimplifyCFG.cpp
  llvm/test/LTO/X86/type-mapping-bug3.ll
  llvm/tools/llvm-diff/DiffConsumer.cpp
  llvm/tools/llvm-diff/DifferenceEngine.cpp
  mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp

Index: mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
===
--- mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
+++ mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
@@ -720,7 +720,7 @@
   op = b.create(loc, tys, b.getSymbolRefAttr(callee->getName()),
 ops);
 } else {
-  Value calledValue = processValue(ci->getCalledValue());
+  Value calledValue = processValue(ci->getCalledOperand());
   if (!calledValue)
 return failure();
   ops.insert(ops.begin(), calledValue);
@@ -766,7 +766,7 @@
   ops, blocks[ii->getNormalDest()], normalArgs,
   blocks[ii->getUnwindDest()], unwindArgs);
 } else {
-  ops.i

[Lldb-commits] [PATCH] D78882: [IR] Replace all uses of CallBase::getCalledValue() with getCalledOperand().

2020-04-28 Thread Craig Topper via Phabricator via lldb-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa58b62b4a2b9: [IR] Replace all uses of 
CallBase::getCalledValue() with getCalledOperand(). (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78882/new/

https://reviews.llvm.org/D78882

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/CodeGen/CGObjC.cpp
  clang/lib/CodeGen/CodeGenFunction.cpp
  lldb/source/Expression/IRInterpreter.cpp
  lldb/source/Plugins/ExpressionParser/Clang/IRDynamicChecks.cpp
  lldb/source/Plugins/ExpressionParser/Clang/IRForTarget.cpp
  llvm/include/llvm-c/Core.h
  llvm/include/llvm/CodeGen/FastISel.h
  llvm/include/llvm/IR/AbstractCallSite.h
  llvm/include/llvm/IR/InstrTypes.h
  llvm/lib/Analysis/AliasAnalysisEvaluator.cpp
  llvm/lib/Analysis/InstructionSimplify.cpp
  llvm/lib/Analysis/Lint.cpp
  llvm/lib/Analysis/MemorySSA.cpp
  llvm/lib/Analysis/ModuleSummaryAnalysis.cpp
  llvm/lib/Analysis/StackSafetyAnalysis.cpp
  llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
  llvm/lib/CodeGen/CodeGenPrepare.cpp
  llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
  llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
  llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp
  llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
  llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
  llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/CodeGen/WasmEHPrepare.cpp
  llvm/lib/CodeGen/WinEHPrepare.cpp
  llvm/lib/ExecutionEngine/Interpreter/Execution.cpp
  llvm/lib/IR/AsmWriter.cpp
  llvm/lib/IR/Core.cpp
  llvm/lib/IR/Instructions.cpp
  llvm/lib/IR/Verifier.cpp
  llvm/lib/Target/AArch64/AArch64PromoteConstant.cpp
  llvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp
  llvm/lib/Target/AMDGPU/AMDGPUFixFunctionBitcasts.cpp
  llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/ARM/ARMFastISel.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp
  llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyFixFunctionBitcasts.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86WinEHState.cpp
  llvm/lib/Transforms/Coroutines/CoroSplit.cpp
  llvm/lib/Transforms/IPO/CalledValuePropagation.cpp
  llvm/lib/Transforms/IPO/GlobalOpt.cpp
  llvm/lib/Transforms/IPO/PruneEH.cpp
  llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
  llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
  llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
  llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
  llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
  llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
  llvm/lib/Transforms/Instrumentation/ValueProfilePlugins.inc
  llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
  llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
  llvm/lib/Transforms/Utils/Evaluator.cpp
  llvm/lib/Transforms/Utils/InlineFunction.cpp
  llvm/lib/Transforms/Utils/Local.cpp
  llvm/lib/Transforms/Utils/LowerInvoke.cpp
  llvm/lib/Transforms/Utils/SimplifyCFG.cpp
  llvm/test/LTO/X86/type-mapping-bug3.ll
  llvm/tools/llvm-diff/DiffConsumer.cpp
  llvm/tools/llvm-diff/DifferenceEngine.cpp
  mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp

Index: mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
===
--- mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
+++ mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
@@ -720,7 +720,7 @@
   op = b.create(loc, tys, b.getSymbolRefAttr(callee->getName()),
 ops);
 } else {
-  Value calledValue = processValue(ci->getCalledValue());
+  Value calledValue = processValue(ci->getCalledOperand());
   if (!calledValue)
 return failure();
   ops.insert(ops.begin(), calledValue);
@@ -766,7 +766,7 @@
   ops, blocks[ii->getNormalDest()], normalArgs,
   blocks[ii->getUnwindDest()], unwindArgs);
 } else {
-  ops.insert(ops.begin(), processValue(ii->getCalledValue()));
+  ops.insert(ops.begin(), processValue(ii->getCalledOperand()));
   op = b.create(loc, tys, ops, blocks[ii->getNormalDest()],
   normalArgs, blocks[ii->getUnwindDest()],
   unwindArgs);
Index: llvm/tools/llvm-diff/DifferenceEngine.cpp
===
--- llvm/tools/llvm-diff/DifferenceEngine.cpp
+++ llvm/tools/llvm-diff/DifferenceEngine.cpp
@@ -224,7 +224,7 @@
 
   bool diffCallSites(CallBase &L, CallBase &R, bool Compl