[Lldb-commits] [PATCH] D46889: [DWARF] Extract indexing code into a separate class hierarchy

2018-05-18 Thread Amara Emerson via Phabricator via lldb-commits 
aemerson added a comment.

This caused a failure in green dragon: 
http://green.lab.llvm.org/green/job/lldb-xcode/6644

Can you please fix or revert this change, thanks.


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[Lldb-commits] [PATCH] D46889: [DWARF] Extract indexing code into a separate class hierarchy

2018-05-18 Thread Amara Emerson via Phabricator via lldb-commits 
aemerson reopened this revision.
aemerson added a comment.
This revision is now accepted and ready to land.

Hi Pavel,

I reverted this in r332730 due to the bot breaking. Please have a look and 
commit again when ready.

Thanks,
Amara


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[Lldb-commits] [PATCH] D46889: [DWARF] Extract indexing code into a separate class hierarchy

2018-05-18 Thread Amara Emerson via Phabricator via lldb-commits 
aemerson added a comment.

In https://reviews.llvm.org/D46889#1104823, @aprantl wrote:

> Thanks for jumping on this Amara — I just wanted to point out that we 
> ususally don't revert lldb changes that only break the lldb-xcode bot if they 
> pass on the lldb-cmake bot at the same time. When this happens it usually 
> means that the lldb Xcode project must be updated and it's too much to ask 
> from all open source contributors to get access to a machine running Xcode to 
> do this. Instead one of the Apple LLDB developers usually goes in and updates 
> the Xcode project for them.
>
> - adrian


Ah ok. Does that include cases like this one with the link error:

  Undefined symbols for architecture x86_64:
"lldb_private::AppleDWARFIndex::Create(lldb_private::Module&, 
lldb_private::DWARFDataExtractor, lldb_private::DWARFDataExtractor, 
lldb_private::DWARFDataExtractor, lldb_private::DWARFDataExtractor, 
lldb_private::DWARFDataExtractor)", referenced from:
SymbolFileDWARF::InitializeObject() in liblldb-core.a(SymbolFileDWARF.o)
"vtable for lldb_private::ManualDWARFIndex", referenced from:
SymbolFileDWARF::InitializeObject() in liblldb-core.a(SymbolFileDWARF.o)
NOTE: a missing vtable usually means the first non-inline virtual member 
function has no definition.


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[Lldb-commits] [PATCH] D128465: [llvm] add zstd to `llvm::compression` namespace

2022-12-06 Thread Amara Emerson via Phabricator via lldb-commits 
aemerson added a comment.

I just reverted this in 6e6be5f9504d 
 because 
it seems to have broken macOS builds:

  llvm/lib/Support/Compression.cpp:24:10: fatal error: 'zstd.h' file not found
  #include 
   ^~~~


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[Lldb-commits] [PATCH] D75555: [GlobalISel][Localizer] Enable intra-block localization of already-local uses.

2020-03-05 Thread Amara Emerson via Phabricator via lldb-commits 
aemerson updated this revision to Diff 248567.
aemerson added a comment.
Herald added a project: LLDB.
Herald added a subscriber: lldb-commits.

@omjavaid can you look over the lldb changes? I don't have the hardware to be 
able to actually run this test but I've tried to relax the checks.


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Files:
  lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
  llvm/lib/CodeGen/GlobalISel/Localizer.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
  llvm/test/CodeGen/AArch64/GlobalISel/localizer.mir
  llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
  llvm/test/CodeGen/AArch64/GlobalISel/translate-constant-dag.ll
  llvm/test/CodeGen/AArch64/tail-call.ll
  llvm/test/CodeGen/AArch64/tiny_model.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll

Index: llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
===
--- llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
@@ -1466,9 +1466,9 @@
   ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
   ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
   ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
-  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
   ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)
   ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY6]]
+  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
   ; CHECK:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
   ; CHECK:   [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]]
   ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
@@ -1493,9 +1493,9 @@
   ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
   ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
   ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
-  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
   ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)
   ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY6]], [[COPY4]]
+  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
   ; CHECK:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
   ; CHECK:   [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]]
   ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
===
--- llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
@@ -203,8 +203,8 @@
 ; GFX6-LABEL: mubuf_store_vgpr_ptr_offset4294967297:
 ; GFX6:   ; %bb.0:
 ; GFX6-NEXT:s_mov_b32 s0, 4
-; GFX6-NEXT:s_mov_b32 s2, 0
 ; GFX6-NEXT:s_mov_b32 s1, s0
+; GFX6-NEXT:s_mov_b32 s2, 0
 ; GFX6-NEXT:v_mov_b32_e32 v2, 0
 ; GFX6-NEXT:s_mov_b32 s3, 0xf000
 ; GFX6-NEXT:buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
@@ -213,8 +213,8 @@
 ; GFX7-LABEL: mubuf_store_vgpr_ptr_offset4294967297:
 ; GFX7:   ; %bb.0:
 ; GFX7-NEXT:s_mov_b32 s0, 4
-; GFX7-NEXT:s_mov_b32 s2, 0
 ; GFX7-NEXT:s_mov_b32 s1, s0
+; GFX7-NEXT:s_mov_b32 s2, 0
 ; GFX7-NEXT:v_mov_b32_e32 v2, 0
 ; GFX7-NEXT:s_mov_b32 s3, 0xf000
 ; GFX7-NEXT:buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
@@ -252,11 +252,11 @@
 define amdgpu_ps void @mubuf_store_sgpr_ptr_sgpr_offset(i32 addrspace(1)* inreg %ptr, i32 inreg %soffset) {
 ; GFX6-LABEL: mubuf_store_sgpr_ptr_sgpr_offset:
 ; GFX6:   ; %bb.0:
-; GFX6-NEXT:s_bfe_i64 s[4:5], s[4:5], 0x20
-; GFX6-NEXT:s_lshl_b64 s[4:5], s[4:5], 2
-; GFX6-NEXT:v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:s_mov_b32 s0, s2
 ; GFX6-NEXT:s_mov_b32 s1, s3
+; GFX6-NEXT:s_bfe_i64 s[2:3], s[4:5], 0x20
+; GFX6-NEXT:s_lshl_b64 s[4:5], s[2:3], 2
+; GFX6-NEXT:v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:s_mov_b32 s2, 0
 ; GFX6-NEXT:v_mov_b32_e32 v2, 0
 ; GFX6-NEXT:s_mov_b32 s3, 0xf000
@@ -266,11 +266,11 @@
 ;
 ; GFX7-LABEL: mubuf_store_sgpr_ptr_sgpr_offset:
 ; GFX7:   ; %bb.0:
-; GFX7-NEXT:s_bfe_i64 s[4:5], s[4:5], 0x20
-; GFX7-NEXT:s_lshl_b64 s[4:5], s[4:5], 2
-; GFX7-NEXT:v_mov_b32_e32 v0, s4
 ; GFX7-NEXT:s_mov_b32 s0, s2
 ; GFX7-NEXT:s_mov_b32 s1, s3
+; GFX7-NEXT:s_bfe_i64 s[2:3], s[4:5], 0x20
+; GFX7-NEXT:s_lshl_b64 s[4:5], s[2:3], 2
+; GFX7-NEXT:v_mov_b32_e32 v0, s4
 ; GFX7-NEXT:s_mov_b3

[Lldb-commits] [PATCH] D75555: [GlobalISel][Localizer] Enable intra-block localization of already-local uses.

2020-03-06 Thread Amara Emerson via Phabricator via lldb-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rGc1a97e992da6: Revert "Revert 
"[GlobalISel][Localizer] Enable intra-block localization of… (authored by 
aemerson).

Changed prior to commit:
  https://reviews.llvm.org/D7?vs=248567&id=248898#toc

Repository:
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Files:
  llvm/lib/CodeGen/GlobalISel/Localizer.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
  llvm/test/CodeGen/AArch64/GlobalISel/localizer.mir
  llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
  llvm/test/CodeGen/AArch64/GlobalISel/translate-constant-dag.ll
  llvm/test/CodeGen/AArch64/tail-call.ll
  llvm/test/CodeGen/AArch64/tiny_model.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll

Index: llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
===
--- llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
@@ -1466,9 +1466,9 @@
   ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
   ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
   ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
-  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
   ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)
   ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY4]], [[COPY6]]
+  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
   ; CHECK:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
   ; CHECK:   [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]]
   ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
@@ -1493,9 +1493,9 @@
   ; CHECK:   [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
   ; CHECK:   [[COPY5:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
   ; CHECK:   [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
-  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
   ; CHECK:   [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY5]](s32)
   ; CHECK:   [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY6]], [[COPY4]]
+  ; CHECK:   [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1024
   ; CHECK:   [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
   ; CHECK:   [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[COPY7]]
   ; CHECK:   [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
===
--- llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
@@ -203,8 +203,8 @@
 ; GFX6-LABEL: mubuf_store_vgpr_ptr_offset4294967297:
 ; GFX6:   ; %bb.0:
 ; GFX6-NEXT:s_mov_b32 s0, 4
-; GFX6-NEXT:s_mov_b32 s2, 0
 ; GFX6-NEXT:s_mov_b32 s1, s0
+; GFX6-NEXT:s_mov_b32 s2, 0
 ; GFX6-NEXT:v_mov_b32_e32 v2, 0
 ; GFX6-NEXT:s_mov_b32 s3, 0xf000
 ; GFX6-NEXT:buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
@@ -213,8 +213,8 @@
 ; GFX7-LABEL: mubuf_store_vgpr_ptr_offset4294967297:
 ; GFX7:   ; %bb.0:
 ; GFX7-NEXT:s_mov_b32 s0, 4
-; GFX7-NEXT:s_mov_b32 s2, 0
 ; GFX7-NEXT:s_mov_b32 s1, s0
+; GFX7-NEXT:s_mov_b32 s2, 0
 ; GFX7-NEXT:v_mov_b32_e32 v2, 0
 ; GFX7-NEXT:s_mov_b32 s3, 0xf000
 ; GFX7-NEXT:buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
@@ -252,11 +252,11 @@
 define amdgpu_ps void @mubuf_store_sgpr_ptr_sgpr_offset(i32 addrspace(1)* inreg %ptr, i32 inreg %soffset) {
 ; GFX6-LABEL: mubuf_store_sgpr_ptr_sgpr_offset:
 ; GFX6:   ; %bb.0:
-; GFX6-NEXT:s_bfe_i64 s[4:5], s[4:5], 0x20
-; GFX6-NEXT:s_lshl_b64 s[4:5], s[4:5], 2
-; GFX6-NEXT:v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:s_mov_b32 s0, s2
 ; GFX6-NEXT:s_mov_b32 s1, s3
+; GFX6-NEXT:s_bfe_i64 s[2:3], s[4:5], 0x20
+; GFX6-NEXT:s_lshl_b64 s[4:5], s[2:3], 2
+; GFX6-NEXT:v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:s_mov_b32 s2, 0
 ; GFX6-NEXT:v_mov_b32_e32 v2, 0
 ; GFX6-NEXT:s_mov_b32 s3, 0xf000
@@ -266,11 +266,11 @@
 ;
 ; GFX7-LABEL: mubuf_store_sgpr_ptr_sgpr_offset:
 ; GFX7:   ; %bb.0:
-; GFX7-NEXT:s_bfe_i64 s[4:5], s[4:5], 0x20
-; GFX7-NEXT:s_lshl_b64 s[4:5], s[4:5], 2
-; GFX7-NEXT:v_mov_b32_e32 v0, s4
 ; GFX7-NEXT:s_mov_b32 s0, s2
 ; GFX7-NEXT:s_mov_b32 s1, s3
+; GFX7-NEXT:s_bfe_i64 s[2:3], s[4:5], 0x20
+; GFX7-NEXT:s_lshl_b64 s[4:5], s[2:3], 2
+; GFX7-NEXT:v_mov_b32_e32 v0, s4
 ; GFX7-NEXT:s_mov_b32 s2, 0
 ; GFX7-NEXT:v_mov_b32_e32 v2, 0
 ; GFX7-NEXT:s_mov_b32 s3, 0