date:20221230

[Lldb-commits] [PATCH] D140759: [LLDB][LoongArch] Add FP branch instructions for EmulateInstructionLoongArch

2022-12-30 Thread Hui Li via Phabricator via lldb-commits

lh03061238 added inline comments.



Comment at: 
lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp:42
"bnez rj, offs21"},
+  {0xfc00, 0x4800, &EmulateInstructionLoongArch::EmulateBCXXZ,
+   "bceqz/bcnez cj, offs21"},

SixWeining wrote:
> It should be 0xfc000300. BCEQZ and BCNEZ should be seperated.
> See 
> https://github.com/loongson/LoongArch-Documentation/blob/main/docs/LoongArch-Vol1-EN/table-of-instruction-encoding.adoc
My understanding of this opcode is not accurate,  This will be modified.
Thanks for pointing out.



Comment at: 
lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp:303
 
+// bceqz   cj, offs21
+// if CFR[cj] == 0:

SixWeining wrote:
> A single space is enough.
will be modified， thanks



Comment at: 
lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp:312
+  uint32_t bcxxz = (inst >> 8) & 0b11;
+  uint32_t cj = Bits32(inst, 7, 5) + fpr_first_loongarch + 32;
+  uint64_t pc = ReadPC(&success);

SixWeining wrote:
> Is this number of FPRs? Would it be changed in future when we support vertor 
> registers? Adding some comment may help future readers.
It's a little complicated here,  I will use “Bits32(inst, 7, 5) + 
fpr_fcc0_loongarch”  to make it clearer.
will be modified， thanks



Comment at: lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp:157
+static uint32_t BCEQZ(uint8_t cj, int32_t offs21) {
+  return EncodeBCZcondType(0b010010, cj, 0b00, uint32_t(offs21));
+}

SixWeining wrote:
> The opcode is 8 bits `0b01001000`. See: 
> https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td#L109
> 
> I think you can remove the third argument `bcxxz`.
This will be modified.
Thanks for pointing out.



Comment at: lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp:256
+  tester->fpr.fcc = cj_val;
+  // bcz  fcc0, (256)
+  uint32_t inst = encoder(0, 256);

SixWeining wrote:
> Ditto.
will be modified， thanks


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  rG LLVM Github Monorepo

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[Lldb-commits] [PATCH] D140759: [LLDB][LoongArch] Add FP branch instructions for EmulateInstructionLoongArch

2022-12-30 Thread Hui Li via Phabricator via lldb-commits

lh03061238 updated this revision to Diff 485680.
lh03061238 added a comment.

1、Modify BCEQZ/BCNEZ instruction opcode and mask
2、Separate BCEQZ and BCNEZ
3、Use "Bits32(inst, 7, 5) + fpr_fcc0_loongarch" to calculate cj


CHANGES SINCE LAST ACTION
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Files:
  lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp
  lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.h
  lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp

Index: lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp
===
--- lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp
+++ lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp
@@ -38,6 +38,14 @@
 testBZcondBranch(this, name, false, rj_val_continued); \
   }
 
+#define GEN_BCZCOND_TEST(bit, name, cj_val_branched, cj_val_continued) \
+  TEST_F(LoongArch##bit##EmulatorTester, test##name##branched) {   \
+testBCZcondBranch(this, name, true, cj_val_branched);  \
+  }\
+  TEST_F(LoongArch##bit##EmulatorTester, test##name##continued) {  \
+testBCZcondBranch(this, name, false, cj_val_continued);\
+  }
+
 struct LoongArch64EmulatorTester : public EmulateInstructionLoongArch,
testing::Test {
   RegisterInfoPOSIX_loongarch64::GPR gpr;
@@ -136,8 +144,27 @@
   return EncodeBZcondType(0b010001, rj, uint32_t(offs21));
 }
 
+// BCEQZ BCNEZ
+static uint32_t EncodeBCZcondType(uint32_t opcode, uint8_t cj,
+  uint32_t offs21) {
+  uint32_t offs20_16 = (offs21 & 0x001f) >> 16;
+  uint32_t offs15_0 = offs21 & 0x;
+  uint32_t bcxxz = opcode & 0b11;
+  opcode = opcode >> 2;
+  return opcode << 26 | offs15_0 << 10 | bcxxz << 8 | cj << 5 | offs20_16;
+}
+
+static uint32_t BCEQZ(uint8_t cj, int32_t offs21) {
+  return EncodeBCZcondType(0b01001000, cj, uint32_t(offs21));
+}
+
+static uint32_t BCNEZ(uint8_t cj, int32_t offs21) {
+  return EncodeBCZcondType(0b01001001, cj, uint32_t(offs21));
+}
+
 using EncoderBcond = uint32_t (*)(uint32_t rj, uint32_t rd, int32_t offs16);
 using EncoderBZcond = uint32_t (*)(uint32_t rj, int32_t offs21);
+using EncoderBCZcond = uint32_t (*)(uint8_t cj, int32_t offs21);
 
 TEST_F(LoongArch64EmulatorTester, testJIRL) {
   bool success = false;
@@ -220,6 +247,21 @@
   ASSERT_EQ(pc, old_pc + (branched ? (-256 * 4) : 4));
 }
 
+static void testBCZcondBranch(LoongArch64EmulatorTester *tester,
+  EncoderBCZcond encoder, bool branched,
+  uint32_t cj_val) {
+  bool success = false;
+  addr_t old_pc = 0x12000600;
+  tester->WritePC(old_pc);
+  tester->fpr.fcc = cj_val;
+  // bcz fcc0, 256
+  uint32_t inst = encoder(0, 256);
+  ASSERT_TRUE(tester->TestExecute(inst));
+  auto pc = tester->ReadPC(&success);
+  ASSERT_TRUE(success);
+  ASSERT_EQ(pc, old_pc + (branched ? (256 * 4) : 4));
+}
+
 GEN_BCOND_TEST(64, BEQ, 1, 1, 0)
 GEN_BCOND_TEST(64, BNE, 1, 0, 1)
 GEN_BCOND_TEST(64, BLT, -2, 1, -3)
@@ -228,3 +270,5 @@
 GEN_BCOND_TEST(64, BGEU, -2, 1, -1)
 GEN_BZCOND_TEST(64, BEQZ, 0, 1)
 GEN_BZCOND_TEST(64, BNEZ, 1, 0)
+GEN_BCZCOND_TEST(64, BCEQZ, 0, 1)
+GEN_BCZCOND_TEST(64, BCNEZ, 1, 0)
Index: lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.h
===
--- lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.h
+++ lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.h
@@ -74,6 +74,8 @@
 
   bool EmulateBEQZ(uint32_t inst);
   bool EmulateBNEZ(uint32_t inst);
+  bool EmulateBCEQZ(uint32_t inst);
+  bool EmulateBCNEZ(uint32_t inst);
   bool EmulateJIRL(uint32_t inst);
   bool EmulateB(uint32_t inst);
   bool EmulateBL(uint32_t inst);
@@ -87,6 +89,8 @@
 
   bool EmulateBEQZ64(uint32_t inst);
   bool EmulateBNEZ64(uint32_t inst);
+  bool EmulateBCEQZ64(uint32_t inst);
+  bool EmulateBCNEZ64(uint32_t inst);
   bool EmulateJIRL64(uint32_t inst);
   bool EmulateB64(uint32_t inst);
   bool EmulateBL64(uint32_t inst);
Index: lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp
===
--- lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp
+++ lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp
@@ -39,6 +39,10 @@
"beqz rj, offs21"},
   {0xfc00, 0x4400, &EmulateInstructionLoongArch::EmulateBNEZ,
"bnez rj, offs21"},
+  {0xfc000300, 0x4800, &EmulateInstructionLoongArch::EmulateBCEQZ,
+   "bceqz cj, offs21"},
+  {0xfc000300, 0x48000100, &EmulateInstructionLoongArch::EmulateBCNEZ,
+   "bcnez cj, offs21"},
   {

[Lldb-commits] [PATCH] D140759: [LLDB][LoongArch] Add FP branch instructions for EmulateInstructionLoongArch

2022-12-30 Thread Lu Weining via Phabricator via lldb-commits

SixWeining accepted this revision.
SixWeining added a comment.
This revision is now accepted and ready to land.

LGTM from the LoongArch side. Thanks.




Comment at: lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp:154
+  opcode = opcode >> 2;
+  return opcode << 26 | offs15_0 << 10 | bcxxz << 8 | cj << 5 | offs20_16;
+}

Seems you can use `opcode & 0b11` directly.


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[Lldb-commits] [PATCH] D137838: [Support] Move TargetParsers to new component

2022-12-30 Thread Sam Elliott via Phabricator via lldb-commits

lenary added a comment.

In D137838#4018930 , @vitalybuka 
wrote:

> This bot is broken after the patch 
> https://lab.llvm.org/buildbot/#/builders/236/builds/1480

Thanks for letting me know. I'm back in the office on the 3rd, and it looks 
like this will be top of my list to look at, not that I'm very familiar with 
the pass and what it's up to.

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[Lldb-commits] [PATCH] D140759: [LLDB][LoongArch] Add FP branch instructions for EmulateInstructionLoongArch

[Lldb-commits] [PATCH] D140759: [LLDB][LoongArch] Add FP branch instructions for EmulateInstructionLoongArch

[Lldb-commits] [PATCH] D140759: [LLDB][LoongArch] Add FP branch instructions for EmulateInstructionLoongArch

[Lldb-commits] [PATCH] D137838: [Support] Move TargetParsers to new component

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