[Lldb-commits] [PATCH] D140386: [LLDB][LoongArch] Add unittests for EmulateInstructionLoongArch

2022-12-29 Thread Hui Li via Phabricator via lldb-commits 
lh03061238 updated this revision to Diff 485586.
lh03061238 added a comment.

Modify the first two lines in TestLoongArchEmulator.cpp


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140386/new/

https://reviews.llvm.org/D140386

Files:
  lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp
  lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.h
  lldb/unittests/Instruction/CMakeLists.txt
  lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp

Index: lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp
===
--- /dev/null
+++ lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp
@@ -0,0 +1,230 @@
+//===-- TestLoongArchEmulator.cpp -===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+#include "lldb/Core/Address.h"
+#include "lldb/Core/Disassembler.h"
+#include "lldb/Core/PluginManager.h"
+#include "lldb/Target/ExecutionContext.h"
+#include "lldb/Utility/ArchSpec.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "gtest/gtest.h"
+
+#include "Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.h"
+#include "Plugins/Process/Utility/lldb-loongarch-register-enums.h"
+
+using namespace llvm;
+using namespace lldb;
+using namespace lldb_private;
+
+#define GEN_BCOND_TEST(bit, name, rj_val, rd_val_branched, rd_val_continued)   \
+  TEST_F(LoongArch##bit##EmulatorTester, test##name##branched) {   \
+testBcondBranch(this, name, true, rj_val, rd_val_branched);\
+  }\
+  TEST_F(LoongArch##bit##EmulatorTester, test##name##continued) {  \
+testBcondBranch(this, name, false, rj_val, rd_val_continued);  \
+  }
+
+#define GEN_BZCOND_TEST(bit, name, rj_val_branched, rj_val_continued)  \
+  TEST_F(LoongArch##bit##EmulatorTester, test##name##branched) {   \
+testBZcondBranch(this, name, true, rj_val_branched);   \
+  }\
+  TEST_F(LoongArch##bit##EmulatorTester, test##name##continued) {  \
+testBZcondBranch(this, name, false, rj_val_continued); \
+  }
+
+struct LoongArch64EmulatorTester : public EmulateInstructionLoongArch,
+   testing::Test {
+  RegisterInfoPOSIX_loongarch64::GPR gpr;
+  RegisterInfoPOSIX_loongarch64::FPR fpr;
+
+  LoongArch64EmulatorTester(
+  std::string triple = "loongarch64-unknown-linux-gnu")
+  : EmulateInstructionLoongArch(ArchSpec(triple)) {
+EmulateInstruction::SetReadRegCallback(ReadRegisterCallback);
+EmulateInstruction::SetWriteRegCallback(WriteRegisterCallback);
+  }
+
+  static bool ReadRegisterCallback(EmulateInstruction *instruction, void *baton,
+   const RegisterInfo *reg_info,
+   RegisterValue ®_value) {
+LoongArch64EmulatorTester *tester =
+(LoongArch64EmulatorTester *)instruction;
+uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
+if (reg >= gpr_r0_loongarch && reg <= gpr_r31_loongarch)
+  reg_value.SetUInt(tester->gpr.gpr[reg], reg_info->byte_size);
+else if (reg == gpr_orig_a0_loongarch)
+  reg_value.SetUInt(tester->gpr.orig_a0, reg_info->byte_size);
+else if (reg == gpr_pc_loongarch)
+  reg_value.SetUInt(tester->gpr.csr_era, reg_info->byte_size);
+else if (reg == gpr_badv_loongarch)
+  reg_value.SetUInt(tester->gpr.csr_badv, reg_info->byte_size);
+else if (reg == fpr_first_loongarch + 32)
+  // fcc0
+  reg_value.SetUInt(tester->fpr.fcc, reg_info->byte_size);
+return true;
+  }
+
+  static bool WriteRegisterCallback(EmulateInstruction *instruction,
+void *baton, const Context &context,
+const RegisterInfo *reg_info,
+const RegisterValue ®_value) {
+LoongArch64EmulatorTester *tester =
+(LoongArch64EmulatorTester *)instruction;
+uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
+if (reg >= gpr_r0_loongarch && reg <= gpr_r31_loongarch)
+  tester->gpr.gpr[reg] = reg_value.GetAsUInt64();
+else if (reg == gpr_orig_a0_loongarch)
+  tester->gpr.orig_a0 = reg_value.GetAsUInt64();
+else if (reg == gpr_pc_loongarch)
+  tester->gpr.csr_era = reg_value.GetAsUInt64();
+else if (reg == gpr_badv_loongarch)
+  tester->gpr.csr_badv = reg_value.GetAsUInt64();
+return true;
+  }
+};
+
+// BEQ

[Lldb-commits] [PATCH] D140386: [LLDB][LoongArch] Add unittests for EmulateInstructionLoongArch

2022-12-29 Thread Hui Li via Phabricator via lldb-commits 
lh03061238 added inline comments.



Comment at: lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp:1-2
+//===-- TestLoongArchEmulator.cpp
+//-===//
+//

SixWeining wrote:
> Merge these lines into one.
It has been modified, thanks.


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[Lldb-commits] [PATCH] D140615: [LLDB][LoongArch] Delete the s9 register alias definition

2022-12-29 Thread Lu Weining via Phabricator via lldb-commits 
SixWeining accepted this revision.
SixWeining added a comment.
This revision is now accepted and ready to land.

LGTM.


Repository:
  rG LLVM Github Monorepo

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[Lldb-commits] [PATCH] D140759: [LLDB][LoongArch] Add FP branch instructions for EmulateInstructionLoongArch

2022-12-29 Thread Hui Li via Phabricator via lldb-commits 
lh03061238 created this revision.
lh03061238 added reviewers: SixWeining, wangleiat, xen0n, xry111, MaskRay, 
seehearfeel, DavidSpickett.
Herald added a subscriber: StephenFan.
Herald added a project: All.
lh03061238 requested review of this revision.
Herald added a project: LLDB.
Herald added a subscriber: lldb-commits.

Add floating-point branch Instructions for EmulateInstructionLoongArch and 
add relevant unit tests.

Without this patch:

  $ ninja check-lldb-unit
  [0/1] Running lldb unit test suite
  
  Testing Time: 10.45s
Passed: 1044

With this patch:

  $ ninja check-lldb-unit
  [0/1] Running lldb unit test suite
  
  Testing Time: 10.20s
Passed: 1048

Depends on D140615  and D140386 



Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140759

Files:
  lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp
  lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.h
  lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp

Index: lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp
===
--- lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp
+++ lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp
@@ -38,6 +38,14 @@
 testBZcondBranch(this, name, false, rj_val_continued); \
   }
 
+#define GEN_BCZCOND_TEST(bit, name, cj_val_branched, cj_val_continued) \
+  TEST_F(LoongArch##bit##EmulatorTester, test##name##branched) {   \
+testBCZcondBranch(this, name, true, cj_val_branched);  \
+  }\
+  TEST_F(LoongArch##bit##EmulatorTester, test##name##continued) {  \
+testBCZcondBranch(this, name, false, cj_val_continued);\
+  }
+
 struct LoongArch64EmulatorTester : public EmulateInstructionLoongArch,
testing::Test {
   RegisterInfoPOSIX_loongarch64::GPR gpr;
@@ -136,8 +144,26 @@
   return EncodeBZcondType(0b010001, rj, uint32_t(offs21));
 }
 
+// BCEQZ BCNEZ
+static uint32_t EncodeBCZcondType(uint32_t opcode, uint8_t cj, uint8_t bcxxz,
+  uint32_t offs21) {
+  uint32_t offs20_16 = (offs21 & 0x001f) >> 16;
+  uint32_t offs15_0 = offs21 & 0x;
+  bcxxz = bcxxz & 0b0011;
+  return opcode << 26 | offs15_0 << 10 | bcxxz << 8 | cj << 5 | offs20_16;
+}
+
+static uint32_t BCEQZ(uint8_t cj, int32_t offs21) {
+  return EncodeBCZcondType(0b010010, cj, 0b00, uint32_t(offs21));
+}
+
+static uint32_t BCNEZ(uint8_t cj, int32_t offs21) {
+  return EncodeBCZcondType(0b010010, cj, 0b01, uint32_t(offs21));
+}
+
 using EncoderBcond = uint32_t (*)(uint32_t rj, uint32_t rd, int32_t offs16);
 using EncoderBZcond = uint32_t (*)(uint32_t rj, int32_t offs21);
+using EncoderBCZcond = uint32_t (*)(uint8_t cj, int32_t offs21);
 
 TEST_F(LoongArch64EmulatorTester, testJIRL) {
   bool success = false;
@@ -220,6 +246,21 @@
   ASSERT_EQ(pc, old_pc + (branched ? (-256 * 4) : 4));
 }
 
+static void testBCZcondBranch(LoongArch64EmulatorTester *tester,
+  EncoderBCZcond encoder, bool branched,
+  uint32_t cj_val) {
+  bool success = false;
+  addr_t old_pc = 0x12000600;
+  tester->WritePC(old_pc);
+  tester->fpr.fcc = cj_val;
+  // bcz  fcc0, (256)
+  uint32_t inst = encoder(0, 256);
+  ASSERT_TRUE(tester->TestExecute(inst));
+  auto pc = tester->ReadPC(&success);
+  ASSERT_TRUE(success);
+  ASSERT_EQ(pc, old_pc + (branched ? (256 * 4) : 4));
+}
+
 GEN_BCOND_TEST(64, BEQ, 1, 1, 0)
 GEN_BCOND_TEST(64, BNE, 1, 0, 1)
 GEN_BCOND_TEST(64, BLT, -2, 1, -3)
@@ -228,3 +269,5 @@
 GEN_BCOND_TEST(64, BGEU, -2, 1, -1)
 GEN_BZCOND_TEST(64, BEQZ, 0, 1)
 GEN_BZCOND_TEST(64, BNEZ, 1, 0)
+GEN_BCZCOND_TEST(64, BCEQZ, 0, 1)
+GEN_BCZCOND_TEST(64, BCNEZ, 1, 0)
Index: lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.h
===
--- lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.h
+++ lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.h
@@ -74,6 +74,7 @@
 
   bool EmulateBEQZ(uint32_t inst);
   bool EmulateBNEZ(uint32_t inst);
+  bool EmulateBCXXZ(uint32_t inst);
   bool EmulateJIRL(uint32_t inst);
   bool EmulateB(uint32_t inst);
   bool EmulateBL(uint32_t inst);
@@ -87,6 +88,7 @@
 
   bool EmulateBEQZ64(uint32_t inst);
   bool EmulateBNEZ64(uint32_t inst);
+  bool EmulateBCXXZ64(uint32_t inst);
   bool EmulateJIRL64(uint32_t inst);
   bool EmulateB64(uint32_t inst);
   bool EmulateBL64(uint32_t inst);
Index: lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp
===
--- lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoon

[Lldb-commits] [PATCH] D140759: [LLDB][LoongArch] Add FP branch instructions for EmulateInstructionLoongArch

2022-12-29 Thread Lu Weining via Phabricator via lldb-commits 
SixWeining added inline comments.



Comment at: 
lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp:42
"bnez rj, offs21"},
+  {0xfc00, 0x4800, &EmulateInstructionLoongArch::EmulateBCXXZ,
+   "bceqz/bcnez cj, offs21"},

It should be 0xfc000300. BCEQZ and BCNEZ should be seperated.
See 
https://github.com/loongson/LoongArch-Documentation/blob/main/docs/LoongArch-Vol1-EN/table-of-instruction-encoding.adoc



Comment at: 
lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp:303
 
+// bceqz   cj, offs21
+// if CFR[cj] == 0:

A single space is enough.



Comment at: 
lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp:312
+  uint32_t bcxxz = (inst >> 8) & 0b11;
+  uint32_t cj = Bits32(inst, 7, 5) + fpr_first_loongarch + 32;
+  uint64_t pc = ReadPC(&success);

Is this number of FPRs? Would it be changed in future when we support vertor 
registers? Adding some comment may help future readers.



Comment at: lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp:157
+static uint32_t BCEQZ(uint8_t cj, int32_t offs21) {
+  return EncodeBCZcondType(0b010010, cj, 0b00, uint32_t(offs21));
+}

The opcode is 8 bits `0b01001000`. See: 
https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td#L109

I think you can remove the third argument `bcxxz`.



Comment at: lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp:256
+  tester->fpr.fcc = cj_val;
+  // bcz  fcc0, (256)
+  uint32_t inst = encoder(0, 256);

Ditto.


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