[Lldb-commits] [PATCH] D137509: [NFC][intelpt] Improve IntelPT trace bundle documentation
jj10306 created this revision. jj10306 added reviewers: wallace, persona0220. Herald added a project: All. jj10306 requested review of this revision. Herald added a project: LLDB. Herald added a subscriber: lldb-commits. Mention that the LLVM/clang triple must be provided if the trace will be consumed via `SBTraceCursor` Test Plan: Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D137509 Files: lldb/source/Plugins/Trace/intel-pt/TraceIntelPTBundleLoader.cpp Index: lldb/source/Plugins/Trace/intel-pt/TraceIntelPTBundleLoader.cpp === --- lldb/source/Plugins/Trace/intel-pt/TraceIntelPTBundleLoader.cpp +++ lldb/source/Plugins/Trace/intel-pt/TraceIntelPTBundleLoader.cpp @@ -241,6 +241,7 @@ "pid": integer, "triple"?: string, // Optional clang/llvm target triple. + // This must be provided if the trace will be consumed using `SBTraceCursor`. "threads": [ // A list of known threads for the given process. When context switch // data is provided, LLDB will automatically create threads for the Index: lldb/source/Plugins/Trace/intel-pt/TraceIntelPTBundleLoader.cpp === --- lldb/source/Plugins/Trace/intel-pt/TraceIntelPTBundleLoader.cpp +++ lldb/source/Plugins/Trace/intel-pt/TraceIntelPTBundleLoader.cpp @@ -241,6 +241,7 @@ "pid": integer, "triple"?: string, // Optional clang/llvm target triple. + // This must be provided if the trace will be consumed using `SBTraceCursor`. "threads": [ // A list of known threads for the given process. When context switch // data is provided, LLDB will automatically create threads for the ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [PATCH] D137509: [NFC][intelpt] Improve IntelPT trace bundle documentation
wallace added inline comments. Comment at: lldb/source/Plugins/Trace/intel-pt/TraceIntelPTBundleLoader.cpp:244 // Optional clang/llvm target triple. + // This must be provided if the trace will be consumed using `SBTraceCursor`. "threads": [ something along these lines is more accurate Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137509/new/ https://reviews.llvm.org/D137509 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [PATCH] D137509: [NFC][intelpt] Improve IntelPT trace bundle documentation
jj10306 updated this revision to Diff 473515. jj10306 added a comment. Improve docs Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137509/new/ https://reviews.llvm.org/D137509 Files: lldb/source/Plugins/Trace/intel-pt/TraceIntelPTBundleLoader.cpp Index: lldb/source/Plugins/Trace/intel-pt/TraceIntelPTBundleLoader.cpp === --- lldb/source/Plugins/Trace/intel-pt/TraceIntelPTBundleLoader.cpp +++ lldb/source/Plugins/Trace/intel-pt/TraceIntelPTBundleLoader.cpp @@ -241,6 +241,7 @@ "pid": integer, "triple"?: string, // Optional clang/llvm target triple. + // This must be provided if the trace will be created not using the CLI or on a machine other than where the target was traced. "threads": [ // A list of known threads for the given process. When context switch // data is provided, LLDB will automatically create threads for the Index: lldb/source/Plugins/Trace/intel-pt/TraceIntelPTBundleLoader.cpp === --- lldb/source/Plugins/Trace/intel-pt/TraceIntelPTBundleLoader.cpp +++ lldb/source/Plugins/Trace/intel-pt/TraceIntelPTBundleLoader.cpp @@ -241,6 +241,7 @@ "pid": integer, "triple"?: string, // Optional clang/llvm target triple. + // This must be provided if the trace will be created not using the CLI or on a machine other than where the target was traced. "threads": [ // A list of known threads for the given process. When context switch // data is provided, LLDB will automatically create threads for the ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [PATCH] D137509: [NFC][intelpt] Improve IntelPT trace bundle documentation
jj10306 marked an inline comment as done. jj10306 added a comment. resolve comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137509/new/ https://reviews.llvm.org/D137509 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [PATCH] D137509: [NFC][intelpt] Improve IntelPT trace bundle documentation
wallace added inline comments. Comment at: lldb/source/Plugins/Trace/intel-pt/TraceIntelPTBundleLoader.cpp:244 // Optional clang/llvm target triple. + // This must be provided if the trace will be created not using the CLI or on a machine other than where the target was traced. "threads": [ split this into 80-char lines, please :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137509/new/ https://reviews.llvm.org/D137509 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [PATCH] D137519: [LLDB][LoongArch] Add LoongArch software breakpoint trap code
seehearfeel created this revision.
seehearfeel added reviewers: SixWeining, wangleiat, xen0n, xry111, MaskRay,
DavidSpickett.
Herald added a subscriber: StephenFan.
Herald added a project: All.
seehearfeel requested review of this revision.
Herald added a project: LLDB.
Herald added a subscriber: lldb-commits.
Take LoongArch "break" instruction as breakpoint trap code, so
our breakpoint works as expected now.
By the way, LoongArch doesn't support hardware single stepping
yet in upstream Linux, ptrace(PTRACE_SINGLESTEP) returns -EIO
now, a software implementation may come in future commit.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D137519
Files:
lldb/source/Host/common/NativeProcessProtocol.cpp
lldb/source/Target/Platform.cpp
Index: lldb/source/Target/Platform.cpp
===
--- lldb/source/Target/Platform.cpp
+++ lldb/source/Target/Platform.cpp
@@ -1939,6 +1939,14 @@
}
} break;
+ case llvm::Triple::loongarch32:
+ case llvm::Triple::loongarch64: {
+static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a,
+ 0x00}; // break
+trap_opcode = g_loongarch_opcode;
+trap_opcode_size = sizeof(g_loongarch_opcode);
+ } break;
+
default:
return 0;
}
Index: lldb/source/Host/common/NativeProcessProtocol.cpp
===
--- lldb/source/Host/common/NativeProcessProtocol.cpp
+++ lldb/source/Host/common/NativeProcessProtocol.cpp
@@ -507,6 +507,7 @@
static const uint8_t g_ppcle_opcode[] = {0x08, 0x00, 0xe0, 0x7f}; // trap
static const uint8_t g_riscv_opcode[] = {0x73, 0x00, 0x10, 0x00}; // ebreak
static const uint8_t g_riscv_opcode_c[] = {0x02, 0x90}; // c.ebreak
+ static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a, 0x00}; //
break
switch (GetArchitecture().GetMachine()) {
case llvm::Triple::aarch64:
@@ -541,6 +542,10 @@
: llvm::makeArrayRef(g_riscv_opcode);
}
+ case llvm::Triple::loongarch32:
+ case llvm::Triple::loongarch64:
+return llvm::makeArrayRef(g_loongarch_opcode);
+
default:
return llvm::createStringError(llvm::inconvertibleErrorCode(),
"CPU type not supported!");
@@ -567,6 +572,8 @@
case llvm::Triple::ppc64le:
case llvm::Triple::riscv32:
case llvm::Triple::riscv64:
+ case llvm::Triple::loongarch32:
+ case llvm::Triple::loongarch64:
// On these architectures the PC doesn't get updated for breakpoint hits.
return 0;
Index: lldb/source/Target/Platform.cpp
===
--- lldb/source/Target/Platform.cpp
+++ lldb/source/Target/Platform.cpp
@@ -1939,6 +1939,14 @@
}
} break;
+ case llvm::Triple::loongarch32:
+ case llvm::Triple::loongarch64: {
+static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a,
+ 0x00}; // break
+trap_opcode = g_loongarch_opcode;
+trap_opcode_size = sizeof(g_loongarch_opcode);
+ } break;
+
default:
return 0;
}
Index: lldb/source/Host/common/NativeProcessProtocol.cpp
===
--- lldb/source/Host/common/NativeProcessProtocol.cpp
+++ lldb/source/Host/common/NativeProcessProtocol.cpp
@@ -507,6 +507,7 @@
static const uint8_t g_ppcle_opcode[] = {0x08, 0x00, 0xe0, 0x7f}; // trap
static const uint8_t g_riscv_opcode[] = {0x73, 0x00, 0x10, 0x00}; // ebreak
static const uint8_t g_riscv_opcode_c[] = {0x02, 0x90}; // c.ebreak
+ static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a, 0x00}; // break
switch (GetArchitecture().GetMachine()) {
case llvm::Triple::aarch64:
@@ -541,6 +542,10 @@
: llvm::makeArrayRef(g_riscv_opcode);
}
+ case llvm::Triple::loongarch32:
+ case llvm::Triple::loongarch64:
+return llvm::makeArrayRef(g_loongarch_opcode);
+
default:
return llvm::createStringError(llvm::inconvertibleErrorCode(),
"CPU type not supported!");
@@ -567,6 +572,8 @@
case llvm::Triple::ppc64le:
case llvm::Triple::riscv32:
case llvm::Triple::riscv64:
+ case llvm::Triple::loongarch32:
+ case llvm::Triple::loongarch64:
// On these architectures the PC doesn't get updated for breakpoint hits.
return 0;
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[Lldb-commits] [PATCH] D137519: [LLDB][LoongArch] Add LoongArch software breakpoint trap code
xen0n added a comment.
I think eventually the upstream Linux would gain support for hardware
single-stepping, before the architecture is widely adopted (to be frank, if at
all), so it's probably not necessary to mention this point in the commit
message. Focus on the code changes being made right here.
Also the commit message is a bit unnatural (the English "take" feels very
different than Chinese "取" in this context). Let me tweak it a little bit and
please check if it's still conveying the message you intended.
Comment at: lldb/source/Host/common/NativeProcessProtocol.cpp:510
static const uint8_t g_riscv_opcode_c[] = {0x02, 0x90}; // c.ebreak
+ static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a, 0x00}; //
break
This is not a plain `break`, but rather `break 0x5` or `break BRK_SSTEPBP` as
the constant/magic 5 comes from Linux/LoongArch `asm/break.h`. Better reflect
this in the comment.
Comment at: lldb/source/Target/Platform.cpp:1945
+static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a,
+ 0x00}; // break
+trap_opcode = g_loongarch_opcode;
Same here.
Repository:
rG LLVM Github Monorepo
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[Lldb-commits] [PATCH] D137519: [LLDB] Add LoongArch software breakpoint trap opcode
seehearfeel updated this revision to Diff 473542.
seehearfeel retitled this revision from "[LLDB] Add LoongArch software
breakpoint trap opcode" to " [LLDB] Add LoongArch software breakpoint trap
opcode".
seehearfeel edited the summary of this revision.
seehearfeel added a comment.
Use "break 0x5" in the code comment.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D137519/new/
https://reviews.llvm.org/D137519
Files:
lldb/source/Host/common/NativeProcessProtocol.cpp
lldb/source/Target/Platform.cpp
Index: lldb/source/Target/Platform.cpp
===
--- lldb/source/Target/Platform.cpp
+++ lldb/source/Target/Platform.cpp
@@ -1939,6 +1939,14 @@
}
} break;
+ case llvm::Triple::loongarch32:
+ case llvm::Triple::loongarch64: {
+static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a,
+ 0x00}; // break 0x5
+trap_opcode = g_loongarch_opcode;
+trap_opcode_size = sizeof(g_loongarch_opcode);
+ } break;
+
default:
return 0;
}
Index: lldb/source/Host/common/NativeProcessProtocol.cpp
===
--- lldb/source/Host/common/NativeProcessProtocol.cpp
+++ lldb/source/Host/common/NativeProcessProtocol.cpp
@@ -507,6 +507,8 @@
static const uint8_t g_ppcle_opcode[] = {0x08, 0x00, 0xe0, 0x7f}; // trap
static const uint8_t g_riscv_opcode[] = {0x73, 0x00, 0x10, 0x00}; // ebreak
static const uint8_t g_riscv_opcode_c[] = {0x02, 0x90}; // c.ebreak
+ static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a,
+ 0x00}; // break 0x5
switch (GetArchitecture().GetMachine()) {
case llvm::Triple::aarch64:
@@ -541,6 +543,10 @@
: llvm::makeArrayRef(g_riscv_opcode);
}
+ case llvm::Triple::loongarch32:
+ case llvm::Triple::loongarch64:
+return llvm::makeArrayRef(g_loongarch_opcode);
+
default:
return llvm::createStringError(llvm::inconvertibleErrorCode(),
"CPU type not supported!");
@@ -567,6 +573,8 @@
case llvm::Triple::ppc64le:
case llvm::Triple::riscv32:
case llvm::Triple::riscv64:
+ case llvm::Triple::loongarch32:
+ case llvm::Triple::loongarch64:
// On these architectures the PC doesn't get updated for breakpoint hits.
return 0;
Index: lldb/source/Target/Platform.cpp
===
--- lldb/source/Target/Platform.cpp
+++ lldb/source/Target/Platform.cpp
@@ -1939,6 +1939,14 @@
}
} break;
+ case llvm::Triple::loongarch32:
+ case llvm::Triple::loongarch64: {
+static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a,
+ 0x00}; // break 0x5
+trap_opcode = g_loongarch_opcode;
+trap_opcode_size = sizeof(g_loongarch_opcode);
+ } break;
+
default:
return 0;
}
Index: lldb/source/Host/common/NativeProcessProtocol.cpp
===
--- lldb/source/Host/common/NativeProcessProtocol.cpp
+++ lldb/source/Host/common/NativeProcessProtocol.cpp
@@ -507,6 +507,8 @@
static const uint8_t g_ppcle_opcode[] = {0x08, 0x00, 0xe0, 0x7f}; // trap
static const uint8_t g_riscv_opcode[] = {0x73, 0x00, 0x10, 0x00}; // ebreak
static const uint8_t g_riscv_opcode_c[] = {0x02, 0x90}; // c.ebreak
+ static const uint8_t g_loongarch_opcode[] = {0x05, 0x00, 0x2a,
+ 0x00}; // break 0x5
switch (GetArchitecture().GetMachine()) {
case llvm::Triple::aarch64:
@@ -541,6 +543,10 @@
: llvm::makeArrayRef(g_riscv_opcode);
}
+ case llvm::Triple::loongarch32:
+ case llvm::Triple::loongarch64:
+return llvm::makeArrayRef(g_loongarch_opcode);
+
default:
return llvm::createStringError(llvm::inconvertibleErrorCode(),
"CPU type not supported!");
@@ -567,6 +573,8 @@
case llvm::Triple::ppc64le:
case llvm::Triple::riscv32:
case llvm::Triple::riscv64:
+ case llvm::Triple::loongarch32:
+ case llvm::Triple::loongarch64:
// On these architectures the PC doesn't get updated for breakpoint hits.
return 0;
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[Lldb-commits] [PATCH] D137519: [LLDB] Add LoongArch software breakpoint trap opcode
xen0n accepted this revision. xen0n added a comment. This revision is now accepted and ready to land. You removed the formatting in the commit message and added an extra space in front of the patch title, all fixed for you. The changes look good LoongArch-wise now. Thanks! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137519/new/ https://reviews.llvm.org/D137519 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
[Lldb-commits] [PATCH] D137519: [LLDB] Add LoongArch software breakpoint trap opcode
SixWeining accepted this revision. SixWeining added a comment. LGTM. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137519/new/ https://reviews.llvm.org/D137519 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
