Re: [PATCH v3 03/24] arm: Remove COMMAND_LINE_SIZE from uapi
On Tue, Feb 14, 2023 at 08:49:04AM +0100, Alexandre Ghiti wrote: > From: Palmer Dabbelt > > As far as I can tell this is not used by userspace and thus should not > be part of the user-visible API. > > Signed-off-by: Palmer Dabbelt Looks good to me. What's the merge plan for this? Thanks. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last! ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [PATCH v3 03/24] arm: Remove COMMAND_LINE_SIZE from uapi
On Wed, Feb 15, 2023, at 13:59, Russell King (Oracle) wrote: > On Tue, Feb 14, 2023 at 08:49:04AM +0100, Alexandre Ghiti wrote: >> From: Palmer Dabbelt >> >> As far as I can tell this is not used by userspace and thus should not >> be part of the user-visible API. >> >> Signed-off-by: Palmer Dabbelt > > Looks good to me. What's the merge plan for this? The easiest way is probably if I merge it through the whole series through the asm-generic tree. The timing is a bit unfortunate as we're just ahead of the merge window, so unless we really need this in 6.3, I'd suggest that Alexandre resend the series to me in two weeks with the Acks added in and I'll pick it up for 6.4. Arnd ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: How many colours does the ARC cache have?
On 2/10/23 09:06, Matthew Wilcox wrote: I see a discrepancy here ... arch/arc/include/asm/shmparam.h: /* Handle upto 2 cache bins */ #define SHMLBA (2 * PAGE_SIZE) arch/arc/include/asm/cacheflush.h: #define CACHE_COLORS_NUM4 The initial aliasing dcache support assumed 2 colors but was later bumped to 4, w/o making the adjustment in shmparam.h (there are some other problems with the arc cache flushing code; The VIPT aliasing config (which is pretty much dead and unused) or regular parts ? I'm working on patches to address them, but those are things I understand a little better. I know nothing about the ARC architecture itself) Legacy ARC700 cpus had VIPT D$. The cache size was configurable by Soc builder and the specific geometry could yield an aliasing configuration (e.g. standard page size 8K, 4 way set associative D$: so D$ > 32K were aliasing and needed CONFIG_ARC_CACHE_VIPT_ALIASING). Although there was ever only 1 customer who taped out an aliasing cache config. The newer ARC HS cores have PIPT D$ and thus don't need the aliasing support. FWIW we could rip out all the VIPT aliasing code as I don't think it is needed anymore. @Alexey can you confirm ? -Vineet ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
