Re: [PATCH 05/27] arc: TCG instruction generator and hand-definitions
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote:
+/*
+ * Function to add boiler plate code for conditional execution.
+ * It will add tcg_gen codes only if there is a condition to
+ * be checked (ctx->insn.cc != 0).
+ * Remember to pair it with gen_cc_epilogue(ctx) macro.
+ */
+static void gen_cc_prologue(DisasCtxt *ctx)
+{
+ctx->tmp_reg = tcg_temp_local_new();
+ctx->label = gen_new_label();
There's no point in creating these when insn.cc is false.
+if (ctx->insn.cc) {
+arc_gen_verifyCCFlag(ctx, ctx->tmp_reg);
+tcg_gen_brcondi_tl(TCG_COND_NE, ctx->tmp_reg, 1, ctx->label);
You don't need a local temp for tmp_reg.
You can create and free it here.
+/*
+ * The finishing counter part of gen_cc_prologue. This is supposed
+ * to be put at the end of the function using it.
+ */
+static void gen_cc_epilogue(const DisasCtxt *ctx)
+{
+if (ctx->insn.cc) {
+gen_set_label(ctx->label);
+}
+tcg_temp_free(ctx->tmp_reg);
+}
You do not need to keep it live til here.
+/*
+ * Populates a 32-bit vector with repeating SHIMM:
+ * vec32=(00u6,00u6)
+ * vec32=(s12,s12)
+ * It's crucial that the s12 part of an encoding is in signed
+ * integer form while passed along in SHIMM, e.g:
+ * s12 = -125 (0xf803) --> 0xf803
+ * Do not forget to free the returned TCGv_i32 when done!
+ */
+static TCGv_i32 dup_shimm_to_i32(int16_t shimm)
+{
+TCGv_i32 vec32 = tcg_temp_new_i32();
+int32_t val = shimm;
+val = ((val << 16) & 0x) | (val & 0x);
+tcg_gen_movi_i32(vec32, val);
+return vec32;
+}
return tcg_constant_i32(dup_const(MO_16, shimm));
+static TCGv_i64 dup_limm_to_i64(int32_t limm)
+{
+TCGv_i64 vec64 = tcg_temp_new_i64();
+int64_t val = limm;
+val = (val << 32) | (val & 0x);
+tcg_gen_movi_i64(vec64, val);
+return vec64;
+}
return tcg_constant_i64(dup_const(MO_32, limm));
+static TCGv_i64 quad_shimm_to_i64(int16_t shimm)
+{
+TCGv_i64 vec64 = tcg_temp_new_i64();
+int64_t val = shimm;
+val = (val << 48) | ((val << 32) & 0x) |
+ ((val << 16) & 0x) | (val & 0x);
+tcg_gen_movi_i64(vec64, val);
+return vec64;
+}
return tcg_constant_i64(dup_const(MO_16, shimm));
Note that, tcg_constant_* are hashed and need not be freed (but are silently
accepted if you do). However, you cannot assign to them. If you really
require a mutable temporary, use tcg_const_*.
+static void gen_vec_op2h(const DisasCtxt *ctx,
+ void (*OP)(TCGv, TCGv, TCGv),
+ TCGv_i32 dest,
+ TCGv_i32 b32,
+ TCGv_i32 c32)
+{
+TCGv_i32 t0, t1;
+
+/* If no real register for result, then this a nop. Bail out! */
+if (!(ctx->insn.operands[0].type & ARC_OPERAND_IR)) {
+return;
+}
+
+t0 = tcg_temp_new();
+tcg_gen_mov_i32(t0, b32);
+/*
+ * If the last operand is a u6/s12, say 63, there is no "HI" in it.
+ * Instead, it must be duplicated to form a pair; e.g.: (63, 63).
+ */
+if (ctx->insn.operands[2].type & ARC_OPERAND_SHIMM) {
+t1 = dup_shimm_to_i32(ctx->insn.operands[2].value);
+} else {
+t1 = tcg_temp_new();
+tcg_gen_mov_i32(t1, c32);
+}
+
+(*OP)(dest, t0, t1);
+
+tcg_temp_free(t1);
+tcg_temp_free(t0);
+}
Why are you copying b32 to a new temp? Do you have callbacks that are not
careful about overlap between dest, t0, t1, and assume that you have
non-overlapping inputs?
If you don't require uniqueness, and use tcg_constant_* above, then you don't
need to copy c32 into a new temp either, nor worry about conditionally freeing it.
+static void gen_add16(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
+{
+TCGv_i32 tmp = tcg_temp_new_i32();
+tcg_gen_xor_i32(tmp, t0, t1);
+tcg_gen_andi_i32(tmp, tmp, 0x8000);
+tcg_gen_andi_i32(t0, t0, ~0x8000);
+tcg_gen_andi_i32(t1, t1, ~0x8000);
+tcg_gen_add_i32(t0, t0, t1);
+tcg_gen_xor_i32(dest, t0, tmp);
+tcg_temp_free_i32(tmp);
+}
I guess that answers my question of whether you're relying on new unique temps
as inputs: yes.
+static void arc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
+{
+bool in_a_delayslot_instruction = false;
+DisasContext *dc = container_of(dcbase, DisasContext, base);
+CPUARCState *env = cpu->env_ptr;
+
+/* TODO (issue #62): these must be removed */
+dc->zero = tcg_const_local_tl(0);
+dc->one = tcg_const_local_tl(1);
+
+if (env->stat.is_delay_slot_instruction == 1) {
+in_a_delayslot_instruction = true;
+}
+
+dc->cpc = dc->base.pc_next;
+decode_opc(env, dc);
+
+dc->base.pc_next = dc->npc;
+tcg_gen_movi_tl(cpu_npc, dc->npc);
+
+if (in_a_delayslot_instruction == true) {
+dc->base.is_jmp = DISAS_NORETURN;
+
+/* Post execution delayslot logic. */
+TCGLabel *DEf_not_set_label1 =
Re: [PATCH 06/27] arc: semfunc.c tcg code generator.
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote: From: Cupertino Miranda TCG generator scripts for semfunc.c file. Signed-off-by: Cupertino Miranda --- My only comment here is: do we really want to re-write semfunc.c, as opposed to read one input file and output another? I presume that the original comments come from some canonical source at Synopsys? I don't know ruby at all, and don't really know how to evaluate the rest. r~ ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [PATCH 06/27] arc: semfunc.c tcg code generator.
On Wed, 7 Apr 2021 at 18:17, Richard Henderson wrote: > > On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote: > > From: Cupertino Miranda > > > > TCG generator scripts for semfunc.c file. > > > > Signed-off-by: Cupertino Miranda > I don't know ruby at all, and don't really know how to evaluate the rest. Yes; there is a massive hill to climb to justify adding yet another scripting language to the code base. The strong presumption would be that this should be a Python script. I agree that rewriting the .c file is very weird and probably best avoided. thanks -- PMM ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [PATCH 07/27] arc: TCG instruction definitions
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote:
+void arc_gen_verifyCCFlag(const DisasCtxt *ctx, TCGv ret)
Why "verify"? I don't see anything that verifies here...
I'll note that this can be done better, if you expose the actual comparison
rather than a simple boolean. This could remove 2-3 insns from gen_cc_prologue().
See e.g. disas_jcc and DisasCompare from target/s390x.
+{ MO_UL, MO_UB, MO_UW }, /* non sign-extended */
"non sign-extended" => "zero-extended".
+void arc_gen_no_further_loads_pending(const DisasCtxt *ctx, TCGv ret)
+{
+/* TODO: To complete on SMP support. */
+tcg_gen_movi_tl(ret, 1);
+}
+
+void arc_gen_set_debug(const DisasCtxt *ctx, bool value)
+{
+/* TODO: Could not find a reson to set this. */
+}
What's the point of these within the semantics? It seems like some sort of
in-chip debugging thing that tcg should ignore?
+void
+arc_gen_execute_delayslot(DisasCtxt *ctx, TCGv bta, TCGv take_branch)
+{
+assert(ctx->insn.limm_p == 0 && !ctx->in_delay_slot);
+
+ctx->in_delay_slot = true;
+uint32_t cpc = ctx->cpc;
+uint32_t pcl = ctx->pcl;
+insn_t insn = ctx->insn;
+
+ctx->cpc = ctx->npc;
+ctx->pcl = ctx->cpc & ((target_ulong) 0xfffc);
+
+++ctx->ds;
+
+TCGLabel *do_not_set_bta_and_de = gen_new_label();
+tcg_gen_brcondi_tl(TCG_COND_NE, take_branch, 1, do_not_set_bta_and_de);
+/*
+ * In case an exception should be raised during the execution
+ * of delay slot, bta value is used to set erbta.
+ */
+tcg_gen_mov_tl(cpu_bta, bta);
+/* We are in a delay slot */
+tcg_gen_mov_tl(cpu_DEf, take_branch);
+gen_set_label(do_not_set_bta_and_de);
+
+tcg_gen_movi_tl(cpu_is_delay_slot_instruction, 1);
+
+/* Set the pc to the next pc */
+tcg_gen_movi_tl(cpu_pc, ctx->npc);
+/* Necessary for the likely call to restore_state_to_opc() */
+tcg_gen_insn_start(ctx->npc);
This is unlikely to work reliably.
I suspect it does not work at all with icount.
+ctx->env->enabled_interrupts = false;
Illegal, as mentioned before.
+/*
+ * In case we might be in a situation where the delayslot is in a
+ * different MMU page. Make a fake exception to interrupt
+ * delayslot execution in the context of the branch.
+ * The delayslot will then be re-executed in isolation after the
+ * branch code has set bta and DEf status flag.
+ */
+if ((cpc & PAGE_MASK) < 0x8000 &&
+(cpc & PAGE_MASK) != (ctx->cpc & PAGE_MASK)) {
+ctx->in_delay_slot = false;
+TCGv dpc = tcg_const_local_tl(ctx->npc);
+tcg_gen_mov_tl(cpu_pc, dpc);
+gen_helper_fake_exception(cpu_env, dpc);
I think you should *always* execute the delay slot separately. That's the only
way the instruction count will be done right.
I'm pretty sure I asked you before to have a look at some of the other targets
that implement delay slots for ideas on how to do this correctly.
+void arc_gen_get_bit(TCGv ret, TCGv a, TCGv pos)
+{
+tcg_gen_rotr_tl(ret, a, pos);
+tcg_gen_andi_tl(ret, ret, 1);
+}
Should be a plain shift, not a rotate, surely.
+void arc_gen_extract_bits(TCGv ret, TCGv a, TCGv start, TCGv end)
+{
+TCGv tmp1 = tcg_temp_new();
+
+tcg_gen_shr_tl(ret, a, end);
+
+tcg_gen_sub_tl(tmp1, start, end);
+tcg_gen_addi_tl(tmp1, tmp1, 1);
+tcg_gen_shlfi_tl(tmp1, 1, tmp1);
+tcg_gen_subi_tl(tmp1, tmp1, 1);
+
+tcg_gen_and_tl(ret, ret, tmp1);
Doesn't work for start == 31, end = 0,
due to shift count of 32.
You could rewrite this to
t = 31 - start;
ret = a << t;
t = 31 - end;
ret = ret >> t;
Amusingly, there's exactly one instance of extractBits that doesn't use
constant arguments, and that's in ROR. And there, the extract *would* use
constant arguments if the extract was from @dest instead of from lsrc. At
which point you could just use tcg_gen_extract_tl.
+TCGv arc_gen_next_reg(const DisasCtxt *ctx, TCGv reg)
+{
+int i;
+for (i = 0; i < 64; i += 2) {
+if (reg == cpu_r[i]) {
+return cpu_r[i + 1];
+}
+}
+/* Check if REG is an odd register. */
+for (i = 1; i < 64; i += 2) {
+/* If so, that is unsanctioned. */
+if (reg == cpu_r[i]) {
+arc_gen_excp(ctx, EXCP_INST_ERROR, 0, 0);
+return NULL;
+}
+}
This is really ugly. Surely you can do something better.
Perhaps not resolving regno to TCGv quite so early, so that it's easy to simply
add one and index.
+void arc_gen_verifyCCFlag(const DisasCtxt *ctx, TCGv ret);
+#define getCCFlag(R)arc_gen_verifyCCFlag(ctx, R)
I wonder if it would be clearer if the ruby translator simply added the context
parameter itself, rather than have 99 macros to do the same.
+#define getNFlag(R) cpu_Nf
+#define setNFlag(ELEM) tcg_gen_shri_tl(cpu_Nf, ELEM, (TARGET_LONG_BITS - 1))
I'll note that setting of flags happens much more often than checking of flags.
Re: [GIT PULL] ARC fixes for 5.12-rc7
The pull request you sent on Wed, 7 Apr 2021 20:15:54 +: > git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git/ > tags/arc-5.12-rc7 has been merged into torvalds/linux.git: https://git.kernel.org/torvalds/c/454859c552da78b0f587205d308401922b56863e Thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/prtracker.html ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [PATCH 14/27] arc: Add support for ARCv2
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote: diff --git a/configure b/configure index 535e6a9269..80d993fac7 100755 --- a/configure +++ b/configure @@ -680,6 +680,8 @@ elif check_define __arm__ ; then cpu="arm" elif check_define __aarch64__ ; then cpu="aarch64" +elif check_define __arc__ ; then + cpu="arc" else cpu=$(uname -m) fi This is host related, not target. diff --git a/disas.c b/disas.c index a61f95b580..a10fa41330 100644 --- a/disas.c +++ b/disas.c @@ -208,6 +208,8 @@ static void initialize_debug_host(CPUDebug *s) s->info.cap_insn_split = 6; #elif defined(__hppa__) s->info.print_insn = print_insn_hppa; +#elif defined(__arc__) +s->info.print_insn = print_insn_arc; #endif As is this. Until arc can self-host qemu, you don't need them. --- a/hw/arc/Makefile.objs Leftover from before meson.build. r~ ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [PATCH 15/27] tests/tcg: ARC: Add TCG instruction definition tests
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote: From: Claudiu Zissulescu The added tests verify basic instructions execution as well as more advanced features such as zero overhead loops interrupt system, memory management unit and memory protection unit. Signed-off-by: Claudiu Zissulescu Signed-off-by: Cupertino Miranda --- tests/Makefile.include| 1 + tests/tcg/arc/Makefile| 114 tests/tcg/arc/Makefile.softmmu-target | 43 ++ tests/tcg/arc/Makefile.target | 101 You shoud *only* need Makefile.softmmu-target. The bare Makefile is (or should be) unused. The Makefile.target is for arc-linux-user, which you do not build. r~ ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [PATCH 16/27] tests/acceptance: ARC: Add linux boot testing.
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote:
From: Cupertino Miranda
Just an acceptance test with ARC Linux booting.
Signed-off-by: Cupertino Miranda
---
tests/acceptance/boot_linux_console.py | 55 ++
1 file changed, 55 insertions(+)
diff --git a/tests/acceptance/boot_linux_console.py
b/tests/acceptance/boot_linux_console.py
index 1ca32ecf25..b5a781b6b4 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -138,6 +138,26 @@ def test_mips_malta(self):
console_pattern = 'Kernel command line: %s' % kernel_command_line
self.wait_for_console_pattern(console_pattern)
+def test_mips_malta(self):
+"""
+:avocado: tags=arch:arc
+"""
+deb_url = ('http://snapshot.debian.org/archive/debian/'
+ '20130217T032700Z/pool/main/l/linux-2.6/'
+ 'linux-image-2.6.32-5-4kc-malta_2.6.32-48_mips.deb')
+deb_hash = 'a8cfc28ad8f45f54811fc6cf74fc43ffcfe0ba04'
+deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
+kernel_path = self.extract_from_deb(deb_path,
+'/boot/vmlinux-archs')
+
+self.vm.set_console()
+kernel_command_line = self.KERNEL_COMMON_COMMAND_LINE + 'console=ttyS0'
+self.vm.add_args('-kernel', kernel_path,
+ '-append', kernel_command_line)
+self.vm.launch()
+console_pattern = 'Kernel command line: %s' % kernel_command_line
+self.wait_for_console_pattern(console_pattern)
+
Careful with your rebasing. This is obviously not what you wanted.
r~
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Re: [PATCH 18/27] arcv3: Decoder code
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote: From: Cupertino Miranda --- disas/arc.c| 51 +- target/arc/decoder-v3.c| 1547 target/arc/decoder-v3.h| 322 target/arc/flags-v3.def| 103 +++ target/arc/operands-v3.def | 133 5 files changed, 2147 insertions(+), 9 deletions(-) create mode 100644 target/arc/decoder-v3.c create mode 100644 target/arc/decoder-v3.h create mode 100644 target/arc/flags-v3.def create mode 100644 target/arc/operands-v3.def Do we really need a complete copy of the v2 decoder included with the v3 decoder? r~ ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [PATCH 20/27] arcv3: TCG, decoder glue code and helper changes
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote:
+uint64_t helper_carry_add_flag32(uint64_t dest, uint64_t b, uint64_t c) {
+return carry_add_flag(dest, b, c, 32);
+}
+
+target_ulong helper_overflow_add_flag32(target_ulong dest, target_ulong b,
target_ulong c) {
+return overflow_add_flag(dest, b, c, 32);
+}
+
+target_ulong helper_overflow_sub_flag32(target_ulong dest, target_ulong b,
target_ulong c) {
+dest = dest & 0x;
+b = b & 0x;
+c = c & 0x;
+return overflow_sub_flag(dest, b, c, 32);
+}
You shouldn't need to replicate these functions. Use the correct types and
masking in the first place.
+uint64_t helper_rotate_left32(uint64_t orig, uint64_t n)
+{
+uint64_t t;
+uint64_t dest = (orig << n) & ((0x << n) & 0x);
+
+t = (orig >> (32 - n)) & ((1 << n) - 1);
+dest |= t;
+
+return dest;
+}
+
+uint64_t helper_rotate_right32(uint64_t orig, uint64_t n)
+{
+uint64_t t;
+uint64_t dest = (orig >> n) & (0x >> n);
+
+t = ((orig & ((1 << n) - 1)) << (32 - n));
+dest |= t;
+
+return dest;
+}
rol32 and ror32.
+uint64_t helper_asr_32(uint64_t b, uint64_t c)
+{
+ uint64_t t;
+ c = c & 31;
+ t = b;
+ for(int i = 0; i < c; i++) {
+t >>= 1;
+if((b & 0x8000) != 0)
+ t |= 0x8000;
+ }
+ //t |= ((1 << (c+1)) - 1) << (32 - c);
+
+ return t;
Really? I can't imagine what lead you to write this.
Who writes a simple shift operation with a loop?
Perhaps no helper at all and
tcg_gen_sra_tl(ret, b, c);
tcg_gen_ext32s_tl(ret, ret);
+target_ulong helper_ffs32(CPUARCState *env, uint64_t src)
+{
+int i;
+if (src == 0) {
+ return 31;
+}
+for (i = 0; i <= 31; i++) {
+ if (((src >> i) & 1) != 0) {
+break;
+ }
+}
+return i;
+}
tcg_gen_ori_tl(ret, src, MAKE_64BIT_MASK(32, 32));
tcg_gen_ctzi_tl(ret, ret, 31);
Though I really wonder if you've got that function correct, as it's not the
*normal* definition of ffs...
+target_ulong helper_norml(CPUARCState *env, uint64_t src1)
+{
+int i;
+int64_t tmp = (int64_t) src1;
+if (tmp == 0 || tmp == -1) {
+ return 0;
+}
+for (i = 0; i <= 63; i++) {
+ if ((tmp >> i) == 0) {
+ break;
+ }
+ if ((tmp >> i) == -1) {
+ break;
+ }
+}
+return i;
+}
This is some cognate of count-leading-repititions-of-sign-bit,
tcg_gen_clrsb_tl. A decent computation should be like
tcg_gen_clrsb_i64(ret, src);
tcg_gen_subfi_i64(ret, 63, ret);
diff --git a/target/arc/semfunc-v2_mapping.def
b/target/arc/semfunc-v2_mapping.def
new file mode 100644
index 00..ab8d9ff123
--- /dev/null
+++ b/target/arc/semfunc-v2_mapping.def
You could have named this properly to start.
r~
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Re: [PATCH 21/27] arcv3: TCG instruction generator changes
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote:
+if(ctx->insn.limm & 0x8000)
+ ctx->insn.limm += 0x;
(1) bad braces, but
(2) use an unconditional cast to int32_t.
Qemu forces the compiler to use standard 2's compliment arithmetic. We don't
have to go out of our way to work around the ISO-C lunacy of "undefined values"
that for no good reason still allows sign-magnitude and 1's compliment arithmetic.
+if (ctx->insn.cc) {
+TCGv cc = tcg_temp_local_new();
+arc_gen_verifyCCFlag(ctx, cc);
+tcg_gen_brcondi_tl(TCG_COND_NE, cc, 1, done);
+tcg_temp_free(cc);
+}
+
Lots of non-uses of gen_cc_prologue/epilogue.
r~
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Re: [PATCH 22/27] arcv3: TCG instruction definitions
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote: From: Cupertino Miranda --- target/arc/semfunc-helper.c |13 + target/arc/semfunc-helper.h |31 + target/arc/semfunc-v3.c | 14653 ++ target/arc/semfunc-v3.h |55 + 4 files changed, 14752 insertions(+) create mode 100644 target/arc/semfunc-v3.c create mode 100644 target/arc/semfunc-v3.h And there's no good way to share code between v2 and v3? r~ ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[GIT PULL] ARC fixes for 5.12-rc7
Hi Linus, Please pull a few straggler fixes for ARC for 5.12 ! Thx, -Vineet --> The following changes since commit fe07bfda2fb9cdef8a4d4008a409bb02f35f1bd8: Linux 5.12-rc1 (2021-02-28 16:05:19 -0800) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git/ tags/arc-5.12-rc7 for you to fetch changes up to 83520d62cc5a94d2ff0e2d37c8204fca13dd2637: ARC: treewide: avoid the pointer addition with NULL pointer (2021-03-22 10:05:43 -0700) ARC fixlets for 5.12-rc7 Vineet Gupta (1): ARC: haps: bump memory to 1 GB Wang Qing (1): arc: kernel: Return -EFAULT if copy_to_user() fails dean.yang_cp (1): ARC: treewide: avoid the pointer addition with NULL pointer arch/arc/boot/dts/haps_hs.dts | 2 +- arch/arc/kernel/signal.c | 4 ++-- arch/arc/kernel/unwind.c | 27 ++- 3 files changed, 17 insertions(+), 16 deletions(-) ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [PATCH 07/27] arc: TCG instruction definitions
On 4/5/21 7:31 AM, cupertinomira...@gmail.com wrote:
+/*
+ * ADD
+ *Variables: @b, @c, @a
+ *Functions: getCCFlag, getFFlag, setZFlag, setNFlag, setCFlag, CarryADD,
+ * setVFlag, OverflowADD
+ * --- code ---
+ * {
+ * cc_flag = getCCFlag ();
+ * lb = @b;
+ * lc = @c;
+ * if((cc_flag == true))
+ * {
+ * lb = @b;
+ * lc = @c;
+ * @a = (@b + @c);
+ * if((getFFlag () == true))
+ * {
+ * setZFlag (@a);
+ * setNFlag (@a);
+ * setCFlag (CarryADD (@a, lb, lc));
+ * setVFlag (OverflowADD (@a, lb, lc));
+ * };
+ * };
+ * }
+ */
+
+int
+arc_gen_ADD(DisasCtxt *ctx, TCGv b, TCGv c, TCGv a)
+{
+int ret = DISAS_NEXT;
+TCGv temp_3 = tcg_temp_local_new();
+TCGv cc_flag = tcg_temp_local_new();
+TCGv lb = tcg_temp_local_new();
+TCGv lc = tcg_temp_local_new();
+TCGv temp_1 = tcg_temp_local_new();
+TCGv temp_2 = tcg_temp_local_new();
+TCGv temp_5 = tcg_temp_local_new();
+TCGv temp_4 = tcg_temp_local_new();
+TCGv temp_7 = tcg_temp_local_new();
+TCGv temp_6 = tcg_temp_local_new();
+getCCFlag(temp_3);
+tcg_gen_mov_tl(cc_flag, temp_3);
+tcg_gen_mov_tl(lb, b);
+tcg_gen_mov_tl(lc, c);
+TCGLabel *done_1 = gen_new_label();
+tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true);
+tcg_gen_xori_tl(temp_2, temp_1, 1);
+tcg_gen_andi_tl(temp_2, temp_2, 1);
+tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);
+tcg_gen_mov_tl(lb, b);
+tcg_gen_mov_tl(lc, c);
+tcg_gen_add_tl(a, b, c);
+if ((getFFlag () == true)) {
+setZFlag(a);
+setNFlag(a);
+CarryADD(temp_5, a, lb, lc);
+tcg_gen_mov_tl(temp_4, temp_5);
+setCFlag(temp_4);
+OverflowADD(temp_7, a, lb, lc);
+tcg_gen_mov_tl(temp_6, temp_7);
+setVFlag(temp_6);
+}
+gen_set_label(done_1);
+tcg_temp_free(temp_3);
+tcg_temp_free(cc_flag);
+tcg_temp_free(lb);
+tcg_temp_free(lc);
+tcg_temp_free(temp_1);
+tcg_temp_free(temp_2);
+tcg_temp_free(temp_5);
+tcg_temp_free(temp_4);
+tcg_temp_free(temp_7);
+tcg_temp_free(temp_6);
+
+return ret;
+}
I must say I'm not really impressed by the results here.
Your input is clearly intended to be fed to an optimizing compiler, which TCG
is not.
+/*
+ * DIV
+ *Variables: @src2, @src1, @dest
+ *Functions: getCCFlag, divSigned, getFFlag, setZFlag, setNFlag, setVFlag
+ * --- code ---
+ * {
+ * cc_flag = getCCFlag ();
+ * if((cc_flag == true))
+ * {
+ * if(((@src2 != 0) && ((@src1 != 2147483648) || (@src2 != 4294967295
+ * {
+ * @dest = divSigned (@src1, @src2);
+ * if((getFFlag () == true))
+ * {
+ * setZFlag (@dest);
+ * setNFlag (@dest);
+ * setVFlag (0);
+ * };
+ * }
+ * else
+ * {
+ * };
+ * };
+ * }
+ */
+
+int
+arc_gen_DIV(DisasCtxt *ctx, TCGv src2, TCGv src1, TCGv dest)
+{
+int ret = DISAS_NEXT;
+TCGv temp_9 = tcg_temp_local_new();
+TCGv cc_flag = tcg_temp_local_new();
+TCGv temp_1 = tcg_temp_local_new();
+TCGv temp_2 = tcg_temp_local_new();
+TCGv temp_3 = tcg_temp_local_new();
+TCGv temp_4 = tcg_temp_local_new();
+TCGv temp_5 = tcg_temp_local_new();
+TCGv temp_6 = tcg_temp_local_new();
+TCGv temp_7 = tcg_temp_local_new();
+TCGv temp_8 = tcg_temp_local_new();
+TCGv temp_10 = tcg_temp_local_new();
+TCGv temp_11 = tcg_temp_local_new();
+getCCFlag(temp_9);
+tcg_gen_mov_tl(cc_flag, temp_9);
+TCGLabel *done_1 = gen_new_label();
+tcg_gen_setcond_tl(TCG_COND_EQ, temp_1, cc_flag, arc_true);
+tcg_gen_xori_tl(temp_2, temp_1, 1);
+tcg_gen_andi_tl(temp_2, temp_2, 1);
+tcg_gen_brcond_tl(TCG_COND_EQ, temp_2, arc_true, done_1);
+TCGLabel *else_2 = gen_new_label();
+TCGLabel *done_2 = gen_new_label();
+tcg_gen_setcondi_tl(TCG_COND_NE, temp_3, src2, 0);
+tcg_gen_setcondi_tl(TCG_COND_NE, temp_4, src1, 2147483648);
+tcg_gen_setcondi_tl(TCG_COND_NE, temp_5, src2, 4294967295);
+tcg_gen_or_tl(temp_6, temp_4, temp_5);
+tcg_gen_and_tl(temp_7, temp_3, temp_6);
+tcg_gen_xori_tl(temp_8, temp_7, 1);
+tcg_gen_andi_tl(temp_8, temp_8, 1);
+tcg_gen_brcond_tl(TCG_COND_EQ, temp_8, arc_true, else_2);
+divSigned(temp_10, src1, src2);
+tcg_gen_mov_tl(dest, temp_10);
+if ((getFFlag () == true)) {
+setZFlag(dest);
+setNFlag(dest);
+tcg_gen_movi_tl(temp_11, 0);
+setVFlag(temp_11);
+}
+tcg_gen_br(done_2);
+gen_set_label(else_2);
+gen_set_label(done_2);
+gen_set_label(done_1);
Nor is your compiler, for that matter, creating branches for empty elses. The
two together produce cringe-worthy results.
I can't help but feeling that the same amount of effort would have produced a
legible, maintainable conversion directly to TCG, and
Re: [PATCH] arcc/kernel/process: Few mundane typo fixes
On 3/22/21 5:51 AM, Bhaskar Chowdhury wrote:
> s/defintion/definition/
> s/succeded/succeeded/
> s/commiting/committing/
> s/interrutps/interrupts/
>
> Signed-off-by: Bhaskar Chowdhury
I've squashed all your 3 patches into one (no reason to break them out)
and queued for 5.13.
Thx,
-Vineet
> ---
> diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c
> index d838d0d57696..3793876f42d9 100644
> --- a/arch/arc/kernel/process.c
> +++ b/arch/arc/kernel/process.c
> @@ -50,14 +50,14 @@ SYSCALL_DEFINE3(arc_usr_cmpxchg, int *, uaddr, int,
> expected, int, new)
> int ret;
>
> /*
> - * This is only for old cores lacking LLOCK/SCOND, which by defintion
> + * This is only for old cores lacking LLOCK/SCOND, which by definition
>* can't possibly be SMP. Thus doesn't need to be SMP safe.
>* And this also helps reduce the overhead for serializing in
>* the UP case
>*/
> WARN_ON_ONCE(IS_ENABLED(CONFIG_SMP));
>
> - /* Z indicates to userspace if operation succeded */
> + /* Z indicates to userspace if operation succeeded */
> regs->status32 &= ~STATUS_Z_MASK;
>
> ret = access_ok(uaddr, sizeof(*uaddr));
> @@ -107,7 +107,7 @@ SYSCALL_DEFINE3(arc_usr_cmpxchg, int *, uaddr, int,
> expected, int, new)
>
> void arch_cpu_idle(void)
> {
> - /* Re-enable interrupts <= default irq priority before commiting SLEEP
> */
> + /* Re-enable interrupts <= default irq priority before committing SLEEP
> */
> const unsigned int arg = 0x10 | ARCV2_IRQ_DEF_PRIO;
>
> __asm__ __volatile__(
> @@ -120,7 +120,7 @@ void arch_cpu_idle(void)
>
> void arch_cpu_idle(void)
> {
> - /* sleep, but enable both set E1/E2 (levels of interrutps) before
> committing */
> + /* sleep, but enable both set E1/E2 (levels of interrupts) before
> committing */
> __asm__ __volatile__("sleep 0x3 \n");
> }
>
> --
> 2.31.0
>
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Re: [PATCH] arc/kernel/signal.c: Fix couple of typos
On 3/23/21 10:52 PM, Bhaskar Chowdhury wrote:
> s/unconditonally/unconditionally/
> s/gaurantees/guarantees/
>
> Signed-off-by: Bhaskar Chowdhury
And this one too.
Thx,
-Vineet
> ---
> arch/arc/kernel/signal.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arc/kernel/signal.c b/arch/arc/kernel/signal.c
> index a78d8f745a67..cf1788fd3812 100644
> --- a/arch/arc/kernel/signal.c
> +++ b/arch/arc/kernel/signal.c
> @@ -259,7 +259,7 @@ setup_rt_frame(struct ksignal *ksig, sigset_t *set,
> struct pt_regs *regs)
> regs->r2 = (unsigned long)&sf->uc;
>
> /*
> - * small optim to avoid unconditonally calling do_sigaltstack
> + * small optim to avoid unconditionally calling do_sigaltstack
>* in sigreturn path, now that we only have rt_sigreturn
>*/
> magic = MAGIC_SIGALTSTK;
> @@ -391,7 +391,7 @@ void do_signal(struct pt_regs *regs)
> void do_notify_resume(struct pt_regs *regs)
> {
> /*
> - * ASM glue gaurantees that this is only called when returning to
> + * ASM glue guarantees that this is only called when returning to
>* user mode
>*/
> if (test_thread_flag(TIF_NOTIFY_RESUME))
> --
> 2.30.1
>
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