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2020-09-30 Thread Cupertino Miranda 
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[PATCH 00/14] *** ARC port for review ***

2020-09-30 Thread cupertinomiranda 
From: Cupertino Miranda 

Hello everyone,

It is with utmost pleasure that on behalf of Synopsys I initiate the
upstream process for our ARCv2 architecture QEMU port.

I am one of the main contributors to this port and member of the
Synopsys GNU toolchain team, together with Claudiu Zissulescu and 
Shahab Vahedi.

ARCv2 processors use RISC, and employ the 16-/32-bit instruction set
architecture (ISA).
ARC processors are configurable and extensible for a wide range of uses
in system on a chip (SoC) devices.
It is a common processor in deeply embedded systems, used in storage,
digital home, mobile, automotive, and Internet of Things (IoT) 
applications.

To facilitate reviewing, we split the files through several commits,
attempting to keep file size to reviewable chunks.

The port as presented implements the system softmmu hardware emulation,
capable to boot and run Linux kernel.
It has also been integrated as a patch in Zephyr project, where it is
being used.
To validate and guarantee correctness of the port through development, 
we have created TCG tests from the very beggining, covering the most 
fundamental CPU features.
For the remaining instructions we validate the port through compiler 
testsuites, like DejaGNU, comparing results with real hardware 
executions.

Would like also to thank our colleagues Vineet Gupta and Alexey Broadkin
for their contributions, which due to the collapse of the development
commits, got their contributions overcast by major ones.

Link for Synopsys ARC processor page:
 - https://www.synopsys.com/designware-ip/processor-solutions.html

ARC PRM for both HS and EM processors can be found in:
 - 
https://www.synopsys.com/dw/doc.php/ds/cc/programmers-reference-manual-ARC-EM.pdf
 - 
https://www.synopsys.com/dw/doc.php/ds/cc/programmers-reference-manual-ARC-HS.pdf.

Looking forward to your comments and suggestions.

Best regards,
Cupertino Miranda

*** BLURB HERE ***

Claudiu Zissulescu (5):
  arc: Decoder code
  arc: Opcode definitions table
  arc: Add IRQ and timer subsystem support
  arc: Add Synopsys ARC emulation boards
  tests/tcg: ARC: Add TCG instruction definition tests

Cupertino Miranda (5):
  arc: Add initial core cpu files
  arc: TCG and decoder glue code and helpers
  arc: TCG instruction definitions
  arc: Add BCR and AUX registers implementation
  arc: Add memory management unit (MMU) support

Shahab Vahedi (4):
  arc: TCG instruction generator and hand-definitions
  arc: Add memory protection unit (MPU) support
  arc: Add gdbstub and XML for debugging support
  arc: Add support for ARCv2

 configure | 5 +
 default-configs/arc-softmmu.mak   | 5 +
 disas.c   | 2 +
 disas/arc.c   |   460 +
 disas/meson.build | 1 +
 gdb-xml/arc-aux-minimal.xml   |32 +
 gdb-xml/arc-aux-other.xml |   235 +
 gdb-xml/arc-core-v2.xml   |45 +
 hw/arc/Makefile.objs  |21 +
 hw/arc/arc_sim.c  |   143 +
 hw/arc/arc_uart.c |   267 +
 hw/arc/board-hsdk.c   |   107 +
 hw/arc/boot.c |95 +
 hw/arc/boot.h |21 +
 hw/arc/meson.build|13 +
 hw/arc/nsim.c |86 +
 hw/arc/pic_cpu.c  |   111 +
 hw/arc/sample.c   |77 +
 hw/arc/sim-hs.c   |   107 +
 hw/meson.build| 1 +
 include/disas/dis-asm.h   |10 +-
 include/elf.h | 3 +
 include/exec/poison.h | 2 +
 include/hw/arc/arc_uart.h |43 +
 include/hw/arc/cpudevs.h  |10 +
 include/sysemu/arch_init.h| 1 +
 meson.build   | 3 +-
 softmmu/arch_init.c   | 2 +
 target/arc/Makefile.objs  |34 +
 target/arc/arc-common.h   |55 +
 target/arc/cache.c|   180 +
 target/arc/cache.h|42 +
 target/arc/cpu-param.h|20 +
 target/arc/cpu-qom.h  |53 +
 target/arc/cpu.c  |   468 +
 target/arc/cpu.h  |   532 +
 target/arc/decoder.c  |  1276 ++
 target/arc/decoder.h  |   350 +
 target/arc/extra_mapping.def  |40 +
 target/arc/flags.def  |85 +
 target/arc/gdbstub.c  |   421 +
 target/arc/helper.c   |   293 +
 target/arc/helper.h   |46 +
 target/arc/internals.h|37 +
 target/arc/irq.c  |   658 +
 target/arc/irq.h  |37 +
 target/arc/meson.build|20 +
 target/arc/mmu.c  |   775 +
 target/arc/mmu.h  |   165 +
 target/arc/mpu.

[PATCH 07/14] arc: Add BCR and AUX registers implementation

2020-09-30 Thread cupertinomiranda 
From: Cupertino Miranda 

Add the infrastructure to define build configuration (BCR) and auxiliary
registers allowing independent modules (MMU, MPU, etc.) to use and extend
them.

Signed-off-by: Cupertino Miranda 
---
 target/arc/cache.c | 180 
 target/arc/cache.h |  42 +++
 target/arc/regs-detail.def | 542 +
 target/arc/regs.c  | 139 ++
 target/arc/regs.def| 399 +++
 target/arc/regs.h  | 118 
 6 files changed, 1420 insertions(+)
 create mode 100644 target/arc/cache.c
 create mode 100644 target/arc/cache.h
 create mode 100644 target/arc/regs-detail.def
 create mode 100644 target/arc/regs.c
 create mode 100644 target/arc/regs.def
 create mode 100644 target/arc/regs.h

diff --git a/target/arc/cache.c b/target/arc/cache.c
new file mode 100644
index 00..fe0921823b
--- /dev/null
+++ b/target/arc/cache.c
@@ -0,0 +1,180 @@
+/*
+ * QEMU ARC CPU
+ *
+ * Copyright (c) 2019 Synopsys, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "hw/hw.h"
+#include "cpu.h"
+#include "target/arc/regs.h"
+#include "target/arc/cache.h"
+
+void arc_cache_aux_set(const struct arc_aux_reg_detail *aux_reg_detail,
+   uint32_t val, void *data)
+{
+
+CPUARCState *env = (CPUARCState *) data;
+struct arc_cache *cache = &env->cache;
+
+switch (aux_reg_detail->id) {
+case AUX_ID_ic_ivic:
+case AUX_ID_ic_ivil:
+case AUX_ID_dc_ivdc:
+case AUX_ID_dc_ivdl:
+case AUX_ID_dc_flsh:
+case AUX_ID_dc_fldl:
+case AUX_ID_dc_startr:
+   /* Do nothing as we don't simulate cache memories */
+   break;
+
+case AUX_ID_ic_ctrl:
+cache->ic_disabled = val & 1;
+break;
+
+case AUX_ID_ic_ivir:
+cache->ic_ivir = val & 0xff00;
+break;
+
+case AUX_ID_ic_endr:
+cache->ic_endr = val & 0xff00;
+break;
+
+case AUX_ID_ic_ptag:
+cache->ic_ptag = val;
+break;
+
+case AUX_ID_ic_ptag_hi:
+cache->ic_ptag_hi = val & 0xff;
+break;
+
+/*
+ * Description of the register content in order:
+ *   DC - Disable Cache: Enables/Disables the cache: 0 - Enabled, 1 - Disabled
+ *   IM - Invalidate Mode: Selects the invalidate type
+ */
+case AUX_ID_dc_ctrl:
+cache->dc_disabled = val & 1; /* DC */
+cache->dc_inv_mode = (val >> 6) & 1; /* IM */
+break;
+
+case AUX_ID_dc_endr:
+cache->dc_endr = val & 0xff00;
+break;
+
+case AUX_ID_dc_ptag_hi:
+cache->dc_ptag_hi = val & 0xff;
+break;
+
+default:
+hw_error("%s@%d: Attempt to write read-only register 0x%02x!\n",
+ __func__, __LINE__, (unsigned int)aux_reg_detail->id);
+break;
+}
+
+return;
+}
+
+uint32_t arc_cache_aux_get(const struct arc_aux_reg_detail *aux_reg_detail,
+   void *data)
+{
+CPUARCState *env = (CPUARCState *) data;
+struct arc_cache *cache = &env->cache;
+uint32_t reg = 0;
+
+switch (aux_reg_detail->id) {
+/*
+ * Description of the register content in order.
+ * Layout:   -DFF  
+ *   D - indicates that IC is disabled on reset
+ *   FL - Feature level: 10b - line lock, invalidate, advanced debug features
+ *   BSize - indicates the cache block size in bytes: 0011b - 64 bytes
+ *   Cache capacity: 0111b - 64 Kbytes
+ *   Cache Associativiy: 0010b - Four-way set associative
+ *   Version number: 4 - ARCv2
+ */
+case AUX_ID_i_cache_build:
+reg = (0 << 22) | /* D */
+  (2 << 20) | /* FL */
+  (3 << 16) | /* BBSixe*/
+  (7 << 12) | /* Cache capacity */
+  (2 << 8)  | /* Cache Associativiy */
+  (4 << 0);   /* Version Number */
+break;
+
+case AUX_ID_ic_ctrl:
+reg = cache->ic_disabled & 1;
+break;
+
+case AUX_ID_ic_ivir:
+reg = cache->ic_ivir;
+break;
+
+case AUX_ID_ic_endr:
+reg = cache->ic_endr;
+break;
+
+case AUX_ID_ic_ptag:
+reg = cache->ic_ptag;
+break;
+
+case AUX_ID_ic_ptag_hi:
+reg = cache->ic_ptag_hi;
+break;
+
+/*
+ * Description of the register content in order:
+ *   FL - Feature level: 10b - line lock, invalidate, advanced debug features
+ *   BSize - indicates

[PATCH 02/14] arc: Decoder code

2020-09-30 Thread cupertinomiranda 
From: Claudiu Zissulescu 

The decoder and the disassembler inspired by ARC GNU binutils.

Signed-off-by: Claudiu Zissulescu 
---
 disas/arc.c |  460 ++
 target/arc/decoder.c| 1276 +++
 target/arc/decoder.h|  350 +++
 target/arc/flags.def|   85 +++
 target/arc/operands.def |  123 
 5 files changed, 2294 insertions(+)
 create mode 100644 disas/arc.c
 create mode 100644 target/arc/decoder.c
 create mode 100644 target/arc/decoder.h
 create mode 100644 target/arc/flags.def
 create mode 100644 target/arc/operands.def

diff --git a/disas/arc.c b/disas/arc.c
new file mode 100644
index 00..1041b5a5b5
--- /dev/null
+++ b/disas/arc.c
@@ -0,0 +1,460 @@
+/*
+ * Disassembler code for ARC.
+ * Copyright 2020 Free Software Foundation, Inc.
+ * Written by Claudiu Zissulescu.
+ *
+ * QEMU ARCv2 Disassembler.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2, or (at your option) any later
+ * version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "disas/dis-asm.h"
+#include "target/arc/arc-common.h"
+#include "target/arc/decoder.h"
+#include "target/arc/regs.h"
+
+/* Register names. */
+
+static const char * const regnames[64] = {
+"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
+"r24", "r25", "r26", "fp", "sp", "ilink", "r30", "blink",
+
+"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
+"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
+"r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
+"r56", "r57", "r58", "r59", "lp_count", "rezerved", "LIMM", "pcl"
+};
+
+#define ARRANGE_ENDIAN(info, buf)   \
+(info->endian == BFD_ENDIAN_LITTLE ? bfd_getm32(bfd_getl32(buf))\
+ : bfd_getb32(buf))
+
+/*
+ * Helper function to convert middle-endian data to something more
+ * meaningful.
+ */
+
+static bfd_vma bfd_getm32(unsigned int data)
+{
+bfd_vma value = 0;
+
+value  = (data & 0x) << 16;
+value |= (data & 0x) >> 16;
+return value;
+}
+
+/* Helper for printing instruction flags. */
+
+static bfd_boolean special_flag_p(const char *opname, const char *flgname)
+{
+const struct arc_flag_special *flg_spec;
+unsigned i, j, flgidx;
+
+for (i = 0; i < arc_num_flag_special; ++i) {
+flg_spec = &arc_flag_special_cases[i];
+
+if (strcmp(opname, flg_spec->name) != 0) {
+continue;
+}
+
+/* Found potential special case instruction. */
+for (j = 0; ; ++j) {
+flgidx = flg_spec->flags[j];
+if (flgidx == 0) {
+break; /* End of the array. */
+}
+
+if (strcmp(flgname, arc_flag_operands[flgidx].name) == 0) {
+return TRUE;
+}
+}
+}
+return FALSE;
+}
+
+/* Print instruction flags. */
+
+static void print_flags(const struct arc_opcode *opcode,
+uint64_t insn,
+struct disassemble_info *info)
+{
+const unsigned char *flgidx;
+unsigned int value;
+
+/* Now extract and print the flags. */
+for (flgidx = opcode->flags; *flgidx; flgidx++) {
+/* Get a valid flag class. */
+const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
+const unsigned *flgopridx;
+
+/* Check first the extensions. Not supported yet. */
+if (cl_flags->flag_class & F_CLASS_EXTEND) {
+value = insn & 0x1F;
+}
+
+for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx) {
+const struct arc_flag_operand *flg_operand =
+&arc_flag_operands[*flgopridx];
+
+/* Implicit flags are only used for the insn decoder. */
+if (cl_flags->flag_class & F_CLASS_IMPLICIT) {
+continue;
+}
+
+if (!flg_operand->favail) {
+continue;
+}
+
+value = (insn >> flg_operand->shift) &
+((1 << flg_operand->bits) - 1);
+if (value == flg_operand->code) {
+/* FIXME!: print correctly nt/t flag. */
+if (!special_flag_p(opcode->name, flg_operand->name)) {
+(*info->fprintf_func)(info->stream, ".");
+}
+

[PATCH 01/14] arc: Add initial core cpu files

2020-09-30 Thread cupertinomiranda 
From: Cupertino Miranda 

Signed-off-by: Cupertino Miranda 
---
 target/arc/Makefile.objs |  34 +++
 target/arc/arc-common.h  |  55 
 target/arc/cpu-param.h   |  20 ++
 target/arc/cpu-qom.h |  53 
 target/arc/cpu.c | 468 ++
 target/arc/cpu.h | 532 +++
 target/arc/internals.h   |  37 +++
 target/arc/meson.build   |  20 ++
 8 files changed, 1219 insertions(+)
 create mode 100644 target/arc/Makefile.objs
 create mode 100644 target/arc/arc-common.h
 create mode 100644 target/arc/cpu-param.h
 create mode 100644 target/arc/cpu-qom.h
 create mode 100644 target/arc/cpu.c
 create mode 100644 target/arc/cpu.h
 create mode 100644 target/arc/internals.h
 create mode 100644 target/arc/meson.build

diff --git a/target/arc/Makefile.objs b/target/arc/Makefile.objs
new file mode 100644
index 00..7b2afd08e4
--- /dev/null
+++ b/target/arc/Makefile.objs
@@ -0,0 +1,34 @@
+#
+#  QEMU ARC CPU
+#
+#  Copyright (c) 2020
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+#  Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, see
+#  
+#
+
+obj-y   += translate.o
+obj-y   += helper.o
+obj-y   += cpu.o
+obj-y   += op_helper.o
+obj-y   += gdbstub.o
+obj-y   += decoder.o
+obj-y   += regs.o
+obj-y   += semfunc.o
+obj-y   += semfunc-helper.o
+obj-y   += mmu.o
+obj-y   += mpu.o
+obj-y   += timer.o
+obj-y   += irq.o
+obj-y   += cache.o
diff --git a/target/arc/arc-common.h b/target/arc/arc-common.h
new file mode 100644
index 00..8013e1d2ed
--- /dev/null
+++ b/target/arc/arc-common.h
@@ -0,0 +1,55 @@
+/*
+ *  Common header file to be used by cpu and disassembler.
+ *  Copyright (C) 2017 Free Software Foundation, Inc.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with GAS or GDB; see the file COPYING3. If not, write to
+ *  the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ *  MA 02110-1301, USA.
+ */
+
+#ifndef ARC_COMMON_H
+#define ARC_COMMON_H
+
+#include "qemu/osdep.h"
+
+/* CPU combi. */
+#define ARC_OPCODE_ARCALL  (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700   \
+| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
+#define ARC_OPCODE_ARCFPX  (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
+#define ARC_OPCODE_ARCV1   (ARC_OPCODE_ARC700 | ARC_OPCODE_ARC600)
+#define ARC_OPCODE_ARCV2   (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
+#define ARC_OPCODE_ARCMPY6E  (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCV2)
+
+
+enum arc_cpu_family {
+  ARC_OPCODE_NONE= 0,
+  ARC_OPCODE_DEFAULT = 1 << 0,
+  ARC_OPCODE_ARC600  = 1 << 1,
+  ARC_OPCODE_ARC700  = 1 << 2,
+  ARC_OPCODE_ARCv2EM = 1 << 3,
+  ARC_OPCODE_ARCv2HS = 1 << 4
+};
+
+typedef struct {
+uint32_t value;
+uint32_t type;
+} operand_t;
+
+typedef struct {
+uint32_t class;
+uint32_t limm;
+uint8_t len;
+bool limm_p;
+operand_t operands[3];
+uint8_t n_ops;
+uint8_t cc;
+uint8_t aa;
+uint8_t zz;
+bool d;
+bool f;
+bool di;
+bool x;
+} insn_t;
+
+#endif
diff --git a/target/arc/cpu-param.h b/target/arc/cpu-param.h
new file mode 100644
index 00..a38548d3db
--- /dev/null
+++ b/target/arc/cpu-param.h
@@ -0,0 +1,20 @@
+/*
+ * ARC cpu parameters for qemu.
+ *
+ * Copyright (c) 2019 Shahab Vahedi
+ * SPDX-License-Identifier: LGPL-2.0+
+ */
+
+#ifndef ARC_CPU_PARAM_H
+#define ARC_CPU_PARAM_H 1
+
+#define TARGET_LONG_BITS32
+#define TARGET_PAGE_BITS13
+#define TARGET_PHYS_ADDR_SPACE_BITS 32
+#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#define NB_MMU_MODES2
+
+#endif
+
+/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-*/
+/* vim: set ts=4 sw=4 et: */
diff --git a/target/arc/cpu-qom.h b/target/arc/cpu-qom.h
new file mode 100644
index 00..413b693558
--- /dev/null
+++ b/target/arc/cpu-qom.h
@@ -0,0 +1,53 @@
+/*
+ * QEMU ARC CPU
+ *
+ * Copyright (c) 2016 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

[PATCH 10/14] arc: Add memory protection unit (MPU) support

2020-09-30 Thread cupertinomiranda 
From: Shahab Vahedi 

Add memory implementation for Synopsys MPU unit version 3.
Synopsys MPU allows to create memory regions against unauthorized
execution/read/writes accesses.

Signed-off-by: Shahab Vahedi 
---
 target/arc/mpu.c | 653 +++
 target/arc/mpu.h | 140 ++
 2 files changed, 793 insertions(+)
 create mode 100644 target/arc/mpu.c
 create mode 100644 target/arc/mpu.h

diff --git a/target/arc/mpu.c b/target/arc/mpu.c
new file mode 100644
index 00..60f56100d0
--- /dev/null
+++ b/target/arc/mpu.c
@@ -0,0 +1,653 @@
+/*
+ * QEMU ARC CPU
+ *
+ * Copyright (c) 2019 Shahab Vahedi (Synopsys)
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+
+#include "mpu.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "mmu.h"
+
+/*
+ * In case of exception, this signals the effective region
+ * was the default one
+ */
+#define MPU_DEFAULT_REGION_NR 0xff
+
+/* Defines used by in-house functions */
+#define MPU_EN_EN_BIT   30
+#define MPU_EN_KR_BIT8
+#define MPU_EN_KW_BIT7
+#define MPU_EN_KE_BIT6
+#define MPU_EN_UR_BIT5
+#define MPU_EN_UW_BIT4
+#define MPU_EN_UE_BIT3
+
+#define MPU_ECR_EC_CODE_BIT 16
+#define MPU_ECR_VT_BIT   8
+
+#define MPU_BASE_ADDR_MASK  0xffe0  /* ignore least 5 bits */
+#define MPU_BASE_VALID_MASK 0x0001  /* bit #0 */
+
+/*
+ * Given a number of bits as width, calc the mask to
+ * "and" with. e.g.: 3 bits --> 8 - 1 --> 7 (111b)
+ */
+#define MPU_WIDTH_TO_MASK(w) ((1 << (w)) - 1)
+#define MPU_PERMS_REG_LOWER_SIZE_WIDTH  2
+#define MPU_PERMS_REG_HIGHER_SIZE_WIDTH 3
+#define MPU_PERMS_REG_HIGHER_SIZE_POS   9
+
+/*
+ * After knowing the operating mode (user/kernel),
+ * this struct represents the effective permissions.
+ */
+typedef struct MPUEffectPerm {
+bool read;
+bool write;
+bool exec;
+} MPUEffectPerm;
+
+/* Packer and unpackers (local to this translation unit) */
+static inline uint32_t pack_enable(const bool ena)
+{
+return ena << MPU_EN_EN_BIT;
+}
+
+static inline void unpack_enable(bool *enabled, uint32_t value)
+{
+*enabled = (value >> MPU_EN_EN_BIT) & 1;
+}
+
+static inline uint32_t pack_permissions(const MPUPermissions *perms)
+{
+return perms->KR << MPU_EN_KR_BIT |
+   perms->KW << MPU_EN_KW_BIT |
+   perms->KE << MPU_EN_KE_BIT |
+   perms->UR << MPU_EN_UR_BIT |
+   perms->UW << MPU_EN_UW_BIT |
+   perms->UE << MPU_EN_UE_BIT;
+}
+
+static inline void unpack_permissions(MPUPermissions *perms, uint32_t value)
+{
+perms->KR = (value >> MPU_EN_KR_BIT) & 1;
+perms->KW = (value >> MPU_EN_KW_BIT) & 1;
+perms->KE = (value >> MPU_EN_KE_BIT) & 1;
+perms->UR = (value >> MPU_EN_UR_BIT) & 1;
+perms->UW = (value >> MPU_EN_UW_BIT) & 1;
+perms->UE = (value >> MPU_EN_UE_BIT) & 1;
+}
+
+static inline uint32_t pack_enable_reg(const MPUEnableReg *mpuen)
+{
+return pack_enable(mpuen->enabled) |
+   pack_permissions(&mpuen->permission);
+}
+
+static inline void unpack_enable_reg(MPUEnableReg *mpuen, uint32_t value)
+{
+unpack_enable(&mpuen->enabled, value);
+unpack_permissions(&mpuen->permission, value);
+}
+
+static inline uint32_t pack_ecr(const MPUECR *mpuecr)
+{
+return ARC_MPU_ECR_VEC_NUM << MPU_ECR_EC_CODE_BIT |
+   (mpuecr->violation & 3) << MPU_ECR_VT_BIT  |
+   mpuecr->region;
+}
+
+static inline uint32_t pack_base_reg(const MPUBaseReg *mpurdb)
+{
+return mpurdb->addr | mpurdb->valid;
+}
+
+static inline void unpack_base_reg(MPUBaseReg *mpurdb, uint32_t value)
+{
+mpurdb->addr  = value & MPU_BASE_ADDR_MASK;
+mpurdb->valid = value & MPU_BASE_VALID_MASK;
+}
+
+
+/*
+ * Break the "size" field into "higher" and "lower" parts
+ * e.g.: a b c d e --> a b c . . . d e
+ * higher lower
+ */
+static uint32_t pack_region_size_bits(uint8_t size_bits)
+{
+uint32_t lower =
+size_bits & MPU_WIDTH_TO_MASK(MPU_PERMS_REG_LOWER_SIZE_WIDTH);
+uint32_t higher = size_bits >> MPU_PERMS_REG_LOWER_SIZE_WIDTH;
+higher &= MPU_WIDTH_TO_MASK(MPU_PERMS_REG_HIGHER_SIZE_WIDTH);
+return (higher << MPU_PERMS_REG_HIGHER_SIZE_POS) | lower;
+}
+
+/*
+ * Put the higher and lower parts of "size" field together
+ * e.g.: a b c . . . d e ---> abcde
+ *   higher lower
+ */
+static void unpack_region_size_bits(

[PATCH 08/14] arc: Add IRQ and timer subsystem support

2020-09-30 Thread cupertinomiranda 
From: Claudiu Zissulescu 

Signed-off-by: Claudiu Zissulescu 
---
 target/arc/irq.c   | 658 +
 target/arc/irq.h   |  37 +++
 target/arc/timer.c | 456 +++
 target/arc/timer.h |  32 +++
 4 files changed, 1183 insertions(+)
 create mode 100644 target/arc/irq.c
 create mode 100644 target/arc/irq.h
 create mode 100644 target/arc/timer.c
 create mode 100644 target/arc/timer.h

diff --git a/target/arc/irq.c b/target/arc/irq.c
new file mode 100644
index 00..ebbb2e1442
--- /dev/null
+++ b/target/arc/irq.c
@@ -0,0 +1,658 @@
+/*
+ * QEMU ARC CPU - IRQ subsystem
+ *
+ * Copyright (c) 2020
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * http://www.gnu.org/licenses/lgpl-2.1.html
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+#include "hw/irq.h"
+#include "cpu.h"
+#include "qemu/main-loop.h"
+#include "irq.h"
+#include "exec/cpu_ldst.h"
+#include "translate.h"
+#include "qemu/host-utils.h"
+
+/* Static functions and variables. */
+
+static uint32_t save_reg_pair_32[] = {
+0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
+};
+
+static uint32_t save_reg_pair_16[] = {
+0, 2, 10, 12, 14, 26, 28, 30
+};
+
+bool enabled_interrupts = false;
+
+/* Given a struct STATUS_R, pack it to 32 bit. */
+uint32_t pack_status32(status_t *status_r)
+{
+uint32_t res = 0x;
+
+res |= (status_r->IEf & 0x1) << 31;
+res |= (status_r->USf & 0x1) << 20;
+res |= (status_r->ADf & 0x1) << 19;
+res |= (status_r->RBf & 0x7) << 16;
+res |= (status_r->ESf & 0x1) << 15;
+res |= (status_r->SCf & 0x1) << 14;
+res |= (status_r->DZf & 0x1) << 13;
+res |= (status_r->Lf  & 0x1) << 12;
+res |= (status_r->Zf  & 0x1) << 11;
+res |= (status_r->Nf  & 0x1) << 10;
+res |= (status_r->Cf  & 0x1) << 9;
+res |= (status_r->Vf  & 0x1) << 8;
+res |= (status_r->Uf  & 0x1) << 7;
+res |= (status_r->DEf & 0x1) << 6;
+res |= (status_r->AEf & 0x1) << 5;
+res |= (status_r->Ef  & 0xf) << 1;
+
+return res;
+}
+
+/* Reverse of the above function. */
+void unpack_status32(status_t *status_r, uint32_t value)
+{
+status_r->IEf = ((value >> 31) & 0x1);
+status_r->USf = ((value >> 20) & 0x1);
+status_r->ADf = ((value >> 19) & 0x1);
+status_r->RBf = ((value >> 16) & 0x7);
+status_r->ESf = ((value >> 15) & 0x1);
+status_r->SCf = ((value >> 14) & 0x1);
+status_r->DZf = ((value >> 13) & 0x1);
+status_r->Lf  = ((value >> 12) & 0x1);
+status_r->Zf  = ((value >> 11) & 0x1);
+status_r->Nf  = ((value >> 10) & 0x1);
+status_r->Cf  = ((value >> 9)  & 0x1);
+status_r->Vf  = ((value >> 8)  & 0x1);
+status_r->Uf  = ((value >> 7)  & 0x1);
+status_r->DEf = ((value >> 6)  & 0x1);
+status_r->AEf = ((value >> 5)  & 0x1);
+status_r->Ef  = ((value >> 1)  & 0xf);
+}
+
+/* Return from fast interrupts. */
+
+static void arc_rtie_firq(CPUARCState *env)
+{
+assert(env->stat.AEf == 0);
+
+qemu_log_mask(CPU_LOG_INT, "[IRQ] exit firq: U=%d, AUX_IRQ_ACT.U=%d\n",
+  env->stat.Uf, env->aux_irq_act >> 31);
+
+/* Clear currently active interrupt. */
+env->aux_irq_act &= 0xfffe;
+
+/* Check if we need to restore userland SP. */
+if (((env->aux_irq_act & 0x) == 0) && (env->aux_irq_act & 0x8000)) 
{
+switchSP(env);
+}
+
+env->stat = env->stat_l1; /* FIXME use status32_p0 reg. */
+env->aux_irq_act &= ~(env->stat.Uf << 31); /* Keep U-bit in sync. */
+
+/* FIXME! fix current reg bank if RB bit is changed. */
+
+CPU_PCL(env) = CPU_ILINK(env);
+env->pc = CPU_ILINK(env);
+}
+
+/* Implements a pop operation from the CPU stack. */
+static uint32_t irq_pop(CPUARCState *env, const char *str)
+{
+uint32_t rval;
+rval = cpu_ldl_data(env, CPU_SP(env));
+
+qemu_log_mask(CPU_LOG_INT, "[IRQ] Pop [SP:0x%08x] => 0x%08x (%s)\n",
+  CPU_SP(env), rval, str ? str : "unk");
+CPU_SP(env) += 4;
+return rval;
+}
+
+/* Return from regular interrupts. */
+
+static void arc_rtie_irq(CPUARCState *env)
+{
+uint32_t tmp;
+ARCCPU *cpu = env_archcpu(env);
+
+assert((env->aux_irq_act & 0x) != 0);
+assert(env->stat.AEf == 0);
+
+/* Clear currently active interrupt. */
+tmp = ctz32(env->aux_irq_act & 0x);
+
+qemu_log_mask(CPU_LOG_INT,
+  "[IR

[PATCH 05/14] arc: TCG instruction generator and hand-definitions

2020-09-30 Thread cupertinomiranda 
From: Shahab Vahedi 

Add the most generic parts of TCG constructions. It contains the basic 
infrastructure
for fundamental ARC features, such as ZOL (zero overhead loops) and delay-slots.
Also includes hand crafted TCG for more intricate instructions, such as vector
instructions.

Signed-off-by: Shahab Vahedi 
---
 target/arc/translate.c | 1344 
 target/arc/translate.h |  202 ++
 2 files changed, 1546 insertions(+)
 create mode 100644 target/arc/translate.c
 create mode 100644 target/arc/translate.h

diff --git a/target/arc/translate.c b/target/arc/translate.c
new file mode 100644
index 00..1d679db943
--- /dev/null
+++ b/target/arc/translate.c
@@ -0,0 +1,1344 @@
+/*
+ *  QEMU ARC CPU
+ * Copyright (C) 2019 Free Software Foundation, Inc.
+
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public License
+ * as published by the Free Software Foundation; either version 2.1 of
+ * the License, or (at your option) any later version.
+
+ * This library is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License
+ * along with GAS or GDB; see the file COPYING3.  If not, write to
+ * the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include "translate.h"
+#include "qemu/qemu-print.h"
+#include "tcg/tcg-op-gvec.h"
+#include "target/arc/semfunc.h"
+#include "target/arc/arc-common.h"
+
+/* Globals */
+TCGvcpu_gp;/*  Global Pointer  */
+TCGvcpu_fp;/*  Frame Pointer   */
+TCGvcpu_sp;/*  Stack Pointer   */
+TCGvcpu_ilink1;/*  Level 1 interrupt link register */
+TCGvcpu_ilink2;/*  Level 2 interrupt link register */
+TCGvcpu_blink; /*  Branch link register*/
+TCGvcpu_acclo; /*  64-bit accumulator register: low*/
+TCGvcpu_acchi; /*  64-bit accumulator register: high   */
+TCGvcpu_limm;  /*  Long immediate data indicator   */
+TCGvcpu_pcl;   /*  Program Counter [31:2], read-only.  */
+
+TCGvcpu_S1f;
+TCGvcpu_S2f;
+TCGvcpu_CSf;
+
+TCGvcpu_Lf;
+TCGvcpu_Zf;
+TCGvcpu_Nf;
+TCGvcpu_Cf;
+TCGvcpu_Vf;
+TCGvcpu_Uf;
+
+TCGvcpu_DEf;
+TCGvcpu_ESf;
+TCGvcpu_AEf;
+TCGvcpu_Hf;
+TCGvcpu_IEf;
+TCGvcpu_Ef;
+
+TCGvcpu_is_delay_slot_instruction;
+
+TCGvcpu_l1_Lf;
+TCGvcpu_l1_Zf;
+TCGvcpu_l1_Nf;
+TCGvcpu_l1_Cf;
+TCGvcpu_l1_Vf;
+TCGvcpu_l1_Uf;
+
+TCGvcpu_l1_DEf;
+TCGvcpu_l1_AEf;
+TCGvcpu_l1_Hf;
+
+TCGvcpu_l2_Lf;
+TCGvcpu_l2_Zf;
+TCGvcpu_l2_Nf;
+TCGvcpu_l2_Cf;
+TCGvcpu_l2_Vf;
+TCGvcpu_l2_Uf;
+
+TCGvcpu_l2_DEf;
+TCGvcpu_l2_AEf;
+TCGvcpu_l2_Hf;
+
+TCGvcpu_er_Lf;
+TCGvcpu_er_Zf;
+TCGvcpu_er_Nf;
+TCGvcpu_er_Cf;
+TCGvcpu_er_Vf;
+TCGvcpu_er_Uf;
+
+TCGvcpu_er_DEf;
+TCGvcpu_er_AEf;
+TCGvcpu_er_Hf;
+
+TCGvcpu_eret;
+TCGvcpu_erbta;
+TCGvcpu_ecr;
+TCGvcpu_efa;
+
+TCGvcpu_bta;
+TCGvcpu_bta_l1;
+TCGvcpu_bta_l2;
+
+TCGvcpu_pc;
+TCGvcpu_lpc;
+/* replaced by AUX_REG array */
+TCGvcpu_lps;
+TCGvcpu_lpe;
+
+TCGvcpu_r[64];
+
+TCGvcpu_intvec;
+
+TCGvcpu_debug_LD;
+TCGvcpu_debug_SH;
+TCGvcpu_debug_BH;
+TCGvcpu_debug_UB;
+TCGvcpu_debug_ZZ;
+TCGvcpu_debug_RA;
+TCGvcpu_debug_IS;
+TCGvcpu_debug_FH;
+TCGvcpu_debug_SS;
+
+TCGvcpu_lock_lf_var;
+
+/* NOTE: Pseudo register required for comparison with lp_end */
+TCGvcpu_npc;
+
+/* Macros */
+
+#include "exec/gen-icount.h"
+#define REG(x)  (cpu_r[x])
+
+/* macro used to fix middle-endianess. */
+#define ARRANGE_ENDIAN(endianess, buf)  \
+((endianess) ? arc_getm32(buf) : bswap32(buf))
+
+/*
+ * The macro to add boiler plate code for conditional execution.
+ * It will add tcg_gen codes only if there is a condition to
+ * be checked (ctx->insn.cc != 0). This macro assumes that there
+ * is a "ctx" variable of type "DisasCtxt *" in context. Remember
+ * to pair it with CC_EPILOGUE macro.
+ */
+#define CC_PROLOGUE   \
+  TCGv cc = tcg_temp_local_new(); \
+  TCGLabel *done = gen_new_label();   \
+  do {\
+if (ctx->insn.cc) {   \
+arc_gen_verifyCCFlag(ctx, cc);\
+tcg_gen_brcondi_tl(TCG_COND_NE, cc, 1, done); \
+} \
+  } while (0)
+
+/*
+ * The finishing counter part of CC_PROLUGE. This is supposed
+ * to be put at the e

[PATCH 04/14] arc: TCG and decoder glue code and helpers

2020-09-30 Thread cupertinomiranda 
From: Cupertino Miranda 

Signed-off-by: Cupertino Miranda 
---
 target/arc/extra_mapping.def   |  40 ++
 target/arc/helper.c| 293 +
 target/arc/helper.h|  46 ++
 target/arc/op_helper.c | 749 +
 target/arc/semfunc_mapping.def | 329 +++
 5 files changed, 1457 insertions(+)
 create mode 100644 target/arc/extra_mapping.def
 create mode 100644 target/arc/helper.c
 create mode 100644 target/arc/helper.h
 create mode 100644 target/arc/op_helper.c
 create mode 100644 target/arc/semfunc_mapping.def

diff --git a/target/arc/extra_mapping.def b/target/arc/extra_mapping.def
new file mode 100644
index 00..6bc36d8d46
--- /dev/null
+++ b/target/arc/extra_mapping.def
@@ -0,0 +1,40 @@
+/*
+ * QEMU ARC EXTRA MAPPING
+ *
+ * Copyright (c) 2020
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * http://www.gnu.org/licenses/lgpl-2.1.html
+ */
+
+SEMANTIC_FUNCTION(SWI, 1)
+SEMANTIC_FUNCTION(SWI, 1)
+SEMANTIC_FUNCTION(UNIMP, 0)
+SEMANTIC_FUNCTION(RTIE, 0)
+SEMANTIC_FUNCTION(SLEEP, 1)
+
+MAPPING(swi, SWI, 0)
+CONSTANT(SWI, swi_s, 0, 0)
+MAPPING(swi_s, SWI, 1, 0)
+MAPPING(trap_s, TRAP, 1, 0)
+MAPPING(rtie, RTIE, 0)
+MAPPING(sleep, SLEEP, 1, 0)
+MAPPING(vadd2, VADD, 3, 0, 1, 2)
+MAPPING(vadd2h, VADD, 3, 0, 1, 2)
+MAPPING(vadd4h, VADD, 3, 0, 1, 2)
+MAPPING(vsub2, VSUB, 3, 0, 1, 2)
+MAPPING(vsub2h, VSUB, 3, 0, 1, 2)
+MAPPING(vsub4h, VSUB, 3, 0, 1, 2)
+MAPPING(mpyd, MPYD, 3, 0, 1, 2)
+MAPPING(mpydu, MPYD, 3, 0, 1, 2)
diff --git a/target/arc/helper.c b/target/arc/helper.c
new file mode 100644
index 00..cbc072e66b
--- /dev/null
+++ b/target/arc/helper.c
@@ -0,0 +1,293 @@
+/*
+ * QEMU ARC CPU
+ *
+ * Copyright (c) 2019
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * http://www.gnu.org/licenses/lgpl-2.1.html
+ */
+
+#include "qemu/osdep.h"
+
+#include "cpu.h"
+#include "hw/irq.h"
+#include "include/hw/sysbus.h"
+#include "include/sysemu/sysemu.h"
+#include "qemu/qemu-print.h"
+#include "exec/exec-all.h"
+#include "exec/cpu_ldst.h"
+#include "qemu/host-utils.h"
+#include "exec/helper-proto.h"
+#include "irq.h"
+
+#if defined(CONFIG_USER_ONLY)
+
+void arc_cpu_do_interrupt(CPUState *cs)
+{
+ARCCPU *cpu = ARC_CPU(cs);
+CPUARCState *env = &cpu->env;
+
+cs->exception_index = -1;
+CPU_ILINK(env) = env->pc;
+}
+
+#else /* !CONFIG_USER_ONLY */
+
+void arc_cpu_do_interrupt(CPUState *cs)
+{
+ARCCPU  *cpu= ARC_CPU(cs);
+CPUARCState *env= &cpu->env;
+uint32_t offset = 0;
+uint32_t vectno;
+const char  *name;
+
+/*
+ * NOTE: Special LP_END exception. Immediatelly return code execution to
+ * lp_start.
+ * Now also used for delayslot MissI cases.
+ * This special exception should not execute any of the exception
+ * handling code. Instead it returns immediately after setting PC to the
+ * address passed as exception parameter.
+ */
+if (cs->exception_index == EXCP_LPEND_REACHED
+|| cs->exception_index == EXCP_FAKE) {
+env->pc = env->param;
+CPU_PCL(env) = env->pc & 0xfffe;
+return;
+}
+
+/* If we take an exception within an exception => fatal Machine Check. */
+if (env->stat.AEf == 1) {
+cs->exception_index = EXCP_MACHINE_CHECK;
+env->causecode = 0;
+env->param = 0;
+env->mmu.enabled = false; /* no more MMU */
+env->mpu.enabled = false; /* no more MPU */
+}
+vectno = cs->exception_index & 0x0F;
+offset = vectno << 2;
+
+/* Generic computation for exceptions. */
+switch (cs->exception_index) {
+case EXCP_RESET:
+name = "Reset";
+break;
+case EXCP_MEMORY_ERROR:
+name = "Memory Error";
+break;
+case EXCP_INST_ERROR:
+

[PATCH 13/14] arc: Add support for ARCv2

2020-09-30 Thread cupertinomiranda 
From: Shahab Vahedi 

Add remaining bits of the Synopsys ARCv2 (EM/HS) support into QEMU,
configure bits, arch_init and configuration files for softmmu (hardware
emulation).

Signed-off-by: Shahab Vahedi 
---
 configure   |  5 +
 default-configs/arc-softmmu.mak |  5 +
 disas.c |  2 ++
 disas/meson.build   |  1 +
 hw/meson.build  |  1 +
 include/disas/dis-asm.h | 10 +-
 include/elf.h   |  3 +++
 include/exec/poison.h   |  2 ++
 include/sysemu/arch_init.h  |  1 +
 meson.build |  3 ++-
 softmmu/arch_init.c |  2 ++
 target/meson.build  |  1 +
 12 files changed, 34 insertions(+), 2 deletions(-)
 create mode 100644 default-configs/arc-softmmu.mak

diff --git a/configure b/configure
index ecc8e90e8b..65862d8371 100755
--- a/configure
+++ b/configure
@@ -7570,6 +7570,9 @@ case "$target_name" in
 mttcg="yes"
 TARGET_SYSTBL_ABI=common
   ;;
+  arc)
+gdb_xml_files="arc-core-v2.xml arc-aux-minimal.xml arc-aux-other.xml"
+  ;;
   arm|armeb)
 TARGET_ARCH=arm
 TARGET_SYSTBL_ABI=common,oabi
@@ -7852,8 +7855,10 @@ DIRS="$DIRS docs docs/interop fsdev scsi"
 DIRS="$DIRS pc-bios/optionrom pc-bios/s390-ccw"
 DIRS="$DIRS roms/seabios"
 DIRS="$DIRS contrib/plugins/"
+#DIRS="$DIRS tests/tcg/arc"
 LINKS="Makefile"
 LINKS="$LINKS tests/tcg/lm32/Makefile"
+#LINKS="$LINKS tests/tcg/arc/Makefile.target"
 LINKS="$LINKS tests/tcg/Makefile.target"
 LINKS="$LINKS pc-bios/optionrom/Makefile"
 LINKS="$LINKS pc-bios/s390-ccw/Makefile"
diff --git a/default-configs/arc-softmmu.mak b/default-configs/arc-softmmu.mak
new file mode 100644
index 00..4300a90c93
--- /dev/null
+++ b/default-configs/arc-softmmu.mak
@@ -0,0 +1,5 @@
+# Default configuration for arc-softmmu
+
+CONFIG_VIRTIO_MMIO=y
+CONFIG_SERIAL=y
+CONFIG_OPENCORES_ETH=y
diff --git a/disas.c b/disas.c
index c1397d3933..41aabbca63 100644
--- a/disas.c
+++ b/disas.c
@@ -671,6 +671,8 @@ void disas(FILE *out, void *code, unsigned long size, const 
char *note)
 print_insn = print_insn_s390;
 #elif defined(__hppa__)
 print_insn = print_insn_hppa;
+#elif defined(__arc__)
+print_insn = print_insn_arc;
 #endif
 
 if (s.info.cap_arch >= 0 && cap_disas_host(&s.info, code, size, note)) {
diff --git a/disas/meson.build b/disas/meson.build
index bde8280c73..47ff300d0f 100644
--- a/disas/meson.build
+++ b/disas/meson.build
@@ -4,6 +4,7 @@ subdir('libvixl')
 common_ss.add(when: 'CONFIG_ALPHA_DIS', if_true: files('alpha.c'))
 common_ss.add(when: 'CONFIG_ARM_A64_DIS', if_true: files('arm-a64.cc'))
 common_ss.add_all(when: 'CONFIG_ARM_A64_DIS', if_true: libvixl_ss)
+common_ss.add(when: 'CONFIG_ARC_DIS', if_true: files('arc.c'))
 common_ss.add(when: 'CONFIG_ARM_DIS', if_true: files('arm.c'))
 common_ss.add(when: 'CONFIG_CRIS_DIS', if_true: files('cris.c'))
 common_ss.add(when: 'CONFIG_HPPA_DIS', if_true: files('hppa.c'))
diff --git a/hw/meson.build b/hw/meson.build
index 010de7219c..e2b14a9ed8 100644
--- a/hw/meson.build
+++ b/hw/meson.build
@@ -43,6 +43,7 @@ subdir('xen')
 subdir('xenpv')
 
 subdir('alpha')
+subdir('arc')
 subdir('arm')
 subdir('avr')
 subdir('cris')
diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h
index 9856bf7921..621164c510 100644
--- a/include/disas/dis-asm.h
+++ b/include/disas/dis-asm.h
@@ -206,7 +206,14 @@ enum bfd_architecture
   bfd_arch_v850,   /* NEC V850 */
 #define bfd_mach_v850  0
   bfd_arch_arc,/* Argonaut RISC Core */
-#define bfd_mach_arc_base 0
+#define bfd_mach_arc_a40
+#define bfd_mach_arc_a51
+#define bfd_mach_arc_arc6002
+#define bfd_mach_arc_arc6014
+#define bfd_mach_arc_arc7003
+#define bfd_mach_arc_arcv2 5
+#define bfd_mach_arc_arcv2em   6
+#define bfd_mach_arc_arcv2hs   7
   bfd_arch_m32r,   /* Mitsubishi M32R/D */
 #define bfd_mach_m32r  0  /* backwards compatibility */
   bfd_arch_mn10200,/* Matsushita MN10200 */
@@ -460,6 +467,7 @@ int print_insn_xtensa   (bfd_vma, 
disassemble_info*);
 int print_insn_riscv32  (bfd_vma, disassemble_info*);
 int print_insn_riscv64  (bfd_vma, disassemble_info*);
 int print_insn_rx(bfd_vma, disassemble_info *);
+int print_insn_arc  (bfd_vma, disassemble_info*);
 
 #if 0
 /* Fetch the disassembler for a given BFD, if that support is available.  */
diff --git a/include/elf.h b/include/elf.h
index c117a4d1ab..5f6165da37 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -201,6 +201,9 @@ typedef struct mips_elf_abiflags_v0 {
 
 #define EM_TILEGX   191 /* TILE-Gx */
 
+#define EM_ARC_COMPACT  93  /* Synopsys ARCompact */
+#define EM_ARC_COMPACT2 195 /* Synopsys ARCompact V2 */
+
 #define EM_MOXIE   223 /* Moxie processor family */
 #define EM_MOXIE_OLD   0xFEED
 
diff --git a/include/exec/poison.h b/include/exec/poison.h
index 7b9ac361dc..635ccc66a1 100644
--- a/include/exec/poison.h
+++ b/include

[PATCH 09/14] arc: Add memory management unit (MMU) support

2020-09-30 Thread cupertinomiranda 
From: Cupertino Miranda 

Add Synopsys ARC MMU version 4 support. The implementation is
restricted to 8K page size support.

Signed-off-by: Cupertino Miranda 
---
 target/arc/mmu.c | 775 +++
 target/arc/mmu.h | 165 ++
 2 files changed, 940 insertions(+)
 create mode 100644 target/arc/mmu.c
 create mode 100644 target/arc/mmu.h

diff --git a/target/arc/mmu.c b/target/arc/mmu.c
new file mode 100644
index 00..77d0a2af97
--- /dev/null
+++ b/target/arc/mmu.c
@@ -0,0 +1,775 @@
+/*
+ * QEMU ARC CPU
+ *
+ * Copyright (c) 2018 Cupertino Miranda (cmira...@synopsys.com)
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * http://www.gnu.org/licenses/lgpl-2.1.html
+ */
+
+#include "mmu.h"
+#include "target/arc/regs.h"
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+
+
+uint32_t
+arc_mmu_aux_get(const struct arc_aux_reg_detail *aux_reg_detail, void *data)
+{
+CPUARCState *env = (CPUARCState *) data;
+struct arc_mmu *mmu = &env->mmu;
+uint32_t reg = 0;
+
+switch (aux_reg_detail->id) {
+case AUX_ID_mmu_build:
+/*
+ * For now hardcode the TLB geometry and canonical page sizes
+ * MMUv4: 2M Super Page, 8k Page, 4 way set associative,
+ *1K entries (256x4), 4 uITLB, 8 uDTLB
+ */
+reg = 0x04e21a4a;
+break;
+case AUX_ID_tlbindex:
+reg = mmu->tlbindex;
+break;
+case AUX_ID_tlbpd0:
+reg = mmu->tlbpd0;
+break;
+case AUX_ID_tlbpd1:
+reg = mmu->tlbpd1;
+break;
+case AUX_ID_tlbpd1_hi:
+reg = mmu->tlbpd1_hi;
+break;
+case AUX_ID_scratch_data0:
+reg = mmu->scratch_data0;
+break;
+case AUX_ID_tlbcommand:
+reg = mmu->tlbcmd;
+break;
+case AUX_ID_pid:
+reg = (mmu->enabled << 31) | mmu->pid_asid;
+break;
+case AUX_ID_sasid0:
+reg = mmu->sasid0;
+break;
+case AUX_ID_sasid1:
+reg = mmu->sasid1;
+break;
+default:
+break;
+}
+
+return reg;
+}
+
+void
+arc_mmu_aux_set(const struct arc_aux_reg_detail *aux_reg_detail,
+uint32_t val, void *data)
+{
+CPUARCState *env = (CPUARCState *) data;
+CPUState *cs = env_cpu(env);
+struct arc_mmu *mmu = &env->mmu;
+
+switch (aux_reg_detail->id) {
+/* AUX_ID_tlbcommand is more involved and handled seperately */
+case AUX_ID_tlbindex:
+mmu->tlbindex = val;
+break;
+case AUX_ID_tlbpd0:
+mmu->tlbpd0 = val;
+break;
+case AUX_ID_tlbpd1:
+mmu->tlbpd1 = val;
+break;
+case AUX_ID_tlbpd1_hi:
+mmu->tlbpd1_hi = val;
+break;
+case AUX_ID_scratch_data0:
+mmu->scratch_data0 = val;
+break;
+case AUX_ID_pid:
+qemu_log_mask(CPU_LOG_MMU,
+  "[MMU] Writing PID_ASID with value 0x%08x at 0x%08x\n",
+  val, env->pc);
+mmu->enabled = (val >> 31);
+mmu->pid_asid = val & 0xff;
+tlb_flush(cs);
+break;
+case AUX_ID_sasid0:
+mmu->sasid0 = val;
+break;
+case AUX_ID_sasid1:
+mmu->sasid1 = val;
+break;
+default:
+break;
+}
+}
+
+/* vaddr can't have top bit */
+#define VPN(addr) ((addr) & (PAGE_MASK & (~0x8000)))
+#define PFN(addr) ((addr) & PAGE_MASK)
+
+static void
+arc_mmu_debug_tlb_for_set(CPUARCState *env, int set)
+{
+int j;
+bool set_printed = false;
+
+for (j = 0; j < N_WAYS; j++) {
+struct arc_tlb_e *tlb = &env->mmu.nTLB[set][j];
+
+if ((tlb->pd0 & PD0_V) != 0) {
+if (set_printed == false) {
+printf("set %d\n", set);
+set_printed = true;
+}
+if (set_printed == true) {
+printf(" way %d\n", j);
+}
+printf("  tlppd0: %08x: vaddr=\t%08x %s %s%s asid=%02x\n",
+   (unsigned int) tlb->pd0, (unsigned int) VPN(tlb->pd0),
+   (char *) ((tlb->pd0 & PD0_SZ) != 0 ? "sz1" : "sz0"),
+   (char *) ((tlb->pd0 & PD0_V) != 0 ? "V" : ""),
+   (char *) ((tlb->pd0 & PD0_G) != 0 ? "g" : ""),
+   tlb->pd0 & PD0_ASID);
+
+printf("  tlppd1: %08x: paddr=\t%08x k:%s%s%s u:%s%s%s f:%s\n",
+   (un

[PATCH 12/14] arc: Add Synopsys ARC emulation boards

2020-09-30 Thread cupertinomiranda 
From: Claudiu Zissulescu 

Add the Synopsys ARC boards, arc_sim for testing, sim-hs main emulation
board using standard UART and nsim which includes a Synopsys ARC specific
UART implementation.

Signed-off-by: Claudiu Zissulescu 
---
 hw/arc/Makefile.objs  |  21 +++
 hw/arc/arc_sim.c  | 143 
 hw/arc/arc_uart.c | 267 ++
 hw/arc/board-hsdk.c   | 107 +++
 hw/arc/boot.c |  95 ++
 hw/arc/boot.h |  21 +++
 hw/arc/meson.build|  13 ++
 hw/arc/nsim.c |  86 
 hw/arc/pic_cpu.c  | 111 
 hw/arc/sample.c   |  77 +++
 hw/arc/sim-hs.c   | 107 +++
 include/hw/arc/arc_uart.h |  43 ++
 include/hw/arc/cpudevs.h  |  10 ++
 13 files changed, 1101 insertions(+)
 create mode 100644 hw/arc/Makefile.objs
 create mode 100644 hw/arc/arc_sim.c
 create mode 100644 hw/arc/arc_uart.c
 create mode 100644 hw/arc/board-hsdk.c
 create mode 100644 hw/arc/boot.c
 create mode 100644 hw/arc/boot.h
 create mode 100644 hw/arc/meson.build
 create mode 100644 hw/arc/nsim.c
 create mode 100644 hw/arc/pic_cpu.c
 create mode 100644 hw/arc/sample.c
 create mode 100644 hw/arc/sim-hs.c
 create mode 100644 include/hw/arc/arc_uart.h
 create mode 100644 include/hw/arc/cpudevs.h

diff --git a/hw/arc/Makefile.objs b/hw/arc/Makefile.objs
new file mode 100644
index 00..28d7766cd9
--- /dev/null
+++ b/hw/arc/Makefile.objs
@@ -0,0 +1,21 @@
+#
+#  QEMU ARC CPU
+#
+#  Copyright (c) 2019
+#
+#  This library is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU Lesser General Public
+#  License as published by the Free Software Foundation; either
+#  version 2.1 of the License, or (at your option) any later version.
+#
+#  This library is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+#  Lesser General Public License for more details.
+#
+#  You should have received a copy of the GNU Lesser General Public
+#  License along with this library; if not, see
+#  http://www.gnu.org/licenses/lgpl-2.1.html
+#
+
+obj-y   = arc_sim.o arc_uart.o sample.o pic_cpu.o boot.o board-hsdk.o sim-hs.o 
nsim.o
diff --git a/hw/arc/arc_sim.c b/hw/arc/arc_sim.c
new file mode 100644
index 00..8020a03d85
--- /dev/null
+++ b/hw/arc/arc_sim.c
@@ -0,0 +1,143 @@
+/*
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see .
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "cpu.h"
+#include "hw/hw.h"
+#include "hw/boards.h"
+#include "elf.h"
+#include "hw/char/serial.h"
+#include "net/net.h"
+#include "hw/loader.h"
+#include "exec/memory.h"
+#include "exec/address-spaces.h"
+#include "sysemu/reset.h"
+#include "sysemu/runstate.h"
+#include "sysemu/sysemu.h"
+#include "hw/sysbus.h"
+#include "hw/arc/cpudevs.h"
+#include "boot.h"
+
+static void arc_sim_net_init(MemoryRegion *address_space,
+ hwaddr base,
+ hwaddr descriptors,
+ qemu_irq irq, NICInfo *nd)
+{
+DeviceState *dev;
+SysBusDevice *s;
+
+dev = qdev_new("open_eth");
+qdev_set_nic_properties(dev, nd);
+sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+
+s = SYS_BUS_DEVICE(dev);
+sysbus_connect_irq(s, 0, irq);
+memory_region_add_subregion(address_space, base,
+sysbus_mmio_get_region(s, 0));
+memory_region_add_subregion(address_space, descriptors,
+sysbus_mmio_get_region(s, 1));
+}
+
+static uint64_t arc_io_read(void *opaque, hwaddr addr, unsigned size)
+{
+return 0;
+}
+
+static void arc_io_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+switch (addr) {
+case 0x08: /* board reset. */
+qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+break;
+default:
+break;
+}
+}
+
+static const MemoryRegionOps arc_io_ops = {
+.read = arc_io_read,
+.write = arc_io_write,
+.endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void arc_sim_init(MachineState *machine)
+{
+static struct arc_boot_info boot_info;
+unsigned int smp_cpus

[PATCH 11/14] arc: Add gdbstub and XML for debugging support

2020-09-30 Thread cupertinomiranda 
From: Shahab Vahedi 

Register layout for the target and the mechanisms to read and set them.

Signed-off-by: Shahab Vahedi 
---
 gdb-xml/arc-aux-minimal.xml |  32 +++
 gdb-xml/arc-aux-other.xml   | 235 
 gdb-xml/arc-core-v2.xml |  45 
 target/arc/gdbstub.c| 421 
 4 files changed, 733 insertions(+)
 create mode 100644 gdb-xml/arc-aux-minimal.xml
 create mode 100644 gdb-xml/arc-aux-other.xml
 create mode 100644 gdb-xml/arc-core-v2.xml
 create mode 100644 target/arc/gdbstub.c

diff --git a/gdb-xml/arc-aux-minimal.xml b/gdb-xml/arc-aux-minimal.xml
new file mode 100644
index 00..7809c97a8d
--- /dev/null
+++ b/gdb-xml/arc-aux-minimal.xml
@@ -0,0 +1,32 @@
+
+
+
+
+
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+
diff --git a/gdb-xml/arc-aux-other.xml b/gdb-xml/arc-aux-other.xml
new file mode 100644
index 00..86b114af98
--- /dev/null
+++ b/gdb-xml/arc-aux-other.xml
@@ -0,0 +1,235 @@
+
+
+
+
+
+  
+
+
+
+
+
+
+  
+  
+
+
+
+
+
+  
+  
+
+
+
+
+
+  
+  
+
+
+  
+  
+
+
+
+
+
+
+
+
+
+
+  
+  
+
+
+
+
+
+  
+  
+
+
+
+
+
+
+  
+  
+
+
+
+
+
+
+
+
+  
+  
+
+
+
+  
+  
+
+  
+  
+
+
+
+  
+  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+  
+
+
+
+
+
+  
+  
+
+
+
+
+
+  
+  
+
+
+  
+  
+
+
+
+
+  
+  
+
+
+  
+  
+
+
+
+
+
+
+
+  
+  
+
+
+
+  
+  
+
+
+  
+  
+
+
+
+
+
+
+
+
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+
diff --git a/gdb-xml/arc-core-v2.xml b/gdb-xml/arc-core-v2.xml
new file mode 100644
index 00..550dae3411
--- /dev/null
+++ b/gdb-xml/arc-core-v2.xml
@@ -0,0 +1,45 @@
+
+
+
+
+
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+
diff --git a/target/arc/gdbstub.c b/target/arc/gdbstub.c
new file mode 100644
index 00..574e8fdf4b
--- /dev/null
+++ b/target/arc/gdbstub.c
@@ -0,0 +1,421 @@
+
+/*
+ * QEMU ARC CPU
+ *
+ * Copyright (c) 2016 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * http://www.gnu.org/licenses/lgpl-2.1.html
+ */
+
+#include "qemu/osdep.h"
+#include "exec/gdbstub.h"
+#include "arc-common.h"
+#include "target/arc/regs.h"
+#include "internals.h"
+#include "irq.h"
+
+/* gets the register address for a particular processor */
+#define REG_ADDR(reg, processor_type) \
+arc_aux_reg_address_for((reg), (processor_type))
+
+int arc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
+{
+ARCCPU *cpu = ARC_CPU(cs);
+CPUARCState *env = &cpu->env;
+uint32_t regval = 0;
+
+switch (n) {
+case 0 ... 31:
+   regval = env->r[n];
+   break;
+case GDB_REG_58:
+   regval = env->r[58];
+   break;
+case GDB_REG_59:
+   regval = env->r[59];
+   break;
+case GDB_REG_60:
+   regval = env->r[60];
+   break;
+case GDB_REG_63:
+   regval = env->r[63];
+   break;
+default:
+   assert(!"Unsupported register is being read.");
+}
+
+return gdb_get_reg32(mem_buf, regval);
+}
+
+int arc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+{
+ARCCPU *cpu = ARC_CPU(cs);
+CPUARCState *env = &cpu->env;
+uint32_t regval = ldl_p(mem_buf);
+
+switch (n) {
+case 0 ... 31:
+env->r[n] = regval;
+break;
+case GDB_REG_58:
+env->r[58] = regval;
+break;
+case GDB_REG_59:
+env->r[59] = regval;
+break;
+case GDB_REG_60:
+env->r[60] = regval;
+break;
+case GDB_REG_63:
+env->r[63] = regval;
+break;
+default:
+

Re: {standard input}:1174: Error: inappropriate arguments for opcode 'mpydu' (fwd)

2020-09-30 Thread Vineet Gupta 
Hi Nicolas,

On 9/30/20 2:23 PM, Nicolas Pitre wrote:
> Hello,
>
> I just realized you might not be aware of the following issue.
>
> The kernel kbuild test robot project identified a build failure on ARC 
> that bisects down to a patch of mine. 

Your patch to Linux kernel ? Indeed the report we got for build failure didn't
provide that context and we will appreciate pointers to same just for curiosity.

> It turns out that my patch is 
> highlighting a bug in gcc for ARC.

In any case, we did reach the same conclusion it is indeed an ARC gcc bug (for 
Big
endian builds only) and have created a github ticket for our gcc maintainer to
resolve. Please note that we've not seen it internally as Big Endian is an
optional configuration option and not in wide spread use for us.

https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/issues/300


And we can also confirm this is seen in gcc 9 and gcc 10 both.

Thx,
-Vineet

>
> -- Forwarded message --
> Date: Mon, 28 Sep 2020 17:43:20 -0400 (EDT)
> From: Nicolas Pitre 
> To: Rong Chen 
> Cc: kernel test robot , kbuild-...@lists.01.org,
> linux-ker...@vger.kernel.org, Arnd Bergmann , 
> g...@gcc.gnu.org
> Message-ID: 
> Subject: Re: {standard input}:1174: Error: inappropriate arguments for opcode
> 'mpydu'
>
> On Sun, 27 Sep 2020, Rong Chen wrote:
>
>> Hi Nicolas,
>>
>> Thanks for the feedback, the error still remains with gcc 10.2.0:
> I've created the simplest test case that can be. You won't believe it.
>
> Test case:
>
> $ cat test.c
> unsigned int test(unsigned int x, unsigned long long y)
> {
>   y /= 0x2000;
>   if (x > 1)
>   y *= x;
>   return y;
> }
> $ export 
> LD_LIBRARY_PATH=$LD_LIBRARY_PATH:~/0day/gcc-9.3.0-nolibc/arc-elf/libexec/gcc/arc-elf/9.3.0
> $ ~/0day/gcc-9.3.0-nolibc/arc-elf/bin/arc-elf-gcc -mcpu=hs38 -mbig-endian -O2 
> -c test.c
> /tmp/cc0GAomh.s: Assembler messages:
> /tmp/cc0GAomh.s:21: Error: inappropriate arguments for opcode 'mpydu'
>
> I know nothing about ARC. Please anyone take it over from here.
>
>
> Nicolas

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Re: {standard input}:1174: Error: inappropriate arguments for opcode 'mpydu' (fwd)

2020-09-30 Thread Nicolas Pitre 
On Wed, 30 Sep 2020, Vineet Gupta wrote:

> Hi Nicolas,
> 
> On 9/30/20 2:23 PM, Nicolas Pitre wrote:
> > Hello,
> >
> > I just realized you might not be aware of the following issue.
> >
> > The kernel kbuild test robot project identified a build failure on ARC 
> > that bisects down to a patch of mine. 
> 
> Your patch to Linux kernel ? Indeed the report we got for build failure didn't
> provide that context and we will appreciate pointers to same just for 
> curiosity.

Here is the original report:

https://www.spinics.net/lists/kernel/msg3596096.html

> > It turns out that my patch is 
> > highlighting a bug in gcc for ARC.
> 
> In any case, we did reach the same conclusion it is indeed an ARC gcc bug 
> (for Big
> endian builds only) and have created a github ticket for our gcc maintainer to
> resolve. Please note that we've not seen it internally as Big Endian is an
> optional configuration option and not in wide spread use for us.
> 
> https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/issues/300
> 
> 
> And we can also confirm this is seen in gcc 9 and gcc 10 both.
> 
> Thx,
> -Vineet
> 
> >
> > -- Forwarded message --
> > Date: Mon, 28 Sep 2020 17:43:20 -0400 (EDT)
> > From: Nicolas Pitre 
> > To: Rong Chen 
> > Cc: kernel test robot , kbuild-...@lists.01.org,
> > linux-ker...@vger.kernel.org, Arnd Bergmann , 
> > g...@gcc.gnu.org
> > Message-ID: 
> > Subject: Re: {standard input}:1174: Error: inappropriate arguments for 
> > opcode
> > 'mpydu'
> >
> > On Sun, 27 Sep 2020, Rong Chen wrote:
> >
> >> Hi Nicolas,
> >>
> >> Thanks for the feedback, the error still remains with gcc 10.2.0:
> > I've created the simplest test case that can be. You won't believe it.
> >
> > Test case:
> >
> > $ cat test.c
> > unsigned int test(unsigned int x, unsigned long long y)
> > {
> > y /= 0x2000;
> > if (x > 1)
> > y *= x;
> > return y;
> > }
> > $ export 
> > LD_LIBRARY_PATH=$LD_LIBRARY_PATH:~/0day/gcc-9.3.0-nolibc/arc-elf/libexec/gcc/arc-elf/9.3.0
> > $ ~/0day/gcc-9.3.0-nolibc/arc-elf/bin/arc-elf-gcc -mcpu=hs38 -mbig-endian 
> > -O2 -c test.c
> > /tmp/cc0GAomh.s: Assembler messages:
> > /tmp/cc0GAomh.s:21: Error: inappropriate arguments for opcode 'mpydu'
> >
> > I know nothing about ARC. Please anyone take it over from here.
> >
> >
> > Nicolas
> 
> 

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