Re: [RFC] etnaviv: missing dma_mask
Am Freitag, den 17.08.2018, 08:42 +0200 schrieb Christoph Hellwig: > On Tue, Aug 14, 2018 at 05:12:25PM +0300, Eugeniy Paltsev wrote: > > Hi Lucas, Christoph, > > > > After switching ARC to generic dma_noncoherent cache ops > > etnaviv driver start failing on dma maping functions because of > > dma_mask lack. > > > > So I'm wondering is it valid case to have device which is > > DMA capable and doesn't have dma_mask set? > > > > If not, then I guess something like that should work > > (at least it works for ARC): > > This looks ok is a minimal fix: > > Reviewed-by: Christoph Hellwig > > But why doesn't this device have a dma-range property in DT? Because the etnaviv device is a virtual device not represented in DT, as it is only used to expose the DRM device, which may cover multiple GPU core devices. The GPU core devices are properly configured from DT, but unfortunately many of the dma related operations happen through the DRM device. We could fix this by replacing many of the DRM helpers with etnaviv specific functions handling dma per GPU core, but it isn't a clear win right now, as generally on SoCs with multiple GPU cores, the devices are on the same bus and have the same dma requirements. Regards, Lucas ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [PATCH v2 2/4] ARC: allow to use IOC and non-IOC DMA devices simultaneously
Btw, given that I assume this is 4.20 material now, any chance we could merge it through the dma-mapping tree? I have some major changes pending that would clash if done in a different tree, so I'd rather get it all together. > We check this flag in arch_dma_alloc (which are used in non-coherent case) to > skip MMU mapping if we are advertised that consistency is not required. > > So, actually we can get rid of this flag checking in arch_dma_alloc and > simply always do MMU mapping to enforce non-cachability and return > non-cacheable memory even if DMA_ATTR_NON_CONSISTENT is passed. > But I don't sure we want to do that. I plan to kill this flag for 4.20 (or 4.20 at latest) in favor of a better interface. But your implementation looks ok, so I'm fine with keeping it for now. ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH 0/2] GPIO: add single-register gpio via creg driver
Add single-register MMIO gpio driver for complex cases where only several fields in register belong to GPIO and each GPIO owns field with different length and on/off values. Here is the example: 31118 75 0 < bit number | || || | [ not used | gpio-1 | shift-1 | gpio-0 | shift-0 ] < 32 bit MMIO ^ ^ (3 bit)(2 bit) | | | | | write 0x2 == set output to "1" (on) | write 0x3 == set output to "0" (off) | write 0x1 == set output to "1" (on) write 0x4 == set output to "0" (off) This is different from gpio-reg, gpio-mmio and gpio-74xx-mmio: * They all don't support cases when GPIO output register have more than one bit per GPIO line. * They don't support holes in MMIO register. * They don't support cases when GPIO lines have different on/off values. This driver supports GPIOs via CREG on various Synopsys SoCs/boards. Eugeniy Paltsev (2): GPIO: add single-register gpio via creg driver dt-bindings: Document the Synopsys GPIO via CREG bindings .../devicetree/bindings/gpio/snps,creg-gpio.txt| 48 MAINTAINERS| 6 + drivers/gpio/Kconfig | 9 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-creg-snps.c | 242 + 5 files changed, 306 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/snps,creg-gpio.txt create mode 100644 drivers/gpio/gpio-creg-snps.c -- 2.14.4 ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH 2/2] dt-bindings: Document the Synopsys GPIO via CREG bindings
This patch adds documentation of device tree bindings for the Synopsys
GPIO via CREG driver.
Signed-off-by: Eugeniy Paltsev
---
.../devicetree/bindings/gpio/snps,creg-gpio.txt| 48 ++
1 file changed, 48 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/snps,creg-gpio.txt
diff --git a/Documentation/devicetree/bindings/gpio/snps,creg-gpio.txt
b/Documentation/devicetree/bindings/gpio/snps,creg-gpio.txt
new file mode 100644
index ..2ab1b49eee7b
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/snps,creg-gpio.txt
@@ -0,0 +1,48 @@
+GPIO via CREG (Control REGisers) driver
+
+To control such strangely mapped MMIO outputs:
+
+31118 75 0 < bit number
+| || || |
+[ not used | gpio-1 | shift-1 | gpio-0 | shift-0 ] < 32 bit MMIO register
+ ^ ^
+ | |
+ | write 0x2 == set output to "1" (on)
+ | write 0x3 == set output to "0" (off)
+ |
+write 0x1 == set output to "1" (on)
+write 0x4 == set output to "0" (off)
+
+
+Required properties:
+- compatible : "snps,creg-gpio"
+- reg : Exactly one register range with length 0x4.
+- #gpio-cells : Should be one - the pin number.
+- gpio-controller : Marks the device node as a GPIO controller.
+- snps,ngpios: Number of GPIO pins.
+- snps,bit-per-line: Number of bits per each gpio line (see picture).
+ Array the size of "snps,ngpios"
+- snps,shift: Shift (in bits) of the each GPIO field from the previous one in
+ register (see picture). Array the size of "snps,ngpios"
+- snps,on-val: Value should be set in corresponding field to set
+ output to "1" (see picture). Array the size of "snps,ngpios"
+- snps,off-val: Value should be set in corresponding field to set
+ output to "0" (see picture). Array the size of "snps,ngpios"
+
+Optional properties:
+- snps,default-val: default output field values. Array the size of
"snps,ngpios"
+
+Example (see picture):
+
+gpio: gpio@f00014b0 {
+ compatible = "snps,creg-gpio";
+ reg = <0xf00014b0 0x4>;
+ gpio-controller;
+ #gpio-cells = <1>;
+ snps,ngpios = <2>;
+ snps,shift = <5 1>;
+ snps,bit-per-line = <2 3>;
+ snps,on-val = <2 1>;
+ snps,off-val = <3 4>;
+ snps,default-val = <2 1>;
+};
--
2.14.4
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[PATCH 1/2] GPIO: add single-register gpio via creg driver
Add single-register MMIO gpio driver for complex cases where
only several fields in register belong to GPIO and each GPIO
owns field with different length and on/off values.
Here is the example:
31118 75 0 < bit number
| || || |
[ not used | gpio-1 | shift-1 | gpio-0 | shift-0 ] < 32 bit MMIO
^ ^
(3 bit)(2 bit)
| |
| |
| write 0x2 == set output to "1" (on)
| write 0x3 == set output to "0" (off)
|
write 0x1 == set output to "1" (on)
write 0x4 == set output to "0" (off)
This is different from gpio-reg, gpio-mmio and gpio-74xx-mmio:
* They all don't support cases when GPIO output register have
more than one bit per GPIO line.
* They don't support holes in MMIO register.
* They don't support cases when GPIO lines have different on/off
values.
Signed-off-by: Eugeniy Paltsev
---
MAINTAINERS | 6 ++
drivers/gpio/Kconfig | 9 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-creg-snps.c | 242 ++
4 files changed, 258 insertions(+)
create mode 100644 drivers/gpio/gpio-creg-snps.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 544cac829cf4..e731f2f9648a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13734,6 +13734,12 @@ S: Supported
F: drivers/reset/reset-axs10x.c
F: Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt
+SYNOPSYS CREG GPIO DRIVER
+M: Eugeniy Paltsev
+S: Maintained
+F: drivers/gpio/gpio-creg-snps.c
+F: Documentation/devicetree/bindings/gpio/snps,creg-gpio.txt
+
SYNOPSYS DESIGNWARE 8250 UART DRIVER
R: Andy Shevchenko
S: Maintained
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 71c0ab46f216..0f9cc1582cab 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -430,6 +430,15 @@ config GPIO_REG
A 32-bit single register GPIO fixed in/out implementation. This
can be used to represent any register as a set of GPIO signals.
+config GPIO_SNPS_CREG
+ bool "GPIO via CREG (Control REGisers) driver"
+ select OF_GPIO
+ help
+ This driver supports GPIOs via CREG on various Synopsys SoCs.
+ This is is single-register MMIO gpio driver for complex cases
+ where only several fields in register belong to GPIO and
+ each GPIO owns field with different length and on/off values.
+
config GPIO_SPEAR_SPICS
bool "ST SPEAr13xx SPI Chip Select as GPIO support"
depends on PLAT_SPEAR
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 1324c8f966a7..993f8ad54a19 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -109,6 +109,7 @@ obj-$(CONFIG_GPIO_REG) += gpio-reg.o
obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
obj-$(CONFIG_GPIO_SCH) += gpio-sch.o
obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o
+obj-$(CONFIG_GPIO_SNPS_CREG) += gpio-creg-snps.o
obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o
obj-$(CONFIG_GPIO_SPEAR_SPICS) += gpio-spear-spics.o
obj-$(CONFIG_GPIO_SPRD)+= gpio-sprd.o
diff --git a/drivers/gpio/gpio-creg-snps.c b/drivers/gpio/gpio-creg-snps.c
new file mode 100644
index ..b684b7257aae
--- /dev/null
+++ b/drivers/gpio/gpio-creg-snps.c
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Synopsys CREG (Control REGisers) GPIO driver
+//
+// Copyright (C) 2018 Synopsys
+// Author: Eugeniy Paltsev
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "gpiolib.h"
+
+/*
+ * GPIO via CREG (Control REGisers) driver
+ *
+ * 31 118 75 0 < bit number
+ * ||| || |
+ * [not used| gpio-1 | shift-1 | gpio-0 | shift-0 ] < 32 bit register
+ * ^ ^
+ * | |
+ * | write 0x2 == set output to "1" (on)
+ * | write 0x3 == set output to "0" (off)
+ * |
+ * write 0x1 == set output to "1" (on)
+ * write 0x4 == set output to "0" (off)
+ */
+
+#define MAX_GPIO 32
+
+struct creg_gpio {
+ struct of_mm_gpio_chip mmchip;
+ spinlock_t lock;
+
+ u32 shift[MAX_GPIO];
+ u32 on[MAX_GPIO];
+ u32 off[MAX_GPIO];
+ u32 bit_per_gpio[MAX_GPIO];
+};
+
+static void _creg_gpio_set(struct creg_gpio *hcg, unsigned int gpio, u32 val)
+{
+ u32 reg, reg_shift;
+ unsigned long flags;
+ int i;
+
+ reg_shift = hcg->shift[gpio];
+ for (i = 0; i < gpio; i++)
+ reg_shift += hcg->bit_per_gpio[
Re: [PATCH 1/2] GPIO: add single-register gpio via creg driver
On 08/23/2018 08:00 AM, Eugeniy Paltsev wrote: > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig > index 71c0ab46f216..0f9cc1582cab 100644 > --- a/drivers/gpio/Kconfig > +++ b/drivers/gpio/Kconfig > @@ -430,6 +430,15 @@ config GPIO_REG > A 32-bit single register GPIO fixed in/out implementation. This > can be used to represent any register as a set of GPIO signals. > > +config GPIO_SNPS_CREG > + bool "GPIO via CREG (Control REGisers) driver" REGisters) > + select OF_GPIO > + help > + This driver supports GPIOs via CREG on various Synopsys SoCs. > + This is is single-register MMIO gpio driver for complex cases This is a MMIO GPIO > + where only several fields in register belong to GPIO and in a register > + each GPIO owns field with different length and on/off values. maybe: fields with different lengths > + > config GPIO_SPEAR_SPICS > bool "ST SPEAr13xx SPI Chip Select as GPIO support" > depends on PLAT_SPEAR -- ~Randy ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH] etnaviv: setup missing dma_mask
As for today etnaviv device doesn't setup dma_mask.
The etnaviv device is a virtual device not represented in DT
so missing dma_mask isn't setup by generic plaform code
(by of_dma_configure function).
Missing dma_mask causes fails in some dma cache ops functions.
For example it causes fails on map_* operations in generic
dma_noncoherent_ops and dma_direct_ops.
We faced with this behaviour after switching ARC to generic
dma_noncoherent cache ops using.
So fix this by setting dma_mask via dma_coerce_mask_and_coherent()
Reviewed-by: Christoph Hellwig
Signed-off-by: Eugeniy Paltsev
---
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
index 540b59fb4103..69d80937e021 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
@@ -593,7 +593,7 @@ static int etnaviv_pdev_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct component_match *match = NULL;
- dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
+ dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
if (!dev->platform_data) {
struct device_node *core_node;
--
2.14.4
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