Re: update timer frequencies
Hi Thomas, On 03/10/2017 03:58 PM, Thomas Gleixner wrote: Vlad, On Fri, 10 Mar 2017, Vlad Zakharov wrote: I am trying to implement a cpufreq driver for ARC CPUs. The point is that ARC timers (including those are used for timekeeping) are driven by the same clock as ARC CPU core(s). To be honest: That's broken by design and you really should go and tell your hardware folks to fix that. Proper timekeeping is essential for any Operating System (not only Linux). It's well known for more than TWO decades that changing the frequency of the timekeeper clocksource is a complete disaster, but obviously every hardware vendor has to learn that the hard way instead of simply learning from history. ... Your hardware design is broken by making the clocksource clock depend on the CPU frequency. Tell your hardware people to fix that or just use a seperate independent clocksource. The hardware is being changed and I had a couple of questions to help do it right: 1. The clocksource timers TIMER1, GFRC, RTC etc will now be clocked independent of core using a fixed clk. Is there some magic freq value which best works so we can recommend that to implementors. AFAIKR ARM has 24 MHz. 2. I'm not sure if the timer generating interrupts (periodic or oneshot) needs to be fed invariant fixed clk or dynamic core clk. Naively it should follow the core - but what happens to scheduled timers (say TCP timeouts): if this clk changes - they need to be canceled/updated. If it doesn't then the notion of timing is broken ? I'm likely not thinking this through correctly. Thx, -Vineet ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: update timer frequencies
On Fri, Aug 04, 2017 at 12:28:43PM +0530, Vineet Gupta wrote: > The hardware is being changed and I had a couple of questions to help do it > right: Awesome ;-) > 2. I'm not sure if the timer generating interrupts (periodic or oneshot) > needs to be fed invariant fixed clk or dynamic core clk. Naively it should > follow the core - but what happens to scheduled timers (say TCP timeouts): > if this clk changes - they need to be canceled/updated. If it doesn't then > the notion of timing is broken ? I'm likely not thinking this through > correctly. Please keep the timers on the very same clock as your clocksource. clockevent and clocksource having different (and possibly) drifting timelines is painful. Having them on the same clock makes everything so much easier, since you _know_ what time it is when they fire and won't have to recompute and possibly rearm the timer. ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH v2 2/2] ARC: DTS: Add device-tree for Anarion-based development board
Signed-off-by: Alexandru Gagniuc
---
Changes since v1:
* Updated CPU core clock to 24 MHz to match HW changes.
arch/arc/boot/dts/adaptrum_anarion.dtsi | 108
arch/arc/boot/dts/adaptrum_anarion_fpga.dts | 49 +
2 files changed, 157 insertions(+)
create mode 100644 arch/arc/boot/dts/adaptrum_anarion.dtsi
create mode 100644 arch/arc/boot/dts/adaptrum_anarion_fpga.dts
diff --git a/arch/arc/boot/dts/adaptrum_anarion.dtsi
b/arch/arc/boot/dts/adaptrum_anarion.dtsi
new file mode 100644
index 000..31ed204
--- /dev/null
+++ b/arch/arc/boot/dts/adaptrum_anarion.dtsi
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2017 Adaptrum, Inc.
+ * Written by Alexandru Gagniuc for Adaptrum, Inc.
+ * Licensed under the GPLv2 or (at your option) any later version
+ */
+
+/* This skeleton is based on the ARC700 CPU */
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "adaptrum,anarion";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ soc {
+ compatible = "simple-bus";
+ device_type = "soc";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-parent = <&core_intc>;
+
+ core_intc: interrupt-controller {
+ compatible = "snps,arc700-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ uart0: serial@f2202100 {
+ compatible = "ns16550";
+ reg = <0xf2202100 0x20>;
+ interrupts = <8>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <19200>;
+ status = "disabled";
+ };
+
+ uart1: serial@f2202200 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xf2202200 0x20>;
+ interrupts = <8>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <19200>;
+ status = "disabled";
+ };
+
+ uart2: serial@f2202300 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xf2202300 0x20>;
+ interrupts = <8>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <19200>;
+ status = "disabled";
+ };
+
+ uart3: serial@f2202400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xf2202400 0x20>;
+ interrupts = <8>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <19200>;
+ status = "disabled";
+ };
+
+ qspi: qspi@f200f000 {
+ compatible = "adaptrum,anarion-qspi";
+ reg = <0xf200f000 0x1000>,
+ <0x2000 0x0800>;
+
+ interrupts = <10>;
+ status = "disabled";
+ };
+
+ gmac0: ethernet@f201 {
+ compatible = "adaptrum,anarion-gmac", "snps,dwmac";
+ reg = <0xf201 0x4000>;
+
+ interrupt-parent = <&core_intc>;
+ interrupts = <20>;
+ interrupt-names = "macirq";
+
+ clocks = <&core_clk>;
+ clock-names = "stmmaceth";
+
+ snps,pbl = <32>;
+ status = "disabled";
+ };
+
+ gmac1: ethernet@f2014000 {
+ compatible = "adaptrum,anarion-gmac", "snps,dwmac";
+ reg = <0xf2014000 0x4000>, <0xf2018100 8>;
+
+ interrupt-parent = <&core_intc>;
+ interrupts = <21>;
+ interrupt-names = "macirq";
+
+ clocks = <&core_clk>;
+ clock-names = "stmmaceth";
+
+ snps,pbl = <32>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arc/boot/dts/adaptrum_anarion_fpga.dts
b/arch/arc/boot/dts/adaptrum_anarion_fpga.dts
new file mode 100644
index 000..02b838f
--- /dev/null
+++ b/arch/arc/boot/dts/adaptrum_anarion_fpga.dts
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2017 Adaptrum, Inc.
+ * Written by Alexandru Gagniuc for Adaptrum, Inc.
+ * Licensed under the GPLv2 or (at your option) any later version
+ */
+
+/dts-v1/;
+
+#include "adaptrum_anarion.dtsi"
+
+/ {
+ model = "adaptrum,anarion";
+ compatible = "adaptrum,anarion";
+
+ chosen {
+ bo
[PATCH v2 1/2] ARC: [plat-anarion] Add early boot workarounds for Anarion SOC
An ARC, the interrupts are enabled globally, rather than per-line, as
drivers request it. Thus, we need to make sure that peripherals don't
generate any before the respective drivers are probed.
The GMAC is infamous for spamming interrupts, so it must be kept in
reset until the driver is probed and interrupt mapping established.
Signed-off-by: Alexandru Gagniuc
---
Changes since v1:
* None
arch/arc/Kconfig | 1 +
arch/arc/Makefile| 1 +
arch/arc/plat-anarion/Kconfig| 10 ++
arch/arc/plat-anarion/Makefile | 7 +++
arch/arc/plat-anarion/platform.c | 39 +++
5 files changed, 58 insertions(+)
create mode 100644 arch/arc/plat-anarion/Kconfig
create mode 100644 arch/arc/plat-anarion/Makefile
create mode 100644 arch/arc/plat-anarion/platform.c
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index a545969..dff8423 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -100,6 +100,7 @@ source "arch/arc/plat-sim/Kconfig"
source "arch/arc/plat-tb10x/Kconfig"
source "arch/arc/plat-axs10x/Kconfig"
#New platform adds here
+source "arch/arc/plat-anarion/Kconfig"
source "arch/arc/plat-eznps/Kconfig"
endmenu
diff --git a/arch/arc/Makefile b/arch/arc/Makefile
index 44ef35d..9bc0048 100644
--- a/arch/arc/Makefile
+++ b/arch/arc/Makefile
@@ -109,6 +109,7 @@ core-y += arch/arc/boot/dts/
core-$(CONFIG_ARC_PLAT_SIM)+= arch/arc/plat-sim/
core-$(CONFIG_ARC_PLAT_TB10X) += arch/arc/plat-tb10x/
+core-$(CONFIG_ARC_PLAT_ANARION)+= arch/arc/plat-anarion/
core-$(CONFIG_ARC_PLAT_AXS10X) += arch/arc/plat-axs10x/
core-$(CONFIG_ARC_PLAT_EZNPS) += arch/arc/plat-eznps/
diff --git a/arch/arc/plat-anarion/Kconfig b/arch/arc/plat-anarion/Kconfig
new file mode 100644
index 000..632c7be
--- /dev/null
+++ b/arch/arc/plat-anarion/Kconfig
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2017 Adaptrum, Inc.
+# Written by Alexandru Gagniuc for Adaptrum, Inc.
+# Licensed under the GPLv2 or (at your option) any later version.
+#
+
+menuconfig ARC_PLAT_ANARION
+ bool "Adaptrum Anarion based platforms"
+ help
+ Support for Adaptrum Anarion based ARC platforms.
diff --git a/arch/arc/plat-anarion/Makefile b/arch/arc/plat-anarion/Makefile
new file mode 100644
index 000..9596a41
--- /dev/null
+++ b/arch/arc/plat-anarion/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2017 Adaptrum, Inc.
+# Written by Alexandru Gagniuc for Adaptrum, Inc.
+# Licensed under the GPLv2 or (at your option) any later version.
+#
+
+obj-y := platform.o
diff --git a/arch/arc/plat-anarion/platform.c b/arch/arc/plat-anarion/platform.c
new file mode 100644
index 000..ef0d381
--- /dev/null
+++ b/arch/arc/plat-anarion/platform.c
@@ -0,0 +1,39 @@
+/*
+ * Workarounds for Adaptrum Anarion SOC
+ *
+ * Copyright (C) 2017, Adaptrum, Inc.
+ * (Written by Alexandru Gagniuc for Adaptrum, Inc.)
+ * Licensed under the GPLv2 or (at your option) any later version.
+ */
+
+#include
+#include
+#include
+
+#define GMAC0_RESET0xf2018000
+#define GMAC1_RESET0xf2018100
+
+/* This works around an issue where the GMAC will generate interrupts before
+ * the driver is probed, confusing the heck out of the early boot.
+ */
+static void __init anarion_gmac_irq_storm_workaround(void)
+{
+ writel(1, (void *)GMAC0_RESET);
+ writel(1, (void *)GMAC1_RESET);
+}
+
+static void __init anarion_early_init(void)
+{
+ anarion_gmac_irq_storm_workaround();
+ /* Please, no more workarounds!!! */
+}
+
+static const char *anarion_compat[] __initconst = {
+ "adaptrum,anarion",
+ NULL,
+};
+
+MACHINE_START(ANARION, "anarion")
+ .dt_compat = anarion_compat,
+ .init_early = anarion_early_init,
+MACHINE_END
--
2.9.3
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