Hi Stephen,
On 07/14/2017 09:01 PM, Eugeniy Paltsev wrote:
HSDKv1 boards manages it's clocks using various PLLs. These PLL has same
dividers and corresponding control registers mapped to different addresses.
So we add one common driver for such PLLs.
Each PLL on HSDK board consist of three dividers: IDIV, FBDIV and
ODIV. Output clock value is managed using these dividers.
We add pre-defined tables with supported rate values and appropriate
configurations of IDIV, FBDIV and ODIV for each value.
As of today we add support for PLLs that generate clock for the
HSDKv1 arc cpus, system, ddr, AXI tunnel and hdmi.
By this patch we add support for several plls (arc cpus pll and others),
so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll
and regular probing for others plls.
Signed-off-by: Eugeniy Paltsev
Gentle ping, any chance you could look at this sometime.
Thx,
-Vineet
---
.../bindings/clock/snps,hsdkv1-pll-clock.txt | 28 ++
MAINTAINERS| 6 +
drivers/clk/Kconfig| 7 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-hsdk-pll.c | 346 +
5 files changed, 388 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/snps,hsdkv1-pll-clock.txt
create mode 100644 drivers/clk/clk-hsdk-pll.c
diff --git a/Documentation/devicetree/bindings/clock/snps,hsdkv1-pll-clock.txt
b/Documentation/devicetree/bindings/clock/snps,hsdkv1-pll-clock.txt
new file mode 100644
index 000..3580aa0
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/snps,hsdkv1-pll-clock.txt
@@ -0,0 +1,28 @@
+Binding for the HSDKv1 Generic PLL clock
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: should be "snps,hsdk--pll-clock"
+ "snps,hsdk-core-pll-clock"
+ "snps,hsdk-gp-pll-clock"
+ "snps,hsdk-hdmi-pll-clock"
+- reg : should contain base register location and length.
+- clocks: shall be the input parent clock phandle for the PLL.
+- #clock-cells: from common clock binding; Should always be set to 0.
+
+Example:
+ input_clk: input-clk {
+ clock-frequency = <>;
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ cpu_clk: cpu-clk@0 {
+ compatible = "snps,hsdk-core-pll-clock";
+ reg = <0x00 0x10>;
+ #clock-cells = <0>;
+ clocks = <&input_clk>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index b5ab794..96d0021 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12768,6 +12768,12 @@ F: arch/arc/plat-axs10x
F:arch/arc/boot/dts/ax*
F:Documentation/devicetree/bindings/arc/axs10*
+SYNOPSYS ARC HSDKv1 SDP pll clock driver
+M: Eugeniy Paltsev
+S: Supported
+F: drivers/clk/clk-hsdk-pll.c
+F: Documentation/devicetree/bindings/clock/snps,hsdkv1-pll-clock.txt
+
SYSTEM CONFIGURATION (SYSCON)
M:Lee Jones
M:Arnd Bergmann
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 68ca2d9..198fc14 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -219,6 +219,13 @@ config COMMON_CLK_VC5
This driver supports the IDT VersaClock5 programmable clock
generator.
+config CLK_HSDK_V1
+ bool "PLL Driver for HSDKv1 platform"
+ depends on OF || COMPILE_TEST
+ ---help---
+ This driver supports the HSDKv1 core, system, ddr, tunnel and hdmi
PLLs
+ control.
+
source "drivers/clk/bcm/Kconfig"
source "drivers/clk/hisilicon/Kconfig"
source "drivers/clk/imgtec/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index cd376b3..91e6cbd 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CS2000_CP)+= clk-cs2000-cp.o
obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
+obj-$(CONFIG_CLK_HSDK_V1) += clk-hsdk-pll.o
obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
obj-$(CONFIG_ARCH_MB86S7X)+= clk-mb86s7x.o
obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c
new file mode 100644
index 000..4e58e55
--- /dev/null
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -0,0 +1,346 @@
+/*
+ * Synopsys HSDKv1 SDP Generic PLL clock driver
+ *
+ * Copyright (C) 2017 Synopsys
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define CGU_PLL_CTRL 0x000 /* ARC PLL control r
