Re: [PATCH v4] clk: axs10x: introduce AXS10X pll driver
On Tue, 2017-07-11 at 22:25 -0700, Stephen Boyd wrote:
> On 06/21, Eugeniy Paltsev wrote:
> > AXS10X boards manages it's clocks using various PLLs. These PLL has
> > same
> > dividers and corresponding control registers mapped to different
> > addresses.
> > So we add one common driver for such PLLs.
> >
> > Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and
> > ODIV. Output clock value is managed using these dividers.
> >
> > We add pre-defined tables with supported rate values and
> > appropriate
> > configurations of IDIV, FBDIV and ODIV for each value.
> >
> > As of today we add support for PLLs that generate clock for the
> > following devices:
> > * ARC core on AXC CPU tiles.
> > * ARC PGU on ARC SDP Mainboard.
> > and more to come later.
> >
> > By this patch we add support for two plls (arc core pll and pgu
> > pll),
> > so we had to use two different init types: CLK_OF_DECLARE for arc
> > core pll and
> > regular probing for pgu pll.
> >
> > Acked-by: Rob Herring
> > Acked-by: Jose Abreu
> >
> > Signed-off-by: Eugeniy Paltsev
> > Signed-off-by: Vlad Zakharov
> > Signed-off-by: Jose Abreu
>
> Sorry this missed the cutoff for new code for v4.13. Should be in
> clk-next next week though.
>
> > +}
> > +
> > +static inline struct axs10x_pll_clk *to_axs10x_pll_clk(struct
> > clk_hw *hw)
> > +{
> > + return container_of(hw, struct axs10x_pll_clk, hw);
> > +}
> > +
> > +static inline u32 axs10x_div_get_value(u32 reg)
> > +{
> > + if (PLL_REG_GET_BYPASS(reg))
> > + return 1;
> > +
> > + return PLL_REG_GET_HIGH(reg) + PLL_REG_GET_LOW(reg);
> > +}
> > +
> > +static inline u32 axs10x_encode_div(unsigned int id, int upd)
> > +{
> > + u32 div = 0;
> > +
> > + PLL_REG_SET_LOW(div, (id % 2 == 0) ? id >> 1 : (id >> 1) +
> > 1);
> > + PLL_REG_SET_HIGH(div, id >> 1);
> > + PLL_REG_SET_EDGE(div, id % 2);
> > + PLL_REG_SET_BYPASS(div, id == 1 ? 1 : 0);
> > + PLL_REG_SET_NOUPD(div, !upd);
>
> So sparse complains here about a "dubious !x & y". Perhaps this
> can be changed to
>
> PLL_REG_SET_NOUPD(div, upd == 0 ? 1 : 0);
>
> That way sparse doesn't complain. I can make the change when
> applying if you agree.
Sure, thanks a lot.
--
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[PATCH 0/3 v8] hsdk: initial port for HSDK board
This series introduces some required preparations and initial
port of ARC HS Development Kit board with some basic features such
as serial port, USB, SD/MMC and Ethernet.
Essentially we run Linux kernel on all 4 cores (i.e. utilize SMP) and
heavily use IO Coherency for speeding-up DMA-aware peripherals.
Note as opposed to other ARC boards we link Linux kernel to
0x9000_ intentionally because cores 1 and 3 configured with DCCM
situated at our more usual link base 0x8000_.
Note that two patches of this series ("ARC: Decouple linux kernel memory
address and link address" and "ARC: Set IO-coherency aperture base to
LINUX_LINK_BASE") are prerequisites for HDSK support as its hardware
configuration differs quite a bit from what we used to have on other
ARC boards.
Alexey Brodkin (1):
ARC: hsdk: initial port for HSDK board
Eugeniy Paltsev (2):
ARC: Set IO-coherency aperture base to LINUX_LINK_BASE
ARC: Decouple linux kernel memory address and link address
Changes v7 -> v8:
* DTS: move cpu_intc, idu_intc, arcpct, timer, gfrc nodes to root
level and out of the cpus node.
* DTS: add vendor-specific compatible for ohci and ehci nodes.
* DTS: style fixes
Changes v6 -> v7:
* DTS: get rid of skeleton.dts, move cpus nodes to hsdk.dts
* DTS: style fixes
* Enable loadable modules, module unloading and NFS client as defaults
* Get rid of ARC_PLAT_HSDK board config option
Changes v5 -> v6:
* Add support of USB-to-HDMI adapter
* Revert removing of resetting CREG_PAE bits.
PAE remapping for DMA clients does not work due to an RTL bug, so
CREG_PAE register must be programmed to all zeroes, otherwise it
will cause problems with DMA to/from peripherals even if PAE40 is
not used.
Changes v4 -> v5:
* Move DCCM outside of 0x8000_ adress at kernel boot time.
* Decouple linux kernel memory address and link address.
* Remove hardcoding of IO-coherency aperture base.
* Remove resetting CREG_PAE bits as default value is suitable for us.
Changes v3 -> v4:
* Removed senseless "ranges" property from "memory" node in .dts
* Refined early-boot code:
- ICCM relocation should be done on each and every core that sports ICCM
so we leave it in init_per_cpu(). Even though init_per_cpu() gets called
on the master core pretty late still it is way much earlier than that
moment when it might affect us - as it only huts us when addresses in
0x7z-0x7fff_ range are used, i.e. virtual addresses that we don't
use during init. This also makes code much cleaner compared to
additional check in case of master etc.
Changes v2 -> v3:
* Added Rob to Cc-list for DT binding approval
* Removed mention of prerequsite patch from commit message
* Removed hsdk_early_init() as hsdk_init_per_cpu() is executed on
all cores anyways including master
* Cleaned-up board's .dts a little bit
* Removed CONFIG_DP83867_PHY from defconfig as it was only used on
FPGA prototype, on real board we use MICREL PHY which is still selected
Changes v1 -> v2:
* Update copyright year from 2016 to more up to date 2017
* Merge early UART clock with AXS10x as in both cases that's 33.3 MHz
* Bump memory to 1Gb, we don't use more for now because it requires
trickier IOC setup and usage
* Update early platform init code:
- Added missing fixup_pae_regs() to per-cpu init
- Mark most of functions as "static __init"
- Use writel_relaxed() for setting CREG_PAE, CREG_PAE_UPDATE is still
written with stronger writel() since we don't want reordering to happen,
otherwise value written to CREG_PAE won't be applied
Documentation/devicetree/bindings/arc/hsdk.txt | 7 ++
arch/arc/Kconfig | 6 +
arch/arc/Makefile | 1 +
arch/arc/boot/dts/hsdk.dts | 150 +
arch/arc/boot/dts/include/dt-bindings | 1 +
arch/arc/configs/hsdk_defconfig| 72
arch/arc/include/asm/page.h| 2 +-
arch/arc/kernel/devtree.c | 5 +-
arch/arc/mm/cache.c| 33 --
arch/arc/mm/init.c | 6 +-
arch/arc/plat-hsdk/Kconfig | 12 ++
arch/arc/plat-hsdk/Makefile| 9 ++
arch/arc/plat-hsdk/platform.c | 77 +
13 files changed, 366 insertions(+), 15 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arc/hsdk.txt
create mode 100644 arch/arc/boot/dts/hsdk.dts
create mode 12 arch/arc/boot/dts/include/dt-bindings
create mode 100644 arch/arc/configs/hsdk_defconfig
create mode 100644 arch/arc/plat-hsdk/Kconfig
create mode 100644 arch/arc/plat-hsdk/Makefile
create mode 100644 arch/arc/plat-hsdk/platform.c
--
2.9.3
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[PATCH 3/3 v8] ARC: hsdk: initial port for HSDK board
From: Alexey Brodkin
This initial port adds support of ARC HS Development Kit board with some
basic features such serial port, USB, SD/MMC and Ethernet.
Essentially we run Linux kernel on all 4 cores (i.e. utilize SMP) and
heavily use IO Coherency for speeding-up DMA-aware peripherals.
Note as opposed to other ARC boards we link Linux kernel to
0x9000_ intentionally because cores 1 and 3 configured with DCCM
situated at our more usual link base 0x8000_. We still can use
memory region starting at 0x8000_ as we reallocate DCCM in our
platform code.
Note that PAE remapping for DMA clients does not work due to an RTL bug,
so CREG_PAE register must be programmed to all zeroes, otherwise it will
cause problems with DMA to/from peripherals even if PAE40 is not used.
Signed-off-by: Alexey Brodkin
Signed-off-by: Eugeniy Paltsev
---
Changes v7 -> v8:
* DTS: move cpu_intc, idu_intc, arcpct, timer, gfrc nodes to root
level and out of the cpus node.
* DTS: add vendor-specific compatible for ohci and ehci nodes.
* DTS: style fixes
Documentation/devicetree/bindings/arc/hsdk.txt | 7 +
arch/arc/Makefile | 1 +
arch/arc/boot/dts/hsdk.dts | 189 +
arch/arc/configs/hsdk_defconfig| 78 ++
arch/arc/kernel/devtree.c | 5 +-
arch/arc/plat-hsdk/Makefile| 9 ++
arch/arc/plat-hsdk/platform.c | 79 +++
7 files changed, 366 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arc/hsdk.txt
create mode 100644 arch/arc/boot/dts/hsdk.dts
create mode 100644 arch/arc/configs/hsdk_defconfig
create mode 100644 arch/arc/plat-hsdk/Makefile
create mode 100644 arch/arc/plat-hsdk/platform.c
diff --git a/Documentation/devicetree/bindings/arc/hsdk.txt
b/Documentation/devicetree/bindings/arc/hsdk.txt
new file mode 100644
index 000..be50654
--- /dev/null
+++ b/Documentation/devicetree/bindings/arc/hsdk.txt
@@ -0,0 +1,7 @@
+Synopsys DesignWare ARC HS Development Kit Device Tree Bindings
+---
+
+ARC HSDK Board with quad-core ARC HS38x4 in silicon.
+
+Required root node properties:
+- compatible = "snps,hsdk";
diff --git a/arch/arc/Makefile b/arch/arc/Makefile
index 44ef35d..e67397e 100644
--- a/arch/arc/Makefile
+++ b/arch/arc/Makefile
@@ -111,6 +111,7 @@ core-$(CONFIG_ARC_PLAT_SIM) += arch/arc/plat-sim/
core-$(CONFIG_ARC_PLAT_TB10X) += arch/arc/plat-tb10x/
core-$(CONFIG_ARC_PLAT_AXS10X) += arch/arc/plat-axs10x/
core-$(CONFIG_ARC_PLAT_EZNPS) += arch/arc/plat-eznps/
+core-y += arch/arc/plat-hsdk/
ifdef CONFIG_ARC_PLAT_EZNPS
KBUILD_CPPFLAGS += -I$(srctree)/arch/arc/plat-eznps/include
diff --git a/arch/arc/boot/dts/hsdk.dts b/arch/arc/boot/dts/hsdk.dts
new file mode 100644
index 000..e096879
--- /dev/null
+++ b/arch/arc/boot/dts/hsdk.dts
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Device Tree for ARC HS Development Kit
+ */
+/dts-v1/;
+
+#include
+
+/ {
+ model = "snps,hsdk";
+ compatible = "snps,hsdk";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen {
+ bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8
console=ttyS0,115200n8 debug print-fatal-signals=1";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "snps,archs38";
+ reg = <0>;
+ clocks = <&core_clk>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "snps,archs38";
+ reg = <1>;
+ clocks = <&core_clk>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "snps,archs38";
+ reg = <2>;
+ clocks = <&core_clk>;
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "snps,archs38";
+ reg = <3>;
+ clocks = <&core_clk>;
+ };
+ };
+
+ core_clk: core-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <10>;
+ };
+
+ cpu_intc: cpu-interrupt-controller {
+ compatible = "snps,archs-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ idu_in
[PATCH 1/3 v8] ARC: Set IO-coherency aperture base to LINUX_LINK_BASE
Most of the time we indeed use the one and only LINUX_LINK_BASE
set to 0x8000_. But there might be good reasons to move
the kernel to another location like 0x9z etc.
And we want IOC aperture to cover entire area used by the kernel,
so let's make its base matching link base and add required asserts:
checking IOC aperture base address and size to be supported by IOC.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/mm/cache.c | 33 -
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index a867575..383ff77 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -1083,7 +1083,8 @@ SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t,
sz, uint32_t, flags)
*/
noinline void __init arc_ioc_setup(void)
{
- unsigned int ap_sz;
+ unsigned int ap_base;
+ long ap_size;
/* Flush + invalidate + disable L1 dcache */
__dc_disable();
@@ -1092,18 +1093,32 @@ noinline void __init arc_ioc_setup(void)
if (read_aux_reg(ARC_REG_SLC_BCR))
slc_entire_op(OP_FLUSH_N_INV);
- /* IOC Aperture start: TDB: handle non default CONFIG_LINUX_LINK_BASE */
- write_aux_reg(ARC_REG_IO_COH_AP0_BASE, 0x8);
-
/*
-* IOC Aperture size:
-* decoded as 2 ^ (SIZE + 2) KB: so setting 0x11 implies 512M
-* TBD: fix for PGU + 1GB of low mem
+* IOC Aperture size is equal to memory size.
+* TBD: fix for PGU + 1GiB of low mem
* TBD: fix for PAE
*/
- ap_sz = order_base_2(arc_get_mem_sz()/1024) - 2;
- write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, ap_sz);
+ ap_size = arc_get_mem_sz();
+
+ if (!is_power_of_2(ap_size) || ap_size < 4096)
+ panic("IOC Aperture size must be power of 2 larger than 4KiB");
+
+ /*
+* IOC Aperture size decoded as 2 ^ (SIZE + 2) KiB,
+* so setting 0x11 implies 512MiB, 0x12 implies 1G...
+*/
+ write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, order_base_2(ap_size / 1024) -
2);
+
+ /*
+* For now we assume IOC aperture to cover all the memory used by the
+* kernel.
+*/
+ ap_base = CONFIG_LINUX_LINK_BASE;
+
+ if (ap_base % ap_size != 0)
+ panic("IOC Aperture start must be aligned to the size of the
aperture");
+ write_aux_reg(ARC_REG_IO_COH_AP0_BASE, ap_base >> 12);
write_aux_reg(ARC_REG_IO_COH_PARTIAL, 1);
write_aux_reg(ARC_REG_IO_COH_ENABLE, 1);
--
2.9.3
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[PATCH 2/3 v8] ARC: Decouple linux kernel memory address and link address
We faced with problem when we tried to utilize 1G DRAM by linux on
HSDK.
We can't use our usual kernel memory address (0x8000) like on
AXS103 because of DCCM memory bank located at exactly same
address (0x8000)
But we can't simply move kernel memory address to another address (like
0x9000) because IOC base address must be aligned to the
size of the aperture as specified in the IOC size register.
So we had to use 1G aligned address for kernel memory.
We can't use 0x or 0x4000 addresses because addresses
lover then 0x8000 are MMU-translated.
We can't use 0xB000 address because we can define a volatile
uncached region only from AUX_NON_VOLATILE_LIMIT to the
0x. (the end of region is hardcoded)
So, the decision is to link kernel to 0x9000, but use
0x8000-0xBFFF memory region and reallocate DCCM in our platform
code.
This patch only makes possible to set kernel memory address not equal to
kernel link address.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/Kconfig| 5 +
arch/arc/include/asm/page.h | 2 +-
arch/arc/mm/cache.c | 2 +-
arch/arc/mm/init.c | 6 +++---
4 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index a545969..75e5276 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -430,6 +430,11 @@ config LINUX_LINK_BASE
However some customers have peripherals mapped at this addr, so
Linux needs to be scooted a bit.
If you don't know what the above means, leave this setting alone.
+
+config KERNEL_RAM_BASE_ADDRESS
+ hex "Linux ram base address"
+ default LINUX_LINK_BASE
+ help
This needs to match memory start address specified in Device Tree
config HIGHMEM
diff --git a/arch/arc/include/asm/page.h b/arch/arc/include/asm/page.h
index 296c342..777f676 100644
--- a/arch/arc/include/asm/page.h
+++ b/arch/arc/include/asm/page.h
@@ -85,7 +85,7 @@ typedef pte_t * pgtable_t;
*/
#define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT)
-#define ARCH_PFN_OFFSETvirt_to_pfn(CONFIG_LINUX_LINK_BASE)
+#define ARCH_PFN_OFFSET
virt_to_pfn(CONFIG_KERNEL_RAM_BASE_ADDRESS)
#ifdef CONFIG_FLATMEM
#define pfn_valid(pfn) (((pfn) - ARCH_PFN_OFFSET) < max_mapnr)
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 383ff77..f303274 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -1113,7 +1113,7 @@ noinline void __init arc_ioc_setup(void)
* For now we assume IOC aperture to cover all the memory used by the
* kernel.
*/
- ap_base = CONFIG_LINUX_LINK_BASE;
+ ap_base = CONFIG_KERNEL_RAM_BASE_ADDRESS;
if (ap_base % ap_size != 0)
panic("IOC Aperture start must be aligned to the size of the
aperture");
diff --git a/arch/arc/mm/init.c b/arch/arc/mm/init.c
index 8c9415e..f84cba2 100644
--- a/arch/arc/mm/init.c
+++ b/arch/arc/mm/init.c
@@ -26,7 +26,7 @@ pgd_t swapper_pg_dir[PTRS_PER_PGD] __aligned(PAGE_SIZE);
char empty_zero_page[PAGE_SIZE] __aligned(PAGE_SIZE);
EXPORT_SYMBOL(empty_zero_page);
-static const unsigned long low_mem_start = CONFIG_LINUX_LINK_BASE;
+static const unsigned long low_mem_start = CONFIG_KERNEL_RAM_BASE_ADDRESS;
static unsigned long low_mem_sz;
#ifdef CONFIG_HIGHMEM
@@ -63,7 +63,7 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size)
if (!low_mem_sz) {
if (base != low_mem_start)
- panic("CONFIG_LINUX_LINK_BASE != DT memory { }");
+ panic("CONFIG_KERNEL_RAM_BASE_ADDRESS != DT memory {
}");
low_mem_sz = size;
in_use = 1;
@@ -161,7 +161,7 @@ void __init setup_arch_memory(void)
* We can't use the helper free_area_init(zones[]) because it uses
* PAGE_OFFSET to compute the @min_low_pfn which would be wrong
* when our kernel doesn't start at PAGE_OFFSET, i.e.
-* PAGE_OFFSET != CONFIG_LINUX_LINK_BASE
+* PAGE_OFFSET != CONFIG_KERNEL_RAM_BASE_ADDRESS
*/
free_area_init_node(0, /* node-id */
zones_size, /* num pages per zone */
--
2.9.3
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Re: [PATCH v4] clk: axs10x: introduce AXS10X pll driver
On 07/12, Eugeniy Paltsev wrote:
> On Tue, 2017-07-11 at 22:25 -0700, Stephen Boyd wrote:
> > On 06/21, Eugeniy Paltsev wrote:
> > > AXS10X boards manages it's clocks using various PLLs. These PLL has
> > > same
> > > dividers and corresponding control registers mapped to different
> > > addresses.
> > > So we add one common driver for such PLLs.
> > >
> > > Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and
> > > ODIV. Output clock value is managed using these dividers.
> > >
> > > We add pre-defined tables with supported rate values and
> > > appropriate
> > > configurations of IDIV, FBDIV and ODIV for each value.
> > >
> > > As of today we add support for PLLs that generate clock for the
> > > following devices:
> > > * ARC core on AXC CPU tiles.
> > > * ARC PGU on ARC SDP Mainboard.
> > > and more to come later.
> > >
> > > By this patch we add support for two plls (arc core pll and pgu
> > > pll),
> > > so we had to use two different init types: CLK_OF_DECLARE for arc
> > > core pll and
> > > regular probing for pgu pll.
> > >
> > > Acked-by: Rob Herring
> > > Acked-by: Jose Abreu
> > >
> > > Signed-off-by: Eugeniy Paltsev
> > > Signed-off-by: Vlad Zakharov
> > > Signed-off-by: Jose Abreu
> >
> > Sorry this missed the cutoff for new code for v4.13. Should be in
> > clk-next next week though.
> >
> > > +}
> > > +
> > > +static inline struct axs10x_pll_clk *to_axs10x_pll_clk(struct
> > > clk_hw *hw)
> > > +{
> > > + return container_of(hw, struct axs10x_pll_clk, hw);
> > > +}
> > > +
> > > +static inline u32 axs10x_div_get_value(u32 reg)
> > > +{
> > > + if (PLL_REG_GET_BYPASS(reg))
> > > + return 1;
> > > +
> > > + return PLL_REG_GET_HIGH(reg) + PLL_REG_GET_LOW(reg);
> > > +}
> > > +
> > > +static inline u32 axs10x_encode_div(unsigned int id, int upd)
> > > +{
> > > + u32 div = 0;
> > > +
> > > + PLL_REG_SET_LOW(div, (id % 2 == 0) ? id >> 1 : (id >> 1) +
> > > 1);
> > > + PLL_REG_SET_HIGH(div, id >> 1);
> > > + PLL_REG_SET_EDGE(div, id % 2);
> > > + PLL_REG_SET_BYPASS(div, id == 1 ? 1 : 0);
> > > + PLL_REG_SET_NOUPD(div, !upd);
> >
> > So sparse complains here about a "dubious !x & y". Perhaps this
> > can be changed to
> >
> > PLL_REG_SET_NOUPD(div, upd == 0 ? 1 : 0);
> >
> > That way sparse doesn't complain. I can make the change when
> > applying if you agree.
>
> Sure, thanks a lot.
>
Ok. Applied to clk-next.
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