[PATCH 08/11] ARC: [plat-eznps] Update the init sequence of aux regs per cpu.
From: Liav Rehana The following commit adds a config that will enable us to distinguish between building the kernel for platforms that have a different set of auxiliary registers for each cpu and platforms that have a shared set of auxiliary registers across every thread in each core. On platforms that implement a different set of auxiliary registers there is a need to initialize them on every cpu and not just the for the first thread of the core. Signed-off-by: Liav Rehana Signed-off-by: Noam Camus --- arch/arc/plat-eznps/Kconfig | 11 +++ arch/arc/plat-eznps/entry.S |2 +- 2 files changed, 12 insertions(+), 1 deletions(-) diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig index daf749e..812bc29 100644 --- a/arch/arc/plat-eznps/Kconfig +++ b/arch/arc/plat-eznps/Kconfig @@ -44,3 +44,14 @@ config EZNPS_MEM_ERROR for NPS, it handled as an interrupt level 2 (like legacy arc real chip architecture).This configuration will cause the kernel to handle memory error as a machine check exception. + +config EZNPS_SHARED_AUX_REGS + bool "ARC-EZchip Shared Auxiliary Registers Per Core" + depends on ARC_PLAT_EZNPS + default y + help + On the real chip of the NPS, auxiliary registers are shared between + all the cpus of the core, whereas on simulator platform for NPS, + each cpu has a different set of auxiliary registers. Configuration + should be unset if auxiliary registers are not shared between the cpus + of the core, so there will be a need to initialize them per cpu. diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S index 21665ae..4a29c80 100644 --- a/arch/arc/plat-eznps/entry.S +++ b/arch/arc/plat-eznps/entry.S @@ -27,7 +27,7 @@ .align 1024 ; HW requierment for restart first PC ENTRY(res_service) -#ifdef CONFIG_EZNPS_MTM_EXT +#if defined(CONFIG_EZNPS_MTM_EXT) && defined(CONFIG_EZNPS_SHARED_AUX_REGS) ; There is no work for HW thread id != 0 lr r3, [CTOP_AUX_THREAD_ID] cmp r3, 0 -- 1.7.1 ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH 02/11] ARC: send ipi to all cpus sharing task mm in case of page fault
From: Noam Camus
This patch is derived due to performance issue.
The use case is a page fault that resides on more than the local cpu.
Trying to broadcast all CPUs results on performance degradation.
So we try to avoid this by sending only to the relevant CPUs.
Signed-off-by: Noam Camus
Reviewed-by: Alexey Brodkin
---
arch/arc/include/asm/cacheflush.h |3 ++-
arch/arc/mm/cache.c | 12 ++--
arch/arc/mm/tlb.c |2 +-
3 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/arch/arc/include/asm/cacheflush.h
b/arch/arc/include/asm/cacheflush.h
index fc662f4..716dba1 100644
--- a/arch/arc/include/asm/cacheflush.h
+++ b/arch/arc/include/asm/cacheflush.h
@@ -33,7 +33,8 @@
void flush_icache_range(unsigned long kstart, unsigned long kend);
void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len);
-void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr);
+void __inv_icache_page(struct vm_area_struct *vma,
+ phys_addr_t paddr, unsigned long vaddr);
void __flush_dcache_page(phys_addr_t paddr, unsigned long vaddr);
#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 15bc3e3..aa4c743 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -934,9 +934,17 @@ void __sync_icache_dcache(phys_addr_t paddr, unsigned long
vaddr, int len)
}
/* wrapper to compile time eliminate alignment checks in flush loop */
-void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr)
+void __inv_icache_page(struct vm_area_struct *vma,
+ phys_addr_t paddr, unsigned long vaddr)
{
- __ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE);
+ struct ic_inv_args ic_inv = {
+ .paddr = paddr,
+ .vaddr = vaddr,
+ .sz = PAGE_SIZE
+ };
+
+ on_each_cpu_mask(mm_cpumask(vma->vm_mm),
+__ic_line_inv_vaddr_helper, &ic_inv, 1);
}
/*
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index c5e70d8..a095608 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -626,7 +626,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned
long vaddr_unaligned,
/* invalidate any existing icache lines (U-mapping) */
if (vma->vm_flags & VM_EXEC)
- __inv_icache_page(paddr, vaddr);
+ __inv_icache_page(vma, paddr, vaddr);
}
}
}
--
1.7.1
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[PATCH 09/11] ARC: [plat-eznps] Save/Restore extra auxiliary registers
From: Noam Camus
thread_struct got new field for data plane of eznps platform.
This field got place for data plane auxiliary registers and for
any extra registers that might be changed in kernel code.
We save EFLAGS, and GPA1 auxiliary registers since they may be
changed by the new task while using atomic operations e.g. cmpxchg.
Signed-off-by: Noam Camus
---
arch/arc/include/asm/arcregs.h |7 +++
arch/arc/include/asm/processor.h |3 +++
arch/arc/include/asm/switch_to.h | 11 +++
arch/arc/plat-eznps/Makefile |2 +-
arch/arc/plat-eznps/ctop.c | 33 +
5 files changed, 55 insertions(+), 1 deletions(-)
create mode 100644 arch/arc/plat-eznps/ctop.c
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index ba8e802..9437d42 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -123,6 +123,13 @@
#define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10)
+#ifdef CONFIG_ARC_PLAT_EZNPS
+struct eznps_dp {
+ unsigned int eflags;
+ unsigned int gpa1;
+};
+#endif
+
/*
***
* Build Configuration Registers, with encoded hardware config
diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h
index fd7bdfa..130bb55 100644
--- a/arch/arc/include/asm/processor.h
+++ b/arch/arc/include/asm/processor.h
@@ -38,6 +38,9 @@ struct thread_struct {
#ifdef CONFIG_ARC_FPU_SAVE_RESTORE
struct arc_fpu fpu;
#endif
+#ifdef CONFIG_ARC_PLAT_EZNPS
+ struct eznps_dp dp;
+#endif
};
#define INIT_THREAD { \
diff --git a/arch/arc/include/asm/switch_to.h b/arch/arc/include/asm/switch_to.h
index 1b171ab..4c53080 100644
--- a/arch/arc/include/asm/switch_to.h
+++ b/arch/arc/include/asm/switch_to.h
@@ -26,13 +26,24 @@
#endif /* !CONFIG_ARC_FPU_SAVE_RESTORE */
+#ifdef CONFIG_ARC_PLAT_EZNPS
+extern void dp_save_restore(struct task_struct *p, struct task_struct *n);
+#define ARC_DP_PREV(p, n) dp_save_restore(p, n)
+#define ARC_DP_NEXT(t)
+#else
+#define ARC_DP_PREV(p, n)
+#define ARC_DP_NEXT(n)
+#endif /* !CONFIG_ARC_PLAT_EZNPS */
+
struct task_struct *__switch_to(struct task_struct *p, struct task_struct *n);
#define switch_to(prev, next, last)\
do { \
+ ARC_DP_PREV(prev, next);\
ARC_FPU_PREV(prev, next); \
last = __switch_to(prev, next);\
ARC_FPU_NEXT(next); \
+ ARC_DP_NEXT(next); \
mb(); \
} while (0)
diff --git a/arch/arc/plat-eznps/Makefile b/arch/arc/plat-eznps/Makefile
index 21091b1..8d43717 100644
--- a/arch/arc/plat-eznps/Makefile
+++ b/arch/arc/plat-eznps/Makefile
@@ -2,6 +2,6 @@
# Makefile for the linux kernel.
#
-obj-y := entry.o platform.o
+obj-y := entry.o platform.o ctop.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_EZNPS_MTM_EXT) += mtm.o
diff --git a/arch/arc/plat-eznps/ctop.c b/arch/arc/plat-eznps/ctop.c
new file mode 100644
index 000..8b13a08
--- /dev/null
+++ b/arch/arc/plat-eznps/ctop.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include
+#include
+#include
+
+void dp_save_restore(struct task_struct *prev, struct task_struct *next)
+{
+ struct eznps_dp *prev_task_dp = &prev->thread.dp;
+ struct eznps_dp *next_task_dp = &next->thread.dp;
+
+ /* Here we save all Data Plane related auxiliary registers */
+ prev_task_dp->eflags = read_aux_reg(CTOP_AUX_EFLAGS);
+ write_aux_reg(CTOP_AUX_EFLAGS, next_task_dp->eflags);
+
+ prev_task_dp->gpa1 = read_aux_reg(CTOP_AUX_GPA1);
+ write_aux_reg(CTOP_AUX_GPA1, next_task_dp->gpa1);
+}
+
--
1.7.1
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[PATCH 10/11] ARC: [plat-eznps] handle dedicated AUX registers
From: Liav Rehana
Preserve eflags and gpa1 auxiliaries during exception
Registers used by compare exchange instructions.
GPA1 is used for compare value, and EFLAGS got bit reflects
atomic operation response.
EFLAGS is zeroed for each new user task so it won't get its
parent value.
Signed-off-by: Noam Camus
---
arch/arc/include/asm/entry-compact.h | 24
arch/arc/include/asm/ptrace.h|5 +
arch/arc/kernel/process.c|4
3 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/arch/arc/include/asm/entry-compact.h
b/arch/arc/include/asm/entry-compact.h
index 14c310f..9e4458a 100644
--- a/arch/arc/include/asm/entry-compact.h
+++ b/arch/arc/include/asm/entry-compact.h
@@ -192,6 +192,12 @@
PUSHAX lp_start
PUSHAX erbta
+#ifdef CONFIG_ARC_PLAT_EZNPS
+ .word CTOP_INST_SCHD_RW
+ PUSHAX CTOP_AUX_GPA1
+ PUSHAX CTOP_AUX_EFLAGS
+#endif
+`
lr r9, [ecr]
st r9, [sp, PT_event]/* EV_Trap expects r9 to have ECR */
.endm
@@ -208,6 +214,12 @@
* by hardware and that is not good.
*-*/
.macro EXCEPTION_EPILOGUE
+#ifdef CONFIG_ARC_PLAT_EZNPS
+ .word CTOP_INST_SCHD_RW
+ POPAX CTOP_AUX_EFLAGS
+ POPAX CTOP_AUX_GPA1
+#endif
+
POPAX erbta
POPAX lp_start
POPAX lp_end
@@ -265,6 +277,12 @@
PUSHAX lp_end
PUSHAX lp_start
PUSHAX bta_l\LVL\()
+
+#ifdef CONFIG_ARC_PLAT_EZNPS
+ .word CTOP_INST_SCHD_RW
+ PUSHAX CTOP_AUX_GPA1
+ PUSHAX CTOP_AUX_EFLAGS
+#endif
.endm
/*--
@@ -277,6 +295,12 @@
* by hardware and that is not good.
*-*/
.macro INTERRUPT_EPILOGUE LVL
+#ifdef CONFIG_ARC_PLAT_EZNPS
+ .word CTOP_INST_SCHD_RW
+ POPAX CTOP_AUX_EFLAGS
+ POPAX CTOP_AUX_GPA1
+#endif
+
POPAX bta_l\LVL\()
POPAX lp_start
POPAX lp_end
diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h
index 5297faa..5a8cb22 100644
--- a/arch/arc/include/asm/ptrace.h
+++ b/arch/arc/include/asm/ptrace.h
@@ -19,6 +19,11 @@
#ifdef CONFIG_ISA_ARCOMPACT
struct pt_regs {
+#ifdef CONFIG_ARC_PLAT_EZNPS
+ unsigned long eflags; /* Extended FLAGS */
+ unsigned long gpa1; /* General Purpose Aux */
+#endif
+
/* Real registers */
unsigned long bta; /* bta_l1, bta_l2, erbta */
diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c
index 5c631a1..5ac3b54 100644
--- a/arch/arc/kernel/process.c
+++ b/arch/arc/kernel/process.c
@@ -234,6 +234,10 @@ void start_thread(struct pt_regs * regs, unsigned long pc,
unsigned long usp)
*/
regs->status32 = STATUS_U_MASK | STATUS_L_MASK | ISA_INIT_STATUS_BITS;
+#ifdef CONFIG_EZNPS_MTM_EXT
+ regs->eflags = 0;
+#endif
+
/* bogus seed values for debugging */
regs->lp_start = 0x10;
regs->lp_end = 0x80;
--
1.7.1
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[PATCH 07/11] ARC: [plat-eznps] new command line argument for HW scheduler at MTM
From: Noam Camus
We add ability for all cores at NPS SoC to control the number of cycles
HW thread can execute before it is replace with another eligible
HW thread within the same core. The replacement is done by the
HE scheduler.
Signed-off-by: Noam Camus
---
Documentation/admin-guide/kernel-parameters.txt |9
arch/arc/plat-eznps/mtm.c | 49 ++-
2 files changed, 56 insertions(+), 2 deletions(-)
diff --git a/Documentation/admin-guide/kernel-parameters.txt
b/Documentation/admin-guide/kernel-parameters.txt
index 15f79c2..5b551f7 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -2693,6 +2693,15 @@
If the dependencies are under your control, you can
turn on cpu0_hotplug.
+ nps_mtm_hs_ctr= [KNL,ARC]
+ This parameter sets the maximum duration, in
+ cycles, each HW thread of the CTOP can run
+ without interruptions, before HW switches it.
+ The actual maximum duration is 16 times this
+ parameter's value.
+ Format: integer between 1 and 255
+ Default: 255
+
nptcg= [IA-64] Override max number of concurrent global TLB
purges which is reported from either PAL_VM_SUMMARY or
SAL PALO.
diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c
index e0cb36b..f77335a 100644
--- a/arch/arc/plat-eznps/mtm.c
+++ b/arch/arc/plat-eznps/mtm.c
@@ -21,10 +21,13 @@
#include
#include
-#define MT_CTRL_HS_CNT 0xFF
+#define MT_HS_CNT_MIN 0x01
+#define MT_HS_CNT_MAX 0xFF
#define MT_CTRL_ST_CNT 0xF
#define NPS_NUM_HW_THREADS 0x10
+static int mtm_hs_ctr = MT_HS_CNT_MAX;
+
static void mtm_init_nat(int cpu)
{
struct nps_host_reg_mtm_cfg mtm_cfg;
@@ -118,7 +121,7 @@ void mtm_enable_core(unsigned int cpu)
/* Enable HW schedule, stall counter, mtm */
mt_ctrl.value = 0;
mt_ctrl.hsen = 1;
- mt_ctrl.hs_cnt = MT_CTRL_HS_CNT;
+ mt_ctrl.hs_cnt = mtm_hs_ctr;
mt_ctrl.mten = 1;
write_aux_reg(CTOP_AUX_MT_CTRL, mt_ctrl.value);
@@ -129,3 +132,45 @@ void mtm_enable_core(unsigned int cpu)
*/
cpu_relax();
}
+
+/* Handle an out of bounds mtm hs counter value */
+static void __init handle_mtm_hs_ctr_out_of_bounds_error(uint8_t val)
+{
+ pr_err("** The value of mtm_hs_ctr is out of bounds!\n"
+ "** It must be in the range [%d,%d] (inclusive)\n"
+ "Setting mtm_hs_ctr to %d\n", MT_HS_CNT_MIN, MT_HS_CNT_MAX, val);
+
+ mtm_hs_ctr = val;
+}
+
+/* Verify and set the value of the mtm hs counter */
+static int __init set_mtm_hs_ctr(char *ctr_str)
+{
+ int ret;
+ long hs_ctr;
+
+ ret = kstrtol(ctr_str, 0, &hs_ctr);
+ if (ret) {
+ pr_err("** Error parsing the value of mtm_hs_ctr\n"
+ "** Make sure you entered a valid integer value\n"
+ "Setting mtm_hs_ctr to default value: %d\n",
+ MT_HS_CNT_MAX);
+ mtm_hs_ctr = MT_HS_CNT_MAX;
+ return -EINVAL;
+ }
+
+ if (hs_ctr > MT_HS_CNT_MAX) {
+ handle_mtm_hs_ctr_out_of_bounds_error(MT_HS_CNT_MAX);
+ return -EDOM;
+ }
+
+ if (hs_ctr < MT_HS_CNT_MIN) {
+ handle_mtm_hs_ctr_out_of_bounds_error(MT_HS_CNT_MIN);
+ return -EDOM;
+ }
+
+ mtm_hs_ctr = hs_ctr;
+
+ return 0;
+}
+early_param("nps_mtm_hs_ctr", set_mtm_hs_ctr);
--
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[PATCH 05/11] ARC: Support more than one PGDIR for KVADDR
From: Noam Camus This way FIXMAP can have 2 PTEs per CPU even for NR_CPUS=4096 For the extreme case like in eznps platform We use all gutter between kernel and user. Signed-off-by: Noam Camus --- arch/arc/Kconfig | 11 +++ arch/arc/include/asm/highmem.h |8 +--- arch/arc/include/asm/pgtable.h |9 + arch/arc/include/asm/processor.h |5 +++-- arch/arc/mm/fault.c |8 arch/arc/mm/highmem.c| 16 +++- arch/arc/mm/tlbex.S | 31 +++ 7 files changed, 78 insertions(+), 10 deletions(-) diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index b759be1..54ba8e6 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -478,6 +478,17 @@ config ARC_HAS_PAE40 Enable access to physical memory beyond 4G, only supported on ARC cores with 40 bit Physical Addressing support +config HIGHMEM_PGDS_SHIFT + int "log num of PGDs for HIGHMEM" + range 0 5 + default "0" if !ARC_PLAT_EZNPS || !HIGHMEM + default "5" if ARC_PLAT_EZNPS + help + This way we can map more pages for HIGHMEM. + Single PGD (2M) is supporting 256 PTEs (8K PAGE_SIZE) + For FIXMAP where at least 2 PTEs are needed per CPU + large NR_CPUS e.g. 4096 will consume 32 PGDs + config ARCH_PHYS_ADDR_T_64BIT def_bool ARC_HAS_PAE40 diff --git a/arch/arc/include/asm/highmem.h b/arch/arc/include/asm/highmem.h index b1585c9..c5cb473 100644 --- a/arch/arc/include/asm/highmem.h +++ b/arch/arc/include/asm/highmem.h @@ -17,13 +17,13 @@ /* start after vmalloc area */ #define FIXMAP_BASE(PAGE_OFFSET - FIXMAP_SIZE - PKMAP_SIZE) -#define FIXMAP_SIZEPGDIR_SIZE /* only 1 PGD worth */ -#define KM_TYPE_NR ((FIXMAP_SIZE >> PAGE_SHIFT)/NR_CPUS) +#define FIXMAP_SIZE(PGDIR_SIZE * _BITUL(CONFIG_HIGHMEM_PGDS_SHIFT)) +#define KM_TYPE_NR (((FIXMAP_SIZE >> PAGE_SHIFT)/NR_CPUS) > 2 ?: 2) #define FIXMAP_ADDR(nr)(FIXMAP_BASE + ((nr) << PAGE_SHIFT)) /* start after fixmap area */ #define PKMAP_BASE (FIXMAP_BASE + FIXMAP_SIZE) -#define PKMAP_SIZE PGDIR_SIZE +#define PKMAP_SIZE (PGDIR_SIZE * _BITUL(CONFIG_HIGHMEM_PGDS_SHIFT)) #define LAST_PKMAP (PKMAP_SIZE >> PAGE_SHIFT) #define LAST_PKMAP_MASK(LAST_PKMAP - 1) #define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT)) @@ -32,6 +32,7 @@ #define kmap_prot PAGE_KERNEL +#ifndef __ASSEMBLY__ #include extern void *kmap(struct page *page); @@ -54,6 +55,7 @@ static inline void kunmap(struct page *page) return; kunmap_high(page); } +#endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h index 08fe338..d08e207 100644 --- a/arch/arc/include/asm/pgtable.h +++ b/arch/arc/include/asm/pgtable.h @@ -224,6 +224,8 @@ #definePTRS_PER_PTE_BITUL(BITS_FOR_PTE) #definePTRS_PER_PGD_BITUL(BITS_FOR_PGD) +#define PTRS_HMEM_PTE _BITUL(BITS_FOR_PTE + CONFIG_HIGHMEM_PGDS_SHIFT) + /* * Number of entries a user land program use. * TASK_SIZE is the maximum vaddr that can be used by a userland program. @@ -285,7 +287,14 @@ static inline void pmd_set(pmd_t *pmdp, pte_t *ptep) /* Don't use virt_to_pfn for macros below: could cause truncations for PAE40*/ #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) +#if CONFIG_HIGHMEM_PGDS_SHIFT +#define __pte_index(addr) (((addr) >= VMALLOC_END) ? \ + (((addr) >> PAGE_SHIFT) & (PTRS_HMEM_PTE - 1)) \ + : \ + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) +#else #define __pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) +#endif /* * pte_offset gets a @ptr to PMD entry (PGD in our 2-tier paging system) diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h index 6e1242d..fd7bdfa 100644 --- a/arch/arc/include/asm/processor.h +++ b/arch/arc/include/asm/processor.h @@ -121,8 +121,9 @@ extern void start_thread(struct pt_regs * regs, unsigned long pc, #define VMALLOC_START (PAGE_OFFSET - (CONFIG_ARC_KVADDR_SIZE << 20)) -/* 1 PGDIR_SIZE each for fixmap/pkmap, 2 PGDIR_SIZE gutter (see asm/highmem.h) */ -#define VMALLOC_SIZE ((CONFIG_ARC_KVADDR_SIZE << 20) - PGDIR_SIZE * 4) +/* 1 << CONFIG_HIGHMEM_PGDS_SHIFT PGDIR_SIZE each for fixmap/pkmap */ +#define VMALLOC_SIZE ((CONFIG_ARC_KVADDR_SIZE << 20) - \ + PGDIR_SIZE * _BITUL(CONFIG_HIGHMEM_PGDS_SHIFT) * 2) #define VMALLOC_END(VMALLOC_START + VMALLOC_SIZE) diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c index a0b7bd6..fd89c9a 100644 --- a/arch/arc/mm/fault.c +++ b/arch/arc/mm/fault.c @@ -17,6 +17,7 @@
[PATCH 04/11] ARC: Add CPU topology
From: Noam Camus
Now it is used for NPS SoC for multi-core of 256 cores
and SMT of 16 HW threads per core.
This way with topology the scheduler is much efficient in
creating domains and later using them.
Signed-off-by: Noam Camus
---
arch/arc/Kconfig| 27
arch/arc/include/asm/Kbuild |1 -
arch/arc/include/asm/topology.h | 34 +++
arch/arc/kernel/Makefile|1 +
arch/arc/kernel/setup.c |4 +-
arch/arc/kernel/smp.c |5 ++
arch/arc/kernel/topology.c | 125 +++
7 files changed, 194 insertions(+), 3 deletions(-)
create mode 100644 arch/arc/include/asm/topology.h
create mode 100644 arch/arc/kernel/topology.c
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index dc1df6f..b759be1 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -203,6 +203,33 @@ config ARC_SMP_HALT_ON_RESET
at designated entry point. For other case, all jump to common
entry point and spin wait for Master's signal.
+config NPS_CPU_TOPOLOGY
+ bool "Support cpu topology definition"
+ depends on EZNPS_MTM_EXT
+ default y
+ help
+ Support NPS cpu topology definition.
+ NPS400 got 16 clusters of cores.
+ NPS400 cluster got 16 cores.
+ NPS core got 16 symetrical threads.
+ Totally there are such 4096 threads (NR_CPUS=4096)
+
+config SCHED_MC
+ bool "Multi-core scheduler support"
+ depends on NPS_CPU_TOPOLOGY
+ help
+ Multi-core scheduler support improves the CPU scheduler's decision
+ making when dealing with multi-core CPU chips at a cost of slightly
+ increased overhead in some places. If unsure say N here.
+
+config SCHED_SMT
+ bool "SMT scheduler support"
+ depends on NPS_CPU_TOPOLOGY
+ help
+ Improves the CPU scheduler's decision making when dealing with
+ MultiThreading at a cost of slightly increased overhead in some
+ places. If unsure say N here.
+
endif #SMP
config ARC_MCIP
diff --git a/arch/arc/include/asm/Kbuild b/arch/arc/include/asm/Kbuild
index 7bee4e4..d8cb607 100644
--- a/arch/arc/include/asm/Kbuild
+++ b/arch/arc/include/asm/Kbuild
@@ -43,7 +43,6 @@ generic-y += stat.h
generic-y += statfs.h
generic-y += termbits.h
generic-y += termios.h
-generic-y += topology.h
generic-y += trace_clock.h
generic-y += types.h
generic-y += ucontext.h
diff --git a/arch/arc/include/asm/topology.h b/arch/arc/include/asm/topology.h
new file mode 100644
index 000..a9be3f8
--- /dev/null
+++ b/arch/arc/include/asm/topology.h
@@ -0,0 +1,34 @@
+#ifndef _ASM_ARC_TOPOLOGY_H
+#define _ASM_ARC_TOPOLOGY_H
+
+#ifdef CONFIG_NPS_CPU_TOPOLOGY
+
+#include
+
+struct cputopo_nps {
+ int thread_id;
+ int core_id;
+ cpumask_t thread_sibling;
+ cpumask_t core_sibling;
+};
+
+extern struct cputopo_nps cpu_topology[NR_CPUS];
+
+#define topology_core_id(cpu) (cpu_topology[cpu].core_id)
+#define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling)
+#define topology_sibling_cpumask(cpu) (&cpu_topology[cpu].thread_sibling)
+
+void init_cpu_topology(void);
+void store_cpu_topology(unsigned int cpuid);
+const struct cpumask *cpu_coregroup_mask(int cpu);
+
+#else
+
+static inline void init_cpu_topology(void) { }
+static inline void store_cpu_topology(unsigned int cpuid) { }
+
+#endif
+
+#include
+
+#endif /* _ASM_ARC_TOPOLOGY_H */
diff --git a/arch/arc/kernel/Makefile b/arch/arc/kernel/Makefile
index 8942c5c..46af80a 100644
--- a/arch/arc/kernel/Makefile
+++ b/arch/arc/kernel/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_ARC_EMUL_UNALIGNED) += unaligned.o
obj-$(CONFIG_KGDB) += kgdb.o
obj-$(CONFIG_ARC_METAWARE_HLINK) += arc_hostlink.o
obj-$(CONFIG_PERF_EVENTS) += perf_event.o
+obj-$(CONFIG_NPS_CPU_TOPOLOGY) += topology.o
obj-$(CONFIG_ARC_FPU_SAVE_RESTORE) += fpu.o
CFLAGS_fpu.o += -mdpfp
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 8494b31..5256205 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -571,14 +571,14 @@ static void c_stop(struct seq_file *m, void *v)
.show = show_cpuinfo
};
-static DEFINE_PER_CPU(struct cpu, cpu_topology);
+static DEFINE_PER_CPU(struct cpu, cpu_topo_info);
static int __init topology_init(void)
{
int cpu;
for_each_present_cpu(cpu)
- register_cpu(&per_cpu(cpu_topology, cpu), cpu);
+ register_cpu(&per_cpu(cpu_topo_info, cpu), cpu);
return 0;
}
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index d1aa917..167a620 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -67,6 +67,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
{
int i;
+ init_cpu_topology();
+ store_cpu_topology(smp_processor_id());
+
/*
* if platform didn't set the present map already, do it n
[PATCH 03/11] ARC: Allow irq threading
From: Noam Camus Working with NPS400 we noticed that there is a possibility of L1 interrupt nesting that may run out kernel stack. The scenario include serving invoke_softirqs() from irq_exit() and once local_irq_enable() called can hit another one before we managed to restore last one and pop some place from kernel stack. Serving softirqs at dedicated kernel thread may mitigate this. We see that many architectures, including x86, behave like this. Note 1: All interrupts which must be non threaded should be marked IRQF_NO_THREAD. Note 2: using kernel param "threadirqs" is needed to actually turn this on. This configuration is only a preperation. Signed-off-by: Noam Camus --- arch/arc/Kconfig |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 92c9128..dc1df6f 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -33,6 +33,7 @@ config ARC select HAVE_OPROFILE select HAVE_PERF_EVENTS select HANDLE_DOMAIN_IRQ + select IRQ_FORCED_THREADING select IRQ_DOMAIN select MODULES_USE_ELF_RELA select NO_BOOTMEM -- 1.7.1 ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH 01/11] ARC: set level of log per CPU during boot to be debug level
From: Noam Camus
The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
scale machines such NPS400
Signed-off-by: Noam Camus
---
arch/arc/kernel/setup.c |6 +++---
arch/arc/kernel/smp.c |4 ++--
arch/arc/mm/cache.c |2 +-
arch/arc/mm/tlb.c |2 +-
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index fc8211f..8494b31 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -385,13 +385,13 @@ void setup_processor(void)
read_arc_build_cfg_regs();
arc_init_IRQ();
- printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
+ pr_debug("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
arc_mmu_init();
arc_cache_init();
- printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
- printk(arc_platform_smp_cpuinfo());
+ pr_debug("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
+ pr_debug("%s", arc_platform_smp_cpuinfo());
arc_chk_core_config();
}
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index f462671..d1aa917 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -177,8 +177,8 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
secondary_idle_tsk = idle;
- pr_info("Idle Task [%d] %p", cpu, idle);
- pr_info("Trying to bring up CPU%u ...\n", cpu);
+ pr_debug("Idle Task [%d] %p", cpu, idle);
+ pr_debug("Trying to bring up CPU%u ...\n", cpu);
if (plat_smp_ops.cpu_kick)
plat_smp_ops.cpu_kick(cpu,
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 3329d0d..15bc3e3 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -1188,7 +1188,7 @@ void __ref arc_cache_init(void)
unsigned int __maybe_unused cpu = smp_processor_id();
char str[256];
- printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
+ pr_debug("%s", arc_cache_mumbojumbo(0, str, sizeof(str)));
/*
* Only master CPU needs to execute rest of function:
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index d0126fd..c5e70d8 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -814,7 +814,7 @@ void arc_mmu_init(void)
char str[256];
struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
- printk(arc_mmu_mumbojumbo(0, str, sizeof(str)));
+ pr_debug("%s", arc_mmu_mumbojumbo(0, str, sizeof(str)));
/*
* Can't be done in processor.h due to header include depenedencies
--
1.7.1
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[PATCH 11/11] ARC: [plat-eznps] avoid toggling of DPC register
From: Elad Kanfi HW bug description: in case of HW thread context switch the dpc configuration of the exiting thread is dragged one cycle into the next thread. In order to avoid the consequences of this bug, the DPC register is set to an initial value, and not changed afterwards. Signed-off-by: Elad Kanfi Signed-off-by: Noam Camus --- arch/arc/plat-eznps/include/plat/ctop.h |1 + arch/arc/plat-eznps/mtm.c | 12 2 files changed, 13 insertions(+), 0 deletions(-) diff --git a/arch/arc/plat-eznps/include/plat/ctop.h b/arch/arc/plat-eznps/include/plat/ctop.h index 7729d3d..0c7d110 100644 --- a/arch/arc/plat-eznps/include/plat/ctop.h +++ b/arch/arc/plat-eznps/include/plat/ctop.h @@ -39,6 +39,7 @@ #define CTOP_AUX_LOGIC_CORE_ID (CTOP_AUX_BASE + 0x018) #define CTOP_AUX_MT_CTRL (CTOP_AUX_BASE + 0x020) #define CTOP_AUX_HW_COMPLY (CTOP_AUX_BASE + 0x024) +#define CTOP_AUX_DPC (CTOP_AUX_BASE + 0x02C) #define CTOP_AUX_LPC (CTOP_AUX_BASE + 0x030) #define CTOP_AUX_EFLAGS(CTOP_AUX_BASE + 0x080) #define CTOP_AUX_IACK (CTOP_AUX_BASE + 0x088) diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c index f77335a..3c7dec9 100644 --- a/arch/arc/plat-eznps/mtm.c +++ b/arch/arc/plat-eznps/mtm.c @@ -101,6 +101,18 @@ void mtm_enable_core(unsigned int cpu) int i; struct nps_host_reg_aux_mt_ctrl mt_ctrl; struct nps_host_reg_mtm_cfg mtm_cfg; + struct nps_host_reg_aux_dpc dpc; + + /* +* Initializing dpc register in each CPU. +* Overwriting the init value of the DPC +* register so that CMEM and FMT virtual address +* spaces are accessible, and Data Plane HW +* facilities are enabled. +*/ + dpc.ien = 1; + dpc.men = 1; + write_aux_reg(CTOP_AUX_DPC, dpc.value); if (NPS_CPU_TO_THREAD_NUM(cpu) != 0) return; -- 1.7.1 ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH 00/11] plat-eznps upstream cont. set 2
From: Noam Camus With this patch set I continue the effort of upstreaming the eznps platform for arch/arc. It comprise of couple of patches from last set yet not accepted, patches for HW erratas and some misc extensions such for HIGHMEM / NUMA. This set got more generic ARC changes than previous set. Additional ifdef seem like unavoidable, however it may seem Ugly. Let's see if we need to do it more elegant. Elad Kanfi (1): ARC: [plat-eznps] avoid toggling of DPC register Liav Rehana (2): ARC: [plat-eznps] Update the init sequence of aux regs per cpu. ARC: [plat-eznps] handle dedicated AUX registers Noam Camus (8): ARC: set level of log per CPU during boot to be debug level ARC: send ipi to all cpus sharing task mm in case of page fault ARC: Allow irq threading ARC: Add CPU topology ARC: Support more than one PGDIR for KVADDR ARC: [NUMA] added CONFIG_NUMA for plat-eznps ARC: [plat-eznps] new command line argument for HW scheduler at MTM ARC: [plat-eznps] Save/Restore extra auxiliary registers Documentation/admin-guide/kernel-parameters.txt |9 ++ arch/arc/Kconfig| 48 + arch/arc/include/asm/Kbuild |1 - arch/arc/include/asm/arcregs.h |7 ++ arch/arc/include/asm/cacheflush.h |3 +- arch/arc/include/asm/entry-compact.h| 24 + arch/arc/include/asm/highmem.h |8 +- arch/arc/include/asm/pgtable.h |9 ++ arch/arc/include/asm/processor.h|8 +- arch/arc/include/asm/ptrace.h |5 + arch/arc/include/asm/switch_to.h| 11 ++ arch/arc/include/asm/topology.h | 40 +++ arch/arc/kernel/Makefile|1 + arch/arc/kernel/process.c |4 + arch/arc/kernel/setup.c | 13 ++- arch/arc/kernel/smp.c |9 ++- arch/arc/kernel/topology.c | 125 +++ arch/arc/mm/cache.c | 14 ++- arch/arc/mm/fault.c |8 ++ arch/arc/mm/highmem.c | 16 ++- arch/arc/mm/init.c |6 + arch/arc/mm/tlb.c |4 +- arch/arc/mm/tlbex.S | 31 ++ arch/arc/plat-eznps/Kconfig | 11 ++ arch/arc/plat-eznps/Makefile|2 +- arch/arc/plat-eznps/ctop.c | 33 ++ arch/arc/plat-eznps/entry.S |2 +- arch/arc/plat-eznps/include/plat/ctop.h |1 + arch/arc/plat-eznps/mtm.c | 61 +++- 29 files changed, 486 insertions(+), 28 deletions(-) create mode 100644 arch/arc/include/asm/topology.h create mode 100644 arch/arc/kernel/topology.c create mode 100644 arch/arc/plat-eznps/ctop.c ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH 06/11] ARC: [NUMA] added CONFIG_NUMA for plat-eznps
From: Noam Camus
This is needed for NPS400 where high memory is assigned to node1
where the associated addresses are lower than node0.
This use case is not typical and just using discontigmem is not enough
since nodes assumed to have increasing address range.
i.e. address range of node0 assumed to be lower than node1.
Signed-off-by: Noam Camus
---
arch/arc/Kconfig|9 +
arch/arc/include/asm/topology.h |6 ++
arch/arc/kernel/setup.c |3 +++
arch/arc/mm/init.c |6 ++
4 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 54ba8e6..d1bbfd3 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -379,6 +379,15 @@ config ARC_HUGEPAGE_16M
endchoice
+config NUMA
+ bool "NUMA Memory Allocation and Scheduler Support"
+ depends on SMP && DISCONTIGMEM
+ default y if ARC_PLAT_EZNPS
+ ---help---
+ NUMA memory allocation is required for NPS400 processors.
+ The reason is that node1 in NPS400 is assigned to lower
+ addresses than node0, which is not typical scenario.
+
config NODES_SHIFT
int "Maximum NUMA Nodes (as a power of 2)"
default "0" if !DISCONTIGMEM
diff --git a/arch/arc/include/asm/topology.h b/arch/arc/include/asm/topology.h
index a9be3f8..dfbc2ab 100644
--- a/arch/arc/include/asm/topology.h
+++ b/arch/arc/include/asm/topology.h
@@ -1,6 +1,12 @@
#ifndef _ASM_ARC_TOPOLOGY_H
#define _ASM_ARC_TOPOLOGY_H
+#ifdef CONFIG_NUMA
+#define cpu_to_node(cpu) ((void)(cpu), 0)
+#define parent_node(node) (node)
+#define cpumask_of_node(node) ((void)node, cpu_online_mask)
+#endif
+
#ifdef CONFIG_NPS_CPU_TOPOLOGY
#include
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 5256205..5f04635 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -577,6 +577,9 @@ static int __init topology_init(void)
{
int cpu;
+ for_each_online_node(cpu)
+ register_one_node(cpu);
+
for_each_present_cpu(cpu)
register_cpu(&per_cpu(cpu_topo_info, cpu), cpu);
diff --git a/arch/arc/mm/init.c b/arch/arc/mm/init.c
index 8c9415e..f9f80d9 100644
--- a/arch/arc/mm/init.c
+++ b/arch/arc/mm/init.c
@@ -113,6 +113,10 @@ void __init setup_arch_memory(void)
init_mm.end_data = (unsigned long)_edata;
init_mm.brk = (unsigned long)_end;
+ node_set_online(0);
+ node_set_state(0, N_MEMORY);
+ node_set_state(0, N_NORMAL_MEMORY);
+
/* first page of system - kernel .vector starts here */
min_low_pfn = ARCH_PFN_OFFSET;
@@ -182,6 +186,8 @@ void __init setup_arch_memory(void)
* populated with normal memory zone while node 1 only has highmem
*/
node_set_online(1);
+ node_set_state(1, N_MEMORY);
+ node_set_state(1, N_HIGH_MEMORY);
min_high_pfn = PFN_DOWN(high_mem_start);
max_high_pfn = PFN_DOWN(high_mem_start + high_mem_sz);
--
1.7.1
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[RFC] arc: Decouple linux kernel memory address and link address
We faced with problem when we tried to utilize 1G DRAM by linux on
HSDK.
We can't use our usual kernel memory address (0x8000) like on
AXS103 because of DCCM memory bank located at exactly same
address (0x8000)
But we can't simply move kernel memory address to another address (like
0x9000) because IOC base address must be aligned to the
size of the aperture as specified in the IOC size register.
So we had to use 1G aligned address for kernel memory.
We can't use 0x or 0x4000 addresses because addresses
lover then 0x8000 are MMU-translated.
We can't use 0xB000 address because we can define a volatile
uncached region only from AUX_NON_VOLATILE_LIMIT to the
0x. (the end of region is hardcoded)
So, the decision is to link kernel to 0x9000, but use
0x8000-0xBFFF memory region and reallocate DCCM in our platform
code.
This patch only makes possible to set kernel memory address not equal to
kernel link address.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/Kconfig| 5 +
arch/arc/boot/dts/hsdk.dts | 2 +-
arch/arc/include/asm/page.h | 2 +-
arch/arc/mm/cache.c | 2 +-
arch/arc/mm/init.c | 4 ++--
5 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 92c9128..825a112 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -431,6 +431,11 @@ config LINUX_LINK_BASE
However some customers have peripherals mapped at this addr, so
Linux needs to be scooted a bit.
If you don't know what the above means, leave this setting alone.
+
+config KERNEL_RAM_BASE_ADDRESS
+ hex "Linux ram base address"
+ default LINUX_LINK_BASE
+ help
This needs to match memory start address specified in Device Tree
config HIGHMEM
diff --git a/arch/arc/boot/dts/hsdk.dts b/arch/arc/boot/dts/hsdk.dts
index fb1a32f..57cb47d 100644
--- a/arch/arc/boot/dts/hsdk.dts
+++ b/arch/arc/boot/dts/hsdk.dts
@@ -145,6 +145,6 @@
#address-cells = <1>;
#size-cells = <1>;
device_type = "memory";
- reg = <0x9000 0x4000>; /* 1 GB */
+ reg = <0x8000 0x4000>; /* 1 GB */
};
};
diff --git a/arch/arc/include/asm/page.h b/arch/arc/include/asm/page.h
index 296c342..777f676 100644
--- a/arch/arc/include/asm/page.h
+++ b/arch/arc/include/asm/page.h
@@ -85,7 +85,7 @@ typedef pte_t * pgtable_t;
*/
#define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT)
-#define ARCH_PFN_OFFSETvirt_to_pfn(CONFIG_LINUX_LINK_BASE)
+#define ARCH_PFN_OFFSET
virt_to_pfn(CONFIG_KERNEL_RAM_BASE_ADDRESS)
#ifdef CONFIG_FLATMEM
#define pfn_valid(pfn) (((pfn) - ARCH_PFN_OFFSET) < max_mapnr)
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 3329d0d..9809e7e 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -1093,7 +1093,7 @@ noinline void __init arc_ioc_setup(void)
slc_entire_op(OP_FLUSH_N_INV);
/* IOC Aperture start */
- write_aux_reg(ARC_REG_IO_COH_AP0_BASE, CONFIG_LINUX_LINK_BASE >> 12);
+ write_aux_reg(ARC_REG_IO_COH_AP0_BASE, CONFIG_KERNEL_RAM_BASE_ADDRESS
>> 12);
/*
* IOC Aperture size:
diff --git a/arch/arc/mm/init.c b/arch/arc/mm/init.c
index 8c9415e..d4ad9fc 100644
--- a/arch/arc/mm/init.c
+++ b/arch/arc/mm/init.c
@@ -26,7 +26,7 @@ pgd_t swapper_pg_dir[PTRS_PER_PGD] __aligned(PAGE_SIZE);
char empty_zero_page[PAGE_SIZE] __aligned(PAGE_SIZE);
EXPORT_SYMBOL(empty_zero_page);
-static const unsigned long low_mem_start = CONFIG_LINUX_LINK_BASE;
+static const unsigned long low_mem_start = CONFIG_KERNEL_RAM_BASE_ADDRESS;
static unsigned long low_mem_sz;
#ifdef CONFIG_HIGHMEM
@@ -63,7 +63,7 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size)
if (!low_mem_sz) {
if (base != low_mem_start)
- panic("CONFIG_LINUX_LINK_BASE != DT memory { }");
+ panic("CONFIG_KERNEL_RAM_BASE_ADDRESS != DT memory {
}");
low_mem_sz = size;
in_use = 1;
--
2.9.3
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[PATCH 00/35] defconfig: Cleanup from old entries
Hi, While cleaning Samsung ARM defconfigs with savedefconfig, I encountered similar obsolete entries in other files. Except the ARM, no dependencies. For ARM, the rest of patches depend on the first change (otherwise it might not apply cleanly). Best regards, Krzysztof Krzysztof Kozlowski (35): ARM: defconfig: Cleanup from old Kconfig options MIPS: defconfig: Cleanup from old Kconfig options blackfin: defconfig: Cleanup from old Kconfig options c6x: defconfig: Cleanup from old Kconfig options m32r: defconfig: Cleanup from old Kconfig options sh: defconfig: Cleanup from old Kconfig options x86: defconfig: Cleanup from old Kconfig options cris: defconfig: Cleanup from old Kconfig options parisc: defconfig: Cleanup from old Kconfig options sparc: defconfig: Cleanup from old Kconfig options hexagon: defconfig: Cleanup from old Kconfig options microblaze: defconfig: Cleanup from old Kconfig options mn10300: defconfig: Cleanup from old Kconfig options score: defconfig: Cleanup from old Kconfig options unicore32: defconfig: Cleanup from old Kconfig options alpha: defconfig: Cleanup from old Kconfig options ARC: defconfig: Cleanup from old Kconfig options m68k: defconfig: Cleanup from old Kconfig options nios2: defconfig: Cleanup from old Kconfig options openrisc: defconfig: Cleanup from old Kconfig options powerpc: defconfig: Cleanup from old Kconfig options um: defconfig: Cleanup from old Kconfig options tile: defconfig: Cleanup from old Kconfig options ARM: defconfig: samsung: Re-order entries to match savedefconfig ARM: mini2440_defconfig: Bring back lost (but wanted) options ARM: tct_hammer_defconfig: Bring back lost (but wanted) options ARM: s3c2410_defconfig: Bring back lost (but wanted) options ARM: s3c6400_defconfig: Bring back lost (but wanted) options ARM: s5pv210_defconfig: Bring back lost (but wanted) options ARM: exynos_defconfig: Save defconfig ARM: s3c2410_defconfig: Save defconfig ARM: mini2440_defconfig: Save defconfig ARM: s3c6400_defconfig: Save defconfig ARM: s5pv210_defconfig: Save defconfig ARM: tct_hammer_defconfig: Save defconfig arch/alpha/defconfig | 2 - arch/arc/configs/nps_defconfig| 1 - arch/arc/configs/tb10x_defconfig | 1 - arch/arm/configs/acs5k_defconfig | 8 -- arch/arm/configs/acs5k_tiny_defconfig | 10 --- arch/arm/configs/am200epdkit_defconfig| 7 -- arch/arm/configs/assabet_defconfig| 3 - arch/arm/configs/axm55xx_defconfig| 1 - arch/arm/configs/badge4_defconfig | 5 -- arch/arm/configs/cerfcube_defconfig | 4 - arch/arm/configs/cm_x2xx_defconfig| 13 arch/arm/configs/cm_x300_defconfig| 10 --- arch/arm/configs/cns3420vb_defconfig | 7 -- arch/arm/configs/colibri_pxa270_defconfig | 13 arch/arm/configs/colibri_pxa300_defconfig | 9 --- arch/arm/configs/collie_defconfig | 4 - arch/arm/configs/corgi_defconfig | 13 arch/arm/configs/dove_defconfig | 1 - arch/arm/configs/ebsa110_defconfig| 1 - arch/arm/configs/efm32_defconfig | 1 - arch/arm/configs/em_x270_defconfig| 13 arch/arm/configs/ep93xx_defconfig | 1 - arch/arm/configs/eseries_pxa_defconfig| 8 -- arch/arm/configs/exynos_defconfig | 6 +- arch/arm/configs/ezx_defconfig| 18 - arch/arm/configs/footbridge_defconfig | 1 - arch/arm/configs/h5000_defconfig | 6 -- arch/arm/configs/hackkit_defconfig| 3 - arch/arm/configs/imote2_defconfig | 16 arch/arm/configs/imx_v4_v5_defconfig | 1 - arch/arm/configs/iop13xx_defconfig| 4 - arch/arm/configs/iop32x_defconfig | 5 -- arch/arm/configs/iop33x_defconfig | 6 -- arch/arm/configs/ixp4xx_defconfig | 9 --- arch/arm/configs/jornada720_defconfig | 8 -- arch/arm/configs/ks8695_defconfig | 7 -- arch/arm/configs/lart_defconfig | 3 - arch/arm/configs/lpc18xx_defconfig| 1 - arch/arm/configs/lpd270_defconfig | 5 -- arch/arm/configs/lubbock_defconfig| 4 - arch/arm/configs/magician_defconfig | 15 arch/arm/configs/mainstone_defconfig | 4 - arch/arm/configs/mini2440_defconfig | 91 +++ arch/arm/configs/mmp2_defconfig | 9 --- arch/arm/configs/moxart_defconfig | 1 - arch/arm/configs/mps2_defconfig | 1 - arch/arm/configs/mv78xx0_defconfig| 8 -- arch/arm/configs/mxs_defconfig
[PATCH 17/35] ARC: defconfig: Cleanup from old Kconfig options
Remove old, dead Kconfig option INET_LRO. It is gone since
commit 7bbf3cae65b6 ("ipv4: Remove inet_lro library").
Signed-off-by: Krzysztof Kozlowski
---
arch/arc/configs/nps_defconfig | 1 -
arch/arc/configs/tb10x_defconfig | 1 -
2 files changed, 2 deletions(-)
diff --git a/arch/arc/configs/nps_defconfig b/arch/arc/configs/nps_defconfig
index ede625c76216..7c9c706ae7f6 100644
--- a/arch/arc/configs/nps_defconfig
+++ b/arch/arc/configs/nps_defconfig
@@ -39,7 +39,6 @@ CONFIG_IP_PNP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
diff --git a/arch/arc/configs/tb10x_defconfig b/arch/arc/configs/tb10x_defconfig
index 4c5118384eb5..f30182549395 100644
--- a/arch/arc/configs/tb10x_defconfig
+++ b/arch/arc/configs/tb10x_defconfig
@@ -38,7 +38,6 @@ CONFIG_IP_MULTICAST=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
--
2.9.3
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Re: [PATCH 17/35] ARC: defconfig: Cleanup from old Kconfig options
On 06/08/2017 09:10 AM, Krzysztof Kozlowski wrote:
Remove old, dead Kconfig option INET_LRO. It is gone since
commit 7bbf3cae65b6 ("ipv4: Remove inet_lro library").
Signed-off-by: Krzysztof Kozlowski
Acked-by: vineet Gupta
Do you want me to pick this up via ARC tree ?
Thx,
-Vineet
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Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception
On 06/07/2017 08:29 PM, Noam Camus wrote: *From:* Noam Camus *Sent:* Wednesday, June 7, 2017 8:06:17 PM *To:* Vineet Gupta; linux-snps-arc@lists.infradead.org *Cc:* linux-ker...@vger.kernel.org; Elad Kanfi *Subject:* Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception *> From:*Vineet Gupta *> Sent:* Wednesday, June 7, 2017 7:15 PM... > So NPS *hardware* generates exception, jumps to vector mem_service(), which you > redirect to the machine check handler - which simply panics. > But this redirection is under EZNPS_MEM_ERROR, which you have defaulted to "n". So > how is the default working for hardware ? Doesn't it need to be "y" The NPS400 architects changed userspace bus error behavior to be machine check instead of Interrupt level 2. The reason was that since we are dealing with imprecise exception. So memory request result will be back to core long time after bad instruction was executed. In the meantime core be able to do HW schedule between threads and result may hit another thread. The core do not keep information on each such bus transaction so it just interfere current thread without knowing if it was the initiator of this bus transaction. In such case we prefer to create machine check and end with PANIC. Ok this make sense ! With simulator we just turn this configuration on, so we redirect the Legacy Synopsys L2 ISR from nSIM into machine check. This way we end up just like with silicon 😊 This doesn't make sense :-) In simulation (where L2 interrupt is asserted), you need to handle it as such - say reading out the banked regs for L2 interrupt. What you are doing here is handling it like an exception which won't work . I really don't see the point of this "alignment" - hardware and simulation are different. simulation semantics are already supported by generic ARC code. And for silicon case, the existing vector woudl MachineCheck would work for both K and U. So I'm not sure what we are trying to achieve here ! >BTW it seems your patch is wrong otherwise too. So the userspace bus error will go >to machine check handler which currently just panic's. You really want to kill the >user space process and continue, thus need to call do_memory_error() So I believe that we do correct thing here, when we deal with multi thread cores. Sure, the imprecise handling of bus error is an issue - but we should atleat try to recover. By just panic'ing unconditionally, you are enabling a one liner user program to panic the system (granted in simulation only) -Vineet ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [PATCH 17/35] ARC: defconfig: Cleanup from old Kconfig options
On Thu, Jun 08, 2017 at 09:31:54AM -0700, Vineet Gupta wrote:
> On 06/08/2017 09:10 AM, Krzysztof Kozlowski wrote:
> > Remove old, dead Kconfig option INET_LRO. It is gone since
> > commit 7bbf3cae65b6 ("ipv4: Remove inet_lro library").
> >
> > Signed-off-by: Krzysztof Kozlowski
>
> Acked-by: vineet Gupta
>
> Do you want me to pick this up via ARC tree ?
Yes, please.
Best regards,
Krzysztof
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Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception
On 06/08/2017 11:23 AM, Noam Camus wrote: *> From:* Vineet Gupta *> Sent:* Thursday, June 8, 2017 7:38 PM >> >> With simulator we just turn this configuration on, so we redirect the Legacy >> Synopsys L2 ISR from nSIM into machine check. >> This way we end up just like with silicon 😊 >This doesn't make sense :-) >In simulation (where L2 interrupt is asserted), you need to handle it as such - >say reading out the banked regs for L2 interrupt. What you are doing here is >handling it like an exception which won't work . I really don't see the point of >this "alignment" - hardware and simulation are different. simulation semantics are >already supported by generic ARC code. And for silicon case, the existing vector >woudl MachineCheck would work for both K and U. So I'm not sure what we are trying >to achieve here ! With EZsim we try to simulate NPS400 CTOP core and not ARC core, and as such we strive to have similar echo system for both silicon and its simulator. Right, but if you are using nSIM which generates L2 interrupt for user mode error - then it is already different from silicon and needs to handled as such. If we could, we would alter nSIM to behave just like our silicon. So in current situation where we lack doing so we suffice in single pretty small adjustment in OS (platform specific code). You are saying contradicting things here. Above u want EZSim to simulate CTOP (i.e. generate machinechk for U errors) but here you claim u use nSIM which will generates L2 intr. So I'm still grossly confused. What does EZSim (based on nSIM) do when bus error is triggered from User mode - does it raise (A) L2 interrupt or (B) MachineCheck ? If it is (A) the the existing common code in ARC will work - mem_service() -> do_memory_error() -> panic() if it is (B), again the common machinecheck handler will be called and will panic. I don't see the need to mix both (A) and (B) i.e. use mem_service() which is a L2 interrupt, but then handle it in MachieChekc which is for exceptions ? How is that supposed to work ! -Vineet ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
