[PATCH] ARC: [arcompact] fix handling of unaligned access in delay slot
Commit 9aed02feae5 ("ARC: [arcompact] handle unaligned access delay slot
corner case") was meant to fix one corner-case of unaligned access
fixup. But for some reason real implementation has an important spello
which prevents kernel to be built with enabled
CONFIG_ARC_EMUL_UNALIGNED:
->8
arch/arc/kernel/unaligned.c: In function 'misaligned_fixup':
arch/arc/kernel/unaligned.c:246:25: error: expected ';' before '~ token
regs->ret = regs->bta ~1U;
^
->8
What needs to be done - LSB bit of regs->bta has to be cleared and now
we do exactly this with "& ~1U".
While at it fix another spello in comments.
Signed-off-by: Alexey Brodkin
Reported-by: John Crispin
Cc: Felix Fietkau
Cc: Vineet Gupta
Cc: Igor Guryanov
---
arch/arc/kernel/unaligned.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arc/kernel/unaligned.c b/arch/arc/kernel/unaligned.c
index 91ebe382147f..39ee23d107cc 100644
--- a/arch/arc/kernel/unaligned.c
+++ b/arch/arc/kernel/unaligned.c
@@ -241,9 +241,9 @@ int misaligned_fixup(unsigned long address, struct pt_regs
*regs,
if (state.fault)
goto fault;
- /* clear any remanants of delay slot */
+ /* clear any remnants of delay slot */
if (delay_mode(regs)) {
- regs->ret = regs->bta ~1U;
+ regs->ret = regs->bta & ~1U;
regs->status32 &= ~STATUS_DE_MASK;
} else {
regs->ret += state.instr_len;
--
2.7.4
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[PATCH] ARC: [arcompact] brown paper bag bug in unaligned access delay slot fixup
Reported-by: Jo-Philipp Wich
Fixes: 9aed02feae57bf7 ("ARC: [arcompact] handle unaligned access delay slot")
Cc: linux-ker...@vger.kernel.org
Cc: linux-snps-arc@lists.infradead.org
Cc: sta...@vger.kernel.org
Signed-off-by: Vineet Gupta
---
arch/arc/kernel/unaligned.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arc/kernel/unaligned.c b/arch/arc/kernel/unaligned.c
index 91ebe382147f..5f69c3bd59bb 100644
--- a/arch/arc/kernel/unaligned.c
+++ b/arch/arc/kernel/unaligned.c
@@ -243,7 +243,7 @@ int misaligned_fixup(unsigned long address, struct pt_regs
*regs,
/* clear any remanants of delay slot */
if (delay_mode(regs)) {
- regs->ret = regs->bta ~1U;
+ regs->ret = regs->bta & ~1U;
regs->status32 &= ~STATUS_DE_MASK;
} else {
regs->ret += state.instr_len;
--
2.7.4
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[PATCH] ARCv2: intc: Disable all core interrupts by default
The kernel emits a lot of warnings about unexpected IRQs when
an appropriate driver is not presented. It happens because all
interrupts in the core controller are enabled by default after
reset. It would be wise to keep all interrupts masked by default.
Thus disable all local and common interrupts. If CPU consists of
only 1 core without IDU then it is necessary to disable all
interrupts in the core interrupt controller. If CPU contains IDU
it means that there are may be more than 1 cores and common
interrupts (>= FIRST_EXT_IRQ) must be disabled in IDU.
Signed-off-by: Yuriy Kolerov
---
arch/arc/kernel/intc-arcv2.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c
index f928795..ac84d09 100644
--- a/arch/arc/kernel/intc-arcv2.c
+++ b/arch/arc/kernel/intc-arcv2.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#define NR_EXCEPTIONS 16
@@ -34,6 +35,7 @@ void arc_init_IRQ(void)
{
unsigned int tmp, irq_prio, i;
struct bcr_irq_arcv2 irq_bcr;
+ struct mcip_bcr mp;
struct aux_irq_ctrl {
#ifdef CONFIG_CPU_BIG_ENDIAN
@@ -75,10 +77,27 @@ void arc_init_IRQ(void)
* Set a default priority for all available interrupts to prevent
* switching of register banks if Fast IRQ and multiple register banks
* are supported by CPU.
+*
+* Disable all local and common interrupts. If CPU consists of only 1
+* core without IDU then it is necessary to disable all interrupts
+* in the core interrupt controller. If CPU contains IDU it means that
+* there are may be more than 1 cores and common interrupts
+* (>= FIRST_EXT_IRQ) must be disabled in IDU.
*/
+
+ READ_BCR(ARC_REG_MCIP_BCR, mp);
+
for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) {
write_aux_reg(AUX_IRQ_SELECT, i);
write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
+
+ /*
+* If IDU exists then all common interrupts >= FIRST_EXT_IRQ
+* are masked by IDU thus disable only local interrupts (below
+* FIRST_EXT_IRQ). Otherwise disable all interrupts.
+*/
+ if (!mp.idu || i < FIRST_EXT_IRQ)
+ write_aux_reg(AUX_IRQ_ENABLE, 0);
}
/* setup status32, don't enable intr yet as kernel doesn't want */
--
2.7.4
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