Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver
Hi Alexey,
On 20-04-2016 17:12, Alexey Brodkin wrote:
> Hi Jose, Stephen,
>
> On Wed, 2016-04-20 at 10:47 +0100, Jose Abreu wrote:
>> Hi Stephen,
>>
>>
>> On 20-04-2016 02:54, Stephen Boyd wrote:
>>> On 04/19, Jose Abreu wrote:
@Stephen: can you give some input so that I can submit a v6?
>>> I don't prefer putting the second register in the same DT node,
>>> but that's really up to the DT reviewers to approve such a
>>> design. The current binding has been acked by Rob right?
>> Yes.
>>
>>> Assuming the new binding is acked/reviewed then that solution is
>>> fine.
>> Ok, will then use the DT to pass the FPGA version register.
> We won't need to know FPGA version at all I think.
> Read my comment below.
>
>>> Otherwise, I still prefer two DTS files for the two different FPGA
>>> versions. At the least, please use ioremap for any pointers that
>>> you readl/writel here.
>>>
>>> Beyond that, we should have a fixed rate source clk somewhere in
>>> the software view of the clk tree, because that reflects reality.
>>> Hardcoding the parent rate in the structure works, but doesn't
>>> properly express the clk tree.
>>>
>> Can I use a property in the DT to pass this reference clock? something like
>> this:
>> snps,parent-freq = <0xFBED9 2700>, <0x0 28224000>; /* Tuple
>> , fpga-version = 0 is default */
>>
>> Or use a parent clock? like:
>> clk {
>> compatible = "fixed-clock";
>> clock-frequency = <2700>;
>> #clock-cells = <0>;
>> snps,fpga-version = <0xFBED9>;
>> }
>>
>> It is important to distinguish between the different versions automatically,
>> is
>> any of these solutions ok?
> I do like that solution with a master clock but with some fine-tuning
> for simplification.
>
> We'll add master clock node for I2S as a fixed clock like that:
> --->8--
> i2s_master_clock: clk {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> clock-frequency = <2700>;
> };
> --->8--
>
> Note there's no mention of MB version, just a value of the frequency.
> And in the driver itself value of that master clock will be used for
> population of "pll_clk->ref_clk" directly.
>
> These are benefits we'll get with that approach:
> [1] We escape any IOs not related to our clock device (I mean
> "snps,i2s-pll-clock") itself.
> [2] We'll use whatever reference clock value is given.
> I.e. we'll be able to do a fix-up of that reference clock
> value early in platform code depending on HW we're running on.
> That's what people do here and there.
> [3] Remember another clock driver for AXS10x board is right around
> the corner. I mean the one for ARC PGU which uses exactly the same
> master clock. So one fixup as mentioned above will work
> at once for 2 clock drivers.
>
> Let me know if above makes sense.
That approach can't be used because the reference clock value will change in the
next firmware release. The new release will have a reference clock of 28224000
Hz instead of the usual 2700 Hz, so we need to have a way to distinguish
between them. Because of that we can't have only one master clock unless you
state to users that they have to change the reference clock value when using the
new firmware release. Stephen suggested to use two DT files (one for each
firmware release), but as Vineet said this would be annoying to the user so I am
trying to use another solution so that only one DT file is required.
>
> -Alexey
Best regards,
Jose Miguel Abreu
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Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver
Hi Jose,
On Thu, 2016-04-21 at 10:51 +0100, Jose Abreu wrote:
> Hi Alexey,
> > > > Otherwise, I still prefer two DTS files for the two different FPGA
> > > > versions. At the least, please use ioremap for any pointers that
> > > > you readl/writel here.
> > > >
> > > > Beyond that, we should have a fixed rate source clk somewhere in
> > > > the software view of the clk tree, because that reflects reality.
> > > > Hardcoding the parent rate in the structure works, but doesn't
> > > > properly express the clk tree.
> > > >
> > > Can I use a property in the DT to pass this reference clock? something
> > > like this:
> > > snps,parent-freq = <0xFBED9 2700>, <0x0 28224000>; /* Tuple
> > > , fpga-version = 0 is default */
> > >
> > > Or use a parent clock? like:
> > > clk {
> > > compatible = "fixed-clock";
> > > clock-frequency = <2700>;
> > > #clock-cells = <0>;
> > > snps,fpga-version = <0xFBED9>;
> > > }
> > >
> > > It is important to distinguish between the different versions
> > > automatically, is
> > > any of these solutions ok?
> > I do like that solution with a master clock but with some fine-tuning
> > for simplification.
> >
> > We'll add master clock node for I2S as a fixed clock like that:
> > --->8--
> > i2s_master_clock: clk {
> > #clock-cells = <0>;
> > compatible = "fixed-clock";
> > clock-frequency = <2700>;
> > };
> > --->8--
> >
> > Note there's no mention of MB version, just a value of the frequency.
> > And in the driver itself value of that master clock will be used for
> > population of "pll_clk->ref_clk" directly.
> >
> > These are benefits we'll get with that approach:
> > [1] We escape any IOs not related to our clock device (I mean
> > "snps,i2s-pll-clock") itself.
> > [2] We'll use whatever reference clock value is given.
> > I.e. we'll be able to do a fix-up of that reference clock
> > value early in platform code depending on HW we're running on.
> > That's what people do here and there.
> > [3] Remember another clock driver for AXS10x board is right around
> > the corner. I mean the one for ARC PGU which uses exactly the same
> > master clock. So one fixup as mentioned above will work
> > at once for 2 clock drivers.
> >
> > Let me know if above makes sense.
> That approach can't be used because the reference clock value will change in
> the
> next firmware release. The new release will have a reference clock of
> 28224000
> Hz instead of the usual 2700 Hz, so we need to have a way to distinguish
> between them. Because of that we can't have only one master clock unless you
> state to users that they have to change the reference clock value when using
> the
> new firmware release. Stephen suggested to use two DT files (one for each
> firmware release), but as Vineet said this would be annoying to the user so I
> am
> trying to use another solution so that only one DT file is required.
Ok reference clock will change.
But I may guess we'll still be able to determine at least that new
firmware version in run-time, right? If so we'll update a fix-up in
early axs10x platform code so that reference clock will be set as 28224000 Hz.
And indeed 2 DT files is a no go - we want to run the same one binary
(with built-in .dtb) on all flavors of AXS boards. And fix-up I'm talking about
will actually do transformation of .dtb early on kernel boot process so that
will
be a complete equivalent of different DT files.
-Alexey
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Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver
Hi Alexey,
On 21-04-2016 13:18, Alexey Brodkin wrote:
> Hi Jose,
>
> On Thu, 2016-04-21 at 10:51 +0100, Jose Abreu wrote:
>> Hi Alexey,
>
> Otherwise, I still prefer two DTS files for the two different FPGA
> versions. At the least, please use ioremap for any pointers that
> you readl/writel here.
>
> Beyond that, we should have a fixed rate source clk somewhere in
> the software view of the clk tree, because that reflects reality.
> Hardcoding the parent rate in the structure works, but doesn't
> properly express the clk tree.
>
Can I use a property in the DT to pass this reference clock? something
like this:
snps,parent-freq = <0xFBED9 2700>, <0x0 28224000>; /* Tuple
, fpga-version = 0 is default */
Or use a parent clock? like:
clk {
compatible = "fixed-clock";
clock-frequency = <2700>;
#clock-cells = <0>;
snps,fpga-version = <0xFBED9>;
}
It is important to distinguish between the different versions
automatically, is
any of these solutions ok?
>>> I do like that solution with a master clock but with some fine-tuning
>>> for simplification.
>>>
>>> We'll add master clock node for I2S as a fixed clock like that:
>>> --->8--
>>> i2s_master_clock: clk {
>>> #clock-cells = <0>;
>>> compatible = "fixed-clock";
>>> clock-frequency = <2700>;
>>> };
>>> --->8--
>>>
>>> Note there's no mention of MB version, just a value of the frequency.
>>> And in the driver itself value of that master clock will be used for
>>> population of "pll_clk->ref_clk" directly.
>>>
>>> These are benefits we'll get with that approach:
>>> [1] We escape any IOs not related to our clock device (I mean
>>> "snps,i2s-pll-clock") itself.
>>> [2] We'll use whatever reference clock value is given.
>>> I.e. we'll be able to do a fix-up of that reference clock
>>> value early in platform code depending on HW we're running on.
>>> That's what people do here and there.
>>> [3] Remember another clock driver for AXS10x board is right around
>>> the corner. I mean the one for ARC PGU which uses exactly the same
>>> master clock. So one fixup as mentioned above will work
>>> at once for 2 clock drivers.
>>>
>>> Let me know if above makes sense.
>> That approach can't be used because the reference clock value will change in
>> the
>> next firmware release. The new release will have a reference clock of
>> 28224000
>> Hz instead of the usual 2700 Hz, so we need to have a way to distinguish
>> between them. Because of that we can't have only one master clock unless you
>> state to users that they have to change the reference clock value when using
>> the
>> new firmware release. Stephen suggested to use two DT files (one for each
>> firmware release), but as Vineet said this would be annoying to the user so
>> I am
>> trying to use another solution so that only one DT file is required.
> Ok reference clock will change.
> But I may guess we'll still be able to determine at least that new
> firmware version in run-time, right? If so we'll update a fix-up in
> early axs10x platform code so that reference clock will be set as 28224000 Hz.
Yes, there is a register where the FPGA version date is encoded, we can use that
to check which firmware is used (if date <= old_firmware_date then
clock=2700; else clock=28224000). If that fix is acceptable it could be a
good solution without having to use custom parameters in the DT (no need to
encode the different clocks and we would only use one master clock) but I am not
sure where and how this can be encoded and I don't know how to change the DT on
runtime. Can you give me some guidelines?
>
> And indeed 2 DT files is a no go - we want to run the same one binary
> (with built-in .dtb) on all flavors of AXS boards. And fix-up I'm talking
> about
> will actually do transformation of .dtb early on kernel boot process so that
> will
> be a complete equivalent of different DT files.
And doing modifications on the DT can cause some misdirections to users.
Besides, we would have clock specific functions in init procedures which is
precisely what we are trying to avoid by submitting this driver.
>
> -Alexey
Best regards,
Jose Miguel Abreu
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Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver
Hi Jose, On Thu, 2016-04-21 at 14:10 +0100, Jose Abreu wrote: > Hi Alexey, > > > On 21-04-2016 13:18, Alexey Brodkin wrote: > > > > Hi Jose, > > > > On Thu, 2016-04-21 at 10:51 +0100, Jose Abreu wrote: > > > > > > Hi Alexey, > > > > > Ok reference clock will change. > > But I may guess we'll still be able to determine at least that new > > firmware version in run-time, right? If so we'll update a fix-up in > > early axs10x platform code so that reference clock will be set as 28224000 > > Hz. > Yes, there is a register where the FPGA version date is encoded, we can use > that > to check which firmware is used (if date <= old_firmware_date then > clock=2700; else clock=28224000). If that fix is acceptable it could be a > good solution without having to use custom parameters in the DT (no need to > encode the different clocks and we would only use one master clock) but I am > not > sure where and how this can be encoded and I don't know how to change the DT > on > runtime. Can you give me some guidelines? Take a look here - http://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/commit/arch/arc/plat-axs10x/axs10x.c?h=for -next&id=5cd0f5102753a7405548d0c66c11a2a0a05bbf2e We do something very similar here - we're patching in run-time core frequency that was specified in .dts. And in the very same way one will be able to do fix-ups for other clocks. Moreover I would propose to think about that fix-up as of completely separate topic. I.e. in your driver for AXS' I2S clock just use a new reference "fixed-clock" (that you'll add in "axs10x_mb.dtsi" as a part of your driver submission). And once your driver gets accepted we'll work on fix-up in axs10x platform. This way we'll move with smaller steps and hopefully will get things done sooner. > > And indeed 2 DT files is a no go - we want to run the same one binary > > (with built-in .dtb) on all flavors of AXS boards. And fix-up I'm talking > > about > > will actually do transformation of .dtb early on kernel boot process so > > that will > > be a complete equivalent of different DT files. > And doing modifications on the DT can cause some misdirections to users. What do you mean here? What kind of problems do you expect to face? > Besides, we would have clock specific functions in init procedures which is > precisely what we are trying to avoid by submitting this driver. You're talking about fixups above here? -Alexey ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH 2/2 v6] arc: axs10x: Add DT bindings for I2S PLL Clock
Add device tree bindings for AXS10X I2S PLL Clock driver.
Signed-off-by: Jose Abreu
---
Changes v5 -> v6:
* Added 'clocks' field
This patch was only introduced in v5.
arch/arc/boot/dts/axs10x_mb.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
index ab5d570..5c6489e 100644
--- a/arch/arc/boot/dts/axs10x_mb.dtsi
+++ b/arch/arc/boot/dts/axs10x_mb.dtsi
@@ -16,7 +16,20 @@
ranges = <0x 0xe000 0x1000>;
interrupt-parent = <&mb_intc>;
+ i2sclk: i2sclk@100a0 {
+ compatible = "snps,axs10x-i2s-pll-clock";
+ reg = <0x100a0 0x10>;
+ clocks = <&i2spll_clk>;
+ #clock-cells = <0>;
+ };
+
clocks {
+ i2spll_clk: i2spll_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <2700>;
+ #clock-cells = <0>;
+ };
+
i2cclk: i2cclk {
compatible = "fixed-clock";
clock-frequency = <5000>;
--
1.9.1
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[PATCH 0/2 v6] Add AXS10X I2S PLL clock driver
The ARC SDP I2S clock can be programmed using a
specific PLL.
This patch series has the goal of adding a clock driver
that programs this PLL.
Changes v5 -> v6:
* Use parent clock to determine PLL input rate instead of using hardcoded values
* Documentation update (added 'clocks' field)
* Device tree update (added 'clocks' field)
Changes v4 -> v5:
* Documentation update (as suggested by Alexey Brodkin)
* Changed compatible string to "snps,axs10x-i2s-pll-clock" (as suggested by
Alexey Brodkin)
* Added DT bindings
Changes v3 -> v4:
* Added binding document (as suggested by Stephen Boyd)
* Minor code style fixes (as suggested by Stephen Boyd)
* Use ioremap (as suggested by Stephen Boyd)
* Implement round_rate (as suggested by Stephen Boyd)
* Change to platform driver (as suggested by Stephen Boyd)
* Use {readl/writel}_relaxed (as suggested by Vineet Gupta)
Changes v2 -> v3:
* Implemented recalc_rate
Changes v1 -> v2:
* Renamed folder to axs10x (as suggested by Alexey Brodkin)
* Added more supported rates
Jose Abreu (2):
clk/axs10x: Add I2S PLL clock driver
arc: axs10x: Add DT bindings for I2S PLL Clock
.../bindings/clock/axs10x-i2s-pll-clock.txt| 25 +++
arch/arc/boot/dts/axs10x_mb.dtsi | 13 ++
drivers/clk/Makefile | 1 +
drivers/clk/axs10x/Makefile| 1 +
drivers/clk/axs10x/i2s_pll_clock.c | 228 +
5 files changed, 268 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt
create mode 100644 drivers/clk/axs10x/Makefile
create mode 100644 drivers/clk/axs10x/i2s_pll_clock.c
--
1.9.1
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[PATCH 1/2 v6] clk/axs10x: Add I2S PLL clock driver
The ARC SDP I2S clock can be programmed using a
specific PLL.
This patch has the goal of adding a clock driver
that programs this PLL.
At this moment the rate values are hardcoded in
a table but in the future it would be ideal to
use a function which determines the PLL values
given the desired rate.
Signed-off-by: Jose Abreu
---
Changes v5 -> v6:
* Use parent clock to determine PLL input rate instead of using hardcoded values
* Documentation update (added 'clocks' field)
Changes v4 -> v5:
* Documentation update (as suggested by Alexey Brodkin)
* Changed compatible string to "snps,axs10x-i2s-pll-clock" (as suggested by
Alexey Brodkin)
Changes v3 -> v4:
* Added binding document (as suggested by Stephen Boyd)
* Minor code style fixes (as suggested by Stephen Boyd)
* Use ioremap (as suggested by Stephen Boyd)
* Implement round_rate (as suggested by Stephen Boyd)
* Change to platform driver (as suggested by Stephen Boyd)
* Use {readl/writel}_relaxed (as suggested by Vineet Gupta)
Changes v2 -> v3:
* Implemented recalc_rate
Changes v1 -> v2:
* Renamed folder to axs10x (as suggested by Alexey Brodkin)
* Added more supported rates
.../bindings/clock/axs10x-i2s-pll-clock.txt| 25 +++
drivers/clk/Makefile | 1 +
drivers/clk/axs10x/Makefile| 1 +
drivers/clk/axs10x/i2s_pll_clock.c | 228 +
4 files changed, 255 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt
create mode 100644 drivers/clk/axs10x/Makefile
create mode 100644 drivers/clk/axs10x/i2s_pll_clock.c
diff --git a/Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt
b/Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt
new file mode 100644
index 000..5ffc8df
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt
@@ -0,0 +1,25 @@
+Binding for the AXS10X I2S PLL clock
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: shall be "snps,axs10x-i2s-pll-clock"
+- reg : address and length of the I2S PLL register set.
+- clocks: shall be the input parent clock phandle for the PLL.
+- #clock-cells: from common clock binding; Should always be set to 0.
+
+Example:
+ pll_clock: pll_clock {
+ compatible = "fixed-clock";
+ clock-frequency = <2700>;
+ #clock-cells = <0>;
+ };
+
+ i2s_clock@100a0 {
+ compatible = "snps,axs10x-i2s-pll-clock";
+ reg = <0x100a0 0x10>;
+ clocks = <&pll_clock>;
+ #clock-cells = <0>;
+ };
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 46869d6..2ca62dc6 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -84,3 +84,4 @@ obj-$(CONFIG_X86) += x86/
obj-$(CONFIG_ARCH_ZX) += zte/
obj-$(CONFIG_ARCH_ZYNQ)+= zynq/
obj-$(CONFIG_H8300)+= h8300/
+obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/
diff --git a/drivers/clk/axs10x/Makefile b/drivers/clk/axs10x/Makefile
new file mode 100644
index 000..01996b8
--- /dev/null
+++ b/drivers/clk/axs10x/Makefile
@@ -0,0 +1 @@
+obj-y += i2s_pll_clock.o
diff --git a/drivers/clk/axs10x/i2s_pll_clock.c
b/drivers/clk/axs10x/i2s_pll_clock.c
new file mode 100644
index 000..411310d
--- /dev/null
+++ b/drivers/clk/axs10x/i2s_pll_clock.c
@@ -0,0 +1,228 @@
+/*
+ * Synopsys AXS10X SDP I2S PLL clock driver
+ *
+ * Copyright (C) 2016 Synopsys
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* PLL registers addresses */
+#define PLL_IDIV_REG 0x0
+#define PLL_FBDIV_REG 0x4
+#define PLL_ODIV0_REG 0x8
+#define PLL_ODIV1_REG 0xC
+
+struct i2s_pll_cfg {
+ unsigned int rate;
+ unsigned int idiv;
+ unsigned int fbdiv;
+ unsigned int odiv0;
+ unsigned int odiv1;
+};
+
+static const struct i2s_pll_cfg i2s_pll_cfg_27m[] = {
+ /* 27 Mhz */
+ { 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
+ { 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
+ { 1536000, 0x208, 0xA28, 0x10B2C, 0x2000 },
+ { 2048000, 0x82, 0x451, 0x10E38, 0x2000 },
+ { 2822400, 0x82, 0x596, 0x10D35, 0x2000 },
+ { 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
+ { 2116800, 0x82, 0x3CF, 0x10C30, 0x2000 },
+ { 2304000, 0x104, 0x79E, 0x10B2C, 0x2000 },
+ { 0, 0, 0, 0, 0 },
+};
+
+static const struct i2s_pll_cfg i2s_pll_cfg_28m[] = {
+ /* 28.224 Mhz */
+ { 1024000, 0x82, 0x105, 0x107DF, 0x2000 },
+ { 1411200, 0x28A, 0x1, 0x10001, 0x2000 },
+ { 1536000, 0xA28, 0x187, 0x10042, 0x2000 },
+
Re: [PATCH 1/2 v6] clk/axs10x: Add I2S PLL clock driver
Adding device tree mailing list and Rob Herring.
On 21-04-2016 18:19, Jose Abreu wrote:
> The ARC SDP I2S clock can be programmed using a
> specific PLL.
>
> This patch has the goal of adding a clock driver
> that programs this PLL.
>
> At this moment the rate values are hardcoded in
> a table but in the future it would be ideal to
> use a function which determines the PLL values
> given the desired rate.
>
> Signed-off-by: Jose Abreu
> ---
>
> Changes v5 -> v6:
> * Use parent clock to determine PLL input rate instead of using hardcoded
> values
> * Documentation update (added 'clocks' field)
>
> Changes v4 -> v5:
> * Documentation update (as suggested by Alexey Brodkin)
> * Changed compatible string to "snps,axs10x-i2s-pll-clock" (as suggested by
> Alexey Brodkin)
>
> Changes v3 -> v4:
> * Added binding document (as suggested by Stephen Boyd)
> * Minor code style fixes (as suggested by Stephen Boyd)
> * Use ioremap (as suggested by Stephen Boyd)
> * Implement round_rate (as suggested by Stephen Boyd)
> * Change to platform driver (as suggested by Stephen Boyd)
> * Use {readl/writel}_relaxed (as suggested by Vineet Gupta)
>
> Changes v2 -> v3:
> * Implemented recalc_rate
>
> Changes v1 -> v2:
> * Renamed folder to axs10x (as suggested by Alexey Brodkin)
> * Added more supported rates
>
> .../bindings/clock/axs10x-i2s-pll-clock.txt| 25 +++
> drivers/clk/Makefile | 1 +
> drivers/clk/axs10x/Makefile| 1 +
> drivers/clk/axs10x/i2s_pll_clock.c | 228
> +
> 4 files changed, 255 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt
> create mode 100644 drivers/clk/axs10x/Makefile
> create mode 100644 drivers/clk/axs10x/i2s_pll_clock.c
>
> diff --git a/Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt
> b/Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt
> new file mode 100644
> index 000..5ffc8df
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt
> @@ -0,0 +1,25 @@
> +Binding for the AXS10X I2S PLL clock
> +
> +This binding uses the common clock binding[1].
> +
> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +Required properties:
> +- compatible: shall be "snps,axs10x-i2s-pll-clock"
> +- reg : address and length of the I2S PLL register set.
> +- clocks: shall be the input parent clock phandle for the PLL.
> +- #clock-cells: from common clock binding; Should always be set to 0.
> +
> +Example:
> + pll_clock: pll_clock {
> + compatible = "fixed-clock";
> + clock-frequency = <2700>;
> + #clock-cells = <0>;
> + };
> +
> + i2s_clock@100a0 {
> + compatible = "snps,axs10x-i2s-pll-clock";
> + reg = <0x100a0 0x10>;
> + clocks = <&pll_clock>;
> + #clock-cells = <0>;
> + };
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index 46869d6..2ca62dc6 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -84,3 +84,4 @@ obj-$(CONFIG_X86) += x86/
> obj-$(CONFIG_ARCH_ZX)+= zte/
> obj-$(CONFIG_ARCH_ZYNQ) += zynq/
> obj-$(CONFIG_H8300) += h8300/
> +obj-$(CONFIG_ARC_PLAT_AXS10X)+= axs10x/
> diff --git a/drivers/clk/axs10x/Makefile b/drivers/clk/axs10x/Makefile
> new file mode 100644
> index 000..01996b8
> --- /dev/null
> +++ b/drivers/clk/axs10x/Makefile
> @@ -0,0 +1 @@
> +obj-y += i2s_pll_clock.o
> diff --git a/drivers/clk/axs10x/i2s_pll_clock.c
> b/drivers/clk/axs10x/i2s_pll_clock.c
> new file mode 100644
> index 000..411310d
> --- /dev/null
> +++ b/drivers/clk/axs10x/i2s_pll_clock.c
> @@ -0,0 +1,228 @@
> +/*
> + * Synopsys AXS10X SDP I2S PLL clock driver
> + *
> + * Copyright (C) 2016 Synopsys
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/* PLL registers addresses */
> +#define PLL_IDIV_REG 0x0
> +#define PLL_FBDIV_REG0x4
> +#define PLL_ODIV0_REG0x8
> +#define PLL_ODIV1_REG0xC
> +
> +struct i2s_pll_cfg {
> + unsigned int rate;
> + unsigned int idiv;
> + unsigned int fbdiv;
> + unsigned int odiv0;
> + unsigned int odiv1;
> +};
> +
> +static const struct i2s_pll_cfg i2s_pll_cfg_27m[] = {
> + /* 27 Mhz */
> + { 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
> + { 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
> + { 1536000, 0x208, 0xA28, 0x10B2C, 0x2000 },
> + { 2048000, 0x82, 0x451, 0x10E38, 0x2000 },
> + { 2822400, 0x82, 0x596, 0x10D35, 0x2000 },
> + { 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
> + { 2116800, 0x82
Re: [PATCH 2/2 v6] arc: axs10x: Add DT bindings for I2S PLL Clock
Adding device tree mailing list and Rob Herring.
On 21-04-2016 18:19, Jose Abreu wrote:
> Add device tree bindings for AXS10X I2S PLL Clock driver.
>
> Signed-off-by: Jose Abreu
> ---
>
> Changes v5 -> v6:
> * Added 'clocks' field
>
> This patch was only introduced in v5.
>
> arch/arc/boot/dts/axs10x_mb.dtsi | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi
> b/arch/arc/boot/dts/axs10x_mb.dtsi
> index ab5d570..5c6489e 100644
> --- a/arch/arc/boot/dts/axs10x_mb.dtsi
> +++ b/arch/arc/boot/dts/axs10x_mb.dtsi
> @@ -16,7 +16,20 @@
> ranges = <0x 0xe000 0x1000>;
> interrupt-parent = <&mb_intc>;
>
> + i2sclk: i2sclk@100a0 {
> + compatible = "snps,axs10x-i2s-pll-clock";
> + reg = <0x100a0 0x10>;
> + clocks = <&i2spll_clk>;
> + #clock-cells = <0>;
> + };
> +
> clocks {
> + i2spll_clk: i2spll_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <2700>;
> + #clock-cells = <0>;
> + };
> +
> i2cclk: i2cclk {
> compatible = "fixed-clock";
> clock-frequency = <5000>;
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Re: [PATCH 02/23] arc: select GPIOLIB directly
On Wednesday 20 April 2016 02:28 PM, Linus Walleij wrote: > Instead of indirectly selecting GPIOLIB via the > ARCH_REQUIRE_GPIOLIB symbol, just select GPIOLIB. > > Cc: Michael Büsch > Cc: Vineet Gupta > Cc: linux-snps-arc@lists.infradead.org > Signed-off-by: Linus Walleij > --- > Various arch maintainers: It would be nice to get the cover latter as well to get more context. The whole series didn't seem to be CCed to lkml either. Anyhow I found some reference on linux-gpio patchworks and seems like a nice cleanup. So for arch/arc/* Acked-by: Vineet Gupta Thx, -Vineet > > either ACK this and I will merge it into the GPIO tree for v4.7 > anticipating no clashes, or you wait until I have the enabling patch > upstream (patch 1 in this series, removing deps on > ARCH_[WANTS_OPTIONAL|REQUIRES]_GPIOLIB), and you will be able to > merge it to your arch trees yourselves for late v4.7 > (post GPIO tree merge) or for v4.8. > > You can also ask me for an immutable branch if you prefer that, I > will put the enabling patch on a branch and the patch for your arch > on top and ask you to pull it. > > Select your option from the menu, silence probably means I will > merge it to the GPIO tree. Unless you are X86 or ARM in which case > I will be cautious. > --- > arch/arc/plat-axs10x/Kconfig | 2 +- > arch/arc/plat-tb10x/Kconfig | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arc/plat-axs10x/Kconfig b/arch/arc/plat-axs10x/Kconfig > index 426ac4b8bb39..c54d1ae57fe0 100644 > --- a/arch/arc/plat-axs10x/Kconfig > +++ b/arch/arc/plat-axs10x/Kconfig > @@ -13,7 +13,7 @@ menuconfig ARC_PLAT_AXS10X > select OF_GPIO > select MIGHT_HAVE_PCI > select GENERIC_IRQ_CHIP > - select ARCH_REQUIRE_GPIOLIB > + select GPIOLIB > help > Support for the ARC AXS10x Software Development Platforms. > > diff --git a/arch/arc/plat-tb10x/Kconfig b/arch/arc/plat-tb10x/Kconfig > index d14b3d3c5dfd..149e0917645d 100644 > --- a/arch/arc/plat-tb10x/Kconfig > +++ b/arch/arc/plat-tb10x/Kconfig > @@ -21,7 +21,7 @@ menuconfig ARC_PLAT_TB10X > select PINCTRL > select PINCTRL_TB10X > select PINMUX > - select ARCH_REQUIRE_GPIOLIB > + select GPIOLIB > select GPIO_TB10X > select TB10X_IRQC > help > ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [RESEND PATCH v4] clk/axs10x: Add I2S PLL clock driver
On Thursday 21 April 2016 05:48 PM, Alexey Brodkin wrote:
> Hi Jose,
>
> On Thu, 2016-04-21 at 10:51 +0100, Jose Abreu wrote:
>> Hi Alexey,
>
>
> Otherwise, I still prefer two DTS files for the two different FPGA
> versions. At the least, please use ioremap for any pointers that
> you readl/writel here.
>
> Beyond that, we should have a fixed rate source clk somewhere in
> the software view of the clk tree, because that reflects reality.
> Hardcoding the parent rate in the structure works, but doesn't
> properly express the clk tree.
>
Can I use a property in the DT to pass this reference clock? something
like this:
snps,parent-freq = <0xFBED9 2700>, <0x0 28224000>; /* Tuple
, fpga-version = 0 is default */
Or use a parent clock? like:
clk {
compatible = "fixed-clock";
clock-frequency = <2700>;
#clock-cells = <0>;
snps,fpga-version = <0xFBED9>;
}
It is important to distinguish between the different versions
automatically, is
any of these solutions ok?
>>> I do like that solution with a master clock but with some fine-tuning
>>> for simplification.
>>>
>>> We'll add master clock node for I2S as a fixed clock like that:
>>> --->8--
>>> i2s_master_clock: clk {
>>> #clock-cells = <0>;
>>> compatible = "fixed-clock";
>>> clock-frequency = <2700>;
>>> };
>>> --->8--
>>>
>>> Note there's no mention of MB version, just a value of the frequency.
>>> And in the driver itself value of that master clock will be used for
>>> population of "pll_clk->ref_clk" directly.
>>>
>>> These are benefits we'll get with that approach:
>>> [1] We escape any IOs not related to our clock device (I mean
>>> "snps,i2s-pll-clock") itself.
>>> [2] We'll use whatever reference clock value is given.
>>> I.e. we'll be able to do a fix-up of that reference clock
>>> value early in platform code depending on HW we're running on.
>>> That's what people do here and there.
>>> [3] Remember another clock driver for AXS10x board is right around
>>> the corner. I mean the one for ARC PGU which uses exactly the same
>>> master clock. So one fixup as mentioned above will work
>>> at once for 2 clock drivers.
>>>
>>> Let me know if above makes sense.
>> That approach can't be used because the reference clock value will change in
>> the
>> next firmware release. The new release will have a reference clock of
>> 28224000
>> Hz instead of the usual 2700 Hz, so we need to have a way to distinguish
>> between them. Because of that we can't have only one master clock unless you
>> state to users that they have to change the reference clock value when using
>> the
>> new firmware release. Stephen suggested to use two DT files (one for each
>> firmware release), but as Vineet said this would be annoying to the user so
>> I am
>> trying to use another solution so that only one DT file is required.
>
> Ok reference clock will change.
> But I may guess we'll still be able to determine at least that new
> firmware version in run-time, right? If so we'll update a fix-up in
> early axs10x platform code so that reference clock will be set as 28224000 Hz.
Please no - lets not bolt-in more hacks and instead try do this cleanly if
possible. And from other discusions it seems there might be a way. The readl
approach seems fine to me (with ioremap) if that is what it takes.
> And indeed 2 DT files is a no go - we want to run the same one binary
> (with built-in .dtb) on all flavors of AXS boards.
Right - 2 DT is not acceptable unless we are feeling bored and want more emails
for AXS board support :-)
And fix-up I'm talking about
> will actually do transformation of .dtb early on kernel boot process so that
> will
> be a complete equivalent of different DT files.
>
> -Alexey--
> To unsubscribe from this list: send the line "unsubscribe linux-clk" in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
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Re: [PATCH V3 00/29] bitops: add parity functions
On Thu, Apr 14, 2016 at 10:36:41AM +0800, zengzhao...@163.com wrote: > drivers/input/joystick/grip_mp.c | 16 +-- > drivers/input/joystick/sidewinder.c | 24 + > drivers/input/mouse/elantech.c | 10 +- > drivers/input/mouse/elantech.h | 1 - > drivers/input/serio/ams_delta_serio.c| 8 +- > drivers/input/serio/pcips2.c | 2 +- > drivers/input/serio/saps2.c | 2 +- For input bits: Acked-by: Dmitry Torokhov Thanks. -- Dmitry ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
