[PATCH 0/2 v5] Add AXS10X I2S PLL clock driver
The ARC SDP I2S clock can be programmed using a
specific PLL.
This patch series has the goal of adding a clock driver
that programs this PLL.
Changes v4 -> v5:
* Documentation update (as suggested by Alexey Brodkin)
* Changed compatible string to "snps,axs10x-i2s-pll-clock" (as suggested by
Alexey Brodkin)
* Added DT bindings
Changes v3 -> v4:
* Added binding document (as suggested by Stephen Boyd)
* Minor code style fixes (as suggested by Stephen Boyd)
* Use ioremap (as suggested by Stephen Boyd)
* Implement round_rate (as suggested by Stephen Boyd)
* Change to platform driver (as suggested by Stephen Boyd)
* Use {readl/writel}_relaxed (as suggested by Vineet Gupta)
Changes v2 -> v3:
* Implemented recalc_rate
Changes v1 -> v2:
* Renamed folder to axs10x (as suggested by Alexey Brodkin)
* Added more supported rates
Jose Abreu (2):
clk/axs10x: Add I2S PLL clock driver
arc: axs10x: Add DT bindings for I2S PLL Clock
.../bindings/clock/axs10x-i2s-pll-clock.txt| 17 ++
arch/arc/boot/dts/axs10x_mb.dtsi | 6 +
drivers/clk/Makefile | 1 +
drivers/clk/axs10x/Makefile| 1 +
drivers/clk/axs10x/i2s_pll_clock.c | 217 +
5 files changed, 242 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt
create mode 100644 drivers/clk/axs10x/Makefile
create mode 100644 drivers/clk/axs10x/i2s_pll_clock.c
--
1.9.1
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[PATCH 1/2 v5] clk/axs10x: Add I2S PLL clock driver
The ARC SDP I2S clock can be programmed using a
specific PLL.
This patch has the goal of adding a clock driver
that programs this PLL.
At this moment the rate values are hardcoded in
a table but in the future it would be ideal to
use a function which determines the PLL values
given the desired rate.
Signed-off-by: Jose Abreu
---
Changes v4 -> v5:
* Documentation update (as suggested by Alexey Brodkin)
* Changed compatible string to "snps,axs10x-i2s-pll-clock" (as suggested by
Alexey Brodkin)
Changes v3 -> v4:
* Added binding document (as suggested by Stephen Boyd)
* Minor code style fixes (as suggested by Stephen Boyd)
* Use ioremap (as suggested by Stephen Boyd)
* Implement round_rate (as suggested by Stephen Boyd)
* Change to platform driver (as suggested by Stephen Boyd)
* Use {readl/writel}_relaxed (as suggested by Vineet Gupta)
Changes v2 -> v3:
* Implemented recalc_rate
Changes v1 -> v2:
* Renamed folder to axs10x (as suggested by Alexey Brodkin)
* Added more supported rates
.../bindings/clock/axs10x-i2s-pll-clock.txt| 17 ++
drivers/clk/Makefile | 1 +
drivers/clk/axs10x/Makefile| 1 +
drivers/clk/axs10x/i2s_pll_clock.c | 217 +
4 files changed, 236 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt
create mode 100644 drivers/clk/axs10x/Makefile
create mode 100644 drivers/clk/axs10x/i2s_pll_clock.c
diff --git a/Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt
b/Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt
new file mode 100644
index 000..6879e81
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/axs10x-i2s-pll-clock.txt
@@ -0,0 +1,17 @@
+Binding for the AXS10X I2S PLL clock
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible: shall be "snps,axs10x-i2s-pll-clock"
+- #clock-cells: from common clock binding; Should always be set to 0.
+- reg : Address and length of the I2S PLL register set.
+
+Example:
+ i2s_clock@100a0 {
+ compatible = "snps,axs10x-i2s-pll-clock";
+ reg = <0x100a0 0x10>;
+ #clock-cells = <0>;
+ };
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 46869d6..2ca62dc6 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -84,3 +84,4 @@ obj-$(CONFIG_X86) += x86/
obj-$(CONFIG_ARCH_ZX) += zte/
obj-$(CONFIG_ARCH_ZYNQ)+= zynq/
obj-$(CONFIG_H8300)+= h8300/
+obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/
diff --git a/drivers/clk/axs10x/Makefile b/drivers/clk/axs10x/Makefile
new file mode 100644
index 000..01996b8
--- /dev/null
+++ b/drivers/clk/axs10x/Makefile
@@ -0,0 +1 @@
+obj-y += i2s_pll_clock.o
diff --git a/drivers/clk/axs10x/i2s_pll_clock.c
b/drivers/clk/axs10x/i2s_pll_clock.c
new file mode 100644
index 000..1267b5b
--- /dev/null
+++ b/drivers/clk/axs10x/i2s_pll_clock.c
@@ -0,0 +1,217 @@
+/*
+ * Synopsys AXS10X SDP I2S PLL clock driver
+ *
+ * Copyright (C) 2016 Synopsys
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* FPGA Version Info */
+#define FPGA_VER_INFO 0xE0011230
+#define FPGA_VER_27M 0x000FBED9
+
+/* PLL registers addresses */
+#define PLL_IDIV_REG 0x0
+#define PLL_FBDIV_REG 0x4
+#define PLL_ODIV0_REG 0x8
+#define PLL_ODIV1_REG 0xC
+
+struct i2s_pll_cfg {
+ unsigned int rate;
+ unsigned int idiv;
+ unsigned int fbdiv;
+ unsigned int odiv0;
+ unsigned int odiv1;
+};
+
+static const struct i2s_pll_cfg i2s_pll_cfg_27m[] = {
+ /* 27 Mhz */
+ { 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
+ { 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
+ { 1536000, 0x208, 0xA28, 0x10B2C, 0x2000 },
+ { 2048000, 0x82, 0x451, 0x10E38, 0x2000 },
+ { 2822400, 0x82, 0x596, 0x10D35, 0x2000 },
+ { 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
+ { 2116800, 0x82, 0x3CF, 0x10C30, 0x2000 },
+ { 2304000, 0x104, 0x79E, 0x10B2C, 0x2000 },
+ { 0, 0, 0, 0, 0 },
+};
+
+static const struct i2s_pll_cfg i2s_pll_cfg_28m[] = {
+ /* 28.224 Mhz */
+ { 1024000, 0x82, 0x105, 0x107DF, 0x2000 },
+ { 1411200, 0x28A, 0x1, 0x10001, 0x2000 },
+ { 1536000, 0xA28, 0x187, 0x10042, 0x2000 },
+ { 2048000, 0x41, 0x105, 0x107DF, 0x2000 },
+ { 2822400, 0x145, 0x1, 0x10001, 0x2000 },
+ { 3072000, 0x514, 0x187, 0x10042, 0x2000 },
+ { 2116800, 0x514, 0x42, 0x10001, 0x2000 },
+ { 2304000, 0x619, 0x82, 0x10001, 0x2000 },
+ { 0, 0, 0, 0, 0 },
+};
+
+struct i2s_pll_clk {
+ void __i
[PATCH 2/2 v5] arc: axs10x: Add DT bindings for I2S PLL Clock
Add device tree bindings for AXS10X I2S PLL Clock driver.
Signed-off-by: Jose Abreu
---
This patch was only introduced in v5.
arch/arc/boot/dts/axs10x_mb.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
index ab5d570..227b215 100644
--- a/arch/arc/boot/dts/axs10x_mb.dtsi
+++ b/arch/arc/boot/dts/axs10x_mb.dtsi
@@ -16,6 +16,12 @@
ranges = <0x 0xe000 0x1000>;
interrupt-parent = <&mb_intc>;
+ i2sclk: i2sclk@100a0 {
+ compatible = "snps,axs10x-i2s-pll-clock";
+ reg = <0x100a0 0x10>;
+ #clock-cells = <0>;
+ };
+
clocks {
i2cclk: i2cclk {
compatible = "fixed-clock";
--
1.9.1
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[PATCH 1/2 v5] ASoC: dwc: Add custom PCM driver
HDMI audio support was added to the AXS board using an
I2S cpu driver and a custom platform driver.
The platform driver supports two channels @ 16 bits with
rates 32k, 44.1k and 48k.
Although the mainline I2S driver uses ALSA DMA engine,
this controller can be built without DMA support so it
was necessary to add this custom platform driver so that
HDMI audio works in AXS boards.
The selection between the use of DMA engine or PIO mode
is detected by declaring or not the DMA parameters in
the device tree.
Signed-off-by: Jose Abreu
---
Changes v4 -> v5:
* Resolve undefined references when compiling as module
* Use DMA properties in I2S to check which mode to use: PIO or DMA (as
suggested by Lars-Peter Clausen)
Changes v3 -> v4:
* Reintroduced custom PCM driver
* Use DT boolean to switch between ALSA DMA engine PCM or custom PCM
Changes v2 -> v3:
* Removed pll_config functions (as suggested by Alexey Brodkin)
* Dropped custom platform driver, using now ALSA DMA engine
* Dropped IRQ handler for I2S
No changes v1 -> v2.
sound/soc/dwc/Kconfig | 9 ++
sound/soc/dwc/Makefile | 1 +
sound/soc/dwc/designware.h | 71 +
sound/soc/dwc/designware_i2s.c | 94 -
sound/soc/dwc/designware_pcm.c | 230 +
5 files changed, 378 insertions(+), 27 deletions(-)
create mode 100644 sound/soc/dwc/designware.h
create mode 100644 sound/soc/dwc/designware_pcm.c
diff --git a/sound/soc/dwc/Kconfig b/sound/soc/dwc/Kconfig
index d50e085..2a21120 100644
--- a/sound/soc/dwc/Kconfig
+++ b/sound/soc/dwc/Kconfig
@@ -7,4 +7,13 @@ config SND_DESIGNWARE_I2S
Synopsys desigwnware I2S device. The device supports upto
maximum of 8 channels each for play and record.
+config SND_DESIGNWARE_PCM
+ tristate "Synopsys I2S PCM Driver"
+ help
+Say Y or M if you want to add support for ALSA ASoC platform driver
+using I2S.
+
+Select this option if you want to be able to create a sound interface
+using the I2S device driver as CPU driver. Instead of using ALSA
+DMA engine by selecting this driver a custom PCM driver will be used.
diff --git a/sound/soc/dwc/Makefile b/sound/soc/dwc/Makefile
index 319371f..1b48bccc 100644
--- a/sound/soc/dwc/Makefile
+++ b/sound/soc/dwc/Makefile
@@ -1,3 +1,4 @@
# SYNOPSYS Platform Support
obj-$(CONFIG_SND_DESIGNWARE_I2S) += designware_i2s.o
+obj-$(CONFIG_SND_DESIGNWARE_PCM) += designware_pcm.o
diff --git a/sound/soc/dwc/designware.h b/sound/soc/dwc/designware.h
new file mode 100644
index 000..f702ed1
--- /dev/null
+++ b/sound/soc/dwc/designware.h
@@ -0,0 +1,71 @@
+/*
+ * ALSA SoC Synopsys Audio Layer
+ *
+ * sound/soc/dwc/designware.h
+ *
+ * Copyright (C) 2016 Synopsys
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __DESIGNWARE_H
+#define __DESIGNWARE_H
+
+#include
+#include
+#include
+#include
+
+struct dw_pcm_binfo {
+ struct snd_pcm_substream *stream;
+ unsigned char *dma_base;
+ unsigned char *dma_pointer;
+ unsigned int period_size_frames;
+ unsigned int size;
+ snd_pcm_uframes_t period_pointer;
+ unsigned int total_periods;
+ unsigned int current_period;
+};
+
+union dw_i2s_snd_dma_data {
+ struct i2s_dma_data pd;
+ struct snd_dmaengine_dai_dma_data dt;
+};
+
+struct dw_i2s_dev {
+ void __iomem *i2s_base;
+ struct clk *clk;
+ int active;
+ unsigned int capability;
+ unsigned int quirks;
+ unsigned int i2s_reg_comp1;
+ unsigned int i2s_reg_comp2;
+ struct device *dev;
+ u32 ccr;
+ u32 xfer_resolution;
+ u32 fifo_th;
+
+ /* data related to DMA transfers b/w i2s and DMAC */
+ bool use_dmaengine;
+ union dw_i2s_snd_dma_data play_dma_data;
+ union dw_i2s_snd_dma_data capture_dma_data;
+ struct i2s_clk_config_data config;
+ int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
+ struct dw_pcm_binfo binfo;
+};
+
+#if defined(CONFIG_SND_DESIGNWARE_PCM) || \
+ defined(CONFIG_SND_DESIGNWARE_PCM_MODULE)
+int dw_pcm_transfer(u32 *lsample, u32 *rsample, int bytes, int buf_size,
+ struct dw_pcm_binfo *bi);
+#else
+int dw_pcm_transfer(u32 *lsample, u32 *rsample, int bytes, int buf_size,
+ struct dw_pcm_binfo *bi)
+{
+ return 0;
+}
+#endif
+
+#endif
diff --git a/sound/soc/dwc/designware_i2s.c b/sound/soc/dwc/designware_i2s.c
index 0db69b7..3040a14 100644
--- a/sound/soc/dwc/designware_i2s.c
+++ b/sound/soc/dwc/designware_i2s.c
@@ -24,6 +24,7 @@
#include
#include
#include
+#include "designware.h"
/* common register for all channel */
#define IER0x000
@@ -84,31 +85,6 @@
#define MAX_CHANNEL_NUM8
#define MIN_CHANNEL_NUM2
-union d
[PATCH 0/2 v5] Add I2S/ADV7511 audio support for ARC AXS10x boards
Hi all, This is v5 of these patches. In this version I dropped the ADV7511 audio patch because, quoting Lars-Peter Clausen: "The reason why this driver is still out of tree, is because there has been no conclusion yet on how to go forward with the whole HDMI integration. So this is not going to get merged until that issue has been addressed." So, until that issue is addressed I will not send any ADV7511 audio related patches but if for some reason anyone wants to merge it I can send the pathes again. V4, which includes the ADV7511 audio patches is available at: http://mailman.alsa-project.org/pipermail/alsa-devel/2016-April/106650.html Looking forward to your comments! Best regards, Jose Miguel Abreu - ARC AXS10x platforms consist of a mainboard with several peripherals. One of those peripherals is an HDMI output port controlled by the ADV7511 transmitter. This patch set adds I2S audio for the AXS10x platform. Changes v4 -> v5 * Resolve undefined references when compiling as module * Dropped adv7511 audio patches * Use DMA properties in I2S to check which mode to use: PIO or DMA (as suggested by Lars-Peter Clausen) Changes v3 -> v4: * Reintroduced custom PCM driver (see note below) * Use DT boolean to switch between ALSA DMA engine PCM or custom PCM * Use fifo depth to program I2S FCR * Update I2S documentation Changes v2 -> v3: * Removed pll_config functions (as suggested by Alexey Brodkin) * Removed HDMI start at adv7511_core (as suggested by Archit Taneja) * Use NOP functions for adv7511_audio (as suggested by Archit Taneja) * Added adv7511_audio_exit() function (as suggested by Archit Taneja) * Moved adv7511 to its own folder (as suggested by Archit Taneja) * Separated file rename of adv7511_core (as suggested by Emil Velikov) * Compile adv7511 as module if ALSA SoC is compiled as module * Load adv7511 audio only if declared in device tree (as suggested by Laurent Pinchart) * Dropped custom platform driver, using now ALSA DMA engine * Dropped IRQ handler for I2S Changes v1 -> v2: * DT bindings moved to separate patch (as suggested by Alexey Brodkin) * Removed defconfigs entries (as suggested by Alexey Brodkin) NOTE: Although the mainline I2S driver uses ALSA DMA engine, this controller can be built without DMA support so it was necessary to add this custom platform driver so that HDMI audio works in AXS boards. Jose Abreu (2): ASoC: dwc: Add custom PCM driver ASoC: dwc: Update DOCUMENTATION for I2S Driver .../devicetree/bindings/sound/designware-i2s.txt | 9 +- sound/soc/dwc/Kconfig | 9 + sound/soc/dwc/Makefile | 1 + sound/soc/dwc/designware.h | 71 +++ sound/soc/dwc/designware_i2s.c | 94 ++--- sound/soc/dwc/designware_pcm.c | 230 + 6 files changed, 385 insertions(+), 29 deletions(-) create mode 100644 sound/soc/dwc/designware.h create mode 100644 sound/soc/dwc/designware_pcm.c -- 1.9.1 ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH 2/2 v5] ASoC: dwc: Update DOCUMENTATION for I2S Driver
This patch updates documentation for the Designware I2S
driver.
Signed-off-by: Jose Abreu
---
Changes v4 -> v5:
* interrupts is now required property
* Drop 'snps-use-dmaengine' property
This patch was only introduced in v4.
Documentation/devicetree/bindings/sound/designware-i2s.txt | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/designware-i2s.txt
b/Documentation/devicetree/bindings/sound/designware-i2s.txt
index 7bb5424..9c1fecd 100644
--- a/Documentation/devicetree/bindings/sound/designware-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/designware-i2s.txt
@@ -3,14 +3,18 @@ DesignWare I2S controller
Required properties:
- compatible : Must be "snps,designware-i2s"
- reg : Must contain the I2S core's registers location and length
+ - interrupts: where IRQ is the interrupt number.
- clocks : Pairs of phandle and specifier referencing the controller's
clocks. The controller expects one clock: the clock used as the sampling
rate reference clock sample.
- clock-names : "i2sclk" for the sample rate reference clock.
+
+Optional properties:
- dmas: Pairs of phandle and specifier for the DMA channels that are used by
the core. The core expects one or two dma channels: one for transmit and
- one for receive.
- - dma-names : "tx" for the transmit channel, "rx" for the receive channel.
+ one for receive. Set this parameter if the I2S DMA block is enabled.
+ - dma-names : "tx" for the transmit channel, "rx" for the receive channel. Set
+ this parameter if the I2S DMA block is enabled.
For more details on the 'dma', 'dma-names', 'clock' and 'clock-names'
properties please check:
@@ -23,6 +27,7 @@ Example:
soc_i2s: i2s@7ff9 {
compatible = "snps,designware-i2s";
reg = <0x0 0x7ff9 0x0 0x1000>;
+ interrupts = <15>;
clocks = <&scpi_i2sclk 0>;
clock-names = "i2sclk";
#sound-dai-cells = <0>;
--
1.9.1
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Re: [PATCH] ARCv2: Additional trace IRQs to support locking correctness validator
Hi Evgeny,
On Wednesday 23 March 2016 02:56 PM, Evgeny Voevodin wrote:
> Flags should be saved in the same format in which clri instruction saves
> them since they are passed directly to seti instruction over
> arch_local_save_flags/arch_local_irq_restore calls.
> Trace of all clri/seti assembly calls is added to support locking
> correctness validator properly.
> With this patch it is possible to use locking correctness framework which
> did stop itself due to incomplete support. Locking tests are also became
> available and work propely.
This is a nice patch !
>
> Signed-off-by: Evgeny Voevodin
> ---
> arch/arc/include/asm/irqflags-arcv2.h | 31 ++-
> arch/arc/kernel/entry-arcv2.S | 14 +-
> 2 files changed, 43 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arc/include/asm/irqflags-arcv2.h
> b/arch/arc/include/asm/irqflags-arcv2.h
> index 37c2f75..bb17044 100644
> --- a/arch/arc/include/asm/irqflags-arcv2.h
> +++ b/arch/arc/include/asm/irqflags-arcv2.h
> @@ -15,8 +15,13 @@
> #define STATUS_AD_BIT19 /* Disable Align chk: core supports
> non-aligned */
> #define STATUS_IE_BIT31
>
> +/* status32 Bits stored on clri instruction */
> +#define CLRI_STATUS_IE_BIT 4
> +
> #define STATUS_AD_MASK (1< #define STATUS_IE_MASK (1< +#define CLRI_STATUS_E_MASK (0xF)
> +#define CLRI_STATUS_IE_MASK (1<
> #define AUX_USER_SP 0x00D
> #define AUX_IRQ_CTRL 0x00E
> @@ -100,6 +105,9 @@ static inline long arch_local_save_flags(void)
> :
> : "memory");
>
> + temp = (1 << 5) |
> + ((!!(temp & STATUS_IE_MASK)) << CLRI_STATUS_IE_BIT) |
> + (temp & CLRI_STATUS_E_MASK);
> return temp;
> }
>
> @@ -108,7 +116,7 @@ static inline long arch_local_save_flags(void)
> */
> static inline int arch_irqs_disabled_flags(unsigned long flags)
> {
> - return !(flags & (STATUS_IE_MASK));
> + return !(flags & (CLRI_STATUS_IE_MASK));
> }
>
> static inline int arch_irqs_disabled(void)
> @@ -128,11 +136,32 @@ static inline void arc_softirq_clear(int irq)
>
> #else
>
> +#ifdef CONFIG_TRACE_IRQFLAGS
> +
> +.macro TRACE_ASM_IRQ_DISABLE
> + bl trace_hardirqs_off
> +.endm
> +
> +.macro TRACE_ASM_IRQ_ENABLE
> + bl trace_hardirqs_on
> +.endm
> +
> +#else
> +
> +.macro TRACE_ASM_IRQ_DISABLE
> +.endm
> +
> +.macro TRACE_ASM_IRQ_ENABLE
> +.endm
> +
> +#endif
> .macro IRQ_DISABLE scratch
> clri
> + TRACE_ASM_IRQ_DISABLE
> .endm
>
> .macro IRQ_ENABLE scratch
> + TRACE_ASM_IRQ_ENABLE
> seti
> .endm
>
> diff --git a/arch/arc/kernel/entry-arcv2.S b/arch/arc/kernel/entry-arcv2.S
> index c126460..24d9431 100644
> --- a/arch/arc/kernel/entry-arcv2.S
> +++ b/arch/arc/kernel/entry-arcv2.S
> @@ -69,8 +69,11 @@ ENTRY(handle_interrupt)
>
> clri; To make status32.IE agree with CPU internal state
>
> - lr r0, [ICAUSE]
> +#ifdef CONFIG_TRACE_IRQFLAGS
> + TRACE_ASM_IRQ_DISABLE
> +#endif
>
> + lr r0, [ICAUSE]
> mov blink, ret_from_exception
>
> b.d arch_do_IRQ
> @@ -173,6 +176,15 @@ END(EV_TLBProtV)
> lr r10, [AUX_IRQ_ACT]
>
> bmskr11, r10, 15; AUX_IRQ_ACT.ACTIVE
> +#ifdef CONFIG_TRACE_IRQFLAGS
> + push r0
> + push r10
> + push r11
> + TRACE_ASM_IRQ_ENABLE
> + pop r11
> + pop r10
> + pop r0
> +#endif
> breqr11, 0, .Lexcept_ret; No intr active, ret from Exception
Can we not call TRACE_ASM_IRQ_ENABLE right after .Lrestore_regs, before reading
any of these registers to avoid the push/pop dance. I don't see why it needs to
be
done where u have placed it currently.
I will give it a spin at my end as well.
Thx,
-Vineet
>
> ;### Return from Intr ###
>
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