Re: [PATCH 1/3 v2] drm/i2c/adv7511: Add audio support
Hi Jose,
Thank you for the patch.
On Monday 28 Mar 2016 15:36:09 Jose Abreu wrote:
> This patch adds audio support for the ADV7511 HDMI transmitter
> using ALSA SoC.
>
> The code was ported from Analog Devices linux tree from
> commit 1770c4a1e32b ("Merge remote-tracking branch
> 'xilinx/master' into xcomm_zynq"), which is available at:
> - https://github.com/analogdevicesinc/linux/
>
> The main core file was renamed from adv7511.c to adv7511_core.c
> so that audio and video compile into a single adv7511.ko module
> and to keep up with Analog Devices kernel tree.
>
> The audio can be disabled using menu-config so it is possible
> to use only video mode.
>
> The HDMI mode is automatically started at boot and the audio
> (when enabled) registers as a codec into ALSA.
>
> SPDIF DAI format was also added to ASoC as it is required
> by adv7511 audio.
>
> Signed-off-by: Jose Abreu
> ---
>
> No changes v1 -> v2.
>
> drivers/gpu/drm/i2c/Kconfig | 11 +
> drivers/gpu/drm/i2c/Makefile|2 +
> drivers/gpu/drm/i2c/adv7511.c | 1024 ---
> drivers/gpu/drm/i2c/adv7511.h | 41 ++
> drivers/gpu/drm/i2c/adv7511_audio.c | 310 +++
> drivers/gpu/drm/i2c/adv7511_core.c | 1005 ++
Please use git-format-patch -M to detect renames if you send a new version of
this series, it will help with review.
> include/sound/soc-dai.h |1 +
> 7 files changed, 1370 insertions(+), 1024 deletions(-)
> delete mode 100644 drivers/gpu/drm/i2c/adv7511.c
> create mode 100644 drivers/gpu/drm/i2c/adv7511_audio.c
> create mode 100644 drivers/gpu/drm/i2c/adv7511_core.c
[snip]
> diff --git a/drivers/gpu/drm/i2c/adv7511_core.c
> b/drivers/gpu/drm/i2c/adv7511_core.c new file mode 100644
> index 000..d54256a
> --- /dev/null
> +++ b/drivers/gpu/drm/i2c/adv7511_core.c
[snip]
> +static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id
> *id) +{
> + struct adv7511_link_config link_config;
> + struct adv7511 *adv7511;
> + struct device *dev = &i2c->dev;
> + unsigned int val;
> + int ret;
> +
> + if (!dev->of_node)
> + return -EINVAL;
> +
> + adv7511 = devm_kzalloc(dev, sizeof(*adv7511), GFP_KERNEL);
> + if (!adv7511)
> + return -ENOMEM;
> +
> + adv7511->powered = false;
> + adv7511->status = connector_status_disconnected;
> +
> + ret = adv7511_parse_dt(dev->of_node, &link_config);
> + if (ret)
> + return ret;
> +
> + /*
> + * The power down GPIO is optional. If present, toggle it from active to
> + * inactive to wake up the encoder.
> + */
> + adv7511->gpio_pd = devm_gpiod_get_optional(dev, "pd", GPIOD_OUT_HIGH);
> + if (IS_ERR(adv7511->gpio_pd))
> + return PTR_ERR(adv7511->gpio_pd);
> +
> + if (adv7511->gpio_pd) {
> + mdelay(5);
> + gpiod_set_value_cansleep(adv7511->gpio_pd, 0);
> + }
> +
> + adv7511->regmap = devm_regmap_init_i2c(i2c, &adv7511_regmap_config);
> + if (IS_ERR(adv7511->regmap))
> + return PTR_ERR(adv7511->regmap);
> +
> + ret = regmap_read(adv7511->regmap, ADV7511_REG_CHIP_REVISION, &val);
> + if (ret)
> + return ret;
> + dev_dbg(dev, "Rev. %d\n", val);
> +
> + ret = regmap_register_patch(adv7511->regmap, adv7511_fixed_registers,
> + ARRAY_SIZE(adv7511_fixed_registers));
> + if (ret)
> + return ret;
> +
> + regmap_write(adv7511->regmap, ADV7511_REG_EDID_I2C_ADDR, edid_i2c_addr);
> + regmap_write(adv7511->regmap, ADV7511_REG_PACKET_I2C_ADDR,
> + packet_i2c_addr);
> + regmap_write(adv7511->regmap, ADV7511_REG_CEC_I2C_ADDR, cec_i2c_addr);
> + adv7511_packet_disable(adv7511, 0x);
> +
> + adv7511->i2c_main = i2c;
> + adv7511->i2c_edid = i2c_new_dummy(i2c->adapter, edid_i2c_addr >> 1);
> + if (!adv7511->i2c_edid)
> + return -ENOMEM;
> +
> + if (i2c->irq) {
> + init_waitqueue_head(&adv7511->wq);
> +
> + ret = devm_request_threaded_irq(dev, i2c->irq, NULL,
> + adv7511_irq_handler,
> + IRQF_ONESHOT, dev_name(dev),
> + adv7511);
> + if (ret)
> + goto err_i2c_unregister_device;
> + }
> +
> + /* CEC is unused for now */
> + regmap_write(adv7511->regmap, ADV7511_REG_CEC_CTRL,
> + ADV7511_CEC_CTRL_POWER_DOWN);
> +
> + adv7511_power_off(adv7511);
> +
> + i2c_set_clientdata(i2c, adv7511);
> +
> +#ifdef CONFIG_DRM_I2C_ADV7511_AUDIO
> + adv7511_audio_init(&i2c->dev);
> +#endif
Shouldn't we condition this to the audio channel being somehow described in DT
? If a board doesn't route audio signals to the ADV7511 audio input, there's
no need to register an audio cod
[PATCH v7 1/3] soc: Support for EZchip SoC
From: Noam Camus
This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.
Signed-off-by: Noam Camus
Cc: Daniel Lezcano
Cc: Vineet Gupta
---
v7:
Rebased on latest HEAD (4.6-rc1)
v6:
Files headers changed to start with:
Copyright (c) 2016, Mellanox Technologies
...
This is due to the acquisition of EZchip made by Mellanox.
One can still find "EZchip" used in tree, and this is ok.
This patch set is a requierement before I can insert new platform to ARC,
one that supports the NPS400 SoC.
v5:
Clocksource, irqchip - Fix gracefull return.
replace call to panic() with pr_err() and
proper return value.
v4:
clocksource -- Apply all Daniel comments (Thanks)
Handle gracefull return and also using
clocksoure mmio driver at init
v3:
irqchip - Fix ARM build failure by adding missing include of linux/irq.h
clocksource -- Avoid 64bit arch's to build driver by adding new dependency
!PHYS_ADDR_T_64BIT
This is since we use explicit io access of 32
bit. So for test coverage we allow
not only build for ARC, but restrict it to 32
bit arch's.
irqchip - Apply all Thomas comments (Thank you)
v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.
General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/
Now ARC is supporting DT for clockevents and the interrupt controller ARC
uses irq domain handling.
Compare to last version now clocksource driver do not include clockevent
registration
since NPS400 can use ARC generic driver.
Compare to last version now irqchip driver sets domain as default since it is
the root domain.
Also mapping of IPI is done in this driver.
Last thing is that drivers can be build cleanly for i386 (still runs only for
ARC)
Note: in order to build we need to merge drivers into srctree which includes
new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.
Regards,
Noam Camus
---
include/soc/nps/common.h | 166 ++
1 files changed, 166 insertions(+), 0 deletions(-)
create mode 100644 include/soc/nps/common.h
diff --git a/include/soc/nps/common.h b/include/soc/nps/common.h
new file mode 100644
index 000..e959176
--- /dev/null
+++ b/include/soc/nps/common.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses. You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ *
+ * - Redistributions of source code must retain the above
+ *copyright notice, this list of conditions and the following
+ *disclaimer.
+ *
+ * - Redistributions in binary form must reproduce the above
+ *copyright notice, this list of conditions and the following
+ *disclaimer in the documentation and/or other materials
+ *provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef SOC_NPS_COMMON_H
+#define SOC_NPS_COMMON_H
+
+#ifdef CONFIG_SMP
+#define IPI_IRQ5
+#endif
+
+#define NPS_HOST_REG_BASE 0xF600
+
+#define NPS_MSU_BLKID 0x018
+
+#define CTOP_INST_RSPI_GIC_0_R12 0x3C56117E
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422
+
+#ifndef __ASSEMBLY__
+
+/* In order to increase compilation test coverage */
+#ifdef CONFIG_ARC
+static inline void nps_ack_gic(void)
+{
+ __asm__ __volatile__ (
+ " .word %0\n"
+ :
+ : "i"(CTOP_INST_RSPI_GIC_0_R12)
+ : "memory");
+}
+#else
+static inline void nps_ack_gic(void) { }
+#define write_aux_reg(r, v)
+#define read_aux_reg(r) 0
+#endif
+
+/* CPU global ID */
+struct global_id {
+ union {
+ struct {
+#ifdef C
[PATCH v7 3/3] irqchip: add nps Internal and external irqchips
From: Noam Camus
Adding EZchip NPS400 support.
Internal interrupts are handled by Multi Thread Manager (MTM)
Once interrupt is serviced MTM is acked for deactivating the interrupt.
External interrupts are handled by MTM as well as at Global Interrupt
Controller (GIC) e.g. serial and network devices.
Signed-off-by: Noam Camus
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: Daniel Lezcano
---
v7:
Rebased on latest HEAD (4.6-rc1)
v6:
Files headers changed to start with:
Copyright (c) 2016, Mellanox Technologies
...
This is due to the acquisition of EZchip made by Mellanox.
One can still find "EZchip" used in tree, and this is ok.
This patch set is a requierement before I can insert new platform to ARC,
one that supports the NPS400 SoC.
v5:
Clocksource, irqchip - Fix gracefull return.
replace call to panic() with pr_err() and
proper return value.
v4:
clocksource -- Apply all Daniel comments (Thanks)
Handle gracefull return and also using
clocksoure mmio driver at init
v3:
irqchip - Fix ARM build failure by adding missing include of linux/irq.h
clocksource -- Avoid 64bit arch's to build driver by adding new dependency
!PHYS_ADDR_T_64BIT
This is since we use explicit io access of 32
bit. So for test coverage we allow
not only build for ARC, but restrict it to 32
bit arch's.
irqchip - Apply all Thomas comments (Thank you)
v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.
General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/
Now ARC is supporting DT for clockevents and the interrupt controller ARC
uses irq domain handling.
Compare to last version now clocksource driver do not include clockevent
registration
since NPS400 can use ARC generic driver.
Compare to last version now irqchip driver sets domain as default since it is
the root domain.
Also mapping of IPI is done in this driver.
Last thing is that drivers can be build cleanly for i386 (still runs only for
ARC)
Note: in order to build we need to merge drivers into srctree which includes
new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.
Regards,
Noam Camus
---
.../interrupt-controller/ezchip,nps400-ic.txt | 17 ++
drivers/irqchip/Kconfig|6 +
drivers/irqchip/Makefile |1 +
drivers/irqchip/irq-eznps.c| 165
4 files changed, 189 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
create mode 100644 drivers/irqchip/irq-eznps.c
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
new file mode 100644
index 000..888b2b9
--- /dev/null
+++
b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
@@ -0,0 +1,17 @@
+EZchip NPS Interrupt Controller
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-ic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+
+
+Example:
+
+intc: interrupt-controller {
+ compatible = "ezchip,nps400-ic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 3e12479..1ab632a 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -244,3 +244,9 @@ config IRQ_MXS
config MVEBU_ODMI
bool
select GENERIC_MSI_IRQ_DOMAIN
+
+config EZNPS_GIC
+ bool "NPS400 Global Interrupt Manager (GIM)"
+ select IRQ_DOMAIN
+ help
+ Support the EZchip NPS400 global interrupt controller
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index b03cfcb..9d54d53 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -65,3 +65,4 @@ obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
obj-$(CONFIG_IMX_GPCV2)+= irq-imx-gpcv2.o
obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o
obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
+obj-$(CONFIG_EZNPS_GIC)+= irq-eznps.o
diff --git a/drivers/irqchip/irq-eznps.c b/drivers/irqchip/irq-eznps.c
new file mode 100644
index 000..97e4294
--- /dev/null
+++ b/drivers/irqchip/irq-eznps.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses. You may choose to be licensed under the terms of the GNU
+ * General Public Li
[PATCH v7 2/3] clocksource: Add NPS400 timers driver
From: Noam Camus
Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.
Signed-off-by: Noam Camus
Cc: Daniel Lezcano
Cc: Rob Herring
Cc: Thomas Gleixner
Cc: John Stultz
Cc: Vineet Gupta
---
v7:
Rebased on latest HEAD (4.6-rc1)
v6:
Files headers changed to start with:
Copyright (c) 2016, Mellanox Technologies
...
This is due to the acquisition of EZchip made by Mellanox.
One can still find "EZchip" used in tree, and this is ok.
This patch set is a requierement before I can insert new platform to ARC,
one that supports the NPS400 SoC.
v5:
Clocksource, irqchip - Fix gracefull return.
replace call to panic() with pr_err() and
proper return value.
v4:
clocksource -- Apply all Daniel comments (Thanks)
Handle gracefull return and also using
clocksoure mmio driver at init
v3:
irqchip - Fix ARM build failure by adding missing include of linux/irq.h
clocksource -- Avoid 64bit arch's to build driver by adding new dependency
!PHYS_ADDR_T_64BIT
This is since we use explicit io access of 32
bit. So for test coverage we allow
not only build for ARC, but restrict it to 32
bit arch's.
irqchip - Apply all Thomas comments (Thank you)
v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.
General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/
Now ARC is supporting DT for clockevents and the interrupt controller ARC
uses irq domain handling.
Compare to last version now clocksource driver do not include clockevent
registration
since NPS400 can use ARC generic driver.
Compare to last version now irqchip driver sets domain as default since it is
the root domain.
Also mapping of IPI is done in this driver.
Last thing is that drivers can be build cleanly for i386 (still runs only for
ARC)
Note: in order to build we need to merge drivers into srctree which includes
new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.
Regards,
Noam Camus
---
.../bindings/timer/ezchip,nps400-timer.txt | 15 +++
drivers/clocksource/Kconfig| 10 ++
drivers/clocksource/Makefile |1 +
drivers/clocksource/timer-nps.c| 98
4 files changed, 124 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 drivers/clocksource/timer-nps.c
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
new file mode 100644
index 000..c8c03d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
@@ -0,0 +1,15 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer"
+
+Clocks required for compatible = "ezchip,nps400-timer":
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+ compatible = "ezchip,nps400-timer";
+ clocks = <&sysclk>;
+};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index c346be6..3932d09 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -181,6 +181,16 @@ config CLKSRC_TI_32K
This option enables support for Texas Instruments 32.768 Hz
clocksource
available on many OMAP-like platforms.
+config CLKSRC_NPS
+ bool "NPS400 clocksource driver" if COMPILE_TEST
+ depends on !PHYS_ADDR_T_64BIT
+ select CLKSRC_MMIO
+ select CLKSRC_OF if OF
+ help
+ NPS400 clocksource support.
+ Got 64 bit counter with update rate up to 1000MHz.
+ This counter is accessed via couple of 32 bit memory mapped registers.
+
config CLKSRC_STM32
bool "Clocksource for STM32 SoCs" if !ARCH_STM32
depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index dc2b899..0b0a4b5 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
obj-$(CONFIG_CLKSRC_TI_32K)+= timer-ti-32k.o
+obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
new file mode 100644
index 000..d461089
--- /dev/null
+++ b/drivers/clocksource/
[PATCH v7 0/3] Adding NPS400 drivers
From: Noam Camus Change Log-- v7: Rebased on latest HEAD (4.6-rc1) Added change log to all patches to ease review. v6: Files headers changed to start with: Copyright (c) 2016, Mellanox Technologies ... This is due to the acquisition of EZchip made by Mellanox. One can still find "EZchip" used in tree, and this is ok. This patch set is a requierement before I can insert new platform to ARC, one that supports the NPS400 SoC. v5: Clocksource, irqchip - Fix gracefull return. replace call to panic() with pr_err() and proper return value. v4: clocksource -- Apply all Daniel comments (Thanks) Handle gracefull return and also using clocksoure mmio driver at init v3: irqchip - Fix ARM build failure by adding missing include of linux/irq.h clocksource -- Avoid 64bit arch's to build driver by adding new dependency !PHYS_ADDR_T_64BIT This is since we use explicit io access of 32 bit. So for test coverage we allow not only build for ARC, but restrict it to 32 bit arch's. irqchip - Apply all Thomas comments (Thank you) v2: Add header file include/soc/nps/common.h. Now to build we do not depend on ARC subtree. General summay: Both drivers are now apart of previous basic patch set of new platform for ARC. The rest is now can be seen at ARC srctree: https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/ Now ARC is supporting DT for clockevents and the interrupt controller ARC uses irq domain handling. Compare to last version now clocksource driver do not include clockevent registration since NPS400 can use ARC generic driver. Compare to last version now irqchip driver sets domain as default since it is the root domain. Also mapping of IPI is done in this driver. Last thing is that drivers can be build cleanly for i386 (still runs only for ARC) Note: in order to build we need to merge drivers into srctree which includes new header: soc/nps/common.h This header is part of patch set applied to ARC srctree. Regards, Noam Camus Noam Camus (3): soc: Support for EZchip SoC clocksource: Add NPS400 timers driver irqchip: add nps Internal and external irqchips .../interrupt-controller/ezchip,nps400-ic.txt | 17 ++ .../bindings/timer/ezchip,nps400-timer.txt | 15 ++ drivers/clocksource/Kconfig| 10 ++ drivers/clocksource/Makefile |1 + drivers/clocksource/timer-nps.c| 98 drivers/irqchip/Kconfig|6 + drivers/irqchip/Makefile |1 + drivers/irqchip/irq-eznps.c| 165 +++ include/soc/nps/common.h | 166 9 files changed, 479 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt create mode 100644 drivers/clocksource/timer-nps.c create mode 100644 drivers/irqchip/irq-eznps.c create mode 100644 include/soc/nps/common.h ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [PATCH v3] clk/axs10x: Add I2S PLL clock driver
On 03/31, Jose Abreu wrote:
>
> arch/arc/boot/dts/axs10x_mb.dtsi | 5 ++
Please remove this diff from this patch. dts changes go through
non-clk trees.
> drivers/clk/Makefile | 1 +
> drivers/clk/axs10x/Makefile| 1 +
> drivers/clk/axs10x/i2s_pll_clock.c | 163
> +
Where is the binding document?
> diff --git a/drivers/clk/axs10x/i2s_pll_clock.c
> b/drivers/clk/axs10x/i2s_pll_clock.c
> new file mode 100644
> index 000..f050e70
> --- /dev/null
> +++ b/drivers/clk/axs10x/i2s_pll_clock.c
> @@ -0,0 +1,163 @@
> +/* FPGA Version Info */
> +#define FPGA_VER_INFO0xE0011230
> +#define FPGA_VER_27M 0x000FBED9
> +
> +/* PLL registers addresses */
> +#define PLL_IDIV_ADDR0xE00100A0
> +#define PLL_FBDIV_ADDR 0xE00100A4
> +#define PLL_ODIV0_ADDR 0xE00100A8
> +#define PLL_ODIV1_ADDR 0xE00100AC
> +
> +struct i2s_pll_cfg {
> + unsigned int rate;
> + unsigned int idiv;
> + unsigned int fbdiv;
> + unsigned int odiv0;
> + unsigned int odiv1;
> +};
> +
> +static struct i2s_pll_cfg i2s_pll_cfg_27m[] = {
const?
> + /* 27 Mhz */
> + { 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
> + { 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
> + { 1536000, 0x208, 0xA28, 0x10B2C, 0x2000 },
> + { 2048000, 0x82, 0x451, 0x10E38, 0x2000 },
> + { 2822400, 0x82, 0x596, 0x10D35, 0x2000 },
> + { 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
> + { 2116800, 0x82, 0x3CF, 0x10C30, 0x2000 },
> + { 2304000, 0x104, 0x79E, 0x10B2C, 0x2000 },
> + { 0, 0, 0, 0, 0 },
> +};
> +
> +static struct i2s_pll_cfg i2s_pll_cfg_28m[] = {
const?
> + /* 28.224 Mhz */
> + { 1024000, 0x82, 0x105, 0x107DF, 0x2000 },
> + { 1411200, 0x28A, 0x1, 0x10001, 0x2000 },
> + { 1536000, 0xA28, 0x187, 0x10042, 0x2000 },
> + { 2048000, 0x41, 0x105, 0x107DF, 0x2000 },
> + { 2822400, 0x145, 0x1, 0x10001, 0x2000 },
> + { 3072000, 0x514, 0x187, 0x10042, 0x2000 },
> + { 2116800, 0x514, 0x42, 0x10001, 0x2000 },
> + { 2304000, 0x619, 0x82, 0x10001, 0x2000 },
> + { 0, 0, 0, 0, 0 },
> +};
> +
> +struct i2s_pll_clk {
> + struct clk_hw hw;
> + unsigned long ref_clk;
> + struct i2s_pll_cfg *pll_cfg;
> +};
> +
> +static inline struct i2s_pll_clk *to_i2s_pll_clk(struct clk_hw *hw)
> +{
> + return container_of(hw, struct i2s_pll_clk, hw);
> +}
> +
> +static unsigned int i2s_pll_get_value(unsigned int val)
> +{
> + return ((val & 0x3F) + ((val >> 6) & 0x3F));
Please drop extraneous parentheses.
> +}
> +
> +static unsigned long i2s_pll_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct i2s_pll_clk *clk = to_i2s_pll_clk(hw);
> + unsigned int idiv, fbdiv, odiv;
> +
> + idiv = i2s_pll_get_value(readl((void *)PLL_IDIV_ADDR));
We need a real ioremap in this driver instead of casting physical
addresses to pointers and calling readl on them.
> + fbdiv = i2s_pll_get_value(readl((void *)PLL_FBDIV_ADDR));
> + odiv = i2s_pll_get_value(readl((void *)PLL_ODIV0_ADDR));
> +
> + return (((clk->ref_clk / idiv ) * fbdiv) / odiv);
Again, too many parentheses. Also, any concerns of 32-bit
truncation here (i.e. is 64-bit math needed)?
> +}
> +
> +static long i2s_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *prate)
> +{
> + /* TODO: Round rate to nearest valid rate */
At the least this should return the rate from the table if it's
there or failure if it isn't an exact match. Basically do exactly
what i2s_pll_set_rate() is doing without changing the rate.
> + return rate;
> +}
> +
> +static int i2s_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct i2s_pll_cfg *pll_cfg = to_i2s_pll_clk(hw)->pll_cfg;
> + int i;
> +
> + for (i = 0; pll_cfg[i].rate != 0; i++) {
> + if (pll_cfg[i].rate == rate) {
> + writel(pll_cfg[i].idiv, (void *)PLL_IDIV_ADDR);
> + writel(pll_cfg[i].fbdiv, (void *)PLL_FBDIV_ADDR);
> + writel(pll_cfg[i].odiv0, (void *)PLL_ODIV0_ADDR);
> + writel(pll_cfg[i].odiv1, (void *)PLL_ODIV1_ADDR);
> + return 0;
> + }
> + }
> +
> + pr_err("%s: invalid rate=%ld, parent_rate=%ld\n", __func__,
> + rate, parent_rate);
> + return -EINVAL;
> +}
> +
> +static const struct clk_ops i2s_pll_ops = {
> + .recalc_rate = i2s_pll_recalc_rate,
> + .round_rate = i2s_pll_round_rate,
> + .set_rate = i2s_pll_set_rate,
> +};
> +
> +static void __init i2s_pll_clk_setup(struct device_node *node)
> +{
> + const char *clk_name = node->name;
> + struct clk *clk;
> + struct i2s_pll_clk *pll_clk;
> + struct clk_init_data init;
> +
> + pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
> + if (!pll_clk)
> + return;
> +
> +
Re: [PATCH v7 3/3] irqchip: add nps Internal and external irqchips
Hi Noam, [auto build test WARNING on tip/irq/core] [also build test WARNING on v4.6-rc1 next-20160401] [if your patch is applied to the wrong git tree, please drop us a note to help improving the system] url: https://github.com/0day-ci/linux/commits/Noam-Camus/Adding-NPS400-drivers/20160402-044058 config: parisc-allyesconfig (attached as .config) reproduce: wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree make.cross ARCH=parisc All warnings (new ones prefixed by >>): In file included from drivers/irqchip/irq-eznps.c:39:0: >> include/soc/nps/common.h:37:0: warning: "IPI_IRQ" redefined #define IPI_IRQ 5 ^ In file included from include/linux/irq.h:26:0, from arch/parisc/include/asm/hardirq.h:12, from include/linux/hardirq.h:8, from include/linux/interrupt.h:12, from drivers/irqchip/irq-eznps.c:33: arch/parisc/include/asm/irq.h:24:0: note: this is the location of the previous definition #define IPI_IRQ (CPU_IRQ_BASE + 1) ^ vim +/IPI_IRQ +37 include/soc/nps/common.h 4ff0d081 Noam Camus 2016-04-01 21 *provided with the distribution. 4ff0d081 Noam Camus 2016-04-01 22 * 4ff0d081 Noam Camus 2016-04-01 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 4ff0d081 Noam Camus 2016-04-01 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 4ff0d081 Noam Camus 2016-04-01 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 4ff0d081 Noam Camus 2016-04-01 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 4ff0d081 Noam Camus 2016-04-01 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 4ff0d081 Noam Camus 2016-04-01 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 4ff0d081 Noam Camus 2016-04-01 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 4ff0d081 Noam Camus 2016-04-01 30 * SOFTWARE. 4ff0d081 Noam Camus 2016-04-01 31 */ 4ff0d081 Noam Camus 2016-04-01 32 4ff0d081 Noam Camus 2016-04-01 33 #ifndef SOC_NPS_COMMON_H 4ff0d081 Noam Camus 2016-04-01 34 #define SOC_NPS_COMMON_H 4ff0d081 Noam Camus 2016-04-01 35 4ff0d081 Noam Camus 2016-04-01 36 #ifdef CONFIG_SMP 4ff0d081 Noam Camus 2016-04-01 @37 #define IPI_IRQ 5 4ff0d081 Noam Camus 2016-04-01 38 #endif 4ff0d081 Noam Camus 2016-04-01 39 4ff0d081 Noam Camus 2016-04-01 40 #define NPS_HOST_REG_BASE 0xF600 4ff0d081 Noam Camus 2016-04-01 41 4ff0d081 Noam Camus 2016-04-01 42 #define NPS_MSU_BLKID 0x018 4ff0d081 Noam Camus 2016-04-01 43 4ff0d081 Noam Camus 2016-04-01 44 #define CTOP_INST_RSPI_GIC_0_R12 0x3C56117E 4ff0d081 Noam Camus 2016-04-01 45 #define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60 :: The code at line 37 was first introduced by commit :: 4ff0d0814a05fc7aa0841df0a58bde13f7254c01 soc: Support for EZchip SoC :: TO: Noam Camus :: CC: 0day robot --- 0-DAY kernel test infrastructureOpen Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation .config.gz Description: Binary data ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
