Re: [PATCH v4 2/3] clocksource: Add NPS400 timers driver

2016-02-11 Thread Daniel Lezcano 

On 02/11/2016 04:02 AM, Noam Camus wrote:

From: Noam Camus 

Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.

Signed-off-by: Noam Camus 
Cc: Daniel Lezcano 
Cc: Rob Herring 
Cc: Thomas Gleixner 
Cc: John Stultz 
Acked-by: Vineet Gupta 
---


Acked-by: Daniel Lezcano 

but ...

[ ... ]


+   clk = of_clk_get(node, 0);
+   if (IS_ERR(clk))
+   panic("Can't get timer clock");


^^

I failed to see that at in the previous review.

Thanks

  -- Daniel

--
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[PATCH 1/2] mm, thp: refactor generic deposit/withdraw routines for wider usage

2016-02-11 Thread Vineet Gupta 
Generic pgtable_trans_huge_deposit()/pgtable_trans_huge_withdraw()
assume pgtable_t to be struct page * which is not true for all arches.
Thus arc, s390, sparch end up with their own copies despite no special
hardware requirements (unlike powerpc).

It seems massaging the code a bit can make it reusbale.

 - Use explicit casts to (struct page *). For existing users, this
   should be semantically no-op for existing users

 - The only addition is zero'ing out of page->lru which for arc leaves
   a stray entry in pgtable_t cause mm spew when such pgtable is freed.

  | huge_memory: BUG: failure at
  | ../mm/huge_memory.c:1858/__split_huge_page_map()!
  | CPU: 0 PID: 901 Comm: bw_mem Not tainted 4.4.0-00015-g0569c1459cfa-dirty
  |
  | Stack Trace:
  |  arc_unwind_core.constprop.1+0x94/0x104
  |  split_huge_page_to_list+0x5c0/0x920
  |  __split_huge_page_pmd+0xc8/0x1b4
  |  vma_adjust_trans_huge+0x104/0x1c8
  |  vma_adjust+0xf8/0x6d8
  |  __split_vma.isra.40+0xf8/0x174
  |  do_munmap+0x360/0x428
  |  SyS_munmap+0x28/0x44

Cc: Kirill A. Shutemov 
Cc: Aneesh Kumar K.V 
Cc: Andrea Arcangeli 
Cc: Andrew Morton 
Cc: David S. Miller 
Cc: Alex Thorlton 
Cc: Gerald Schaefer 
Cc: Martin Schwidefsky 
Cc: linux-snps-arc@lists.infradead.org
Cc: linux-ker...@vger.kernel.org
Cc: linux...@kvack.org
Cc: linux-a...@vger.kernel.org
Signed-off-by: Vineet Gupta 
---
 mm/pgtable-generic.c | 27 +--
 1 file changed, 17 insertions(+), 10 deletions(-)

diff --git a/mm/pgtable-generic.c b/mm/pgtable-generic.c
index 75664ed7e3ab..c9f2f6f8c7bb 100644
--- a/mm/pgtable-generic.c
+++ b/mm/pgtable-generic.c
@@ -155,13 +155,17 @@ void pmdp_splitting_flush(struct vm_area_struct *vma, 
unsigned long address,
 void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
pgtable_t pgtable)
 {
+   struct page *new = (struct page *)pgtable;
+   struct page *head;
+
assert_spin_locked(pmd_lockptr(mm, pmdp));
 
/* FIFO */
-   if (!pmd_huge_pte(mm, pmdp))
-   INIT_LIST_HEAD(&pgtable->lru);
+   head = (struct page *)pmd_huge_pte(mm, pmdp);
+   if (!head)
+   INIT_LIST_HEAD(&new->lru);
else
-   list_add(&pgtable->lru, &pmd_huge_pte(mm, pmdp)->lru);
+   list_add(&new->lru, &head->lru);
pmd_huge_pte(mm, pmdp) = pgtable;
 }
 #endif
@@ -170,20 +174,23 @@ void pgtable_trans_huge_deposit(struct mm_struct *mm, 
pmd_t *pmdp,
 /* no "address" argument so destroys page coloring of some arch */
 pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
 {
-   pgtable_t pgtable;
+   struct page *page;
 
assert_spin_locked(pmd_lockptr(mm, pmdp));
 
+   page = (struct page *)pmd_huge_pte(mm, pmdp);
+
/* FIFO */
-   pgtable = pmd_huge_pte(mm, pmdp);
-   if (list_empty(&pgtable->lru))
+   if (list_empty(&page->lru))
pmd_huge_pte(mm, pmdp) = NULL;
else {
-   pmd_huge_pte(mm, pmdp) = list_entry(pgtable->lru.next,
- struct page, lru);
-   list_del(&pgtable->lru);
+   pmd_huge_pte(mm, pmdp) = (pgtable_t) list_entry(page->lru.next,
+   struct page, lru);
+   list_del(&page->lru);
}
-   return pgtable;
+
+   memset(&page->lru, 0, sizeof(page->lru));
+   return (pgtable_t)page;
 }
 #endif
 
-- 
2.5.0


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[PATCH 0/2] Enable s390/arc/sparc to use generic thp deposit/withdraw

2016-02-11 Thread Vineet Gupta 
Hi,

This came out my debugging THP on ARC. The generic deposit/withdraw routines
can be easily adapted to work with pgtable_t != struct page *.

Build/Run tested on ARC only.

Thx,
-Vineet

Vineet Gupta (2):
  mm,thp: refactor generic deposit/withdraw routines for wider usage
  ARC: mm: THP: use generic THP deposit/withdraw

 arch/arc/include/asm/hugepage.h |  8 
 arch/arc/mm/tlb.c   | 37 -
 mm/pgtable-generic.c| 27 +--
 3 files changed, 17 insertions(+), 55 deletions(-)

-- 
2.5.0


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[PATCH 2/2] ARC: mm: THP: use generic THP deposit/withdraw

2016-02-11 Thread Vineet Gupta 
Generic code can now cope with pgtable_t != struct page *

Signed-off-by: Vineet Gupta 
---
 arch/arc/include/asm/hugepage.h |  8 
 arch/arc/mm/tlb.c   | 37 -
 2 files changed, 45 deletions(-)

diff --git a/arch/arc/include/asm/hugepage.h b/arch/arc/include/asm/hugepage.h
index c5094de86403..8653ed2f2ec5 100644
--- a/arch/arc/include/asm/hugepage.h
+++ b/arch/arc/include/asm/hugepage.h
@@ -66,14 +66,6 @@ extern void update_mmu_cache_pmd(struct vm_area_struct *vma, 
unsigned long addr,
 
 #define has_transparent_hugepage() 1
 
-/* Generic variants assume pgtable_t is struct page *, hence need for these */
-#define __HAVE_ARCH_PGTABLE_DEPOSIT
-extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
-  pgtable_t pgtable);
-
-#define __HAVE_ARCH_PGTABLE_WITHDRAW
-extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t 
*pmdp);
-
 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
 extern void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long 
start,
unsigned long end);
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index 2e731c87011e..b300479b8ad3 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -663,43 +663,6 @@ void update_mmu_cache_pmd(struct vm_area_struct *vma, 
unsigned long addr,
update_mmu_cache(vma, addr, &pte);
 }
 
-void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
-   pgtable_t pgtable)
-{
-   struct list_head *lh = (struct list_head *) pgtable;
-
-   assert_spin_locked(&mm->page_table_lock);
-
-   /* FIFO */
-   if (!pmd_huge_pte(mm, pmdp))
-   INIT_LIST_HEAD(lh);
-   else
-   list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
-   pmd_huge_pte(mm, pmdp) = pgtable;
-}
-
-pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
-{
-   struct list_head *lh;
-   pgtable_t pgtable;
-
-   assert_spin_locked(&mm->page_table_lock);
-
-   pgtable = pmd_huge_pte(mm, pmdp);
-   lh = (struct list_head *) pgtable;
-   if (list_empty(lh))
-   pmd_huge_pte(mm, pmdp) = NULL;
-   else {
-   pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
-   list_del(lh);
-   }
-
-   pte_val(pgtable[0]) = 0;
-   pte_val(pgtable[1]) = 0;
-
-   return pgtable;
-}
-
 void local_flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
   unsigned long end)
 {
-- 
2.5.0


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Re: [PATCH 1/2] mm,thp: refactor generic deposit/withdraw routines for wider usage

2016-02-11 Thread Martin Schwidefsky 
On Thu, 11 Feb 2016 14:58:26 +0530
Vineet Gupta  wrote:

> Generic pgtable_trans_huge_deposit()/pgtable_trans_huge_withdraw()
> assume pgtable_t to be struct page * which is not true for all arches.
> Thus arc, s390, sparch end up with their own copies despite no special
> hardware requirements (unlike powerpc).

s390 does have a special hardware requirement. pgtable_t is an address
for a 2K block of memory. It is *not* equivalent to a struct page *
which refers to a 4K block of memory. That has been the whole point
to introduce pgtable_t.

> It seems massaging the code a bit can make it reusbale.

Imho the new code for asm-generic looks fine, as long as the override
with __HAVE_ARCH_PGTABLE_DEPOSIT/__HAVE_ARCH_PGTABLE_WITHDRAW continues
to work I do not mind.

-- 
blue skies,
   Martin.

"Reality continues to ruin my life." - Calvin.


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Re: [PATCH 1/2] mm,thp: refactor generic deposit/withdraw routines for wider usage

2016-02-11 Thread Vineet Gupta 
On Thursday 11 February 2016 03:52 PM, Martin Schwidefsky wrote:
> On Thu, 11 Feb 2016 14:58:26 +0530
> Vineet Gupta  wrote:
> 
>> Generic pgtable_trans_huge_deposit()/pgtable_trans_huge_withdraw()
>> assume pgtable_t to be struct page * which is not true for all arches.
>> Thus arc, s390, sparch end up with their own copies despite no special
>> hardware requirements (unlike powerpc).
> 
> s390 does have a special hardware requirement. pgtable_t is an address
> for a 2K block of memory. It is *not* equivalent to a struct page *
> which refers to a 4K block of memory. That has been the whole point
> to introduce pgtable_t.

Actually my reference to hardware requirement was more like powerpc style save a
hash value some where etc.

Now pgtable_t need not be struct page * even if the actual sizes are same - e.g.
in ARC port I kept pgtable_t as pte_t * simply to avoid a few page_address() 
calls
in mm code (you could argue that is was a micro-optimization, anyways..)

So given I know nothing about s390 MMU internals, I still think you can switch 
to
the update generic version despite 2K vs. 4K. Agree ?

>> It seems massaging the code a bit can make it reusbale.
> 
> Imho the new code for asm-generic looks fine, as long as the override
> with __HAVE_ARCH_PGTABLE_DEPOSIT/__HAVE_ARCH_PGTABLE_WITHDRAW continues
> to work I do not mind.



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Re: [PATCH 1/2] mm,thp: refactor generic deposit/withdraw routines for wider usage

2016-02-11 Thread Martin Schwidefsky 
On Thu, 11 Feb 2016 16:23:33 +0530
Vineet Gupta  wrote:

> On Thursday 11 February 2016 03:52 PM, Martin Schwidefsky wrote:
> > On Thu, 11 Feb 2016 14:58:26 +0530
> > Vineet Gupta  wrote:
> > 
> >> Generic pgtable_trans_huge_deposit()/pgtable_trans_huge_withdraw()
> >> assume pgtable_t to be struct page * which is not true for all arches.
> >> Thus arc, s390, sparch end up with their own copies despite no special
> >> hardware requirements (unlike powerpc).
> > 
> > s390 does have a special hardware requirement. pgtable_t is an address
> > for a 2K block of memory. It is *not* equivalent to a struct page *
> > which refers to a 4K block of memory. That has been the whole point
> > to introduce pgtable_t.
> 
> Actually my reference to hardware requirement was more like powerpc style 
> save a
> hash value some where etc.
> 
> Now pgtable_t need not be struct page * even if the actual sizes are same - 
> e.g.
> in ARC port I kept pgtable_t as pte_t * simply to avoid a few page_address() 
> calls
> in mm code (you could argue that is was a micro-optimization, anyways..)
> 
> So given I know nothing about s390 MMU internals, I still think you can 
> switch to
> the update generic version despite 2K vs. 4K. Agree ?

No, we can not. For s390 a page table is aligned on a 2K boundary and is
only half the size of a page (except for KVM but that is another story).
For s390 a pgtable_t is a pointer to the memory location with the 256 ptes
and not a struct page *.

The cast "struct page *new = (struct page*)pgtable;" in your first patch
is already broken, "new" points to the memory of the page table and
the list_head operations will clobber that memory. You try to fix it up
with the memset to zero in pgtable_trans_huge_withdraw but that does not
correct the pte entries for s390 as an invalid page-table entry is *not*
all zeros.

In short, please let s390 keep its own copy of deposit/withdraw.

-- 
blue skies,
   Martin.

"Reality continues to ruin my life." - Calvin.


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Re: [PATCH 1/2] mm,thp: refactor generic deposit/withdraw routines for wider usage

2016-02-11 Thread Vineet Gupta 
On Thursday 11 February 2016 04:50 PM, Martin Schwidefsky wrote:
> On Thu, 11 Feb 2016 16:23:33 +0530
> Vineet Gupta  wrote:
> 
>> On Thursday 11 February 2016 03:52 PM, Martin Schwidefsky wrote:
>>> On Thu, 11 Feb 2016 14:58:26 +0530
>>> Vineet Gupta  wrote:
>>>
 Generic pgtable_trans_huge_deposit()/pgtable_trans_huge_withdraw()
 assume pgtable_t to be struct page * which is not true for all arches.
 Thus arc, s390, sparch end up with their own copies despite no special
 hardware requirements (unlike powerpc).
>>>
>>> s390 does have a special hardware requirement. pgtable_t is an address
>>> for a 2K block of memory. It is *not* equivalent to a struct page *
>>> which refers to a 4K block of memory. That has been the whole point
>>> to introduce pgtable_t.
>>
>> Actually my reference to hardware requirement was more like powerpc style 
>> save a
>> hash value some where etc.
>>
>> Now pgtable_t need not be struct page * even if the actual sizes are same - 
>> e.g.
>> in ARC port I kept pgtable_t as pte_t * simply to avoid a few page_address() 
>> calls
>> in mm code (you could argue that is was a micro-optimization, anyways..)
>>
>> So given I know nothing about s390 MMU internals, I still think you can 
>> switch to
>> the update generic version despite 2K vs. 4K. Agree ?
> 
> No, we can not. For s390 a page table is aligned on a 2K boundary and is
> only half the size of a page (except for KVM but that is another story).
> For s390 a pgtable_t is a pointer to the memory location with the 256 ptes
> and not a struct page *.
> 
> The cast "struct page *new = (struct page*)pgtable;" in your first patch
> is already broken, "new" points to the memory of the page table and
> the list_head operations will clobber that memory.

The current s390 code does something similar using a different struct cast. It 
is
still writing in pgtable_t - although at a different location.

> You try to fix it up
> with the memset to zero in pgtable_trans_huge_withdraw but that does not
> correct the pte entries for s390 as an invalid page-table entry is *not*
> all zeros.

Right so that is the problem - just trying to understand.

> In short, please let s390 keep its own copy of deposit/withdraw.

You got it - I'm out of the way :-)

Thx,
-Vineet

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[PATCH v5 0/3] Adding NPS400 drivers

2016-02-11 Thread Noam Camus 
From: Noam Camus 

Change Log--
v5:
Clocksource, irqchip - Fix gracefull return.
replace call to panic() with pr_err() and 
proper return value.

v4:
clocksource -- Apply all Daniel comments (Thanks)
Handle gracefull return and also using 
clocksoure mmio driver at init

v3:
irqchip - Fix ARM build failure by adding missing include of linux/irq.h
clocksource -- Avoid 64bit arch's to build driver by adding new dependency 
!PHYS_ADDR_T_64BIT
This is since we use explicit io access of 32 
bit. So for test coverage we allow
not only build for ARC, but restrict it to 32 
bit arch's.
irqchip - Apply all Thomas comments (Thank you)

v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.

General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/

Now ARC is supporting DT for clockevents and the interrupt controller ARC
uses irq domain handling.

Compare to last version now clocksource driver do not include clockevent 
registration
since NPS400 can use ARC generic driver.

Compare to last version now irqchip driver sets domain as default since it is 
the root domain.
Also mapping of IPI is done in this driver.

Last thing is that drivers can be build cleanly for i386 (still runs only for 
ARC)
Note: in order to build we need to merge drivers into srctree which includes 
new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.

Regards,
Noam Camus

Noam Camus (3):
  soc: Support for EZchip SoC
  clocksource: Add NPS400 timers driver
  irqchip: add nps Internal and external irqchips

 .../interrupt-controller/ezchip,nps400-ic.txt  |   17 +++
 .../bindings/timer/ezchip,nps400-timer.txt |   15 ++
 drivers/clocksource/Kconfig|   10 ++
 drivers/clocksource/Makefile   |1 +
 drivers/clocksource/timer-nps.c|   82 +++
 drivers/irqchip/Kconfig|6 +
 drivers/irqchip/Makefile   |1 +
 drivers/irqchip/irq-eznps.c|  149 +++
 include/soc/nps/common.h   |  150 
 9 files changed, 431 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
 create mode 100644 
Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
 create mode 100644 drivers/clocksource/timer-nps.c
 create mode 100644 drivers/irqchip/irq-eznps.c
 create mode 100644 include/soc/nps/common.h


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[PATCH v5 1/3] soc: Support for EZchip SoC

2016-02-11 Thread Noam Camus 
From: Noam Camus 

This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.

Signed-off-by: Noam Camus 
---
 include/soc/nps/common.h |  150 ++
 1 files changed, 150 insertions(+), 0 deletions(-)
 create mode 100644 include/soc/nps/common.h

diff --git a/include/soc/nps/common.h b/include/soc/nps/common.h
new file mode 100644
index 000..35ebb00
--- /dev/null
+++ b/include/soc/nps/common.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#ifndef SOC_NPS_COMMON_H
+#define SOC_NPS_COMMON_H
+
+#ifdef CONFIG_SMP
+#define IPI_IRQ5
+#endif
+
+#define NPS_HOST_REG_BASE  0xF600
+
+#define NPS_MSU_BLKID  0x018
+
+#define CTOP_INST_RSPI_GIC_0_R12   0x3C56117E
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422
+
+#ifndef __ASSEMBLY__
+
+/* In order to increase compilation test coverage */
+#ifdef CONFIG_ARC
+static inline void nps_ack_gic(void)
+{
+   __asm__ __volatile__ (
+   "   .word %0\n"
+   :
+   : "i"(CTOP_INST_RSPI_GIC_0_R12)
+   : "memory");
+}
+#else
+static inline void nps_ack_gic(void) { }
+#define write_aux_reg(r, v)
+#define read_aux_reg(r) 0
+#endif
+
+/* CPU global ID */
+struct global_id {
+   union {
+   struct {
+#ifdef CONFIG_EZNPS_MTM_EXT
+   u32 __reserved:20, cluster:4, core:4, thread:4;
+#else
+   u32 __reserved:24, cluster:4, core:4;
+#endif
+   };
+   u32 value;
+   };
+};
+
+/*
+ * Convert logical to physical CPU IDs
+ *
+ * The conversion swap bits 1 and 2 of cluster id (out of 4 bits)
+ * Now quad of logical clusters id's are adjacent physically,
+ * and not like the id's physically came with each cluster.
+ * Below table is 4x4 mesh of core clusters as it layout on chip.
+ * Cluster ids are in format: logical (physical)
+ *
+ *-   --
+ * 3 |  5 (3)   7 (7)  | | 13 (11)   15 (15)|
+ *
+ * 2 |  4 (2)   6 (6)  | | 12 (10)   14 (14)|
+ *-   --
+ * 1 |  1 (1)   3 (5)  | |  9  (9)   11 (13)|
+ *
+ * 0 |  0 (0)   2 (4)  | |  8  (8)   10 (12)|
+ *-   --
+ *   0   123
+ */
+static inline int nps_cluster_logic_to_phys(int cluster)
+{
+#ifdef __arc__
+__asm__ __volatile__(
+   "   mov r3,%0\n"
+   "   .short %1\n"
+   "   .word %2\n"
+   "   mov %0,r3\n"
+   : "+r"(cluster)
+   : "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST),
+ "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM)
+   : "r3");
+#endif
+
+   return cluster;
+}
+
+#define NPS_CPU_TO_CLUSTER_NUM(cpu) \
+   ({ struct global_id gid; gid.value = cpu; \
+   nps_cluster_logic_to_phys(gid.cluster); })
+
+struct nps_host_reg_address {
+   union {
+   struct {
+   u32 base:8, cl_x:4, cl_y:4,
+   blkid:6, reg:8, __reserved:2;
+   };
+   u32 value;
+   };
+};
+
+struct nps_host_reg_address_non_cl {
+   union {
+   struct {
+   u32 base:7, blkid:11, reg:12, __reserved:2;
+   };
+   u32 value;
+   };
+};
+
+static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
+{
+   struct nps_host_reg_address_non_cl reg_address;
+
+   reg_address.value = NPS_HOST_REG_BASE;
+   reg_address.blkid = blkid;
+   reg_address.reg = reg;
+
+   return (void *)reg_address.value;
+}
+
+static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
+{
+   struct nps_host_reg_address reg_address;
+   u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
+
+   reg_address.value = NPS_HOST_REG_BASE;
+   reg_address.cl_x  = (cl >> 2) & 0x3;
+   reg_address.cl_y  = cl & 0x3;
+   reg_address.blkid = blkid;
+   reg_address.reg   = reg;
+
+   return (void *)reg_address.value;
+}
+#endif /* __ASSEMBLY__ */
+
+#endif /* SOC_NPS_COMMON_H */
-- 
1.7.1


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[PATCH v5 2/3] clocksource: Add NPS400 timers driver

2016-02-11 Thread Noam Camus 
From: Noam Camus 

Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.

Signed-off-by: Noam Camus 
Cc: Daniel Lezcano 
Cc: Rob Herring 
Cc: Thomas Gleixner 
Cc: John Stultz 
Acked-by: Vineet Gupta 
---
 .../bindings/timer/ezchip,nps400-timer.txt |   15 
 drivers/clocksource/Kconfig|   10 +++
 drivers/clocksource/Makefile   |1 +
 drivers/clocksource/timer-nps.c|   82 
 4 files changed, 108 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
 create mode 100644 drivers/clocksource/timer-nps.c

diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt 
b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
new file mode 100644
index 000..c8c03d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
@@ -0,0 +1,15 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer"
+
+Clocks required for compatible = "ezchip,nps400-timer":
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+   compatible = "ezchip,nps400-timer";
+   clocks = <&sysclk>;
+};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 2eb5f0e..fa7be50 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -132,6 +132,16 @@ config CLKSRC_TI_32K
  This option enables support for Texas Instruments 32.768 Hz 
clocksource
  available on many OMAP-like platforms.
 
+config CLKSRC_NPS
+   bool "NPS400 clocksource driver" if COMPILE_TEST
+   depends on !PHYS_ADDR_T_64BIT
+   select CLKSRC_MMIO
+   select CLKSRC_OF if OF
+   help
+ NPS400 clocksource support.
+ Got 64 bit counter with update rate up to 1000MHz.
+ This counter is accessed via couple of 32 bit memory mapped registers.
+
 config CLKSRC_STM32
bool "Clocksource for STM32 SoCs" if !ARCH_STM32
depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 56bd16e..056cffd 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
 obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
 obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
 obj-$(CONFIG_CLKSRC_TI_32K)+= timer-ti-32k.o
+obj-$(CONFIG_CLKSRC_NPS)   += timer-nps.o
 
 obj-$(CONFIG_ARM_ARCH_TIMER)   += arm_arch_timer.o
 obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
new file mode 100644
index 000..a89aecb
--- /dev/null
+++ b/drivers/clocksource/timer-nps.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define NPS_MSU_TICK_LOW   0xC8
+#define NPS_CLUSTER_OFFSET 8
+#define NPS_CLUSTER_NUM16
+
+/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
+static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
+
+static unsigned long nps_timer_rate;
+
+static cycle_t nps_clksrc_read(struct clocksource *clksrc)
+{
+   int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
+
+   return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
+}
+
+static void __init nps_setup_clocksource(struct device_node *node,
+struct clk *clk)
+{
+   int ret, cluster;
+
+   for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
+   nps_msu_reg_low_addr[cluster] =
+   nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
+NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
+
+   ret = clk_prepare_enable(clk);
+   if (ret) {
+   pr_err("Couldn't enable parent clock\n");
+   return;
+   }
+
+   nps_timer_rate = clk_get_rate(clk);
+
+   ret = clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick",
+   nps_timer_rate, 301, 32, nps_clksrc_read);
+

[PATCH v5 3/3] irqchip: add nps Internal and external irqchips

2016-02-11 Thread Noam Camus 
From: Noam Camus 

Adding EZchip NPS400 support.
NPS internal interrupts are internally handled at
Multi Thread Manager (MTM) that is signaled for deactivating
an interrupt.
External interrupts is handled also at Global Interrupt
Controller (GIC) e.g. serial and network devices.

Signed-off-by: Noam Camus 
Cc: Thomas Gleixner 
Cc: Jason Cooper 
Cc: Marc Zyngier 
---
 .../interrupt-controller/ezchip,nps400-ic.txt  |   17 +++
 drivers/irqchip/Kconfig|6 +
 drivers/irqchip/Makefile   |1 +
 drivers/irqchip/irq-eznps.c|  149 
 4 files changed, 173 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
 create mode 100644 drivers/irqchip/irq-eznps.c

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt 
b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
new file mode 100644
index 000..888b2b9
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
@@ -0,0 +1,17 @@
+EZchip NPS Interrupt Controller
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-ic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 1.
+
+
+Example:
+
+intc: interrupt-controller {
+   compatible = "ezchip,nps400-ic";
+   interrupt-controller;
+   #interrupt-cells = <1>;
+};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 4d7294e..bc5e775 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -193,3 +193,9 @@ config IRQ_MXS
def_bool y if MACH_ASM9260 || ARCH_MXS
select IRQ_DOMAIN
select STMP_DEVICE
+
+config EZNPS_GIC
+   bool "NPS400 Global Interrupt Manager (GIM)"
+   select IRQ_DOMAIN
+   help
+ Support the EZchip NPS400 global interrupt controller
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 177f78f..1390142 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_RENESAS_H8S_INTC)+= 
irq-renesas-h8s.o
 obj-$(CONFIG_ARCH_SA1100)  += irq-sa11x0.o
 obj-$(CONFIG_INGENIC_IRQ)  += irq-ingenic.o
 obj-$(CONFIG_IMX_GPCV2)+= irq-imx-gpcv2.o
+obj-$(CONFIG_EZNPS_GIC)+= irq-eznps.o
diff --git a/drivers/irqchip/irq-eznps.c b/drivers/irqchip/irq-eznps.c
new file mode 100644
index 000..9decd7d
--- /dev/null
+++ b/drivers/irqchip/irq-eznps.c
@@ -0,0 +1,149 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define NPS_NR_CPU_IRQS 8  /* number of interrupt lines of NPS400 CPU */
+#define NPS_TIMER0_IRQ  3
+
+/*
+ * NPS400 core includes an Interrupt Controller (IC) support.
+ * All cores can deactivate level irqs at first level control
+ * at cores mesh layer called MTM.
+ * For devices out side chip e.g. uart, network there is another
+ * level called Global Interrupt Manager (GIM).
+ * This second level can control level and edge interrupt.
+ *
+ * NOTE: AUX_IENABLE and CTOP_AUX_IACK are auxiliary registers
+ * with private HW copy per CPU.
+ */
+
+static void nps400_irq_mask(struct irq_data *irqd)
+{
+   unsigned int ienb;
+   unsigned int irq = irqd_to_hwirq(irqd);
+
+   ienb = read_aux_reg(AUX_IENABLE);
+   ienb &= ~(1 << irq);
+   write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_unmask(struct irq_data *irqd)
+{
+   unsigned int ienb;
+   unsigned int irq = irqd_to_hwirq(irqd);
+
+   ienb = read_aux_reg(AUX_IENABLE);
+   ienb |= (1 << irq);
+   write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_eoi_global(struct irq_data *irqd)
+{
+   unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+   write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+
+   /* Don't ack GIC before all device access attempts are done */
+   mb();
+
+   nps_ack_gic();
+}
+
+static void nps400_irq_eoi(struct irq_data *irqd)
+{
+   unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+   write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+}
+
+static struct irq_chip nps400_irq_chip_fas

Re: [PATCH v5 2/3] clocksource: Add NPS400 timers driver

2016-02-11 Thread Daniel Lezcano 

On 02/11/2016 07:40 PM, Noam Camus wrote:

From: Noam Camus 

Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.

Signed-off-by: Noam Camus 
Cc: Daniel Lezcano 
Cc: Rob Herring 
Cc: Thomas Gleixner 
Cc: John Stultz 
Acked-by: Vineet Gupta 
---


Acked-by: Daniel Lezcano 


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