RE: [PATCH v3 2/3] clocksource: Add NPS400 timers driver

2016-02-10 Thread Noam Camus 
>From: Daniel Lezcano [mailto:daniel.lezc...@linaro.org] 
>Sent: Wednesday, February 10, 2016 12:55 AM

>> pr_err() in case of error just like most drivers around. By "hang" do 
>> you mean calling panic()?

>No. I meant the errors are caught but no action is taken, the execution 
>continues normally as nothing wrong happened. This is why I asked if you 
>expect the host to hang at boot time with the last error as a hint.

>I was expecting to see a call to clk_disable_unprepare if 
>clocksource_register_hz fails, and returning 'ret' if clk_prepare_enable fails.
Ok, I will fix that, and handle gracefull return. Thanks


>Using the mmio generic code will save:

>+static struct clocksource nps_counter = {
>+  .name   = "EZnps-tick",
>+  .rating = 301,
>+  .read   = nps_clksrc_read,
>+  .mask   = CLOCKSOURCE_MASK(32),
>+  .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
>+};

>Up to you.
I will do that, thanks again

Noam

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Re: [PATCH v9 2/2] pcie-designware platform driver

2016-02-10 Thread Joao Pinto 
Hi Bjorn,

On 2/8/2016 11:28 PM, Bjorn Helgaas wrote:
>>  if (!pci_has_flag(PCI_PROBE_ONLY)) {
>>^
>>drivers/pci/host/pcie-designware.c:581:20: note: each undeclared 
>> identifier is reported only once for each function it appears in
>>cc1: some warnings being treated as errors
> 
> I have fixes for this on my pci/misc branch, so you don't need to
> worry about these errors.  Basically I'm moving the PCI_PROBE_ONLY and
> pci_has_flag() declarations from the arch-specific asm/pci-bridge.h
> files to the generic linux/pci.h file.

Ok, thanks.

> 
>> vim +/pci_has_flag +581 drivers/pci/host/pcie-designware.c
>>
>> cbce7900 Zhou Wang   2015-10-29  575  
>> cbce7900 Zhou Wang   2015-10-29  576  #ifdef CONFIG_ARM
>> cbce7900 Zhou Wang   2015-10-29  577 /* support old dtbs that 
>> incorrectly describe IRQs */
>> cbce7900 Zhou Wang   2015-10-29  578 
>> pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
>> 0815f957 Yijing Wang 2014-11-11  579  #endif
>> 0815f957 Yijing Wang 2014-11-11  580  
>> cbce7900 Zhou Wang   2015-10-29 @581 if 
>> (!pci_has_flag(PCI_PROBE_ONLY)) {
>> cbce7900 Zhou Wang   2015-10-29  582 
>> pci_bus_size_bridges(bus);
>> cbce7900 Zhou Wang   2015-10-29  583 
>> pci_bus_assign_resources(bus);
>> 4b1ced84 Jingoo Han  2013-07-31  584  
>>
>> :: The code at line 581 was first introduced by commit
>> :: cbce7900598c26a12652f8ca9c41c5b29034c38d PCI: designware: Make driver 
>> arch-agnostic
>>
>> :: TO: Zhou Wang 
>> :: CC: Bjorn Helgaas 
>>
>> ---
>> 0-DAY kernel test infrastructureOpen Source Technology Center
>> https://lists.01.org/pipermail/kbuild-all   Intel Corporation
> 
> 

If there's anything else that is needed for the pcie-designware platform driver,
please let me know.

Thanks,
Joao

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Re: [PATCH] mm,thp: khugepaged: call pte flush at the time of collapse

2016-02-10 Thread Kirill A. Shutemov 
On Wed, Feb 10, 2016 at 10:26:15AM +0530, Vineet Gupta wrote:
> This showed up on ARC when running LMBench bw_mem tests as
> Overlapping TLB Machine Check Exception triggered due to STLB entry
> (2M pages) overlapping some NTLB entry (regular 8K page).
> 
> bw_mem 2m touches a large chunk of vaddr creating NTLB entries.
> In the interim khugepaged kicks in, collapsing the contiguous ptes into
> a single pmd. pmdp_collapse_flush()->flush_pmd_tlb_range() is called to
> flush out NTLB entries for the ptes. This for ARC (by design) can only
> shootdown STLB entries (for pmd). The stray NTLB entries cause the overlap
> with the subsequent STLB entry for collapsed page.
> So make pmdp_collapse_flush() call pte flush interface not pmd flush.
> 
> Note that originally all thp flush call sites in generic code called
> flush_tlb_range() leaving it to architecture to implement the flush for
> pte and/or pmd. Commit 12ebc1581ad11454 changed this by calling a new
> opt-in API flush_pmd_tlb_range() which made the semantics more explicit
> but failed to distinguish the pte vs pmd flush in generic code, which is
> what this patch fixes.
> 
> Note that ARC can fixed w/o touching the generic pmdp_collapse_flush()
> by defining a ARC version, but that defeats the purpose of generic
> version, plus sementically this is the right thing to do.
> 
> Fixes STAR 9000961194: LMBench on AXS103 triggering duplicate TLB
> exceptions with super pages
> 
> Cc: Kirill A. Shutemov 
> Cc: Aneesh Kumar K.V 
> Cc: Andrea Arcangeli 
> Cc: Andrew Morton 
> Cc:  #4.4
> Cc: 
> Cc: linux-ker...@vger.kernel.org
> Cc: linux...@kvack.org
> Fixes: 12ebc1581ad11454 ("mm,thp: introduce flush_pmd_tlb_range")
> Signed-off-by: Vineet Gupta 

Acked-by: Kirill A. Shutemov 

-- 
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Re: [PATCH 6/9] ARC: clocksource: DT based probe

2016-02-10 Thread Daniel Lezcano 

On 02/08/2016 01:23 PM, Vineet Gupta wrote:

On Monday 08 February 2016 05:40 PM, Daniel Lezcano wrote:

On 02/02/2016 11:58 AM, Vineet Gupta wrote:

- Remove explicit clocksource setup and let it be done by OF framework
by defining CLOCKSOURCE_OF_DECLARE() for various timers

- This allows multiple clocksources to be potentially registered
simultaneouly: previously we could only do one - as all of them had
same arc_counter_setup() routine for registration

- Setup routines also ensure that the underlying timer actually exists.

- Remove some of the panic() calls if underlying timer is NOT detcted as
a fallback clocksource might still be available
1. If GRFC doesn't exist, jiffies clocksource gets registered anyways
2. if RTC doesn't exist, TIMER1 cetainly will take over (as it is
   always present)

Cc: Daniel Lezcano 
Signed-off-by: Vineet Gupta 


May be it is time to move these drivers into the drivers/clocksource directory
where they belong to.


I suppose we could, but that is only possible after this round of 
"moderization",
i.e. usage of CLOCKSOURCE_OF_DECLARE() et al.

Plus the move will require a bunch of mechanical crap such as read_aux_reg() 
which
only ARC defines (similar to headaches Noam had for his clksrc).

So if we could agree on the sanity of this round of changes, I can work towards
the imminent move into drivers.


Ok, sounds good.


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[PATCH v4 0/3] Adding NPS400 drivers

2016-02-10 Thread Noam Camus 
From: Noam Camus 

Change Log--
v4:
clocksource -- Apply all Daniel comments (Thanks)
Handle gracefull return and also using 
clocksoure mmio driver

v3:
irqchip - Fix ARM build failure by adding missing include of linux/irq.h
clocksource -- Avoid 64bit arch's to build driver by adding new dependency 
!PHYS_ADDR_T_64BIT
This is since we use explicit io access of 32 
bit. So for test coverage we allow
not only build for ARC, but restrict it to 32 
bit arch's.
irqchip - Apply all Thomas comments (Thank you)

v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.

General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/

Now ARC is supporting DT for clockevents and the interrupt controller ARC
uses irq domain handling.

Compare to last version now clocksource driver do not include clockevent 
registration
since NPS400 can use ARC generic driver.

Compare to last version now irqchip driver sets domain as default since it is 
the root domain.
Also mapping of IPI is done in this driver.

Last thing is that drivers can be build cleanly for i386 (still runs only for 
ARC)
Note: in order to build we need to merge drivers into srctree which includes 
new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.

Regards,
Noam Camus

Noam Camus (3):
  soc: Support for EZchip SoC
  clocksource: Add NPS400 timers driver
  irqchip: add nps Internal and external irqchips

 .../interrupt-controller/ezchip,nps400-ic.txt  |   17 +++
 .../bindings/timer/ezchip,nps400-timer.txt |   15 ++
 drivers/clocksource/Kconfig|   10 ++
 drivers/clocksource/Makefile   |1 +
 drivers/clocksource/timer-nps.c|   80 +++
 drivers/irqchip/Kconfig|6 +
 drivers/irqchip/Makefile   |1 +
 drivers/irqchip/irq-eznps.c|  145 +++
 include/soc/nps/common.h   |  150 
 9 files changed, 425 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
 create mode 100644 
Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
 create mode 100644 drivers/clocksource/timer-nps.c
 create mode 100644 drivers/irqchip/irq-eznps.c
 create mode 100644 include/soc/nps/common.h


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[PATCH v4 2/3] clocksource: Add NPS400 timers driver

2016-02-10 Thread Noam Camus 
From: Noam Camus 

Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.

Signed-off-by: Noam Camus 
Cc: Daniel Lezcano 
Cc: Rob Herring 
Cc: Thomas Gleixner 
Cc: John Stultz 
Acked-by: Vineet Gupta 
---
 .../bindings/timer/ezchip,nps400-timer.txt |   15 
 drivers/clocksource/Kconfig|   10 +++
 drivers/clocksource/Makefile   |1 +
 drivers/clocksource/timer-nps.c|   80 
 4 files changed, 106 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
 create mode 100644 drivers/clocksource/timer-nps.c

diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt 
b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
new file mode 100644
index 000..c8c03d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
@@ -0,0 +1,15 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer"
+
+Clocks required for compatible = "ezchip,nps400-timer":
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+   compatible = "ezchip,nps400-timer";
+   clocks = <&sysclk>;
+};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 2eb5f0e..fa7be50 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -132,6 +132,16 @@ config CLKSRC_TI_32K
  This option enables support for Texas Instruments 32.768 Hz 
clocksource
  available on many OMAP-like platforms.
 
+config CLKSRC_NPS
+   bool "NPS400 clocksource driver" if COMPILE_TEST
+   depends on !PHYS_ADDR_T_64BIT
+   select CLKSRC_MMIO
+   select CLKSRC_OF if OF
+   help
+ NPS400 clocksource support.
+ Got 64 bit counter with update rate up to 1000MHz.
+ This counter is accessed via couple of 32 bit memory mapped registers.
+
 config CLKSRC_STM32
bool "Clocksource for STM32 SoCs" if !ARCH_STM32
depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 56bd16e..056cffd 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
 obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
 obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
 obj-$(CONFIG_CLKSRC_TI_32K)+= timer-ti-32k.o
+obj-$(CONFIG_CLKSRC_NPS)   += timer-nps.o
 
 obj-$(CONFIG_ARM_ARCH_TIMER)   += arm_arch_timer.o
 obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
new file mode 100644
index 000..5a15970
--- /dev/null
+++ b/drivers/clocksource/timer-nps.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define NPS_MSU_TICK_LOW   0xC8
+#define NPS_CLUSTER_OFFSET 8
+#define NPS_CLUSTER_NUM16
+
+/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
+static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
+
+static unsigned long nps_timer_rate;
+
+static cycle_t nps_clksrc_read(struct clocksource *clksrc)
+{
+   int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
+
+   return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
+}
+
+static void __init nps_setup_clocksource(struct device_node *node,
+struct clk *clk)
+{
+   int ret, cluster;
+
+   for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
+   nps_msu_reg_low_addr[cluster] =
+   nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
+NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
+
+   ret = clk_prepare_enable(clk);
+   if (ret) {
+   pr_err("Couldn't enable parent clock\n");
+   return;
+   }
+
+   nps_timer_rate = clk_get_rate(clk);
+
+   ret = clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick",
+   nps_timer_rate, 301, 32, nps_clksrc_read);
+

[PATCH v4 1/3] soc: Support for EZchip SoC

2016-02-10 Thread Noam Camus 
From: Noam Camus 

This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.

Signed-off-by: Noam Camus 
---
 include/soc/nps/common.h |  150 ++
 1 files changed, 150 insertions(+), 0 deletions(-)
 create mode 100644 include/soc/nps/common.h

diff --git a/include/soc/nps/common.h b/include/soc/nps/common.h
new file mode 100644
index 000..35ebb00
--- /dev/null
+++ b/include/soc/nps/common.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#ifndef SOC_NPS_COMMON_H
+#define SOC_NPS_COMMON_H
+
+#ifdef CONFIG_SMP
+#define IPI_IRQ5
+#endif
+
+#define NPS_HOST_REG_BASE  0xF600
+
+#define NPS_MSU_BLKID  0x018
+
+#define CTOP_INST_RSPI_GIC_0_R12   0x3C56117E
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422
+
+#ifndef __ASSEMBLY__
+
+/* In order to increase compilation test coverage */
+#ifdef CONFIG_ARC
+static inline void nps_ack_gic(void)
+{
+   __asm__ __volatile__ (
+   "   .word %0\n"
+   :
+   : "i"(CTOP_INST_RSPI_GIC_0_R12)
+   : "memory");
+}
+#else
+static inline void nps_ack_gic(void) { }
+#define write_aux_reg(r, v)
+#define read_aux_reg(r) 0
+#endif
+
+/* CPU global ID */
+struct global_id {
+   union {
+   struct {
+#ifdef CONFIG_EZNPS_MTM_EXT
+   u32 __reserved:20, cluster:4, core:4, thread:4;
+#else
+   u32 __reserved:24, cluster:4, core:4;
+#endif
+   };
+   u32 value;
+   };
+};
+
+/*
+ * Convert logical to physical CPU IDs
+ *
+ * The conversion swap bits 1 and 2 of cluster id (out of 4 bits)
+ * Now quad of logical clusters id's are adjacent physically,
+ * and not like the id's physically came with each cluster.
+ * Below table is 4x4 mesh of core clusters as it layout on chip.
+ * Cluster ids are in format: logical (physical)
+ *
+ *-   --
+ * 3 |  5 (3)   7 (7)  | | 13 (11)   15 (15)|
+ *
+ * 2 |  4 (2)   6 (6)  | | 12 (10)   14 (14)|
+ *-   --
+ * 1 |  1 (1)   3 (5)  | |  9  (9)   11 (13)|
+ *
+ * 0 |  0 (0)   2 (4)  | |  8  (8)   10 (12)|
+ *-   --
+ *   0   123
+ */
+static inline int nps_cluster_logic_to_phys(int cluster)
+{
+#ifdef __arc__
+__asm__ __volatile__(
+   "   mov r3,%0\n"
+   "   .short %1\n"
+   "   .word %2\n"
+   "   mov %0,r3\n"
+   : "+r"(cluster)
+   : "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST),
+ "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM)
+   : "r3");
+#endif
+
+   return cluster;
+}
+
+#define NPS_CPU_TO_CLUSTER_NUM(cpu) \
+   ({ struct global_id gid; gid.value = cpu; \
+   nps_cluster_logic_to_phys(gid.cluster); })
+
+struct nps_host_reg_address {
+   union {
+   struct {
+   u32 base:8, cl_x:4, cl_y:4,
+   blkid:6, reg:8, __reserved:2;
+   };
+   u32 value;
+   };
+};
+
+struct nps_host_reg_address_non_cl {
+   union {
+   struct {
+   u32 base:7, blkid:11, reg:12, __reserved:2;
+   };
+   u32 value;
+   };
+};
+
+static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
+{
+   struct nps_host_reg_address_non_cl reg_address;
+
+   reg_address.value = NPS_HOST_REG_BASE;
+   reg_address.blkid = blkid;
+   reg_address.reg = reg;
+
+   return (void *)reg_address.value;
+}
+
+static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
+{
+   struct nps_host_reg_address reg_address;
+   u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
+
+   reg_address.value = NPS_HOST_REG_BASE;
+   reg_address.cl_x  = (cl >> 2) & 0x3;
+   reg_address.cl_y  = cl & 0x3;
+   reg_address.blkid = blkid;
+   reg_address.reg   = reg;
+
+   return (void *)reg_address.value;
+}
+#endif /* __ASSEMBLY__ */
+
+#endif /* SOC_NPS_COMMON_H */
-- 
1.7.1


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[PATCH v4 3/3] irqchip: add nps Internal and external irqchips

2016-02-10 Thread Noam Camus 
From: Noam Camus 

Adding EZchip NPS400 support.
NPS internal interrupts are internally handled at
Multi Thread Manager (MTM) that is signaled for deactivating
an interrupt.
External interrupts is handled also at Global Interrupt
Controller (GIC) e.g. serial and network devices.

Signed-off-by: Noam Camus 
Cc: Thomas Gleixner 
Cc: Jason Cooper 
Cc: Marc Zyngier 
---
 .../interrupt-controller/ezchip,nps400-ic.txt  |   17 +++
 drivers/irqchip/Kconfig|6 +
 drivers/irqchip/Makefile   |1 +
 drivers/irqchip/irq-eznps.c|  145 
 4 files changed, 169 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
 create mode 100644 drivers/irqchip/irq-eznps.c

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt 
b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
new file mode 100644
index 000..888b2b9
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
@@ -0,0 +1,17 @@
+EZchip NPS Interrupt Controller
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-ic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 1.
+
+
+Example:
+
+intc: interrupt-controller {
+   compatible = "ezchip,nps400-ic";
+   interrupt-controller;
+   #interrupt-cells = <1>;
+};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 4d7294e..bc5e775 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -193,3 +193,9 @@ config IRQ_MXS
def_bool y if MACH_ASM9260 || ARCH_MXS
select IRQ_DOMAIN
select STMP_DEVICE
+
+config EZNPS_GIC
+   bool "NPS400 Global Interrupt Manager (GIM)"
+   select IRQ_DOMAIN
+   help
+ Support the EZchip NPS400 global interrupt controller
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 177f78f..1390142 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_RENESAS_H8S_INTC)+= 
irq-renesas-h8s.o
 obj-$(CONFIG_ARCH_SA1100)  += irq-sa11x0.o
 obj-$(CONFIG_INGENIC_IRQ)  += irq-ingenic.o
 obj-$(CONFIG_IMX_GPCV2)+= irq-imx-gpcv2.o
+obj-$(CONFIG_EZNPS_GIC)+= irq-eznps.o
diff --git a/drivers/irqchip/irq-eznps.c b/drivers/irqchip/irq-eznps.c
new file mode 100644
index 000..acc55a3
--- /dev/null
+++ b/drivers/irqchip/irq-eznps.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define NPS_NR_CPU_IRQS 8  /* number of interrupt lines of NPS400 CPU */
+#define NPS_TIMER0_IRQ  3
+
+/*
+ * NPS400 core includes an Interrupt Controller (IC) support.
+ * All cores can deactivate level irqs at first level control
+ * at cores mesh layer called MTM.
+ * For devices out side chip e.g. uart, network there is another
+ * level called Global Interrupt Manager (GIM).
+ * This second level can control level and edge interrupt.
+ *
+ * NOTE: AUX_IENABLE and CTOP_AUX_IACK are auxiliary registers
+ * with private HW copy per CPU.
+ */
+
+static void nps400_irq_mask(struct irq_data *irqd)
+{
+   unsigned int ienb;
+   unsigned int irq = irqd_to_hwirq(irqd);
+
+   ienb = read_aux_reg(AUX_IENABLE);
+   ienb &= ~(1 << irq);
+   write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_unmask(struct irq_data *irqd)
+{
+   unsigned int ienb;
+   unsigned int irq = irqd_to_hwirq(irqd);
+
+   ienb = read_aux_reg(AUX_IENABLE);
+   ienb |= (1 << irq);
+   write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_eoi_global(struct irq_data *irqd)
+{
+   unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+   write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+
+   /* Don't ack GIC before all device access attempts are done */
+   mb();
+
+   nps_ack_gic();
+}
+
+static void nps400_irq_eoi(struct irq_data *irqd)
+{
+   unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+   write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+}
+
+static struct irq_chip nps400_irq_chip_fas

Re: Signal handle without calling exit

2016-02-10 Thread Vineet Gupta 

On Thursday 11 February 2016 12:27 PM, Noam Camus wrote:
>
> Hi Vineet,
>
> In case user caused an exception that kernel turned into sinal that the user
> caught with its own implementation without calling exit.
> What we expect to happen when signal handler ends?
> Would it return to the same instruction the one after it or other?
> Is it in the first forbidden to not call exit?
>
> Noam
>

Some signals can't be caught - and depending on default behaviour kernel will 
kill
the task - it is not user task which calls exit.
For those where catching is allowed - e.g. segv, if handler doesn't do anything 
-
kernel will resume at exactly the same instruction.
So u could have an interesting loop in app - if tries to access NULL pointer 
with
signal handler installed for segv, and that handler does nothing.
Now your signal handler can tweak the register corresponding to PC in sigcontext
(ret for ARC) and kernel will use that for return to userspace - so the faulting
instruction will be avoided.

-Vineet

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