Re: [PATCH v9 2/2] pcie-designware platform driver
Hi Joao,
[auto build test ERROR on arc/for-next]
[cannot apply to pci/next v4.5-rc3 next-20160208]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Joao-Pinto/PCI-support-added-to-ARC/20160209-014808
base: https://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc for-next
config: x86_64-allmodconfig (attached as .config)
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All errors (new ones prefixed by >>):
include/linux/compiler.h:228:8: sparse: attribute 'no_sanitize_address':
unknown attribute
drivers/pci/host/pcie-designware.c:581:14: sparse: undefined identifier
'pci_has_flag'
drivers/pci/host/pcie-designware.c: In function 'dw_pcie_host_init':
>> drivers/pci/host/pcie-designware.c:581:7: error: implicit declaration of
>> function 'pci_has_flag' [-Werror=implicit-function-declaration]
if (!pci_has_flag(PCI_PROBE_ONLY)) {
^
>> drivers/pci/host/pcie-designware.c:581:20: error: 'PCI_PROBE_ONLY'
>> undeclared (first use in this function)
if (!pci_has_flag(PCI_PROBE_ONLY)) {
^
drivers/pci/host/pcie-designware.c:581:20: note: each undeclared identifier
is reported only once for each function it appears in
cc1: some warnings being treated as errors
vim +/pci_has_flag +581 drivers/pci/host/pcie-designware.c
cbce7900 Zhou Wang 2015-10-29 575
cbce7900 Zhou Wang 2015-10-29 576 #ifdef CONFIG_ARM
cbce7900 Zhou Wang 2015-10-29 577/* support old dtbs that incorrectly
describe IRQs */
cbce7900 Zhou Wang 2015-10-29 578pci_fixup_irqs(pci_common_swizzle,
of_irq_parse_and_map_pci);
0815f957 Yijing Wang 2014-11-11 579 #endif
0815f957 Yijing Wang 2014-11-11 580
cbce7900 Zhou Wang 2015-10-29 @581if (!pci_has_flag(PCI_PROBE_ONLY)) {
cbce7900 Zhou Wang 2015-10-29 582pci_bus_size_bridges(bus);
cbce7900 Zhou Wang 2015-10-29 583pci_bus_assign_resources(bus);
4b1ced84 Jingoo Han 2013-07-31 584
:: The code at line 581 was first introduced by commit
:: cbce7900598c26a12652f8ca9c41c5b29034c38d PCI: designware: Make driver
arch-agnostic
:: TO: Zhou Wang
:: CC: Bjorn Helgaas
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: Binary data
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RE: [PATCH v3 2/3] clocksource: Add NPS400 timers driver
>From: Daniel Lezcano [mailto:daniel.lezc...@linaro.org]
>Sent: Monday, February 08, 2016 4:22 PM
>> +ret = clk_prepare_enable(clk);
>> +if (ret)
>> +pr_err("Couldn't enable parent clock\n");
>> +
>> +nps_timer_rate = clk_get_rate(clk);
>If there is an error, you continue the execution of the code. I guess you
>expect the system to hang in any case with the error in the >console, right ?
Since our clock is root then returned value will always be valid.
I am far from being expert here, but no one checks for clk_get_rate() return
value for error.
Could you refer to a single place at clocksource drivers that checks for error
in the return value.
>> +ret = clocksource_register_hz(clksrc, nps_timer_rate);
>You can simplify the driver even more by using clocksource_mmio_init.
Since my base address depends on cluster number, which CPU is part of, this
interface is not much of a use. On top of that it assumes that I am little
endian by using readl family accessories.
-Noam
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Re: [PATCH v3 2/3] clocksource: Add NPS400 timers driver
On 02/09/2016 01:36 PM, Noam Camus wrote:
From: Daniel Lezcano [mailto:daniel.lezc...@linaro.org] Sent:
Monday, February 08, 2016 4:22 PM
+ ret = clk_prepare_enable(clk); +if (ret) +
pr_err("Couldn't
enable parent clock\n"); + + nps_timer_rate = clk_get_rate(clk);
If there is an error, you continue the execution of the code. I
guess you expect the system to hang in any case with the error in
the >console, right ?
Since our clock is root then returned value will always be valid. I
am far from being expert here, but no one checks for clk_get_rate()
return value for error. Could you refer to a single place at
clocksource drivers that checks for error in the return value.
Actually I was referring to clk_prepare_enable, clocksource_register_hz.
Agree clk_get_rate is always valid.
+ ret = clocksource_register_hz(clksrc, nps_timer_rate);
You can simplify the driver even more by using
clocksource_mmio_init.
Since my base address depends on cluster number, which CPU is part
of, this interface is not much of a use. On top of that it assumes
that I am little endian by using readl family accessories.
Why can't you use ?
clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick",
nps_timer_rate, 32, nps_clksrc_read);
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Re: [PATCH v3 2/3] clocksource: Add NPS400 timers driver
>From: Daniel Lezcano >Sent: Tuesday, February 9, 2016 3:38 PM >Actually I was referring to clk_prepare_enable, clocksource_register_hz. >Agree clk_get_rate is always valid. Thanks for making this clear. Any way as you can see I do call pr_err() in case of error just like most drivers around. By "hang" do you mean calling panic()? What if there is another clocksource in DT (even with worse rating)? I still prefer using it then having non workable machine. >> >>> You can simplify the driver even more by using >>> clocksource_mmio_init. >> Since my base address depends on cluster number, which CPU is part >> of, this interface is not much of a use. On top of that it assumes >> that I am little endian by using readl family accessories. >Why can't you use ? >clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick", >nps_timer_rate, 32, nps_clksrc_read); I believe that the simplification is meant for drivers that can actually use the clocksource_mmio..() accessories. Could you explain what is the advantage here, for my case, to use clocksource_mmio driver? Thanks for your patience -Noam ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [PATCH v3 2/3] clocksource: Add NPS400 timers driver
On 02/09/2016 10:47 PM, Noam Camus wrote:
From: Daniel Lezcano Sent: Tuesday,
February 9, 2016 3:38 PM
Actually I was referring to clk_prepare_enable,
clocksource_register_hz. Agree clk_get_rate is always valid.
Thanks for making this clear. Any way as you can see I do call
pr_err() in case of error just like most drivers around. By "hang" do
you mean calling panic()?
No. I meant the errors are caught but no action is taken, the execution
continues normally as nothing wrong happened. This is why I asked if you
expect the host to hang at boot time with the last error as a hint.
I was expecting to see a call to clk_disable_unprepare if
clocksource_register_hz fails, and returning 'ret' if clk_prepare_enable
fails.
What if there is another clocksource in DT (even with worse rating)?
I still prefer using it then having non workable machine.
You are right. This is why failing gracefully in the init function is
important.
You can simplify the driver even more by using
clocksource_mmio_init.
Since my base address depends on cluster number, which CPU is
part of, this interface is not much of a use. On top of that it
assumes that I am little endian by using readl family
accessories.
Why can't you use ?
clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick",
nps_timer_rate, 32, nps_clksrc_read);
I believe that the simplification is meant for drivers that can
actually use the clocksource_mmio..() accessories. Could you explain
what is the advantage here, for my case, to use clocksource_mmio
driver?
Using the mmio generic code will save:
+static struct clocksource nps_counter = {
+ .name = "EZnps-tick",
+ .rating = 301,
+ .read = nps_clksrc_read,
+ .mask = CLOCKSOURCE_MASK(32),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
Up to you.
-- Daniel
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Re: [RFC] perf: fix building for ARCv1
On Friday 05 February 2016 09:40 PM, a...@redhat.com wrote: > Em Fri, Feb 05, 2016 at 11:18:52AM +, Noam Camus escreveu: >> Well here for EZchip I also see the: >> undefined reference to `__sync_add_and_fetch_4' >> undefined reference to `__sync_sub_and_fetch_4' > > Yeah, because there is no: tools/arch/arc/include/asm/atomic.h, can't > you guys adapt arch/arc/include/asm/atomic.h to use in userspace? Sure - however we need to support 3 variants: LLSC, !LLSC, EZCHIP If needed, latter 2 could be done using a new atomic assist syscall I presume kernel Kconfig items are no go in this header so this diversity management needs to use toolchain defined macros e.g. __ezchip__ > > - Arnaldo > >> This is since at file tools/include/asm/atomic.h we use the generic >> implementation >> If for ARC I could use just like x86 my own header file then functions like: >> atomic_inc() >> atomic_dec_and_test() >> Are easy to implement and you may see an example for such atomic methods in >> my patch set for the new platform. >> >> You however wants to use some GCC flag -matomic which I assume somehow will >> implement the above __sync*. >> I can't find the implementation but if it uses LLSC then it won't work for >> me since I am not supporting LLSC. > >> So seem that either I have my own header at kernel or that I need to >> change the GCC implementation for __sync* to use my atomic >> instructions. I am personally tend to the x86 solution and not the >> generic one since changing GCC will require to have new compiler >> dependency. ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH] mm,thp: khugepaged: call pte flush at the time of collapse
This showed up on ARC when running LMBench bw_mem tests as
Overlapping TLB Machine Check Exception triggered due to STLB entry
(2M pages) overlapping some NTLB entry (regular 8K page).
bw_mem 2m touches a large chunk of vaddr creating NTLB entries.
In the interim khugepaged kicks in, collapsing the contiguous ptes into
a single pmd. pmdp_collapse_flush()->flush_pmd_tlb_range() is called to
flush out NTLB entries for the ptes. This for ARC (by design) can only
shootdown STLB entries (for pmd). The stray NTLB entries cause the overlap
with the subsequent STLB entry for collapsed page.
So make pmdp_collapse_flush() call pte flush interface not pmd flush.
Note that originally all thp flush call sites in generic code called
flush_tlb_range() leaving it to architecture to implement the flush for
pte and/or pmd. Commit 12ebc1581ad11454 changed this by calling a new
opt-in API flush_pmd_tlb_range() which made the semantics more explicit
but failed to distinguish the pte vs pmd flush in generic code, which is
what this patch fixes.
Note that ARC can fixed w/o touching the generic pmdp_collapse_flush()
by defining a ARC version, but that defeats the purpose of generic
version, plus sementically this is the right thing to do.
Fixes STAR 9000961194: LMBench on AXS103 triggering duplicate TLB
exceptions with super pages
Cc: Kirill A. Shutemov
Cc: Aneesh Kumar K.V
Cc: Andrea Arcangeli
Cc: Andrew Morton
Cc: #4.4
Cc:
Cc: linux-ker...@vger.kernel.org
Cc: linux...@kvack.org
Fixes: 12ebc1581ad11454 ("mm,thp: introduce flush_pmd_tlb_range")
Signed-off-by: Vineet Gupta
---
mm/pgtable-generic.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/mm/pgtable-generic.c b/mm/pgtable-generic.c
index 7d3db0247983..1ba58213ad65 100644
--- a/mm/pgtable-generic.c
+++ b/mm/pgtable-generic.c
@@ -210,7 +210,9 @@ pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
unsigned long address,
VM_BUG_ON(address & ~HPAGE_PMD_MASK);
VM_BUG_ON(pmd_trans_huge(*pmdp));
pmd = pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp);
- flush_pmd_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
+
+ /* collapse entails shooting down ptes not pmd */
+ flush_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
return pmd;
}
#endif
--
2.5.0
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Re: [PATCH] mm, thp: khugepaged: call pte flush at the time of collapse
Vineet Gupta writes:
> This showed up on ARC when running LMBench bw_mem tests as
> Overlapping TLB Machine Check Exception triggered due to STLB entry
> (2M pages) overlapping some NTLB entry (regular 8K page).
>
> bw_mem 2m touches a large chunk of vaddr creating NTLB entries.
> In the interim khugepaged kicks in, collapsing the contiguous ptes into
> a single pmd. pmdp_collapse_flush()->flush_pmd_tlb_range() is called to
> flush out NTLB entries for the ptes. This for ARC (by design) can only
> shootdown STLB entries (for pmd). The stray NTLB entries cause the overlap
> with the subsequent STLB entry for collapsed page.
> So make pmdp_collapse_flush() call pte flush interface not pmd flush.
>
> Note that originally all thp flush call sites in generic code called
> flush_tlb_range() leaving it to architecture to implement the flush for
> pte and/or pmd. Commit 12ebc1581ad11454 changed this by calling a new
> opt-in API flush_pmd_tlb_range() which made the semantics more explicit
> but failed to distinguish the pte vs pmd flush in generic code, which is
> what this patch fixes.
>
> Note that ARC can fixed w/o touching the generic pmdp_collapse_flush()
> by defining a ARC version, but that defeats the purpose of generic
> version, plus sementically this is the right thing to do.
>
> Fixes STAR 9000961194: LMBench on AXS103 triggering duplicate TLB
> exceptions with super pages
>
> Cc: Kirill A. Shutemov
> Cc: Aneesh Kumar K.V
> Cc: Andrea Arcangeli
> Cc: Andrew Morton
> Cc: #4.4
> Cc:
> Cc: linux-ker...@vger.kernel.org
> Cc: linux...@kvack.org
> Fixes: 12ebc1581ad11454 ("mm,thp: introduce flush_pmd_tlb_range")
> Signed-off-by: Vineet Gupta
Reviewed-by: Aneesh Kumar K.V
We do have reverse usage in migration code path, which I have as a patch
here.
https://github.com/kvaneesh/linux/commit/b8a78933fea93cb0b2978868e59a0a4b12eb92eb
> ---
> mm/pgtable-generic.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/mm/pgtable-generic.c b/mm/pgtable-generic.c
> index 7d3db0247983..1ba58213ad65 100644
> --- a/mm/pgtable-generic.c
> +++ b/mm/pgtable-generic.c
> @@ -210,7 +210,9 @@ pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
> unsigned long address,
> VM_BUG_ON(address & ~HPAGE_PMD_MASK);
> VM_BUG_ON(pmd_trans_huge(*pmdp));
> pmd = pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp);
> - flush_pmd_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
> +
> + /* collapse entails shooting down ptes not pmd */
> + flush_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
> return pmd;
> }
> #endif
> --
> 2.5.0
-aneesh
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Re: [PATCH] mm,thp: khugepaged: call pte flush at the time of collapse
On Wednesday 10 February 2016 10:37 AM, Aneesh Kumar K.V wrote:
> Vineet Gupta writes:
>
>> This showed up on ARC when running LMBench bw_mem tests as
>> Overlapping TLB Machine Check Exception triggered due to STLB entry
>> (2M pages) overlapping some NTLB entry (regular 8K page).
>>
>> bw_mem 2m touches a large chunk of vaddr creating NTLB entries.
>> In the interim khugepaged kicks in, collapsing the contiguous ptes into
>> a single pmd. pmdp_collapse_flush()->flush_pmd_tlb_range() is called to
>> flush out NTLB entries for the ptes. This for ARC (by design) can only
>> shootdown STLB entries (for pmd). The stray NTLB entries cause the overlap
>> with the subsequent STLB entry for collapsed page.
>> So make pmdp_collapse_flush() call pte flush interface not pmd flush.
>>
>> Note that originally all thp flush call sites in generic code called
>> flush_tlb_range() leaving it to architecture to implement the flush for
>> pte and/or pmd. Commit 12ebc1581ad11454 changed this by calling a new
>> opt-in API flush_pmd_tlb_range() which made the semantics more explicit
>> but failed to distinguish the pte vs pmd flush in generic code, which is
>> what this patch fixes.
>>
>> Note that ARC can fixed w/o touching the generic pmdp_collapse_flush()
>> by defining a ARC version, but that defeats the purpose of generic
>> version, plus sementically this is the right thing to do.
>>
>> Fixes STAR 9000961194: LMBench on AXS103 triggering duplicate TLB
>> exceptions with super pages
>>
>> Cc: Kirill A. Shutemov
>> Cc: Aneesh Kumar K.V
>> Cc: Andrea Arcangeli
>> Cc: Andrew Morton
>> Cc: #4.4
>> Cc:
>> Cc: linux-ker...@vger.kernel.org
>> Cc: linux...@kvack.org
>> Fixes: 12ebc1581ad11454 ("mm,thp: introduce flush_pmd_tlb_range")
>> Signed-off-by: Vineet Gupta
>
> Reviewed-by: Aneesh Kumar K.V
I hope that there is no other site which needs similar fixup.
> We do have reverse usage in migration code path, which I have as a patch
> here.
>
> https://github.com/kvaneesh/linux/commit/b8a78933fea93cb0b2978868e59a0a4b12eb92eb
Great ! So you must also be defining __HAVE_ARCH_FLUSH_PMD_TLB_RANGE for
powerpc.
What branch is that patch off of ?
>
>> ---
>> mm/pgtable-generic.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/mm/pgtable-generic.c b/mm/pgtable-generic.c
>> index 7d3db0247983..1ba58213ad65 100644
>> --- a/mm/pgtable-generic.c
>> +++ b/mm/pgtable-generic.c
>> @@ -210,7 +210,9 @@ pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
>> unsigned long address,
>> VM_BUG_ON(address & ~HPAGE_PMD_MASK);
>> VM_BUG_ON(pmd_trans_huge(*pmdp));
>> pmd = pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp);
>> -flush_pmd_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
>> +
>> +/* collapse entails shooting down ptes not pmd */
>> +flush_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
>> return pmd;
>> }
>> #endif
>> --
>> 2.5.0
>
> -aneesh
>
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>
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[PATCH] mm, thp: fix spellos in describing __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
Cc: Kirill A. Shutemov Cc: Aneesh Kumar K.V Cc: Andrea Arcangeli Cc: Andrew Morton Cc: Cc: linux-ker...@vger.kernel.org Cc: linux...@kvack.org Signed-off-by: Vineet Gupta --- mm/pgtable-generic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/mm/pgtable-generic.c b/mm/pgtable-generic.c index 1ba58213ad65..75664ed7e3ab 100644 --- a/mm/pgtable-generic.c +++ b/mm/pgtable-generic.c @@ -90,9 +90,9 @@ pte_t ptep_clear_flush(struct vm_area_struct *vma, unsigned long address, * ARCHes with special requirements for evicting THP backing TLB entries can * implement this. Otherwise also, it can help optimize normal TLB flush in * THP regime. stock flush_tlb_range() typically has optimization to nuke the - * entire TLB TLB if flush span is greater than a threshhold, which will + * entire TLB if flush span is greater than a threshhold, which will * likely be true for a single huge page. Thus a single thp flush will - * invalidate the entire TLB which is not desitable. + * invalidate the entire TLB which is not desirable. * e.g. see arch/arc: flush_pmd_tlb_range */ #define flush_pmd_tlb_range(vma, addr, end)flush_tlb_range(vma, addr, end) -- 2.5.0 ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
