ARC stable backport request
Hi,
Please add upstream commit 30b9dbee895ff ("ARC: Fix silly typo in MAINTAINERS
file") to stable releases.
This depends on 9acdc911b55569145 ("MAINTAINERS: Add public mailing list for
ARC")
which was already marked for stable inclusion and is hitting the stable trees
ATM.
Thx,
-Vineet
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[PATCH v3 01/18] Documentation: Add EZchip vendor to binding list
From: Noam Camus Add EZchip to vendor prefixes list. EZchip introduce the NPS platform for the ARC architecture. Signed-off-by: Noam Camus Acked-by: Rob Herring Cc: Pawel Moll --- Documentation/devicetree/bindings/arc/eznps.txt|7 +++ .../devicetree/bindings/vendor-prefixes.txt|1 + 2 files changed, 8 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/arc/eznps.txt diff --git a/Documentation/devicetree/bindings/arc/eznps.txt b/Documentation/devicetree/bindings/arc/eznps.txt new file mode 100644 index 000..f8b5e9b --- /dev/null +++ b/Documentation/devicetree/bindings/arc/eznps.txt @@ -0,0 +1,7 @@ +EZchip NPS Network Proccessor Platforms Device Tree Bindings +--- + +Appliance main board with NPS400 ASIC. + +Required root node properties: +- compatible = "ezchip,arc-nps"; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 55df1d4..d7bff8a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -82,6 +82,7 @@ eukrea Eukréa Electromatique everestEverest Semiconductor Co. Ltd. everspin Everspin Technologies, Inc. excito Excito +ezchip EZchip Semiconductor fcsFairchild Semiconductor fireflyFirefly focaltech FocalTech Systems Co.,Ltd -- 1.7.1 ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH v3 08/18] ARC: Mark secondary cpu online only after all HW setup is done
From: Noam Camus
In SMP setup, master loops for each_present_cpu calling cpu_up().
For ARC it returns as soon as new cpu's status becomes online,
However secondary may still do HW initializing,
machine or platform hook level.
So turn secondary online only after all HW setup is done.
Signed-off-by: Noam Camus
Acked-by: Vineet Gupta
---
arch/arc/kernel/smp.c | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index 0b061a4..bc0e4f6 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -126,11 +126,6 @@ void start_kernel_secondary(void)
current->active_mm = mm;
cpumask_set_cpu(cpu, mm_cpumask(mm));
- notify_cpu_starting(cpu);
- set_cpu_online(cpu, true);
-
- pr_info("## CPU%u LIVE ##: Executing Code...\n", cpu);
-
/* Some SMP H/w setup - for each cpu */
if (plat_smp_ops.init_per_cpu)
plat_smp_ops.init_per_cpu(cpu);
@@ -138,6 +133,11 @@ void start_kernel_secondary(void)
if (machine_desc->init_cpu_smp)
machine_desc->init_cpu_smp(cpu);
+ notify_cpu_starting(cpu);
+ set_cpu_online(cpu, true);
+
+ pr_info("## CPU%u LIVE ##: Executing Code...\n", cpu);
+
arc_local_timer_setup();
local_irq_enable();
--
1.7.1
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[PATCH v3 06/18] ARC: rwlock: disable interrupts in !LLSC variant
From: Noam Camus
If we hold rwlock and interrupt occures we may
end up spinning on it for ever during softirq.
Note that this lock is an internal lock
and since the lock is free to be used from any context,
the lock needs to be IRQ-safe.
Below you may see an example for interrupt we get while
nl_table_lock is holding its rw->lock_mutex and we spinned
on it for ever.
The concept for the fix was taken from SPARC.
[2015-05-12 19:16:12] Stack Trace:
[2015-05-12 19:16:12] arc_unwind_core+0xb8/0x11c
[2015-05-12 19:16:12] dump_stack+0x68/0xac
[2015-05-12 19:16:12] _raw_read_lock+0xa8/0xac
[2015-05-12 19:16:12] netlink_broadcast_filtered+0x56/0x35c
[2015-05-12 19:16:12] nlmsg_notify+0x42/0xa4
[2015-05-12 19:16:13] neigh_update+0x1fe/0x44c
[2015-05-12 19:16:13] neigh_event_ns+0x40/0xa4
[2015-05-12 19:16:13] arp_process+0x46e/0x5a8
[2015-05-12 19:16:13] __netif_receive_skb_core+0x358/0x500
[2015-05-12 19:16:13] process_backlog+0x92/0x154
[2015-05-12 19:16:13] net_rx_action+0xb8/0x188
[2015-05-12 19:16:13] __do_softirq+0xda/0x1d8
[2015-05-12 19:16:14] irq_exit+0x8a/0x8c
[2015-05-12 19:16:14] arch_do_IRQ+0x6c/0xa8
[2015-05-12 19:16:14] handle_interrupt_level1+0xe4/0xf0
Signed-off-by: Noam Camus
Acked-by: Peter Zijlstra
---
arch/arc/include/asm/spinlock.h | 14 ++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arc/include/asm/spinlock.h b/arch/arc/include/asm/spinlock.h
index db8c59d..800e7c4 100644
--- a/arch/arc/include/asm/spinlock.h
+++ b/arch/arc/include/asm/spinlock.h
@@ -610,7 +610,9 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock)
static inline int arch_read_trylock(arch_rwlock_t *rw)
{
int ret = 0;
+ unsigned long flags;
+ local_irq_save(flags);
arch_spin_lock(&(rw->lock_mutex));
/*
@@ -623,6 +625,7 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
}
arch_spin_unlock(&(rw->lock_mutex));
+ local_irq_restore(flags);
smp_mb();
return ret;
@@ -632,7 +635,9 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
static inline int arch_write_trylock(arch_rwlock_t *rw)
{
int ret = 0;
+ unsigned long flags;
+ local_irq_save(flags);
arch_spin_lock(&(rw->lock_mutex));
/*
@@ -646,6 +651,7 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
ret = 1;
}
arch_spin_unlock(&(rw->lock_mutex));
+ local_irq_restore(flags);
return ret;
}
@@ -664,16 +670,24 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
static inline void arch_read_unlock(arch_rwlock_t *rw)
{
+ unsigned long flags;
+
+ local_irq_save(flags);
arch_spin_lock(&(rw->lock_mutex));
rw->counter++;
arch_spin_unlock(&(rw->lock_mutex));
+ local_irq_restore(flags);
}
static inline void arch_write_unlock(arch_rwlock_t *rw)
{
+ unsigned long flags;
+
+ local_irq_save(flags);
arch_spin_lock(&(rw->lock_mutex));
rw->counter = __ARCH_RW_LOCK_UNLOCKED__;
arch_spin_unlock(&(rw->lock_mutex));
+ local_irq_restore(flags);
}
#endif
--
1.7.1
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[PATCH v3 03/18] clocksource: Add NPS400 timers driver
From: Noam Camus
Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.
Signed-off-by: Noam Camus
Cc: Daniel Lezcano
Cc: Rob Herring
Cc: Thomas Gleixner
Cc: John Stultz
Acked-by: Vineet Gupta
---
.../bindings/timer/ezchip,nps400-timer.txt | 11
drivers/clocksource/Kconfig|7 ++
drivers/clocksource/Makefile |1 +
drivers/clocksource/timer-nps.c| 63
4 files changed, 82 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 drivers/clocksource/timer-nps.c
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
new file mode 100644
index 000..c5102c2
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
@@ -0,0 +1,11 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer"
+
+Example:
+
+timer {
+ compatible = "ezchip,nps400-timer";
+};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 71cfdf7..98b12c5 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -131,6 +131,13 @@ config CLKSRC_TI_32K
This option enables support for Texas Instruments 32.768 Hz
clocksource
available on many OMAP-like platforms.
+config CLKSRC_NPS
+ bool "NPS400 clocksource driver" if COMPILE_TEST
+ select CLKSRC_OF if OF
+ help
+ NPS400 clocksource support.
+ Got 64 bit counter with update rate up to 1000MHz.
+
config CLKSRC_STM32
bool "Clocksource for STM32 SoCs" if !ARCH_STM32
depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 56bd16e..20969b0 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
obj-$(CONFIG_CLKSRC_TI_32K)+= timer-ti-32k.o
+obj-$(CONFIG_ARC_PLAT_EZNPS) += timer-nps.o
obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
new file mode 100644
index 000..ef8f287
--- /dev/null
+++ b/drivers/clocksource/timer-nps.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include
+#include
+#include
+#include
+
+#define NPS_MSU_TICK_LOW 0xC8
+#define NPS_CLUSTER_OFFSET 8
+#define NPS_CLUSTER_NUM16
+
+static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
+
+static cycle_t nps_clksrc_read(struct clocksource *clksrc)
+{
+ int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
+
+ return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
+}
+
+static struct clocksource nps_counter = {
+ .name = "EZnps-tick",
+ .rating = 301,
+ .read = nps_clksrc_read,
+ .mask = CLOCKSOURCE_MASK(32),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void __init nps_setup_clocksource(struct device_node *node)
+{
+ struct clocksource *clksrc = &nps_counter;
+ unsigned long rate, dt_root;
+ int ret, cluster;
+
+ for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
+ nps_msu_reg_low_addr[cluster] =
+ nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
+NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
+
+ dt_root = of_get_flat_dt_root();
+ rate = (u32)of_get_flat_dt_prop(dt_root, "clock-frequency", NULL);
+
+ ret = clocksource_register_hz(clksrc, rate);
+ if (ret)
+ pr_err("Couldn't register clock source.\n");
+}
+
+CLOCKSOURCE_OF_DECLARE(nps_400, "ezchip,nps400-timer",
+ nps_setup_clocksource);
--
1.7.1
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[PATCH v3 04/18] irqchip: add nps Internal and external irqchips
From: Noam Camus
Adding EZchip NPS400 support.
NPS internal interrupts are internally handled at
Multi Thread Manager (MTM) that is signaled for deactivating
an interrupt.
External interrupts is handled also at Global Interrupt
Controller (GIC) e.g. serial and network devices.
Signed-off-by: Noam Camus
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
---
.../interrupt-controller/ezchip,nps400-ic.txt | 17 ++
drivers/irqchip/Makefile |1 +
drivers/irqchip/irq-eznps.c| 213
3 files changed, 231 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
create mode 100644 drivers/irqchip/irq-eznps.c
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
new file mode 100644
index 000..888b2b9
--- /dev/null
+++
b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
@@ -0,0 +1,17 @@
+EZchip NPS Interrupt Controller
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-ic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+
+
+Example:
+
+intc: interrupt-controller {
+ compatible = "ezchip,nps400-ic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+};
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 177f78f..b95b954 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_RENESAS_H8S_INTC)+=
irq-renesas-h8s.o
obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o
obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
obj-$(CONFIG_IMX_GPCV2)+= irq-imx-gpcv2.o
+obj-$(CONFIG_ARC_PLAT_EZNPS) += irq-eznps.o
diff --git a/drivers/irqchip/irq-eznps.c b/drivers/irqchip/irq-eznps.c
new file mode 100644
index 000..bb8d547
--- /dev/null
+++ b/drivers/irqchip/irq-eznps.c
@@ -0,0 +1,213 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define NPS_MSU_EN_CFG 0x80/* MSU Enable Configuration Register */
+#define MSU_EN BIT(0) /* MSU block enable */
+#define IPI_EN BIT(16) /* Enable service of incoming IPI Messages */
+#define GIM0_ENBIT(17) /* Enable service of incoming GIM 0
messages */
+#define GIM1_ENBIT(18) /* Enable service of incoming GIM 1
messages */
+
+#define NPS_GIM_P_POL 0x110 /* Peripheral interrupts source polarity */
+#define NPS_GIM_P_SENS 0x114 /* Peripheral interrupts sensitivity */
+#define GIM_UART BIT(7)
+#define GIM_LAN_TX (BIT(10) | BIT(25))
+#define GIM_LAN_RX (BIT(11) | BIT(26))
+#define GIM_PERIPH_ALL (GIM_UART | GIM_LAN_TX | GIM_LAN_RX)
+
+#define NPS_GIM_P_DST100x13A /* Peripheral Interrupt Destination
(LAN RX) */
+#define NPS_GIM_P_DST110x13B /* Peripheral Interrupt Destination
(LAN TX) */
+#define NPS_GIM_P_DST250x149 /* Peripheral Interrupt Destination
(LAN RX) */
+#define NPS_GIM_P_DST260x14A /* Peripheral Interrupt Destination
(LAN TX) */
+#define DST_IS BIT(26) /* Interrupt select for line 7 */
+
+#define NPS_GIM_P_EN 0x100 /* Peripheral interrupts source enable */
+#define NPS_GIM_P_BLK 0x118 /* Peripheral interrupts blocking for sources */
+
+/* Messaging and Scheduling Unit:
+ * Provides message management for a CPU cluster.
+ */
+static void __init eznps_configure_msu(void)
+{
+ int cpu;
+ u32 value = MSU_EN | IPI_EN | GIM0_EN | GIM1_EN;
+
+ /* Enable IPI and GIM messages on all clusters */
+ for (cpu = 0 ; cpu < eznps_max_cpus; cpu += eznps_cpus_per_cluster)
+ iowrite32be(value,
+ nps_host_reg(cpu, NPS_MSU_BLKID, NPS_MSU_EN_CFG));
+}
+
+/* Global Interrupt Manager:
+ * Configures and manages up to 64 interrupts from peripherals,
+ * 16 interrupts from CPUs (virtual interrupts) and ECC interrupts.
+ * Receives the interrupts and transmits them to relevant CPU.
+ */
+static void __init eznps_configure_gim(void)
+{
+ u32 reg_addr, reg_val;
+
+ /* IRQ
[PATCH v3 02/18] ARC: [plat-eznps] define IPI_IRQ
From: Noam Camus We add IPI irq definition to be used later by any irqchip such NPS400 IC. Signed-off-by: Noam Camus --- arch/arc/include/asm/irq.h |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/arc/include/asm/irq.h b/arch/arc/include/asm/irq.h index 4fd7d62..c5f8f0f 100644 --- a/arch/arc/include/asm/irq.h +++ b/arch/arc/include/asm/irq.h @@ -16,7 +16,11 @@ #ifdef CONFIG_ISA_ARCOMPACT #define TIMER0_IRQ 3 #define TIMER1_IRQ 4 +#if defined(CONFIG_SMP) && defined(CONFIG_ARC_PLAT_EZNPS) +#define IPI_IRQ 5 +#else #define IPI_IRQ(NR_CPU_IRQS-1) /* dummy to enable SMP build for up hardware */ +#endif #else #define TIMER0_IRQ 16 #define TIMER1_IRQ 17 -- 1.7.1 ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH v3 05/18] ARC: Set vmalloc size from configuration
From: Noam Camus User space use lower 2G of the virtual address space. However kernel steals upper 512M of this space. This stolen space is used partially for vmalloc and the rest serves as gutter between kernel and user space. The vmalloc size is depend on NR_CPUS since "per cpu" mechanism use vmalloc to allocate chunks for its use. Historically vmalloc size was 256M however it is not enough in case of many CPUs e.g. 4K CPUs. For such case an extra 192M is allocated. We are setting default vmalloc size to be 256M, any addtional space will be taken from kernel/user gutter. This introduce build error since PGDIR_SIZE() cannot use "1UL" ibecause it is called from mm/tlbex.S by VMALLOC_START. Using _BITUL() solves this build error. Signed-off-by: Noam Camus Acked-by: Vineet Gupta --- arch/arc/Kconfig |8 arch/arc/include/asm/pgtable.h |2 +- arch/arc/include/asm/processor.h | 10 +- arch/arc/mm/tlb.c|6 ++ 4 files changed, 20 insertions(+), 6 deletions(-) diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 2c2ac3f..689ccb3 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -468,6 +468,14 @@ config ARCH_PHYS_ADDR_T_64BIT config ARCH_DMA_ADDR_T_64BIT bool +config ARC_VMALLOC_SIZE + hex "Vmalloc size (MB)" + range 0 512 + default "256" + help + By default equals to 256MB and the rest of 512MB is + left for gutter between kernel and user space. + config ARC_CURR_IN_REG bool "Dedicate Register r25 for current_task pointer" default y diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h index 57af2f0..372a282 100644 --- a/arch/arc/include/asm/pgtable.h +++ b/arch/arc/include/asm/pgtable.h @@ -210,7 +210,7 @@ #define BITS_FOR_PGD (32 - BITS_FOR_PTE - BITS_IN_PAGE) #define PGDIR_SHIFT(32 - BITS_FOR_PGD) -#define PGDIR_SIZE (1UL << PGDIR_SHIFT)/* vaddr span, not PDG sz */ +#define PGDIR_SIZE _BITUL(PGDIR_SHIFT) /* vaddr span, not PDG sz */ #define PGDIR_MASK (~(PGDIR_SIZE-1)) #definePTRS_PER_PTE_BITUL(BITS_FOR_PTE) diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h index 1d694c1..8a77ccd 100644 --- a/arch/arc/include/asm/processor.h +++ b/arch/arc/include/asm/processor.h @@ -109,18 +109,18 @@ extern unsigned int get_wchan(struct task_struct *p); * 0xC000_ 0x_ (peripheral uncached space) * - */ -#define VMALLOC_START 0x7000 /* * 1 PGDIR_SIZE each for fixmap/pkmap, 2 PGDIR_SIZE gutter * See asm/highmem.h for details */ -#define VMALLOC_SIZE (PAGE_OFFSET - VMALLOC_START - PGDIR_SIZE * 4) -#define VMALLOC_END(VMALLOC_START + VMALLOC_SIZE) +#define VMALLOC_END(PAGE_OFFSET - PGDIR_SIZE * 4) +#define VMALLOC_SIZE (CONFIG_ARC_VMALLOC_SIZE << 20) +#define VMALLOC_START (VMALLOC_END - VMALLOC_SIZE) -#define USER_KERNEL_GUTTER0x1000 +#define TASK_SIZE 0x6000 -#define TASK_SIZE (VMALLOC_START - USER_KERNEL_GUTTER) +#define USER_KERNEL_GUTTER(VMALLOC_START - TASK_SIZE) #define STACK_TOP TASK_SIZE #define STACK_TOP_MAX STACK_TOP diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c index daf2bf5..843e1a5 100644 --- a/arch/arc/mm/tlb.c +++ b/arch/arc/mm/tlb.c @@ -814,6 +814,12 @@ void arc_mmu_init(void) printk(arc_mmu_mumbojumbo(0, str, sizeof(str))); + /* +* vmalloc size (in MB) sanity check, +* Can't be done in processor.h due to header include depenedencies +*/ + BUILD_BUG_ON(!IS_ALIGNED((CONFIG_ARC_VMALLOC_SIZE << 20), PMD_SIZE)); + /* For efficiency sake, kernel is compile time built for a MMU ver * This must match the hardware it is running on. * Linux built for MMU V2, if run on MMU V1 will break down because V1 -- 1.7.1 ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH v3 00/18] *** SUBJECT HERE ***
From: Noam Camus v3: 1) irqchip: use MACROS instead of structures to decribe registers. 2) clocksource: use 32bit counter and avoid 2 halfs read of 64bit dance. v2: 1) Remove out of tree platform include path 2) Move atomic/bitop/cmpxchg for platform to end. Remove macro duplication. Fix some bad implementation. 3) define cpu_relax_lowlatency() for platform. 4) rename init_irq_cpu() to init_per_cpu() reorder call to init_per_cpu() for secondary use it instead of init_cpu_smp(). 5) set res_service to call stext 6) fix build failure for CTOP_AUX_BASE at assembly code 7) Use ilog2 for mtm_init_nat() 8) Add CLKSRC_NPS option to Kconfig change nps_clksrc_read() to be more readable. General summay: This set introduce new platform to ARC architecture. Platform name called "eznps" for working with EZchip NPS400 Network Proccessor. NPS400 is targeted to service "fast path" network applications. NPS400 got mesh of 256 extended ARC cores (AKA CTOP), each core got 16 HW threads. This is basically SMT core where at any point of time only one HW thread is active. Each core have HW scheduler that round robin between eligible HW threads. Totaly, kernel sees 4096 CPUs which I belive is a high record. There is no cache coherency between cores so generic user applications and kernel do not use D$. Cores got special memory mappings for huge pages (8MB). Mapping is static and should provide application enough memory without any "TLB miss". This mapping is on top of TLB mapping. This is a basic set that will later be followed with additional set of patches with all advanced features. Many thanks to all people helping to make this happen. Regards, Noam Camus Noam Camus (17): Documentation: Add EZchip vendor to binding list ARC: [plat-eznps] define IPI_IRQ clocksource: Add NPS400 timers driver irqchip: add nps Internal and external irqchips ARC: Set vmalloc size from configuration ARC: rwlock: disable interrupts in !LLSC variant ARC: rename smp operation init_irq_cpu() to init_per_cpu() ARC: Mark secondary cpu online only after all HW setup is done ARC: add CONFIG_CLKSRC_OF support to time_init() ARC: [plat-eznps] Add eznps board defconfig and dts ARC: [plat-eznps] Add eznps platform ARC: [plat-eznps] Use dedicated user stack top ARC: [plat-eznps] Use dedicated atomic/bitops/cmpxchg ARC: [plat-eznps] Use dedicated SMP barriers ARC: [plat-eznps] Use dedicated identity auxiliary register. ARC: [plat-eznps] Use dedicated COMMAND_LINE_SIZE ARC: Add eznps platform to Kconfig and Makefile Tal Zilcer (1): ARC: [plat-eznps] Use dedicated cpu_relax() Documentation/devicetree/bindings/arc/eznps.txt|7 + .../interrupt-controller/ezchip,nps400-ic.txt | 17 ++ .../bindings/timer/ezchip,nps400-timer.txt | 11 + .../devicetree/bindings/vendor-prefixes.txt|1 + MAINTAINERS|6 + arch/arc/Kconfig |9 + arch/arc/Makefile |5 + arch/arc/boot/dts/eznps.dts| 76 ++ arch/arc/configs/nps_defconfig | 85 +++ arch/arc/include/asm/atomic.h | 79 ++- arch/arc/include/asm/barrier.h |8 + arch/arc/include/asm/bitops.h | 54 + arch/arc/include/asm/cmpxchg.h | 87 ++-- arch/arc/include/asm/entry-compact.h |8 + arch/arc/include/asm/irq.h |4 + arch/arc/include/asm/pgtable.h |2 +- arch/arc/include/asm/processor.h | 36 +++- arch/arc/include/asm/setup.h |4 + arch/arc/include/asm/smp.h |4 +- arch/arc/include/asm/spinlock.h| 14 + arch/arc/kernel/ctx_sw.c | 13 + arch/arc/kernel/irq.c |4 +- arch/arc/kernel/mcip.c |2 +- arch/arc/kernel/smp.c | 14 +- arch/arc/kernel/time.c |4 + arch/arc/mm/tlb.c | 12 + arch/arc/plat-eznps/Kconfig| 34 +++ arch/arc/plat-eznps/Makefile |7 + arch/arc/plat-eznps/entry.S| 75 ++ arch/arc/plat-eznps/include/plat/ctop.h| 250 arch/arc/plat-eznps/include/plat/mtm.h | 60 + arch/arc/plat-eznps/include/plat/smp.h | 26 ++ arch/arc/plat-eznps/mtm.c | 133 +++ arch/arc/plat-eznps/platform.c | 27 ++ arch/arc/plat-eznps/smp.c | 149 drivers/clocksource/Kconfig|
[PATCH v3 07/18] ARC: rename smp operation init_irq_cpu() to init_per_cpu()
From: Noam Camus
This will better reflect its description i.e. "any needed setup..."
and not just do an "IPI request".
Signed-off-by: Noam Camus
Acked-by: Vineet Gupta
---
arch/arc/include/asm/smp.h |4 ++--
arch/arc/kernel/irq.c |4 ++--
arch/arc/kernel/mcip.c |2 +-
arch/arc/kernel/smp.c |4 ++--
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arc/include/asm/smp.h b/arch/arc/include/asm/smp.h
index 133c867..9913804 100644
--- a/arch/arc/include/asm/smp.h
+++ b/arch/arc/include/asm/smp.h
@@ -48,7 +48,7 @@ extern int smp_ipi_irq_setup(int cpu, int irq);
* @init_early_smp:A SMP specific h/w block can init itself
* Could be common across platforms so not covered by
* mach_desc->init_early()
- * @init_irq_cpu: Called for each core so SMP h/w block driver can do
+ * @init_per_cpu: Called for each core so SMP h/w block driver can do
* any needed setup per cpu (e.g. IPI request)
* @cpu_kick: For Master to kickstart a cpu (optionally at a PC)
* @ipi_send: To send IPI to a @cpu
@@ -57,7 +57,7 @@ extern int smp_ipi_irq_setup(int cpu, int irq);
struct plat_smp_ops {
const char *info;
void(*init_early_smp)(void);
- void(*init_irq_cpu)(int cpu);
+ void(*init_per_cpu)(int cpu);
void(*cpu_kick)(int cpu, unsigned long pc);
void(*ipi_send)(int cpu);
void(*ipi_clear)(int irq);
diff --git a/arch/arc/kernel/irq.c b/arch/arc/kernel/irq.c
index 2ee2265..a650650 100644
--- a/arch/arc/kernel/irq.c
+++ b/arch/arc/kernel/irq.c
@@ -29,8 +29,8 @@ void __init init_IRQ(void)
#ifdef CONFIG_SMP
/* a SMP H/w block could do IPI IRQ request here */
- if (plat_smp_ops.init_irq_cpu)
- plat_smp_ops.init_irq_cpu(smp_processor_id());
+ if (plat_smp_ops.init_per_cpu)
+ plat_smp_ops.init_per_cpu(smp_processor_id());
if (machine_desc->init_cpu_smp)
machine_desc->init_cpu_smp(smp_processor_id());
diff --git a/arch/arc/kernel/mcip.c b/arch/arc/kernel/mcip.c
index 74a9b07..bd237ac 100644
--- a/arch/arc/kernel/mcip.c
+++ b/arch/arc/kernel/mcip.c
@@ -132,7 +132,7 @@ static void mcip_probe_n_setup(void)
struct plat_smp_ops plat_smp_ops = {
.info = smp_cpuinfo_buf,
.init_early_smp = mcip_probe_n_setup,
- .init_irq_cpu = mcip_setup_per_cpu,
+ .init_per_cpu = mcip_setup_per_cpu,
.ipi_send = mcip_ipi_send,
.ipi_clear = mcip_ipi_clear,
};
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index 5805878..0b061a4 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -132,8 +132,8 @@ void start_kernel_secondary(void)
pr_info("## CPU%u LIVE ##: Executing Code...\n", cpu);
/* Some SMP H/w setup - for each cpu */
- if (plat_smp_ops.init_irq_cpu)
- plat_smp_ops.init_irq_cpu(cpu);
+ if (plat_smp_ops.init_per_cpu)
+ plat_smp_ops.init_per_cpu(cpu);
if (machine_desc->init_cpu_smp)
machine_desc->init_cpu_smp(cpu);
--
1.7.1
___
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linux-snps-arc@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH v3 09/18] ARC: add CONFIG_CLKSRC_OF support to time_init()
From: Noam Camus External clock source can be used if included by one of DTS file of a chosen platform. Signed-off-by: Noam Camus Acked-by: Vineet Gupta --- arch/arc/kernel/time.c |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c index dfad287..ea0c47d 100644 --- a/arch/arc/kernel/time.c +++ b/arch/arc/kernel/time.c @@ -283,6 +283,10 @@ void __init time_init(void) */ clocksource_register_hz(&arc_counter, arc_get_core_freq()); +#ifdef CONFIG_CLKSRC_OF + clocksource_probe(); +#endif + /* sets up the periodic event timer */ arc_local_timer_setup(); } -- 1.7.1 ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH v3 10/18] ARC: [plat-eznps] Add eznps board defconfig and dts
From: Noam Camus
Adding default configuration file and DTS file
Signed-off-by: Noam Camus
---
arch/arc/boot/dts/eznps.dts| 76 +++
arch/arc/configs/nps_defconfig | 85
2 files changed, 161 insertions(+), 0 deletions(-)
create mode 100644 arch/arc/boot/dts/eznps.dts
create mode 100644 arch/arc/configs/nps_defconfig
diff --git a/arch/arc/boot/dts/eznps.dts b/arch/arc/boot/dts/eznps.dts
new file mode 100644
index 000..4d4832a
--- /dev/null
+++ b/arch/arc/boot/dts/eznps.dts
@@ -0,0 +1,76 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "ezchip,arc-nps";
+ clock-frequency = <8333>; /* 83.33 MHZ */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ present-cpus = "0-1,16-17";
+ possible-cpus = "0-4095";
+
+ chosen {
+ bootargs = "earlycon=uart8250,mmio32be,0xf7209000,115200n8
console=ttyS0,115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x 0x2000>; /* 512M */
+ };
+
+ fpga {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* child and parent address space 1:1 mapped */
+ ranges;
+
+ intc: interrupt-controller {
+ compatible = "ezchip,nps400-ic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ timer {
+ compatible = "ezchip,nps400-timer";
+ };
+
+ uart@f7209000 {
+ compatible = "snps,dw-apb-uart";
+ device_type = "serial";
+ reg = <0xf7209000 0x100>;
+ interrupts = <6>;
+ clock-frequency = <8333>;
+ baud = <115200>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ native-endian;
+ };
+
+ ethernet@f747 {
+ compatible = "ezchip,nps-mgt-enet";
+ reg = <0xf747 0x1940>;
+ interrupts = <7>;
+ mac-address = [ 00 C0 00 F0 04 03 ];
+ };
+ };
+};
diff --git a/arch/arc/configs/nps_defconfig b/arch/arc/configs/nps_defconfig
new file mode 100644
index 000..13a67ac
--- /dev/null
+++ b/arch/arc/configs/nps_defconfig
@@ -0,0 +1,85 @@
+CONFIG_CROSS_COMPILE="arceb-linux-"
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_EPOLL is not set
+# CONFIG_SIGNALFD is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_EVENTFD is not set
+# CONFIG_AIO is not set
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARC_PLAT_EZNPS=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=4096
+CONFIG_ARC_CACHE_LINE_SHIFT=5
+# CONFIG_ARC_CACHE_PAGES is not set
+# CONFIG_ARC_HAS_LLSC is not set
+CONFIG_ARC_VMALLOC_SIZE=192
+CONFIG_ARC_EMUL_UNALIGNED=y
+CONFIG_ARC_UBOOT_SUPPORT=y
+CONFIG_PREEMPT=y
+CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=1
+CONFIG_BLK_DEV_RAM_SIZE=2048
+CONFIG_NETDEVICES=y
+CONFIG_NETCONSOLE=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# C
[PATCH v3 13/18] ARC: [plat-eznps] Use dedicated atomic/bitops/cmpxchg
From: Noam Camus
We need our own implementaions since we lack LLSC support.
Our extended ISA provided with optimized solution for all 32bit
operations we see in these three headers.
Signed-off-by: Noam Camus
---
arch/arc/include/asm/atomic.h | 79 +++-
arch/arc/include/asm/bitops.h | 54 +
arch/arc/include/asm/cmpxchg.h | 87 +---
3 files changed, 202 insertions(+), 18 deletions(-)
diff --git a/arch/arc/include/asm/atomic.h b/arch/arc/include/asm/atomic.h
index 7730d30..a626996 100644
--- a/arch/arc/include/asm/atomic.h
+++ b/arch/arc/include/asm/atomic.h
@@ -17,6 +17,7 @@
#include
#include
+#ifndef CONFIG_ARC_PLAT_EZNPS
#define atomic_read(v) READ_ONCE((v)->counter)
#ifdef CONFIG_ARC_HAS_LLSC
@@ -180,12 +181,84 @@ ATOMIC_OP(andnot, &= ~, bic)
ATOMIC_OP(or, |=, or)
ATOMIC_OP(xor, ^=, xor)
-#undef ATOMIC_OPS
-#undef ATOMIC_OP_RETURN
-#undef ATOMIC_OP
#undef SCOND_FAIL_RETRY_VAR_DEF
#undef SCOND_FAIL_RETRY_ASM
#undef SCOND_FAIL_RETRY_VARS
+#else /* CONFIG_ARC_PLAT_EZNPS */
+static inline int atomic_read(const atomic_t *v)
+{
+ int temp;
+
+ __asm__ __volatile__(
+ " ld.di %0, [%1]"
+ : "=r"(temp)
+ : "r"(&v->counter)
+ : "memory");
+ return temp;
+}
+
+static inline void atomic_set(atomic_t *v, int i)
+{
+ __asm__ __volatile__(
+ " st.di %0,[%1]"
+ :
+ : "r"(i), "r"(&v->counter)
+ : "memory");
+}
+
+#define ATOMIC_OP(op, c_op, asm_op)\
+static inline void atomic_##op(int i, atomic_t *v) \
+{ \
+ __asm__ __volatile__( \
+ " mov r2, %0\n" \
+ " mov r3, %1\n" \
+ " .word %2\n" \
+ : \
+ : "r"(i), "r"(&v->counter), "i"(asm_op) \
+ : "r2", "r3", "memory");\
+} \
+
+#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
+static inline int atomic_##op##_return(int i, atomic_t *v) \
+{ \
+ unsigned int temp = i; \
+ \
+ /* Explicit full memory barrier needed before/after */ \
+ smp_mb(); \
+ \
+ __asm__ __volatile__( \
+ " mov r2, %0\n" \
+ " mov r3, %1\n" \
+ " .word %2\n" \
+ " mov %0, r2" \
+ : "+r"(temp)\
+ : "r"(&v->counter), "i"(asm_op) \
+ : "r2", "r3", "memory");\
+ \
+ smp_mb(); \
+ \
+ temp c_op i;\
+ \
+ return temp;\
+}
+
+#define ATOMIC_OPS(op, c_op, asm_op) \
+ ATOMIC_OP(op, c_op, asm_op) \
+ ATOMIC_OP_RETURN(op, c_op, asm_op)
+
+ATOMIC_OPS(add, +=, CTOP_INST_AADD_DI_R2_R2_R3)
+#define atomic_sub(i, v) atomic_add(-(i), (v))
+#define atomic_sub_return(i, v) atomic_add_return(-(i), (v))
+
+ATOMIC_OP(and, &=, CTOP_INST_AAND_DI_R2_R2_R3)
+#define atomic_andnot(mask, v) atomic_and(~(mask), (v))
+ATOMIC_OP(or, |=, CTOP_INST_AOR_DI_R2_R2_R3)
+ATOMIC_OP(xor, ^=, CTOP_INST_AXOR_DI_R2_R2_R3)
+#endif /* CONFIG_ARC_PLAT_EZNPS */
+
+#undef ATOMIC_OPS
+#undef ATOMIC_OP_RETURN
+#undef ATOMIC_OP
/**
* __atomic_add_unless - add unless the number is a given value
diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h
index 57c1f33..5a29185 100644
--- a/arch/arc/include/asm/bitops.h
+++ b/arch/arc/include/asm/bitops.h
@@ -22,6 +22,7 @@
#include
#endif
+#ifndef CONFIG_ARC_PLAT_EZNPS
#if defined(CONFIG_ARC_HAS_LLSC)
/*
@@ -155,6 +15
[PATCH v3 12/18] ARC: [plat-eznps] Use dedicated user stack top
From: Noam Camus NPS use special mapping right below TASK_SIZE. Hence we need to lower STACK_TOP so that user stack won't overlap NPS special mapping. Signed-off-by: Noam Camus Acked-by: Vineet Gupta --- arch/arc/include/asm/processor.h | 17 + arch/arc/mm/tlb.c|6 ++ 2 files changed, 23 insertions(+), 0 deletions(-) diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h index 8a77ccd..41142ab 100644 --- a/arch/arc/include/asm/processor.h +++ b/arch/arc/include/asm/processor.h @@ -122,7 +122,24 @@ extern unsigned int get_wchan(struct task_struct *p); #define USER_KERNEL_GUTTER(VMALLOC_START - TASK_SIZE) +#ifdef CONFIG_ARC_PLAT_EZNPS +/* NPS architecture defines special window of 129M in user address space for + * special memory areas, when accessing this window the MMU do not use TLB. + * Instead MMU direct the access to: + * 0x57f0:0x57ff -- 1M of closely coupled memory (aka CMEM) + * 0x5800:0x5fff -- 16 huge pages, 8M each, with fixed map (aka FMTs) + * + * CMEM - is the fastest memory we got and its size is 16K. + * FMT - is used to map either to internal/external memory. + * Internal memory is the second fast memory and its size is 16M + * External memory is the biggest memory (16G) and also the slowest. + * + * STACK_TOP need to be PMD align (21bit) that is why we supply 0x57e0. + */ +#define STACK_TOP 0x57e0 +#else /* CONFIG_ARC_PLAT_EZNPS */ #define STACK_TOP TASK_SIZE +#endif /* CONFIG_ARC_PLAT_EZNPS */ #define STACK_TOP_MAX STACK_TOP /* This decides where the kernel will search for a free chunk of vm diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c index 843e1a5..01f85e5 100644 --- a/arch/arc/mm/tlb.c +++ b/arch/arc/mm/tlb.c @@ -820,6 +820,12 @@ void arc_mmu_init(void) */ BUILD_BUG_ON(!IS_ALIGNED((CONFIG_ARC_VMALLOC_SIZE << 20), PMD_SIZE)); + /* +* stack top size sanity check, +* Can't be done in processor.h due to header include depenedencies +*/ + BUILD_BUG_ON(!IS_ALIGNED(STACK_TOP, PMD_SIZE)); + /* For efficiency sake, kernel is compile time built for a MMU ver * This must match the hardware it is running on. * Linux built for MMU V2, if run on MMU V1 will break down because V1 -- 1.7.1 ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH v3 14/18] ARC: [plat-eznps] Use dedicated SMP barriers
From: Noam Camus
NPS device got 256 cores and each got 16 HW threads (SMT).
We use EZchip dedicated ISA to trigger HW scheduler of the
core that current HW thread belongs to.
This scheduling makes sure that data beyond barrier is available
to all HW threads in core and by that to all in device (4K).
Signed-off-by: Noam Camus
Cc: Peter Zijlstra
---
arch/arc/include/asm/barrier.h |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arc/include/asm/barrier.h b/arch/arc/include/asm/barrier.h
index a720998..a559732 100644
--- a/arch/arc/include/asm/barrier.h
+++ b/arch/arc/include/asm/barrier.h
@@ -34,6 +34,7 @@
#ifdef CONFIG_ISA_ARCOMPACT
+#ifndef CONFIG_ARC_PLAT_EZNPS
/*
* ARCompact based cores (ARC700) only have SYNC instruction which is super
* heavy weight as it flushes the pipeline as well.
@@ -41,6 +42,13 @@
*/
#define mb() asm volatile("sync\n" : : : "memory")
+#else /* CONFIG_ARC_PLAT_EZNPS */
+
+#include
+#define mb() asm volatile (".word %0" : : "i"(CTOP_INST_SCHD_RW) : "memory")
+#define rmb() asm volatile (".word %0" : : "i"(CTOP_INST_SCHD_RD) : "memory")
+#endif /* CONFIG_ARC_PLAT_EZNPS */
+
#endif
#include
--
1.7.1
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[PATCH v3 11/18] ARC: [plat-eznps] Add eznps platform
From: Noam Camus This platform include boards: Hardware Emulator (HE) Simulator based upon nSIM. Signed-off-by: Noam Camus --- MAINTAINERS |6 + arch/arc/plat-eznps/Kconfig | 34 arch/arc/plat-eznps/Makefile|7 + arch/arc/plat-eznps/entry.S | 75 + arch/arc/plat-eznps/include/plat/ctop.h | 250 +++ arch/arc/plat-eznps/include/plat/mtm.h | 60 arch/arc/plat-eznps/include/plat/smp.h | 26 arch/arc/plat-eznps/mtm.c | 133 arch/arc/plat-eznps/platform.c | 27 arch/arc/plat-eznps/smp.c | 149 ++ 10 files changed, 767 insertions(+), 0 deletions(-) create mode 100644 arch/arc/plat-eznps/Kconfig create mode 100644 arch/arc/plat-eznps/Makefile create mode 100644 arch/arc/plat-eznps/entry.S create mode 100644 arch/arc/plat-eznps/include/plat/ctop.h create mode 100644 arch/arc/plat-eznps/include/plat/mtm.h create mode 100644 arch/arc/plat-eznps/include/plat/smp.h create mode 100644 arch/arc/plat-eznps/mtm.c create mode 100644 arch/arc/plat-eznps/platform.c create mode 100644 arch/arc/plat-eznps/smp.c diff --git a/MAINTAINERS b/MAINTAINERS index e9caa4b..abb1897 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4257,6 +4257,12 @@ S: Maintained F: drivers/video/fbdev/exynos/exynos_mipi* F: include/video/exynos_mipi* +EZchip NPS platform support +M: Noam Camus +S: Supported +F: arch/arc/plat-eznps +F: arch/arc/boot/dts/eznps.dts + F71805F HARDWARE MONITORING DRIVER M: Jean Delvare L: lm-sens...@lm-sensors.org diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig new file mode 100644 index 000..051fdca --- /dev/null +++ b/arch/arc/plat-eznps/Kconfig @@ -0,0 +1,34 @@ +# +# For a description of the syntax of this configuration file, +# see Documentation/kbuild/kconfig-language.txt. +# + +menuconfig ARC_PLAT_EZNPS + bool "\"EZchip\" ARC dev platform" + select ARC_HAS_COH_CACHES if SMP + select CPU_BIG_ENDIAN + select CLKSRC_NPS + select EZCHIP_NPS_MANAGEMENT_ENET if ETHERNET + help + Support for EZchip development platforms, + based on ARC700 cores. + We handle few flavours: + - Hardware Emulator AKA HE which is FPGA based chasis + - Simulator based on MetaWare nSIM + - NPS400 chip based on ASIC + +config EZNPS_MTM_EXT + bool "ARC-EZchip MTM Extensions" + select CPUMASK_OFFSTACK + depends on ARC_PLAT_EZNPS && SMP + default y + help + Here we add new hierarchy for CPUs topology. + We got: + Core + Thread + At the new thread level each CPU represent one HW thread. + At highest hierarchy each core contain 16 threads, + any of them seem like CPU from Linux point of view. + All threads within same core share the execution unit of the + core and HW scheduler round robin between them. diff --git a/arch/arc/plat-eznps/Makefile b/arch/arc/plat-eznps/Makefile new file mode 100644 index 000..21091b1 --- /dev/null +++ b/arch/arc/plat-eznps/Makefile @@ -0,0 +1,7 @@ +# +# Makefile for the linux kernel. +# + +obj-y := entry.o platform.o +obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_EZNPS_MTM_EXT) += mtm.o diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S new file mode 100644 index 000..b4dee38 --- /dev/null +++ b/arch/arc/plat-eznps/entry.S @@ -0,0 +1,75 @@ +/*** + + EZNPS CPU startup Code + Copyright(c) 2012 EZchip Technologies. + + This program is free software; you can redistribute it and/or modify it + under the terms and conditions of the GNU General Public License, + version 2, as published by the Free Software Foundation. + + This program is distributed in the hope it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + The full GNU General Public License is included in this distribution in + the file called "COPYING". + +***/ +#include +#include +#include +#include + + .cpu A7 + + .section .init.text, "ax",@progbits + .align 1024 ; HW requierment for restart first PC + +ENTRY(res_service) +#ifdef CONFIG_EZNPS_MTM_EXT + ; For HW thread != 0 there is no work. + lr r3, [CTOP_AUX_THREAD_ID] + cmp r3, 0 + jne stext +#endif + +#ifdef CONFIG_ARC_HAS_DCACHE + ; With no cache coherency mechanism D$ need to be used very carefully. + ; Address space: + ; 0G-2G: We disable CONFIG_ARC_CACHE_PAGES. + ; 2G-3G: We disable D$ by se
[PATCH v3 16/18] ARC: [plat-eznps] Use dedicated cpu_relax()
From: Tal Zilcer
Since the CTOP is SMT hardware multi-threaded, we need to hint
the HW that now will be a very good time to do a hardware
thread context switching. This is done by issuing the schd.rw
instruction (binary coded here so as to not require specific
revision of GCC to build the kernel).
sched.rw means that Thread becomes eligible for execution by
the threads scheduler after all pending read/write
transactions were completed.
Implementing cpu_relax_lowlatency() with barrier()
Since with current semantics of cpu_relax() it may take a
while till yielded CPU will get back.
Signed-off-by: Noam Camus
Cc: Peter Zijlstra
Acked-by: Vineet Gupta
---
arch/arc/include/asm/processor.h |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h
index 41142ab..974b878 100644
--- a/arch/arc/include/asm/processor.h
+++ b/arch/arc/include/asm/processor.h
@@ -57,9 +57,18 @@ struct task_struct;
* A lot of busy-wait loops in SMP are based off of non-volatile data otherwise
* get optimised away by gcc
*/
+#ifndef CONFIG_EZNPS_MTM_EXT
#define cpu_relax()__asm__ __volatile__ ("" : : : "memory")
+#else
+#define cpu_relax() \
+ __asm__ __volatile__ (".word %0" : : "i"(CTOP_INST_SCHD_RW) : "memory")
+#endif
+#ifndef CONFIG_EZNPS_MTM_EXT
#define cpu_relax_lowlatency() cpu_relax()
+#else
+#define cpu_relax_lowlatency() barrier()
+#endif
#define copy_segments(tsk, mm) do { } while (0)
#define release_segments(mm)do { } while (0)
--
1.7.1
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[PATCH v3 15/18] ARC: [plat-eznps] Use dedicated identity auxiliary register.
From: Noam Camus With generic "identity" num of CPUs is limited to 256 (8 bit). We use our alternative AUX register GLOBAL_ID (12 bit). Now we can support up to 4096 CPUs. Signed-off-by: Noam Camus --- arch/arc/include/asm/entry-compact.h |8 arch/arc/kernel/ctx_sw.c | 13 + 2 files changed, 21 insertions(+), 0 deletions(-) diff --git a/arch/arc/include/asm/entry-compact.h b/arch/arc/include/asm/entry-compact.h index 1aff3be..bf9a6a1 100644 --- a/arch/arc/include/asm/entry-compact.h +++ b/arch/arc/include/asm/entry-compact.h @@ -35,6 +35,7 @@ #include #include #include/* For THREAD_SIZE */ +#include /*-- * Switch to Kernel Mode stack if SP points to User Mode stack @@ -298,9 +299,16 @@ /* Get CPU-ID of this core */ .macro GET_CPU_ID reg +#ifdef CONFIG_ARC_PLAT_EZNPS + lr \reg, [CTOP_AUX_LOGIC_GLOBAL_ID] +#ifndef CONFIG_EZNPS_MTM_EXT + lsr \reg, \reg, 4 +#endif +#else lr \reg, [identity] lsr \reg, \reg, 8 bmsk \reg, \reg, 7 +#endif .endm #endif /* __ASM_ARC_ENTRY_COMPACT_H */ diff --git a/arch/arc/kernel/ctx_sw.c b/arch/arc/kernel/ctx_sw.c index 5d446df..6f4cb0d 100644 --- a/arch/arc/kernel/ctx_sw.c +++ b/arch/arc/kernel/ctx_sw.c @@ -16,6 +16,9 @@ #include #include +#ifdef CONFIG_ARC_PLAT_EZNPS +#include +#endif #define KSP_WORD_OFF ((TASK_THREAD + THREAD_KSP) / 4) @@ -67,9 +70,16 @@ __switch_to(struct task_struct *prev_task, struct task_struct *next_task) #ifndef CONFIG_SMP "st %2, [@_current_task] \n\t" #else +#ifdef CONFIG_ARC_PLAT_EZNPS + "lr r24, [%4] \n\t" +#ifndef CONFIG_EZNPS_MTM_EXT + "lsr r24, r24, 4 \n\t" +#endif +#else "lr r24, [identity] \n\t" "lsr r24, r24, 8 \n\t" "bmsk r24, r24, 7 \n\t" +#endif "add2 r24, @_current_task, r24 \n\t" "st %2, [r24]\n\t" #endif @@ -107,6 +117,9 @@ __switch_to(struct task_struct *prev_task, struct task_struct *next_task) : "=r"(tmp) : "n"(KSP_WORD_OFF), "r"(next), "r"(prev) +#ifdef CONFIG_ARC_PLAT_EZNPS + , "i"(CTOP_AUX_LOGIC_GLOBAL_ID) +#endif : "blink" ); -- 1.7.1 ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH v3 17/18] ARC: [plat-eznps] Use dedicated COMMAND_LINE_SIZE
From: Noam Camus The default 256 bytes sometimes is just not enough. We usually provide earlycon=... and console=... and ip=... All this and more may need more room. Signed-off-by: Noam Camus Acked-by: Vineet Gupta --- arch/arc/include/asm/setup.h |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/arc/include/asm/setup.h b/arch/arc/include/asm/setup.h index 3078466..48b37c6 100644 --- a/arch/arc/include/asm/setup.h +++ b/arch/arc/include/asm/setup.h @@ -12,7 +12,11 @@ #include #include +#ifdef CONFIG_ARC_PLAT_EZNPS +#define COMMAND_LINE_SIZE 2048 +#else #define COMMAND_LINE_SIZE 256 +#endif /* * Data structure to map a ID to string -- 1.7.1 ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
[PATCH v3 18/18] ARC: Add eznps platform to Kconfig and Makefile
From: Noam Camus This commit should be left last since only now eznps platform is in state which one can actually use. Signed-off-by: Noam Camus --- arch/arc/Kconfig |1 + arch/arc/Makefile |5 + 2 files changed, 6 insertions(+), 0 deletions(-) diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 689ccb3..8153b79 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -91,6 +91,7 @@ source "arch/arc/plat-sim/Kconfig" source "arch/arc/plat-tb10x/Kconfig" source "arch/arc/plat-axs10x/Kconfig" #New platform adds here +source "arch/arc/plat-eznps/Kconfig" endmenu diff --git a/arch/arc/Makefile b/arch/arc/Makefile index cf0cf34..1357e48 100644 --- a/arch/arc/Makefile +++ b/arch/arc/Makefile @@ -99,6 +99,11 @@ core-y += arch/arc/boot/dts/ core-$(CONFIG_ARC_PLAT_SIM)+= arch/arc/plat-sim/ core-$(CONFIG_ARC_PLAT_TB10X) += arch/arc/plat-tb10x/ core-$(CONFIG_ARC_PLAT_AXS10X) += arch/arc/plat-axs10x/ +core-$(CONFIG_ARC_PLAT_EZNPS) += arch/arc/plat-eznps/ + +ifdef CONFIG_ARC_PLAT_EZNPS +KBUILD_CPPFLAGS += -I$(srctree)/arch/arc/plat-eznps/include +endif drivers-$(CONFIG_OPROFILE) += arch/arc/oprofile/ -- 1.7.1 ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: [PATCH v3 04/18] irqchip: add nps Internal and external irqchips
On 01/12/15 13:02, Noam Camus wrote:
> From: Noam Camus
>
> Adding EZchip NPS400 support.
> NPS internal interrupts are internally handled at
> Multi Thread Manager (MTM) that is signaled for deactivating
> an interrupt.
> External interrupts is handled also at Global Interrupt
> Controller (GIC) e.g. serial and network devices.
>
> Signed-off-by: Noam Camus
> Cc: Thomas Gleixner
> Cc: Jason Cooper
> Cc: Marc Zyngier
> ---
> .../interrupt-controller/ezchip,nps400-ic.txt | 17 ++
> drivers/irqchip/Makefile |1 +
> drivers/irqchip/irq-eznps.c| 213
>
> 3 files changed, 231 insertions(+), 0 deletions(-)
> create mode 100644
> Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
> create mode 100644 drivers/irqchip/irq-eznps.c
>
> diff --git
> a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
> b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
> new file mode 100644
> index 000..888b2b9
> --- /dev/null
> +++
> b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
> @@ -0,0 +1,17 @@
> +EZchip NPS Interrupt Controller
> +
> +Required properties:
> +
> +- compatible : should be "ezchip,nps400-ic"
> +- interrupt-controller : Identifies the node as an interrupt controller
> +- #interrupt-cells : Specifies the number of cells needed to encode an
> + interrupt source. The value shall be 1.
So you never have to encode the interrupt trigger type? Do you only
support edge or level?
> +
> +
> +Example:
> +
> +intc: interrupt-controller {
> + compatible = "ezchip,nps400-ic";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +};
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index 177f78f..b95b954 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -55,3 +55,4 @@ obj-$(CONFIG_RENESAS_H8S_INTC) +=
> irq-renesas-h8s.o
> obj-$(CONFIG_ARCH_SA1100)+= irq-sa11x0.o
> obj-$(CONFIG_INGENIC_IRQ)+= irq-ingenic.o
> obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
> +obj-$(CONFIG_ARC_PLAT_EZNPS) += irq-eznps.o
> diff --git a/drivers/irqchip/irq-eznps.c b/drivers/irqchip/irq-eznps.c
> new file mode 100644
> index 000..bb8d547
> --- /dev/null
> +++ b/drivers/irqchip/irq-eznps.c
> @@ -0,0 +1,213 @@
> +/*
> + * Copyright(c) 2015 EZchip Technologies.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * The full GNU General Public License is included in this distribution in
> + * the file called "COPYING".
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define NPS_MSU_EN_CFG 0x80/* MSU Enable Configuration Register */
> +#define MSU_EN BIT(0) /* MSU block enable */
> +#define IPI_EN BIT(16) /* Enable service of incoming IPI
> Messages */
> +#define GIM0_EN BIT(17) /* Enable service of incoming GIM 0
> messages */
> +#define GIM1_EN BIT(18) /* Enable service of incoming GIM 1
> messages */
> +
> +#define NPS_GIM_P_POL0x110 /* Peripheral interrupts source
> polarity */
> +#define NPS_GIM_P_SENS 0x114 /* Peripheral interrupts sensitivity */
> +#define GIM_UART BIT(7)
> +#define GIM_LAN_TX (BIT(10) | BIT(25))
> +#define GIM_LAN_RX (BIT(11) | BIT(26))
> +#define GIM_PERIPH_ALL (GIM_UART | GIM_LAN_TX | GIM_LAN_RX)
> +
> +#define NPS_GIM_P_DST10 0x13A /* Peripheral Interrupt Destination
> (LAN RX) */
> +#define NPS_GIM_P_DST11 0x13B /* Peripheral Interrupt Destination
> (LAN TX) */
> +#define NPS_GIM_P_DST25 0x149 /* Peripheral Interrupt Destination
> (LAN RX) */
> +#define NPS_GIM_P_DST26 0x14A /* Peripheral Interrupt Destination
> (LAN TX) */
> +#define DST_IS BIT(26) /* Interrupt select for line 7 */
> +
> +#define NPS_GIM_P_EN 0x100 /* Peripheral interrupts source enable */
> +#define NPS_GIM_P_BLK0x118 /* Peripheral interrupts blocking for
> sources */
Are these the interrupts the peripherals are using? If yes, they really
have nothing to do here...
> +
> +/* Messaging and Scheduling Unit:
> + * Provides message management for a CPU cluster.
> + */
> +static void __init eznps_configure_msu(void)
> +{
> + int cpu;
> + u32 value = MSU_EN | IPI_EN | GIM0_EN | GIM1_EN;
> +
> + /* Enable IPI and GIM messages on all clusters */
> + for (cpu = 0 ; cp
Non existing DMA functions in ARC: dma_alloc_attrs, dma_free_attrs, dma_mmap_attrs
Hi guys, I'm bringing up a new ARC PGU driver for DRM framework with latest kernel tree. I'm using ARC AXS101 as a base and selected one the DRM required config: HAVE_DMA_ATTRS due to some memory allocation helpers in DRM. I'm getting some errors with DMA functions not implemented in ARC: dma_alloc_attrs, dma_free_attrs, dma_mmap_attrs Any clue? Regards, C.Palminha --- include/linux/dma-mapping.h: In function ‘dma_alloc_writecombine’: include/linux/dma-mapping.h:283:2: error: implicit declaration of function ‘dma_alloc_attrs’ [-Werror=implicit-function-declaration] return dma_alloc_attrs(dev, size, dma_addr, gfp, &attrs); ^ include/linux/dma-mapping.h:283:2: warning: return makes pointer from integer without a cast [enabled by default] include/linux/dma-mapping.h: In function ‘dma_free_writecombine’: include/linux/dma-mapping.h:291:2: error: implicit declaration of function ‘dma_free_attrs’ [-Werror=implicit-function-declaration] return dma_free_attrs(dev, size, cpu_addr, dma_addr, &attrs); ^ include/linux/dma-mapping.h:291:2: warning: ‘return’ with a value, in function returning void [enabled by default] include/linux/dma-mapping.h: In function ‘dma_mmap_writecombine’: include/linux/dma-mapping.h:301:2: error: implicit declaration of function ‘dma_mmap_attrs’ [-Werror=implicit-function-declaration] return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, &attrs); ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
Re: Non existing DMA functions in ARC: dma_alloc_attrs, dma_free_attrs, dma_mmap_attrs
On Wednesday 02 December 2015 01:09 AM, Carlos Palminha wrote:
> Hi guys,
>
> I'm bringing up a new ARC PGU driver for DRM framework with latest kernel
> tree.
> I'm using ARC AXS101 as a base and selected one the DRM required config:
> HAVE_DMA_ATTRS due to some memory allocation helpers in DRM.
>
> I'm getting some errors with DMA functions not implemented in ARC:
> dma_alloc_attrs, dma_free_attrs, dma_mmap_attrs
>
> Any clue?
>
> Regards,
> C.Palminha
>
> ---
> include/linux/dma-mapping.h: In function ‘dma_alloc_writecombine’:
> include/linux/dma-mapping.h:283:2: error: implicit declaration of function
> ‘dma_alloc_attrs’ [-Werror=implicit-function-declaration]
> return dma_alloc_attrs(dev, size, dma_addr, gfp, &attrs);
This is because ARC port current lacks support for dma_attr_t and associated
helpers.
There is a series in flight in linux-next, by Christoph, which already
addresses that.
You can either cherry-pick those or in the interim use the hack attached.
P.S. Per your comment at top, I'm assuming you are working off of mainline 4.3
or 4.4
-Vineet
From 433f5bfff88d0db9a1f86c622510e491e0daf045 Mon Sep 17 00:00:00 2001
From: Vineet Gupta
Date: Wed, 2 Dec 2015 12:00:41 +0530
Subject: [PATCH] [donot merge]: minimal dma_attr_t support for ARC
Signed-off-by: Vineet Gupta
---
arch/arc/Kconfig | 1 +
arch/arc/include/asm/dma-mapping.h | 21 +
2 files changed, 22 insertions(+)
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 2c2ac3f3ff80..fdf217cf5041 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -38,6 +38,7 @@ config ARC
select OF_EARLY_FLATTREE
select PERF_USE_VMALLOC
select HAVE_DEBUG_STACKOVERFLOW
+ select HAVE_DMA_ATTRS
config TRACE_IRQFLAGS_SUPPORT
def_bool y
diff --git a/arch/arc/include/asm/dma-mapping.h b/arch/arc/include/asm/dma-mapping.h
index 2d28ba939d8e..2b68e2a7b3a1 100644
--- a/arch/arc/include/asm/dma-mapping.h
+++ b/arch/arc/include/asm/dma-mapping.h
@@ -36,6 +36,27 @@ extern int dma_common_get_sgtable(struct device *dev, struct sg_table *sgt,
#define dma_mmap_coherent(d, v, c, h, s) dma_common_mmap(d, v, c, h, s)
#define dma_get_sgtable(d, t, v, h, s) dma_common_get_sgtable(d, t, v, h, s)
+static inline void *dma_alloc_attrs(struct device *dev, size_t size,
+ dma_addr_t *dma_handle, gfp_t flag,
+ struct dma_attrs *attrs)
+{
+ return dma_alloc_coherent(dev, size, dma_handle, flag);
+}
+
+static inline void dma_free_attrs(struct device *dev, size_t size,
+ void *cpu_addr, dma_addr_t dma_handle,
+ struct dma_attrs *attrs)
+{
+ dma_free_coherent(dev, size, cpu_addr, dma_handle);
+}
+
+static inline int
+dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma, void *cpu_addr,
+ dma_addr_t dma_addr, size_t size, struct dma_attrs *attrs)
+{
+ return dma_mmap_coherent(dev, vma, cpu_addr, dma_addr, size);
+}
+
/*
* streaming DMA Mapping API...
* CPU accesses page via normal paddr, thus needs to explicitly made
--
1.9.1
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