[ANNOUNCE] Linaro Binary Toolchain Release GCC 6.5-2018.12
The Linaro Binary Toolchain The Linaro GCC 6.5-2018.12 Release is now available. The GCC 6 Release series has significant changes from the GCC 5 release series. For an explanation of the changes please see the following website: https://gcc.gnu.org/gcc-6/changes.html For help in porting to GCC 6 please see the following explanation: https://gcc.gnu.org/gcc-6/porting_to.html Download release packages from: (sources) http://releases.linaro.org/components/toolchain/gcc-linaro/6.5-2018.12/ (binaries) http://releases.linaro.org/components/toolchain/binaries/6.5-2018.12/ Previous snapshots and release-candidates are at: http://snapshots.linaro.org/components/toolchain/binaries/ Previous releases are at: http://releases.linaro.org/components/toolchain/binaries/ A description of the arm and AArch64 target triples can be found at: https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Triples Host Requirements == Linaro officially supports the current and previous Ubuntu LTS releases (as of the time of this release). This does not mean that the toolchain will not work on other/older Linux distributions. See the following for the life-time of Ubuntu LTS releases. https://wiki.ubuntu.com/Releases The host system upon which the cross-compiler will run requires a minimum of glibc 2.14, because of API changes to glibc's memcpy API. https://bugs.linaro.org/show_bug.cgi?id=1869 Package Versions = Linaro GCC 6.5-2018.12 http://releases.linaro.org/components/toolchain/gcc-linaro/6.5-2018.12/ Linaro glibc 2.23 (linaro/2.23/master) https://lists.gnu.org/archive/html/info-gnu/2016-02/msg9.html Linaro newlib 2.4-2016.03 (linaro_2.4-branch) https://sourceware.org/ml/newlib/2016/msg00370.html Linaro binutils 2.27 (users/linaro/binutils-2_27-branch) https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=binutils/NEWS;hb=refs/tags/binutils-2_27 Linaro GDB 8.2 (gdb-8.2-branch) https://lists.gnu.org/archive/html/info-gnu/2018-09/msg1.html Linaro toolchain package git branches are hosted at: http://git.linaro.org/toolchain NEWS for GCC 6 (as of Linaro GCC 6.5-2018.12) == * Runtest and gdbserver are no longer installed in the toolchain bin/ directory. Binary releases no longer include runtest at all, and gdbserver is a target tool; it is now shipped in the sysroot under usr/bin/. LDTS case #2211: gdbserver and runtest in GCC binary release are in the wrong place or have the wrong name * Gdbserver is no longer linked statically, because this is currently unsupported. Linaro bugzilla #3344: gdbserver broken in Linaro 2017.02 https://bugs.linaro.org/show_bug.cgi?id=3344 * Previous MinGW hosted version of Linaro GCC C preprocessor failed to convert character set used for string, character constants, etc. This is fixed in this release. Linaro bugzilla #3040 : CC1 and cc1plus cannot convert UTF-8. https://bugs.linaro.org/show_bug.cgi?id=3040 * The Linaro GCC 6.3-2017.05 snapshot added support for -mpure-code option to ARMv7-M and ARMv8-M targets. This option ensures functions are put into sections that contain only code and no data. * The GDB version was upgraded from GDB 8.1 to 8.2. * Previous versions of the Linaro GCC 6 toolchain, when -static -E/—dynamic-list are passed to the linker, might create executables with dynamic sections which aren’t supported by run-time. This was exhibited in Perf Tools build system and has been fixed upstream and backported into Linaro Binutils 2.27 branch. Linaro bugzilla #2926 : Perf tools compiled statically for AArch64 with Linaro release 6.1 and later ones was not statically linked. https://bugs.linaro.org/show_bug.cgi?id=2926 * The Linaro GCC 6.3-2017.03 snapshot fixed some ILP32 issues (TLS, exception handling, …) and these have been incorporated into this release. * Previous versions of the Linaro GCC 6 toolchain were incorrectly generating floating-point code for soft-float Linux targets (arm-linux-gnueabi, and armeb-linux-gnueabi). This escaped detection until recently because the soft-float targeted toolchains were configured to use general-purpose registers for passing floating-point values (which is what you would expect for soft-float toolchains) and the intra-routine floating-code was not noticed. The issue would only show up on targets that were run on hardware that truly didn't have floating-point hardware where the kernel did not trap and emulate floating-point routines. This has been solved in Linaro GCC 6.3-2017.02-rc2 by configuring the toolchain (using --with-float=soft) to generate code without any floating-point instructions at all (-mfloat-abi=soft). https://review.linaro.org/#/c
[ACTIVITY] week ending 13 Jan 2019
[VIRT-294 # ARMv8.3-PAuth, Pointer Authentication ] Posted v3 based on feedback. [VIRT-339 # ARMv8.5-BTI, Branch Target Identification ] Posted "v1" to qemu-devel, rebased on v3 pauth [VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ] Progressed to the "write a standalone test case" stage for linux-user. I'll need to discuss address space stuff w/ PMM for system mode. Discovered while writing a test case for this that my document and gas do not agree on the instruction encodings. Putting this on hold until query about document revision numbers is answered. Posted pieces of this implementing TBI for aarch64-linux-user. [VIRT-327 # Richard's upstream QEMU work ] Fixed alpha-linux-user fpcr initialization. Fixed alpha-softmmu double-increment of SIGILL address. Sent v2 patchset for target/arm use of gvec minmax routines. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] 7 - 11 January 2019
== Progress == * [ARM GlobalISel] Select complicated G_CONSTANT [LLVM-491] - Negative constants in particular cause a lot of fallbacks in the test-suite/selfhost - Need to help TableGen produce code for MOVi32imm - Ready to commit next week - Looked a bit into enabling MVNi as well, but that seems to require more effort * Use new version of GCC on buildbots [LLVM-515] - Talked to doko and got a different PPA - Didn't get a chance to test it yet, will do next week * Sanity checks for docker builbbot containers - Sent a quick patch to check slavenames and compatibility between slave and image when starting a bot container * Investigated some buildbot failures - Marked 2 sanitizer tests as unsupported on ARM - Need to investigate further so we can re-enable them - I've been emailing the author, hopefully he can help debug == Plan == * More of the same ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] 7 January - 11 January 2019
== This Week == * SVE ACLE (6/10) - Working on svlsl_wide patch. * PR887881: Infinite loop in malloc_candidate_p_1 (1/10) * Validation (2/10) - Prototype HCQC wrapper script * Misc (1/10) - Meetings == Next Week == - Continue ongoing tasks. ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] 2-11 January 2019
== Progress == * FDPIC - (GNU-499) GCC: wait for feedback on v4 patches, but GCC just entered stage4, so it's probably too late for gcc-9 :-( - (GNU-411) GDB: hacked to build gdbserver, but the resulting binary does not start. * GCC upstream validation: - reported a few regressions - dealing with some random results, still - qemu-3.1.0-rc3, memory consumption: more experiments under LSF show "random" reports for memory consumption. It seems qemu-3.1 consumes more memory in some cases, though. * GCC: - (GNU-99) rebased ubsan / bare-metal patches. No progress. * misc (conf-calls, meetings, emails, ) - reviewing/submitted infra script patches - dealing with nasty ST-internal infrastructure problems - (GNU-592): improved benchmarking scripts - (TCWG-1501) looking at new build servers configs == Next == FDPIC: - GCC: handle feedback on v4 patches - GDB: update patches - uclibc-ng: look at how to test fdpic mode with openadk Validation: - isolate if/why qemu-3.1.0-rc3 consumes more memory than 2.11 for aarch64-linux target ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending Jan. 13 2019
Upstream Work ([VIRT-109])
==
- posted {PATCH v1 0/6} current fpu/next queue Message-Id:
<20190108162154.22259-1-alex.ben...@linaro.org>
- posted {PATCH v1 0/3} gitdm updates Message-Id:
<2019010729.2087-2-alex.ben...@linaro.org>
- posted {PATCH v1 00/19} testing/next queue for travis and docker
Message-Id: <20190110174516.21586-1-alex.ben...@linaro.org>
- also managed to trigger two of the occasional Travis failures
locally
- one is a segfault in mcount (gprof/RCU related)
- the other seems to be a O_NONBLOCK/make interaction (using eBPF
to track it)
- did a little more on re-work of [system test and misc arch] tests
- will be useful for test cases for plugins
- respin {PATCH v3 0/5} support reading some CPUID/CNT registers from
user-space Message-Id:
<20180625160009.17437-1-alex.ben...@linaro.org> :todo
- in branch [v3 branch]
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
[system test and misc arch]
https://github.com/stsquad/qemu/tree/testing/enable-system-tcg-tests-v2
[v3 branch]
https://github.com/stsquad/qemu/tree/misc/cnt-and-misc-reg-fixes-v3
Completed Reviews [2/2]
===
{PATCH v3 0/2} tests: Reorganize MIPS TCG directories and files
Message-Id: <1546621859-28227-1-git-send-email-aleksandar.marko...@rt-rk.com>
- CLOSING NOTE [2019-01-07 Mon 11:23]
A few notes about keeping makefile
{PATCH 00/13} Misc fixes / improvements for the docker and travis configs
Message-Id: <20190109163114.17010-1-berra...@redhat.com>
- CLOSING NOTE [2019-01-10 Thu 12:34]
Queued a chunk of these into testing/next
Absences
- Connect BKK19 (1-5th April 2019)
- holiday after Connect
Current Review Queue
* {Qemu-devel} {PATCH 00/11} target/arm: Implement ARMv8.5-BTI
Message-Id: <20190110121736.23448-1-richard.hender...@linaro.org>
* {PATCH v9 00/21} Fixing record/replay and adding reverse debugging
Message-Id: <154703587757.13472.3898702635363120794.stgit@pasha-VirtualBox>
* {Qemu-devel} {PATCH 0/4} tcg: support heterogenous CPU clusters
Message-Id: <20190108163008.7006-1-peter.mayd...@linaro.org>
* {Qemu-devel} {PATCH v3 00/31} target/arm: Implement ARMv8.3-PAuth
Message-Id: <20190108223129.5570-1-richard.hender...@linaro.org>
* {Qemu-arm} {PATCH 0/3} target/arm: Vector expansion improvments.
Message-Id: <20190106225035.5671-1-richard.hender...@linaro.org>
* {Qemu-devel} {PATCH} configure: Force the C standard to gnu11
Message-Id: <1546857926-5958-1-git-send-email-th...@redhat.com>
--
Alex Bennée
___
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[ACTIVITY] report week ending 11 Jan
Progress: * VIRT-65 [QEMU upstream maintainership] - code review: + rth's pointer-auth emulation patchset + more devices for the microbit board model + support for u-boot "noload" image type + gdbstub multiprocess extension support for use when the board model has multiple asymmetric clusters (like Xilinx Zynq boards) - finished debugging patch for aarch64 host linux-user to distinguish SEGV on read from SEGV on write by looking at the ESR context struct from the kernel rather than by looking at the faulting insn; sent it. - sent patch to fix linux-user pread64/pwrite64 with NULL buffer and 0 length * VIRT-268 [QEMU support for dual-core Cortex-M Musca board] - Sent out patchset fixing heterogenous CPU support (required a lot of thought about what we might need to fix and not all that much code, in the end) - Started work on refactoring our IoTKit model to also support the extra pieces required by the SSE-200 subsystem used in the Musca thanks -- PMM ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 11 Jan
[LLVM-520] LLD Fix movt/movw relocation overflow Now committed upstream. [LLVM-521] Taking the address of an ifunc in AArch64 Prompted by a bug report and comment about pointer equivalence, spent some time looking into gold, lld and bfd behaviour to ensure that LLD is at least correct. Other Some investigation into LLD non-support of common-page-size and whether this is significant for code-size. Used in response to query about whether LLD should change default value of max-page-size. Thoughts about whether a linker must generate cantunwind .ARM.exidx sections for code sections missing a .ARM.exidx section. If C++ code with exceptions is interleaved with some assembly code without .ARM.exidx sections then the assembly code can match the address range of the C++ code that precedes it. ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
