Re: ldr instruction selection in the aarch64 backend

2016-02-12 Thread Virendra Kumar Pathak
Hi Andrew,

Thanks for explaining the process.

On 5 February 2016 at 21:49, Pinski, Andrew <
andrew.pin...@caviumnetworks.com> wrote:

> aarch64_legitimate_address_hook_p is the place where the result of
> aarch64_classify_address  is returned to the middle-end.  The middle-end
> then knows that possibility for a+b is a legitimate address so it forces x3
> << 3 into a register and tries aarch64_legitimate_address_hook_p again.
>
>
>
> Thanks,
>
> Andrew Pinski
>
>
>
> *From:* linaro-toolchain [mailto:linaro-toolchain-boun...@lists.linaro.org]
> *On Behalf Of *Virendra Kumar Pathak
> *Sent:* Friday, February 5, 2016 6:58 AM
> *To:* Linaro Toolchain Mailman List 
> *Subject:* ldr instruction selection in the aarch64 backend
>
>
>
> Hi Linaro Toolchain Group,
>
>
>
> I have a question on the ldr instruction selection in the aarch64 backend.
>
> Could someone help me in this regards, please?
>
>
>
> I am trying to allow only type A instructions while disabling the type B.
>
> Type A example: ldr x4, [x20,x1]---> allow
>
> Type B example: ldr x1, [x9,x3,lsl #3]   --->
> disable
>
>
>
>
>
> Experiment/My Understanding -
>
> aarch64_classify_address() returns true if rtx X is a valid address. If
> allow_reg_index_p=true then it calls aarch64_classify_index().
>
> aarch64_classify_index() identify the address mode of second operand (op1)
> and accordingly calculate the shift.
>
> If shift=0 then type A is generated otherwise Type B will be generated.
>
>
>
> Thus if (shift != 0) then I am returning 'false' from
> aarch64_classify_index().
>
> -patch-
>
> --- a/gcc/config/aarch64/aarch64.c
>
> +++ b/gcc/config/aarch64/aarch64.c
>
> @@ -3586,6 +3586,9 @@ aarch64_classify_index (struct aarch64_address_info
> *info, rtx x,
>
>if (GET_CODE (index) == SUBREG)
>
>  index = SUBREG_REG (index);
>
> +  if (shift != 0)
>
> + return false;
>
>if ((shift == 0 ||
>
> (shift > 0 && shift <= 3
>
> && (1 << shift) == GET_MODE_SIZE (mode)))
>
> ---
>
>
>
> Result -
>
> Before change
>
> ldr x0, [x13,x0,lsl #3]
>
> After Change
>
> lsl x1, x1, #3
>
> ldr x0, [x15,x1]
>
>
>
> Question -
>
> How the returning 'false' from aarch64_classify_index() is resulting in
> the selection of type A versus type B?
>
> I could not find the function which is taking the decision based on return
> from aarch64_classify_address().
>
> Could someone please explain this process or point me to the relevant
> files or code?
>
> Please correct me if my understanding is wrong.
>
>
>
> Thanks in advance for your time and patience.
>
>
>
>
>
> --
>
> with regards,
> Virendra Kumar Pathak
>



-- 
with regards,
Virendra Kumar Pathak
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[ACTIVITY] 08 - 12 February

2016-02-12 Thread Yao Qi

# Progress #

* Support range stepping on arm-linux.  TCWG-518.  [4/10]
  Preparatory patches are pushed in.  Patches are being tested.

* Linaro connect.  [3/10]
** Slides are done.
** Collect documents for visa application.

* GDB 7.11 release.  TCWG-509.  [1/10]
  Release branch is created.  Discuss on issue related to big endian,
  but ARM is the only user of that code.

* Patch review, especially arm tracepoint support.  [2/10].

# Plan #

* TCWG-518, upstream patches if tests are OK.
* TCWG-172, continue look at test parity between arm and x86_64.
* Go to London on Wed for visa application.

--
Yao
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[ACTIVITY]

2016-02-12 Thread Renato Golin
== Progress ==

* Conference (2/10)
 - More EuroLLVM paper reviews, discussions

* Support (5/10)
 - Looking at PR16275 (review D17141)

* Background (3/10)
 - Code review, meetings, discussions, general support, etc.
 - Buildbots broken, bisects, debugging
 - Defining and posting Job ad (wanna work with us?)
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