[ACTIVITY] Week 23
== Issues == * None == Progress == * CARD-1162 : Linaro GCC 4.9 and CARD-1355 : stabilization and optimization effort for ARMv8-a (8/10) - Put the backporting script on https://git.linaro.org/toolchain/backflip.git (documentation still needed) - FSF branch merges for 4.9 and 4.8 - Backported requested fixes in 4.9 - Validate merges and some backports in cbuildv1 - Looked at the different results we have in cbuildv2 and cbuildv1 - Still some issues in Jenkins (build crash or are stuck) - 40 backports stiil need validation * Misc: (2/10) o Various meetings. == Next == * Complete FSF branch merges and release 4.9-2014.06 * Document backporting script usage * Continue feedback and help with the validation ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
[Weekly] 02-06 JUNE 2014
== This week == Backported Launchpad 1234146 - Bad Neon intrinsics code gen when using ld4/st4 on AArch64 (2/10) Bug Investigations (4/10) Launchpad Bug 640521 - Incorrect function prologue with Thumb-1 high register variable Launchpad Bug 1318831 - Invalid unpoisoning of stack redzones on ARM Launchpad bug 771832 - bogus reference to unused symbols Launchpad cleanup (4/10) - 1305042 - Changed status to invalid - 634731 - Marked as won't fix for older releases. Improved code generated for 4.8 and 4.9 - 637882 - Marked as won't fix for older releases. Improved code generated for 4.8 and 4.9 - 638687 - Changed status to invalid. Code for alloca is correct and alignment is necessary - 1312931 - Could not verify. - 772085 - Marked as won't fix for older releases. Fixed in 4.8 and 4.9 - 1225317 - Marked as incomplete due to lack of test case == Next week == Vacation == Future == No Plans. ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
[Activity] 2 - 6 June
Progress: Investigation following review feedback of VLD post-indexing patch TCWG-430 [8/10] libvpx VP9 performance investigation TCWG-429 [2/10] ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] 26-30 May
Progress Bank holiday [2/10] Retested VLD post-indexing patch, held up by trunk breakage TCWG-430 [2/10] libvpx VP9 performance investigation TCWG-429 [4/10] libvpx aarch64 ICE investigation [2/10] ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] Week 23
=Progress= lowlevellock performance bugs - TCWG-435 [1/10] * All ready to go cbuild benchmarking - TCWG-360 [4/10] * Completed a draft implementation for spec2k * Parked pending review Meetings/mail/etc [5/10] =Plan= Send lowlevellock patches to list Get back to benchmarking/improving cortex-strings memset ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] 2- 7 June 2014
= Progress == * LTO experiments (3/10) Tested with various compiler revisions and in native X86 machines. Compare errors in gcc 4.9 Linaro 14.05 version. Aarch64, LTO bootstrap passes in trunk. On FSF GCC 4.9 branch encountering ICE. Opened PRs in GCC Bugzilla. * Misc (2/10) - 1-1 meetings (Ryan, Christophe and Maxim) (0.5/10) - AMD internal support work and meetings (0.5/10) Sick Leave on 2nd June (2/10) UK VISA application processing (3/10) == Plan == * UK VISA processing attend interview, biometrics. * Continue bug fixing. * LTO bootstrap failure * Test libsanitizer patch for christophe. ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] 2 - 6 May 2014
== Progress == * Zero/sign extension elimination (TCWG-15) (2/10) - Posted patch for comment * benchmarking (TCWG-468) (1/10) - Ran a53 benchmarks * regressions (7/10) - THUMB1 regression for ARM fenv * Issue due to thumb1 not supporting mrc/mcr. Patch to fix this is posted for review. - Regression when allocating 128bit integer to VFP register * When LRA assigns DImode value to TImode register, it is not setting up it in the right place of TImode. Due to this, one of the moves becomes dead. Patterns needs to be checked. * VFP registers store big-endian values in little-endian format. Hence, subreg for mode greater than word has to be aware of this. As it is, aarch64_cannot_change_mode_class will need the fix like done in ARM. == Plan == * Benchmarking. * Upstream zero/sign extension elimination activities. ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
