Re: Effect of alignment and peeling on vectorised loops
On 30 November 2011 20:28, Michael Hope wrote:
> On Thu, Dec 1, 2011 at 12:20 AM, Ira Rosen wrote:
>> On 30 November 2011 02:33, Michael Hope wrote:
>>
>
> Peeling and using the vld1.i64 {d16-d17}, [r1:64]! form should be
> faster for larger loops. For some reason vld1.i64 ..., [r1:128] gives
> an illegal instruction trap on my board. Note that the :128 is in
> bits.
Are you sure the address is 128 bit aligned ? I think the reason for
the failure is the behaviour of memalign. Changing the memalign's on
top from 8 to ALIGN appears to fix the problem - or was that
deliberate ?
Regards,
Ramana
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Release notes for GCC 4.6
Hi all, I've copied all those who made commits to GCC 4.6 this month. Could you please give me a sentence or two for the release notes? Thanks Andrew ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
Re: Release notes for GCC 4.6
On 7 December 2011 22:36, Andrew Stubbs wrote: > Hi all, Hi Andrew, > > I've copied all those who made commits to GCC 4.6 this month. > > Could you please give me a sentence or two for the release notes? I committed several patches to enable SLP of libav's weight-h264-pixels16x16-8: - support SLP of operations with arbitrary number of operands - support SLP of conditions - support pattern recognition in basic block SLP - enhance mixed-sized condition pattern to handle non-constant operands I also backported a reduced version of Jakub's mixed-sized condition pattern recognizer. Thanks, Ira > > Thanks > > Andrew ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
