Re: [PATCH v9] RISC-V: Add the 'zfa' extension, version 0.2

2023-05-15 Thread jinma via Gcc-patches 
According to Jeff's review feedback, the issues regarding UNSPEC's 
implementation of round, ceil, nearbyint, etc. still need to be determined:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617706.html

source: 
https://github.com/majin2020/gcc-mirror/commit/93d7a2d995cee588d494d1839f56e8151c6cb057

Re: [PATCH v9] RISC-V: Add the 'zfa' extension, version 0.2

2023-05-16 Thread jinma via Gcc-patches 
On 5/15/23 07:16, Jin Ma wrote:
> > This patch adds the 'Zfa' extension for riscv, which is based on:
> > https://github.com/riscv/riscv-isa-manual/commits/zfb
> > 
> > The binutils-gdb for 'Zfa' extension:
> > https://sourceware.org/pipermail/binutils/2023-April/127060.html
> > 
> > What needs special explanation is:
> > 1, The immediate number of the instructions FLI.H/S/D is represented in the 
> > assembly as a
> >floating-point value, with scientific counting when rs1 is 2,3, and 
> > decimal numbers for
> >the rest.
> > 
> >Related llvm link:
> >  https://reviews.llvm.org/D145645
> >Related discussion link:
> >  https://github.com/riscv/riscv-isa-manual/issues/980
> > 
> > 2, According to riscv-spec, "The FCVTMO D.W.D instruction was added 
> > principally to
> >accelerate the processing of JavaScript Numbers.", so it seems that no 
> > implementation
> >is required.
> > 
> > 3, The instructions FMINM and FMAXM correspond to C23 library function 
> > fminimum and fmaximum.
> >Therefore, this patch has simply implemented the pattern of 
> > fminm3 and
> >fmaxm3 to prepare for later.
> > 
> > gcc/ChangeLog:
> > 
> >  * common/config/riscv/riscv-common.cc: Add zfa extension version.
> >  * config/riscv/constraints.md (zfli): Constrain the floating point number 
> > that the
> >  instructions FLI.H/S/D can load.
> >  * config/riscv/iterators.md (ceil): New.
> >  (rup): New.
> >  * config/riscv/riscv-opts.h (MASK_ZFA): New.
> >  (TARGET_ZFA): New.
> >  * config/riscv/riscv-protos.h (riscv_float_const_rtx_index_for_fli): New.
> >  * config/riscv/riscv.cc (riscv_float_const_rtx_index_for_fli): New.
> >  (riscv_cannot_force_const_mem): If instruction FLI.H/S/D can be used, 
> > memory is not applicable.
> >  (riscv_const_insns): Likewise.
> >  (riscv_legitimize_const_move): Likewise.
> >  (riscv_split_64bit_move_p): If instruction FLI.H/S/D can be used, no split 
> > is required.
> >  (riscv_split_doubleword_move): Likewise.
> >  (riscv_output_move): Output the mov instructions in zfa extension.
> >  (riscv_print_operand): Output the floating-point value of the FLI.H/S/D 
> > immediate in assembly
> >  (riscv_secondary_memory_needed): Likewise.
> >  * config/riscv/riscv.md (fminm3): New.
> >  (fmaxm3): New.
> >  (movsidf2_low_rv32): New.
> >  (movsidf2_high_rv32): New.
> >  (movdfsisi3_rv32): New.
> >  (f_quiet4_zfa): Likewise.
> > 
> > gcc/testsuite/ChangeLog:
> > 
> >  * gcc.target/riscv/zfa-fleq-fltq-rv32.c: New test.
> >  * gcc.target/riscv/zfa-fleq-fltq.c: New test.
> >  * gcc.target/riscv/zfa-fli-rv32.c: New test.
> >  * gcc.target/riscv/zfa-fli-zfh-rv32.c: New test.
> >  * gcc.target/riscv/zfa-fli-zfh.c: New test.
> >  * gcc.target/riscv/zfa-fli.c: New test.
> >  * gcc.target/riscv/zfa-fmovh-fmovp-rv32.c: New test.
> >  * gcc.target/riscv/zfa-fround-rv32.c: New test.
> >  * gcc.target/riscv/zfa-fround.c: New test.
> > ---
> >   gcc/common/config/riscv/riscv-common.cc   |   4 +
> >   gcc/config/riscv/constraints.md   |  21 +-
> >   gcc/config/riscv/iterators.md |   5 +
> >   gcc/config/riscv/riscv-opts.h |   3 +
> >   gcc/config/riscv/riscv-protos.h   |   1 +
> >   gcc/config/riscv/riscv.cc | 204 +-
> >   gcc/config/riscv/riscv.md | 145 +++--
> >   .../gcc.target/riscv/zfa-fleq-fltq-rv32.c |  19 ++
> >   .../gcc.target/riscv/zfa-fleq-fltq.c  |  19 ++
> >   gcc/testsuite/gcc.target/riscv/zfa-fli-rv32.c |  79 +++
> >   .../gcc.target/riscv/zfa-fli-zfh-rv32.c   |  41 
> >   gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c  |  41 
> >   gcc/testsuite/gcc.target/riscv/zfa-fli.c  |  79 +++
> >   .../gcc.target/riscv/zfa-fmovh-fmovp-rv32.c   |  10 +
> >   .../gcc.target/riscv/zfa-fround-rv32.c|  42 
> >   gcc/testsuite/gcc.target/riscv/zfa-fround.c   |  42 
> >   16 files changed, 719 insertions(+), 36 deletions(-)
> >   create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fleq-fltq-rv32.c
> >   create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fleq-fltq.c
> >   create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-rv32.c
> >   create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-zfh-rv32.c
> >   create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c
> >   create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli.c
> >   create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp-rv32.c
> >   create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fround-rv32.c
> >   create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fround.c
> > 
> 
> 
> > +
> > +/* Return index of the FLI instruction table if rtx X is an immediate 
> > constant that can
> > +   be moved using a single FLI instruction in zfa extension. Return -1 if 
> > not found.  */
> > +
> > +int
> > +riscv_float_const_rtx_index_for_fli (rtx x)
> > +{
> > +  unsigned HOST_WIDE_INT *fli_value_array;
> > +
> > +  machin

[PATCH 1/1] Fixed typo in RISCV

2022-12-22 Thread jinma via Gcc-patches 
From 21904908689318ab81c630adc8cc7067e1a12488 Mon Sep 17 00:00:00 2001
From: Jin Ma 
Date: Fri, 23 Dec 2022 10:42:19 +0800
Subject: [PATCH 1/1] Fixed typo

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc:
---
 gcc/common/config/riscv/riscv-common.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 4b7f777c103..0a89fdaffe2 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1538,7 +1538,7 @@ riscv_check_conds (

   for (itr = conds.begin (); itr != conds.end (); ++itr)
 {
-  /* We'll check march= and mabi= in ohter place.  */
+  /* We'll check march= and mabi= in other place.  */
   if (prefixed_with (*itr, "march=") || prefixed_with (*itr, "mabi="))
continue;

--
2.17.1

[PATCH] [RISCV] Change the generation mode of `adjust_sp_rtx` from gen_insn to gen_SET.

2023-01-05 Thread jinma via Gcc-patches 
From 35c1f22d3c9a6910103cf9688c5c2bc3d5b75c68 Mon Sep 17 00:00:00 2001
From: Jin Ma 
Date: Fri, 6 Jan 2023 14:47:37 +0800
Subject: [PATCH] [RISCV] Change the generation mode of `adjust_sp_rtx` from 
gen_insn to gen_SET.

The gen_insn method is used to generate `adjust_sp_rtx` here, which has certain
potential risks:

When the architecture adds pre-processing to `define_insn "adddi3"`, such as
`define_expend "adddi3"`, the gen_expand will be automatically called here,
causing the patern to emit directly, which will cause insn to enter REG_NOTE
for `DWARF` instead of patern.

The following error REG_NOTE occurred:
error: invalid rtl sharing found in the insn:
(insn 19 3 20 2 (parallel [
...
])
(expr_list:REG_CFA_ADJUST_CFA
(insn 18 0 0 (set (reg/f:DI 2 sp)
(plus:DI (reg/f:DI 2 sp)
(const_int -16 [0xfff0]))) -1
(nil

In fact, the correct one should be the following:
(insn 19 3 20 2 (parallel [
...
])
(expr_list:REG_CFA_ADJUST_CFA
(set (reg/f:DI 2 sp)
(plus:DI (reg/f:DI 2 sp)
(const_int -16 [0xfff0])

Following the treatment of arm or other architectures, it is more reasonable to
use gen_SET here.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_adjust_libcall_cfi_prologue):
(riscv_adjust_libcall_cfi_epilogue):
---
 gcc/config/riscv/riscv.cc | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 9a53999a39d..eab0500262f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5044,8 +5044,9 @@ riscv_adjust_libcall_cfi_prologue ()
   }

   /* Debug info for adjust sp.  */
-  adjust_sp_rtx = gen_add3_insn (stack_pointer_rtx,
-stack_pointer_rtx, GEN_INT (-saved_size));
+  adjust_sp_rtx =
+gen_rtx_SET (stack_pointer_rtx,
+gen_rtx_PLUS (GET_MODE(stack_pointer_rtx), stack_pointer_rtx, 
GEN_INT (-saved_size)));
   dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx,
  dwarf);
   return dwarf;
@@ -5166,8 +5167,9 @@ riscv_adjust_libcall_cfi_epilogue ()
   int saved_size = cfun->machine->frame.save_libcall_adjustment;

   /* Debug info for adjust sp.  */
-  adjust_sp_rtx = gen_add3_insn (stack_pointer_rtx,
-stack_pointer_rtx, GEN_INT (saved_size));
+  adjust_sp_rtx =
+gen_rtx_SET (stack_pointer_rtx,
+gen_rtx_PLUS (GET_MODE(stack_pointer_rtx), stack_pointer_rtx, 
GEN_INT (saved_size)));
   dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx,
  dwarf);

--
2.17.1

[PATCH] [RISCV] Add 'Zfa' extension according to riscv-isa-manual

2023-01-11 Thread jinma via Gcc-patches 
From e4ce8e825c145d74e6b9827f972629548e39f118 Mon Sep 17 00:00:00 2001
From: Jin Ma 
Date: Wed, 11 Jan 2023 19:13:27 +0800
Subject: [PATCH] [RISCV] Add 'Zfa' extension according to riscv-isa-manual

This patch adds the 'Zfa' extension for riscv, which is an implementation for
unratified and unfrozen RISC-V extension.

Although the binutils-gdb for 'Zfa' extension is not yet upstream, we can try
to discuss it. And we can test new instructions for your (possibly virtual)
environment and early review for fast adoption after ratification.

This is based on:
https://github.com/riscv/riscv-isa-manual/commit/d74d99e22d5f68832f70982d867614e2149a3bd7
latest 'Zfa' change on the master branch of the RISC-V ISA Manual as
of this writing.

The Wiki Page (details):
https://github.com/a4lg/binutils-gdb/wiki/riscv_zfa

The binutils-gdb for 'Zfa' extension:
(https://sourceware.org/pipermail/binutils/2022-September/122938.html)

gcc/ChangeLog:

 * common/config/riscv/riscv-common.cc:
 * config/riscv/constraints.md (Zf):
 * config/riscv/predicates.md:
 * config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2):
 (AVAIL):
 (RISCV_ATYPE_SF):
 (RISCV_ATYPE_DF):
 (RISCV_FTYPE_ATYPES2):
 * config/riscv/riscv-ftypes.def (2):
 * config/riscv/riscv-opts.h (MASK_ZFA):
 (TARGET_ZFA):
 * config/riscv/riscv-protos.h (riscv_float_const_rtx_index_for_fli):
 * config/riscv/riscv.cc (riscv_float_const_rtx_index_for_fli):
 (riscv_cannot_force_const_mem):
 (riscv_const_insns):
 (riscv_legitimize_const_move):
 (riscv_split_64bit_move_p):
 (riscv_output_move):
 (riscv_memmodel_needs_release_fence):
 (riscv_print_operand):
 (riscv_secondary_memory_needed):
 * config/riscv/riscv.h (GP_REG_RTX_P):
 * config/riscv/riscv.md (riscv_fminm3):
 (riscv_fmaxm3):
 (fix_truncdfsi2_zfa):
 (round2):
 (rint2):
 (f_quiet4_zfa):
 * config/riscv/riscv.opt:

gcc/testsuite/ChangeLog:

 * gcc.target/riscv/zfa-fcvtmod.c: New test.
 * gcc.target/riscv/zfa-fleq-fltq.c: New test.
 * gcc.target/riscv/zfa-fli-zfh.c: New test.
 * gcc.target/riscv/zfa-fli.c: New test.
 * gcc.target/riscv/zfa-fminm-fmaxm.c: New test.
 * gcc.target/riscv/zfa-fmovh-fmovp.c: New test.
 * gcc.target/riscv/zfa-fround.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc   |   4 +
 gcc/config/riscv/constraints.md   |   7 ++
 gcc/config/riscv/predicates.md|   4 +
 gcc/config/riscv/riscv-builtins.cc|  11 ++
 gcc/config/riscv/riscv-ftypes.def |   2 +
 gcc/config/riscv/riscv-opts.h |   3 +
 gcc/config/riscv/riscv-protos.h   |   1 +
 gcc/config/riscv/riscv.cc | 105 +++-
 gcc/config/riscv/riscv.h  |   1 +
 gcc/config/riscv/riscv.md | 114 ++
 gcc/config/riscv/riscv.opt|   4 +
 gcc/testsuite/gcc.target/riscv/zfa-fcvtmod.c  |  12 ++
 .../gcc.target/riscv/zfa-fleq-fltq.c  |  20 +++
 gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c  |  42 +++
 gcc/testsuite/gcc.target/riscv/zfa-fli.c  |  80 
 .../gcc.target/riscv/zfa-fminm-fmaxm.c|  25 
 .../gcc.target/riscv/zfa-fmovh-fmovp.c|  11 ++
 gcc/testsuite/gcc.target/riscv/zfa-fround.c   |  25 
 18 files changed, 448 insertions(+), 23 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fcvtmod.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fleq-fltq.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fminm-fmaxm.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fround.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 0a89fdaffe2..cccec12975c 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -217,6 +217,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zfhmin",ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zfa", ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1242,6 +1244,8 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zfhmin",&gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
   {"zfh",   &gcc_options::x_riscv_zf_subext, MASK_ZFH},
 
+  {"zfa",   &gcc_options::x_riscv_zf_subext, MASK_ZFA},
+
   {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
 
   {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL},
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 51cffb2bcb6..2fd407b1d9c 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -110,6 +110,13 @@ (define_constraint "T"
   (and (match_operand 0 "move_operand")
(match_test "CONSTANT_P (op)")))
 
+;

[PATCH v2] [RISCV] Add 'Zfa' extension according to riscv-isa-manual

2023-01-11 Thread jinma via Gcc-patches 
From e4ce8e825c145d74e6b9827f972629548e39f118 Mon Sep 17 00:00:00 2001
From: Jin Ma 
Date: Wed, 11 Jan 2023 19:13:27 +0800
Subject: [PATCH] [RISCV] Add 'Zfa' extension according to riscv-isa-manual

From e4ce8e825c145d74e6b9827f972629548e39f118 Mon Sep 17 00:00:00 2001
From: Jin Ma 
Date: Wed, 11 Jan 2023 19:13:27 +0800
Subject: [PATCH] [RISCV] Add 'Zfa' extension according to riscv-isa-manual

This patch adds the 'Zfa' extension for riscv, which is an implementation for
unratified and unfrozen RISC-V extension.

Although the binutils-gdb for 'Zfa' extension is not yet upstream, we can try
to discuss it. And we can test new instructions for your (possibly virtual)
environment and early review for fast adoption after ratification.

This is based on:
( 
https://github.com/riscv/riscv-isa-manual/commit/d74d99e22d5f68832f70982d867614e2149a3bd7
 )
latest 'Zfa' change on the master branch of the RISC-V ISA Manual as
of this writing.

The Wiki Page (details):
( https://github.com/a4lg/binutils-gdb/wiki/riscv_zfa ）

The binutils-gdb for 'Zfa' extension:
( https://sourceware.org/pipermail/binutils/2022-September/122938.html )

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc:
* config/riscv/constraints.md (Zf):
* config/riscv/predicates.md:
* config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2):
(AVAIL):
(RISCV_ATYPE_SF):
(RISCV_ATYPE_DF):
(RISCV_FTYPE_ATYPES2):
* config/riscv/riscv-ftypes.def (2):
* config/riscv/riscv-opts.h (MASK_ZFA):
(TARGET_ZFA):
* config/riscv/riscv-protos.h (riscv_float_const_rtx_index_for_fli):
* config/riscv/riscv.cc (riscv_float_const_rtx_index_for_fli):
(riscv_cannot_force_const_mem):
(riscv_const_insns):
(riscv_legitimize_const_move):
(riscv_split_64bit_move_p):
(riscv_output_move):
(riscv_memmodel_needs_release_fence):
(riscv_print_operand):
(riscv_secondary_memory_needed):
* config/riscv/riscv.h (GP_REG_RTX_P):
* config/riscv/riscv.md (riscv_fminm3):
(riscv_fmaxm3):
(fix_truncdfsi2_zfa):
(round2):
(rint2):
(f_quiet4_zfa):
* config/riscv/riscv.opt:

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zfa-fcvtmod.c: New test.
* gcc.target/riscv/zfa-fleq-fltq.c: New test.
* gcc.target/riscv/zfa-fli-zfh.c: New test.
* gcc.target/riscv/zfa-fli.c: New test.
* gcc.target/riscv/zfa-fminm-fmaxm.c: New test.
* gcc.target/riscv/zfa-fmovh-fmovp.c: New test.
* gcc.target/riscv/zfa-fround.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc   |   4 +
 gcc/config/riscv/constraints.md   |   7 ++
 gcc/config/riscv/predicates.md|   4 +
 gcc/config/riscv/riscv-builtins.cc|  11 ++
 gcc/config/riscv/riscv-ftypes.def |   2 +
 gcc/config/riscv/riscv-opts.h |   3 +
 gcc/config/riscv/riscv-protos.h   |   1 +
 gcc/config/riscv/riscv.cc | 105 +++-
 gcc/config/riscv/riscv.h  |   1 +
 gcc/config/riscv/riscv.md | 114 ++
 gcc/config/riscv/riscv.opt|   4 +
 gcc/testsuite/gcc.target/riscv/zfa-fcvtmod.c  |  12 ++
 .../gcc.target/riscv/zfa-fleq-fltq.c  |  20 +++
 gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c  |  42 +++
 gcc/testsuite/gcc.target/riscv/zfa-fli.c  |  80 
 .../gcc.target/riscv/zfa-fminm-fmaxm.c|  25 
 .../gcc.target/riscv/zfa-fmovh-fmovp.c|  11 ++
 gcc/testsuite/gcc.target/riscv/zfa-fround.c   |  25 
 18 files changed, 448 insertions(+), 23 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fcvtmod.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fleq-fltq.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fminm-fmaxm.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fround.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 0a89fdaffe2..cccec12975c 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -217,6 +217,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zfhmin",ISA_SPEC_CLASS_NONE, 1, 0},

+  {"zfa", ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},

   {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1242,6 +1244,8 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zfhmin",&gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
   {"zfh",   &gcc_options::x_riscv_zf_subext, MASK_ZFH},

+  {"zfa",   &gcc_options::x_riscv_zf_subext,

Re: [PATCH v2] [RISCV] Add 'Zfa' extension according to riscv-isa-manual

2023-01-11 Thread jinma via Gcc-patches 
From e4ce8e825c145d74e6b9827f972629548e39f118 Mon Sep 17 00:00:00 2001
From: Jin Ma 
Date: Wed, 11 Jan 2023 19:13:27 +0800
Subject: [PATCH] [RISCV] Add 'Zfa' extension according to riscv-isa-manual
This patch adds the 'Zfa' extension for riscv, which is based on:
( 
https://github.com/riscv/riscv-isa-manual/commit/d74d99e22d5f68832f70982d867614e2149a3bd7
 )
latest 'Zfa' change on the master branch of the RISC-V ISA Manual as
of this writing.
The Wiki Page (details):
( https://github.com/a4lg/binutils-gdb/wiki/riscv_zfa ）
The binutils-gdb for 'Zfa' extension:
( https://sourceware.org/pipermail/binutils/2022-September/122938.html )
gcc/ChangeLog:
 * common/config/riscv/riscv-common.cc:
 * config/riscv/constraints.md (Zf):
 * config/riscv/predicates.md:
 * config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2):
 (AVAIL):
 (RISCV_ATYPE_SF):
 (RISCV_ATYPE_DF):
 (RISCV_FTYPE_ATYPES2):
 * config/riscv/riscv-ftypes.def (2):
 * config/riscv/riscv-opts.h (MASK_ZFA):
 (TARGET_ZFA):
 * config/riscv/riscv-protos.h (riscv_float_const_rtx_index_for_fli):
 * config/riscv/riscv.cc (riscv_float_const_rtx_index_for_fli):
 (riscv_cannot_force_const_mem):
 (riscv_const_insns):
 (riscv_legitimize_const_move):
 (riscv_split_64bit_move_p):
 (riscv_output_move):
 (riscv_memmodel_needs_release_fence):
 (riscv_print_operand):
 (riscv_secondary_memory_needed):
 * config/riscv/riscv.h (GP_REG_RTX_P):
 * config/riscv/riscv.md (riscv_fminm3):
 (riscv_fmaxm3):
 (fix_truncdfsi2_zfa):
 (round2):
 (rint2):
 (f_quiet4_zfa):
 * config/riscv/riscv.opt:
gcc/testsuite/ChangeLog:
 * gcc.target/riscv/zfa-fcvtmod.c: New test.
 * gcc.target/riscv/zfa-fleq-fltq.c: New test.
 * gcc.target/riscv/zfa-fli-zfh.c: New test.
 * gcc.target/riscv/zfa-fli.c: New test.
 * gcc.target/riscv/zfa-fminm-fmaxm.c: New test.
 * gcc.target/riscv/zfa-fmovh-fmovp.c: New test.
 * gcc.target/riscv/zfa-fround.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc | 4 +
 gcc/config/riscv/constraints.md | 7 ++
 gcc/config/riscv/predicates.md | 4 +
 gcc/config/riscv/riscv-builtins.cc | 11 ++
 gcc/config/riscv/riscv-ftypes.def | 2 +
 gcc/config/riscv/riscv-opts.h | 3 +
 gcc/config/riscv/riscv-protos.h | 1 +
 gcc/config/riscv/riscv.cc | 105 +++-
 gcc/config/riscv/riscv.h | 1 +
 gcc/config/riscv/riscv.md | 114 ++
 gcc/config/riscv/riscv.opt | 4 +
 gcc/testsuite/gcc.target/riscv/zfa-fcvtmod.c | 12 ++
 .../gcc.target/riscv/zfa-fleq-fltq.c | 20 +++
 gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c | 42 +++
 gcc/testsuite/gcc.target/riscv/zfa-fli.c | 80 
 .../gcc.target/riscv/zfa-fminm-fmaxm.c | 25 
 .../gcc.target/riscv/zfa-fmovh-fmovp.c | 11 ++
 gcc/testsuite/gcc.target/riscv/zfa-fround.c | 25 
 18 files changed, 448 insertions(+), 23 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fcvtmod.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fleq-fltq.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fminm-fmaxm.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fround.c
diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 0a89fdaffe2..cccec12975c 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -217,6 +217,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 {"zfh", ISA_SPEC_CLASS_NONE, 1, 0},
 {"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zfa", ISA_SPEC_CLASS_NONE, 1, 0},
+
 {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
 {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1242,6 +1244,8 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 {"zfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
 {"zfh", &gcc_options::x_riscv_zf_subext, MASK_ZFH},
+ {"zfa", &gcc_options::x_riscv_zf_subext, MASK_ZFA},
+
 {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
 {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL},
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 51cffb2bcb6..2fd407b1d9c 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -110,6 +110,13 @@ (define_constraint "T"
 (and (match_operand 0 "move_operand")
 (match_test "CONSTANT_P (op)")))
+;; Zfa constraints.
+
+(define_constraint "Zf"
+ "A floating point number that can be loaded using instruction `fli` in zfa."
+ (and (match_code "const_double")
+ (match_test "(riscv_float_const_rtx_index_for_fli (op) != -1)")))
+
 ;; Vector constraints.
 (define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS"
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 5a5a49bf7c0..0e8cf3b3708 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -149,6 +149,10 @@ (define_predicate "move_operand"
 case CONST_PO

Re: [PATCH v2] [RISCV] Add 'Zfa' extension according to riscv-isa-manual

2023-01-11 Thread jinma via Gcc-patches 
From 4ee11f99d23d39d55bdadd86699ac35a60c79705 Mon Sep 17 00:00:00 2001
From: Jin Ma 
Date: Thu, 12 Jan 2023 12:51:37 +0800
Subject: [PATCH v2] [RISCV] Add 'Zfa' extension according to riscv-isa-manual
This patch adds the 'Zfa' extension for riscv, which is based on:
( 
https://github.com/riscv/riscv-isa-manual/commit/d74d99e22d5f68832f70982d867614e2149a3bd7
 )
latest 'Zfa' change on the master branch of the RISC-V ISA Manual as
of this writing.
The Wiki Page (details):
( https://github.com/a4lg/binutils-gdb/wiki/riscv_zfa )
The binutils-gdb for 'Zfa' extension:
( https://sourceware.org/pipermail/binutils/2022-September/122938.html )
gcc/ChangeLog:
 * common/config/riscv/riscv-common.cc:
 * config/riscv/constraints.md (Zf):
 * config/riscv/predicates.md:
 * config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2):
 (AVAIL):
 (RISCV_ATYPE_SF):
 (RISCV_ATYPE_DF):
 (RISCV_FTYPE_ATYPES2):
 * config/riscv/riscv-ftypes.def (2):
 * config/riscv/riscv-opts.h (MASK_ZFA):
 (TARGET_ZFA):
 * config/riscv/riscv-protos.h (riscv_float_const_rtx_index_for_fli):
 * config/riscv/riscv.cc (riscv_float_const_rtx_index_for_fli):
 (riscv_cannot_force_const_mem):
 (riscv_const_insns):
 (riscv_legitimize_const_move):
 (riscv_split_64bit_move_p):
 (riscv_output_move):
 (riscv_memmodel_needs_release_fence):
 (riscv_print_operand):
 (riscv_secondary_memory_needed):
 * config/riscv/riscv.h (GP_REG_RTX_P):
 * config/riscv/riscv.md (riscv_fminm3):
 (riscv_fmaxm3):
 (fix_truncdfsi2_zfa):
 (round2):
 (rint2):
 (f_quiet4_zfa):
 * config/riscv/riscv.opt:
gcc/testsuite/ChangeLog:
 * gcc.target/riscv/zfa-fcvtmod.c: New test.
 * gcc.target/riscv/zfa-fleq-fltq.c: New test.
 * gcc.target/riscv/zfa-fli-zfh.c: New test.
 * gcc.target/riscv/zfa-fli.c: New test.
 * gcc.target/riscv/zfa-fminm-fmaxm.c: New test.
 * gcc.target/riscv/zfa-fmovh-fmovp.c: New test.
 * gcc.target/riscv/zfa-fround.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc | 4 +
 gcc/config/riscv/constraints.md | 7 ++
 gcc/config/riscv/predicates.md | 4 +
 gcc/config/riscv/riscv-builtins.cc | 11 ++
 gcc/config/riscv/riscv-ftypes.def | 2 +
 gcc/config/riscv/riscv-opts.h | 3 +
 gcc/config/riscv/riscv-protos.h | 1 +
 gcc/config/riscv/riscv.cc | 109 -
 gcc/config/riscv/riscv.h | 1 +
 gcc/config/riscv/riscv.md | 114 ++
 gcc/config/riscv/riscv.opt | 4 +
 gcc/testsuite/gcc.target/riscv/zfa-fcvtmod.c | 12 ++
 .../gcc.target/riscv/zfa-fleq-fltq.c | 20 +++
 gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c | 42 +++
 gcc/testsuite/gcc.target/riscv/zfa-fli.c | 80 
 .../gcc.target/riscv/zfa-fminm-fmaxm.c | 25 
 .../gcc.target/riscv/zfa-fmovh-fmovp.c | 11 ++
 gcc/testsuite/gcc.target/riscv/zfa-fround.c | 25 
 18 files changed, 452 insertions(+), 23 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fcvtmod.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fleq-fltq.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fminm-fmaxm.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fround.c
diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 0a89fdaffe2..cccec12975c 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -217,6 +217,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 {"zfh", ISA_SPEC_CLASS_NONE, 1, 0},
 {"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zfa", ISA_SPEC_CLASS_NONE, 1, 0},
+
 {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
 {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1242,6 +1244,8 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 {"zfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
 {"zfh", &gcc_options::x_riscv_zf_subext, MASK_ZFH},
+ {"zfa", &gcc_options::x_riscv_zf_subext, MASK_ZFA},
+
 {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
 {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL},
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 51cffb2bcb6..2fd407b1d9c 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -110,6 +110,13 @@ (define_constraint "T"
 (and (match_operand 0 "move_operand")
 (match_test "CONSTANT_P (op)")))
+;; Zfa constraints.
+
+(define_constraint "Zf"
+ "A floating point number that can be loaded using instruction `fli` in zfa."
+ (and (match_code "const_double")
+ (match_test "(riscv_float_const_rtx_index_for_fli (op) != -1)")))
+
 ;; Vector constraints.
 (define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS"
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 5a5a49bf7c0..0e8cf3b3708 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -149,6 +149,10 @@ (define_predicate "move_operand"
 case CONS

Re: [PATCH v2] [RISCV] Add 'Zfa' extension according to riscv-isa-manual

2023-01-11 Thread jinma via Gcc-patches 
I am very sorry. There seems to be some unknown problems in my email, which
caused a problem with the format of the patch. I will deal with it as soon as 
possible. 
I am very sorry for the trouble.

[PATCH v3] [RISCV] Add 'Zfa' extension according to riscv-isa-manual

2023-01-11 Thread jinma via Gcc-patches 
From 4ee11f99d23d39d55bdadd86699ac35a60c79705 Mon Sep 17 00:00:00 2001
In-Reply-To: <77a18666-f71d-48e2-a502-a879b3eb6ccf.ji...@linux.alibaba.com>
References: <77a18666-f71d-48e2-a502-a879b3eb6ccf.ji...@linux.alibaba.com>
From: Jin Ma 
Date: Thu, 12 Jan 2023 12:51:37 +0800
Subject: [PATCH v3] [RISCV] Add 'Zfa' extension according to riscv-isa-manual
This patch adds the 'Zfa' extension for riscv, which is based on:
( 
https://github.com/riscv/riscv-isa-manual/commit/d74d99e22d5f68832f70982d867614e2149a3bd7
 )
latest 'Zfa' change on the master branch of the RISC-V ISA Manual as
of this writing.
The Wiki Page (details):
( https://github.com/a4lg/binutils-gdb/wiki/riscv_zfa )
The binutils-gdb for 'Zfa' extension:
( https://sourceware.org/pipermail/binutils/2022-September/122938.html )
gcc/ChangeLog:
 * common/config/riscv/riscv-common.cc:
 * config/riscv/constraints.md (Zf):
 * config/riscv/predicates.md:
 * config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2):
 (AVAIL):
 (RISCV_ATYPE_SF):
 (RISCV_ATYPE_DF):
 (RISCV_FTYPE_ATYPES2):
 * config/riscv/riscv-ftypes.def (2):
 * config/riscv/riscv-opts.h (MASK_ZFA):
 (TARGET_ZFA):
 * config/riscv/riscv-protos.h (riscv_float_const_rtx_index_for_fli):
 * config/riscv/riscv.cc (riscv_float_const_rtx_index_for_fli):
 (riscv_cannot_force_const_mem):
 (riscv_const_insns):
 (riscv_legitimize_const_move):
 (riscv_split_64bit_move_p):
 (riscv_output_move):
 (riscv_memmodel_needs_release_fence):
 (riscv_print_operand):
 (riscv_secondary_memory_needed):
 * config/riscv/riscv.h (GP_REG_RTX_P):
 * config/riscv/riscv.md (riscv_fminm3):
 (riscv_fmaxm3):
 (fix_truncdfsi2_zfa):
 (round2):
 (rint2):
 (f_quiet4_zfa):
 * config/riscv/riscv.opt:
gcc/testsuite/ChangeLog:
 * gcc.target/riscv/zfa-fcvtmod.c: New test.
 * gcc.target/riscv/zfa-fleq-fltq.c: New test.
 * gcc.target/riscv/zfa-fli-zfh.c: New test.
 * gcc.target/riscv/zfa-fli.c: New test.
 * gcc.target/riscv/zfa-fminm-fmaxm.c: New test.
 * gcc.target/riscv/zfa-fmovh-fmovp.c: New test.
 * gcc.target/riscv/zfa-fround.c: New test.
---
 gcc/common/config/riscv/riscv-common.cc | 4 +
 gcc/config/riscv/constraints.md | 7 ++
 gcc/config/riscv/predicates.md | 4 +
 gcc/config/riscv/riscv-builtins.cc | 11 ++
 gcc/config/riscv/riscv-ftypes.def | 2 +
 gcc/config/riscv/riscv-opts.h | 3 +
 gcc/config/riscv/riscv-protos.h | 1 +
 gcc/config/riscv/riscv.cc | 109 -
 gcc/config/riscv/riscv.h | 1 +
 gcc/config/riscv/riscv.md | 114 ++
 gcc/config/riscv/riscv.opt | 4 +
 gcc/testsuite/gcc.target/riscv/zfa-fcvtmod.c | 12 ++
 .../gcc.target/riscv/zfa-fleq-fltq.c | 20 +++
 gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c | 42 +++
 gcc/testsuite/gcc.target/riscv/zfa-fli.c | 80 
 .../gcc.target/riscv/zfa-fminm-fmaxm.c | 25 
 .../gcc.target/riscv/zfa-fmovh-fmovp.c | 11 ++
 gcc/testsuite/gcc.target/riscv/zfa-fround.c | 25 
 18 files changed, 452 insertions(+), 23 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fcvtmod.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fleq-fltq.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fminm-fmaxm.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fround.c
diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 0a89fdaffe2..cccec12975c 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -217,6 +217,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 {"zfh", ISA_SPEC_CLASS_NONE, 1, 0},
 {"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zfa", ISA_SPEC_CLASS_NONE, 1, 0},
+
 {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
 {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1242,6 +1244,8 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 {"zfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
 {"zfh", &gcc_options::x_riscv_zf_subext, MASK_ZFH},
+ {"zfa", &gcc_options::x_riscv_zf_subext, MASK_ZFA},
+
 {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
 {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL},
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 51cffb2bcb6..2fd407b1d9c 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -110,6 +110,13 @@ (define_constraint "T"
 (and (match_operand 0 "move_operand")
 (match_test "CONSTANT_P (op)")))
+;; Zfa constraints.
+
+(define_constraint "Zf"
+ "A floating point number that can be loaded using instruction `fli` in zfa."
+ (and (match_code "const_double")
+ (match_test "(riscv_float_const_rtx_index_for_fli (op) != -1)")))
+
 ;; Vector constraints.
 (define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS"
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 5a5a49bf7c0..0e8cf3

Re: [PATCH v8] RISC-V: Add the 'zfa' extension, version 0.2.

2023-05-06 Thread jinma via Gcc-patches 
> > > diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
> > > index 9b767038452..c81b08e3cc5 100644
> > > --- a/gcc/config/riscv/iterators.md
> > > +++ b/gcc/config/riscv/iterators.md
> > > @@ -288,3 +288,8 @@ (define_int_iterator QUIET_COMPARISON 
> > > [UNSPEC_FLT_QUIET UNSPEC_FLE_QUIET])
> > >   (define_int_attr quiet_pattern [(UNSPEC_FLT_QUIET "lt") 
> > > (UNSPEC_FLE_QUIET "le")])
> > >   (define_int_attr QUIET_PATTERN [(UNSPEC_FLT_QUIET "LT") 
> > > (UNSPEC_FLE_QUIET "LE")])
> > >   
> > > +(define_int_iterator ROUND [UNSPEC_ROUND UNSPEC_FLOOR UNSPEC_CEIL 
> > > UNSPEC_BTRUNC UNSPEC_ROUNDEVEN UNSPEC_NEARBYINT])
> > > +(define_int_attr round_pattern [(UNSPEC_ROUND "round") (UNSPEC_FLOOR 
> > > "floor") (UNSPEC_CEIL "ceil")
> > > + (UNSPEC_BTRUNC "btrunc") (UNSPEC_ROUNDEVEN 
> > > "roundeven") (UNSPEC_NEARBYINT "nearbyint")])
> > > +(define_int_attr round_rm [(UNSPEC_ROUND "rmm") (UNSPEC_FLOOR "rdn") 
> > > (UNSPEC_CEIL "rup")
> > > +(UNSPEC_BTRUNC "rtz") (UNSPEC_ROUNDEVEN "rne") 
> > > (UNSPEC_NEARBYINT "dyn")])
> > Do we really need to use unspecs for all these cases?  I would expect 
> > some correspond to the trunc, round, ceil, nearbyint, etc well known RTX 
> > codes.
> > 
> > In general, we should try to avoid unspecs when there is a clear 
> > semantic match between the instruction and GCC's RTX opcodes.  So please 
> > review the existing RTX code semantics to see if any match the new 
> > instructions.  If there are matches, use those RTX codes rather than 
> > UNSPECs.
> 
> I'll try, thanks.


I encountered some confusion about this. I checked gcc's documents and
found no RTX codes that can correspond to round, ceil, nearbyint, etc.
Only "(fix:m x)" seems to correspond to trunc, which can be expressed
as rounding towards zero, while others have not yet been found.


In addition, I found that other architectures also seem to adopt the
unspecs for all these cases  on the latest master branch.
arm: 
https://github.com/gcc-mirror/gcc/commit/1dd4fe1fd892458ce29f15f3ca95125a11b2534f#diff-159a39276c509272adfaeef91c2110f54f65c38f7fd1ab2f1e750af0a7f86377R1251
rs6000: 
https://github.com/gcc-mirror/gcc/commit/7042fe5ef83ff0585eb91144817105f26d566d4c#diff-1a2d4976d867ead4556899cab1dbb39f5069574276e06a2976fb62b771ece2e3R6995
i386: 
https://github.com/gcc-mirror/gcc/commit/3e8c4b925a9825fdb8c81f47b621f63108894362#diff-f00b14a8846eb6aaeb981077e36ac3668160d7dabb490beeb1f62792afa83281R23332

Can you give me some advice?

> > > @@ -1580,6 +1609,26 @@ (define_insn 
> > > "l2"
> > > [(set_attr "type" "fcvt")
> > >  (set_attr "mode" "")])
> > >   
> > > +(define_insn "2"
> > > +  [(set (match_operand:ANYF 0 "register_operand" "=f")
> > > + (unspec:ANYF
> > > + [(match_operand:ANYF 1 "register_operand" " f")]
> > > + ROUND))]
> > > +  "TARGET_HARD_FLOAT && TARGET_ZFA"
> > > +  "fround.\t%0,%1,"
> > > +  [(set_attr "type" "fcvt")
> > > +   (set_attr "mode" "")])
> > > +
> > > +(define_insn "rint2"
> > > +  [(set (match_operand:ANYF 0 "register_operand" "=f")
> > > + (unspec:ANYF
> > > + [(match_operand:ANYF 1 "register_operand" " f")]
> > > + UNSPEC_RINT))]
> > > +  "TARGET_HARD_FLOAT && TARGET_ZFA"
> > > +  "froundnx.\t%0,%1"
> > > +  [(set_attr "type" "fcvt")
> > > +   (set_attr "mode" "")])
> > Please review the existing RTX codes and their semantics in the 
> > internals manual and if any of the new instructions match those existing 
> > primitives, implement them using those RTX codes rather than with an UNSPEC.
> >
> 
> I'll try, thanks.
> 

thanks.

Jin Ma

Re: [PATCH v6] RISC-V: Add support for experimental zfa extension.

2023-04-13 Thread jinma via Gcc-patches 
Thank you very much for your comments. Since a long time has passed and this is 
an initial version, I will update this patch.
--
From:Christoph Müllner 
Sent At:2023 Apr. 13 (Thu.) 17:22
To:Jin Ma 
Cc:gcc-patches ; kito.cheng ; 
kito.cheng ; palmer 
Subject:Re: [PATCH v6] RISC-V: Add support for experimental zfa extension.
On Fri, Mar 10, 2023 at 1:41 PM Jin Ma via Gcc-patches
 wrote:
>
> This patch adds the 'Zfa' extension for riscv, which is based on:
> https://github.com/riscv/riscv-isa-manual/commit/d74d99e22d5f68832f70982d867614e2149a3bd7
> latest 'Zfa' change on the master branch of the RISC-V ISA Manual as
> of this writing.
>
> The Wiki Page (details):
> https://github.com/a4lg/binutils-gdb/wiki/riscv_zfa
>
> The binutils-gdb for 'Zfa' extension:
> https://sourceware.org/pipermail/binutils/2022-September/122938.html
>
> Implementation of zfa extension on LLVM:
> https://reviews.llvm.org/rGc0947dc44109252fcc0f68a542fc6ef250d4d3a9
>
> There are three points that need to be discussed here.
> 1. According to riscv-spec, "The FCVTMO D.W.D instruction was added 
> principally to
> accelerate the processing of JavaScript Numbers.", so it seems that no 
> implementation
> is required in the compiler.
> 2. The FROUND and FROUNDN instructions in this patch use related functions in 
> the math
> library, such as round, floor, ceil, etc. Since there is no interface for 
> half-precision in
> the math library, the instructions FROUN D.H and FROUNDN X.H have not been 
> implemented for
> the time being. Is it necessary to add a built-in interface belonging to 
> riscv such as
> __builtin_roundhf or __builtin_roundf16 to generate half floating point 
> instructions?
> 3. As far as I know, FMINM and FMAXM instructions correspond to C23 library 
> function fminimum
> and fmaximum. Therefore, I have not dealt with such instructions for the time 
> being, but have
> simply implemented the pattern of fminm3 and fmaxm3. Is 
> it necessary to
> add a built-in interface belonging to riscv such as__builtin_fminm to 
> generate half
> floating-point instructions?
I have rebased and tested this patch.
Here are my observations (with fixes below at the actual code):
* There is a compiler warning because of a missing "fallthrough" comment
* There are merge conflicts with a current master
* The constant operand of the fli instruction uses the constant index
in the rs1-field, but not the constant in hex FP literal form
A patch that addresses these issues can also be found here:
 https://github.com/cmuellner/gcc/tree/riscv-zfa
Additionally I observe the following failing test cases with this patch applied:
 === gcc: Unexpected fails for rv64gc lp64d medlow ===
FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O0 (internal compiler
error: Segmentation fault)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O0 (test for excess errors)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O1 (internal compiler
error: Segmentation fault)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O1 (test for excess errors)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O2 (internal compiler
error: Segmentation fault)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O2 (test for excess errors)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O2 -flto
-fno-use-linker-plugin -flto-partition=none (internal compiler error:
Segmentation fault)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O2 -flto
-fno-use-linker-plugin -flto-partition=none (test for excess errors)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects (internal compiler error:
Segmentation fault)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O2 -flto
-fuse-linker-plugin -fno-fat-lto-objects (test for excess errors)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O3 -g (internal
compiler error: Segmentation fault)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O3 -g (test for excess errors)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c -Os (internal compiler
error: Segmentation fault)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c -Os (test for excess errors)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c -Og -g (internal
compiler error: Segmentation fault)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c -Og -g (test for excess errors)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c -Oz (internal compiler
error: Segmentation fault)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c -Oz (test for excess errors)
I have not analysed these ICEs so far.
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc: Add zfa extension.
> * config/riscv/constraints.md (Zf): Constrain the floating point number that 
> the FLI instruction can load.
> * config/riscv/iterators.md (round_pattern): New.
> * config/riscv/predicates.md: Predicate the floating point number that the 
> FLI instruction can load.
> * config/riscv/riscv-opts.h (MASK_ZFA): New.
> (TARGET_ZFA): New.
> * config/riscv/riscv-protos.h (riscv_float_const_rtx_index_for