[PATCH] RISC-V: Fix uninitialized and redundant use of which_alternative

2023-07-27 Thread demin . han 
When pass split2 starts, which_alternative is random depending on
last set of certain pass.

Even initialized, the generated movement is redundant.
The movement can be generated by assembly output template.

Signed-off-by: demin.han 

gcc/ChangeLog:

* config/riscv/autovec.md: Delete which_alternative use in split

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/madd-split2-1.c: New test.

---
 gcc/config/riscv/autovec.md | 12 
 .../gcc.target/riscv/rvv/autovec/madd-split2-1.c| 13 +
 2 files changed, 13 insertions(+), 12 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index d899922586a..b7ea3101f5a 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1012,8 +1012,6 @@ (define_insn_and_split "*fma"
   [(const_int 0)]
   {
 riscv_vector::emit_vlmax_vsetvl (mode, operands[4]);
-if (which_alternative == 2)
-  emit_insn (gen_rtx_SET (operands[0], operands[3]));
 rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
operands[0]};
 riscv_vector::emit_vlmax_ternary_insn (code_for_pred_mul_plus 
(mode),
   riscv_vector::RVV_TERNOP, ops, 
operands[4]);
@@ -1058,8 +1056,6 @@ (define_insn_and_split "*fnma"
   [(const_int 0)]
   {
 riscv_vector::emit_vlmax_vsetvl (mode, operands[4]);
-if (which_alternative == 2)
-  emit_insn (gen_rtx_SET (operands[0], operands[3]));
 rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
operands[0]};
 riscv_vector::emit_vlmax_ternary_insn (code_for_pred_minus_mul 
(mode),
   riscv_vector::RVV_TERNOP, ops, 
operands[4]);
@@ -1102,8 +1098,6 @@ (define_insn_and_split "*fma"
   [(const_int 0)]
   {
 riscv_vector::emit_vlmax_vsetvl (mode, operands[4]);
-if (which_alternative == 2)
-  emit_insn (gen_rtx_SET (operands[0], operands[3]));
 rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
operands[0]};
 riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul (PLUS, 
mode),
  riscv_vector::RVV_TERNOP, ops, 
operands[4]);
@@ -1148,8 +1142,6 @@ (define_insn_and_split "*fnma"
   [(const_int 0)]
   {
 riscv_vector::emit_vlmax_vsetvl (mode, operands[4]);
-if (which_alternative == 2)
-  emit_insn (gen_rtx_SET (operands[0], operands[3]));
 rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
operands[0]};
 riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul_neg (PLUS, 
mode),
  riscv_vector::RVV_TERNOP, ops, 
operands[4]);
@@ -1194,8 +1186,6 @@ (define_insn_and_split "*fms"
   [(const_int 0)]
   {
 riscv_vector::emit_vlmax_vsetvl (mode, operands[4]);
-if (which_alternative == 2)
-  emit_insn (gen_rtx_SET (operands[0], operands[3]));
 rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
operands[0]};
 riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul (MINUS, 
mode),
  riscv_vector::RVV_TERNOP, ops, 
operands[4]);
@@ -1242,8 +1232,6 @@ (define_insn_and_split "*fnms"
   [(const_int 0)]
   {
 riscv_vector::emit_vlmax_vsetvl (mode, operands[4]);
-if (which_alternative == 2)
-  emit_insn (gen_rtx_SET (operands[0], operands[3]));
 rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
operands[0]};
 riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul_neg (MINUS, 
mode),
  riscv_vector::RVV_TERNOP, ops, 
operands[4]);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c
new file mode 100644
index 000..14a9802667e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl256b -O3 -fno-cprop-registers -fno-dce 
--param riscv-autovec-preference=scalable" } */
+
+long
+foo (long *__restrict a, long *__restrict b, long n)
+{
+  long i;
+  for (i = 0; i < n; ++i)
+a[i] = b[i] + i * 8;
+  return a[1];
+}
+
+/* { dg-final { scan-assembler-times {\tvmv1r\.v} 1 } } */
-- 
2.41.0

Re: [PATCH] RISC-V: Fix uninitialized and redundant use of which_alternative

2023-07-27 Thread Demin Han 
Sorry for not consider rv32 config.
The fix is OK. If convenient, please commit it.

On 2023/7/28 4:46, Patrick O'Neill wrote:
> The newly added testcase fails on rv32 targets with this message:
> FAIL: gcc.target/riscv/rvv/autovec/madd-split2-1.c -O3 -ftree-vectorize (test 
> for excess errors)
> 
> verbose log:
> compiler exited with status 1
> output is:
> cc1: error: ABI requires '-march=rv32'
> 
> Something like this appears to fix the issue:
> 
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c
> index 14a9802667e..e10a9e9d0f5 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c
> @@ -1,5 +1,5 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gcv_zvl256b -O3 -fno-cprop-registers -fno-dce 
> --param riscv-autovec-preference=scalable" } */
> +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3
> -fno-cprop-registers -fno-dce --param riscv-autovec-preference=scalable"
>  } */
>  
>  long
>  foo (long *__restrict a, long *__restrict b, long n)
> 
> On 7/27/23 04:57, Kito Cheng via Gcc-patches wrote:
> 
>> My first impression is those emit_insn (gen_rtx_SET()) seems
>> necessary, but I got the point after I checked vector.md :P
>>
>> Committed to trunk, thanks :)
>>
>>
>> On Thu, Jul 27, 2023 at 6:23 pmjuzhe.zh...@rivai.ai
>>   wrote:
>>> Oh, YES.
>>>
>>> Thanks for fixing it. It makes sense since the ternary operations in 
>>> "vector.md"
>>> generate "vmv.v.v" according to RA.
>>>
>>> Thanks for fixing it.
>>>
>>> @kito: Could you confirm it? If it's ok to you, commit it for Han (I am 
>>> lazy to commit patches :).
>>>
>>>
>>>
>>> juzhe.zh...@rivai.ai
>>>
>>> From: demin.han
>>> Date: 2023-07-27 17:48
>>> To:gcc-patches@gcc.gnu.org
>>> CC:kito.ch...@gmail.com;juzhe.zh...@rivai.ai
>>> Subject: [PATCH] RISC-V: Fix uninitialized and redundant use of 
>>> which_alternative
>>> When pass split2 starts, which_alternative is random depending on
>>> last set of certain pass.
>>>
>>> Even initialized, the generated movement is redundant.
>>> The movement can be generated by assembly output template.
>>>
>>> Signed-off-by: demin.han
>>>
>>> gcc/ChangeLog:
>>>
>>> * config/riscv/autovec.md: Delete which_alternative use in split
>>>
>>> gcc/testsuite/ChangeLog:
>>>
>>> * gcc.target/riscv/rvv/autovec/madd-split2-1.c: New test.
>>>
>>> ---
>>> gcc/config/riscv/autovec.md | 12 
>>> .../gcc.target/riscv/rvv/autovec/madd-split2-1.c    | 13 +
>>> 2 files changed, 13 insertions(+), 12 deletions(-)
>>> create mode 100644 
>>> gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c
>>>
>>> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
>>> index d899922586a..b7ea3101f5a 100644
>>> --- a/gcc/config/riscv/autovec.md
>>> +++ b/gcc/config/riscv/autovec.md
>>> @@ -1012,8 +1012,6 @@ (define_insn_and_split "*fma"
>>>     [(const_int 0)]
>>>     {
>>>   riscv_vector::emit_vlmax_vsetvl (mode, operands[4]);
>>> -    if (which_alternative == 2)
>>> -  emit_insn (gen_rtx_SET (operands[0], operands[3]));
>>>   rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
>>> operands[0]};
>>>   riscv_vector::emit_vlmax_ternary_insn (code_for_pred_mul_plus 
>>> (mode),
>>>     riscv_vector::RVV_TERNOP, ops, operands[4]);
>>> @@ -1058,8 +1056,6 @@ (define_insn_and_split "*fnma"
>>>     [(const_int 0)]
>>>     {
>>>   riscv_vector::emit_vlmax_vsetvl (mode, operands[4]);
>>> -    if (which_alternative == 2)
>>> -  emit_insn (gen_rtx_SET (operands[0], operands[3]));
>>>   rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
>>> operands[0]};
>>>   riscv_vector::emit_vlmax_ternary_insn (code_for_pred_minus_mul 
>>> (mode),
>>>  riscv_vector::RVV_TERNOP, ops, operands[4]);
>>> @@ -1102,8 +1098,6 @@ (define_insn_and_split "*fma"
>>>     [(const_int 0)]
>>>     {
>>>   riscv_vector::emit_vlmax_vsetvl (mode, operands[4]);
>>> -    if (which_alternative == 2)
>>> -  emit_insn (gen_rtx_SET (operands[0], operands[3]));
>>>   rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
>>> operands[0]};
>>>   riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul (PLUS, 
>>> mode),
>>>    riscv_vector::RVV_TERNOP, ops, operands[4]);
>>> @@ -1148,8 +1142,6 @@ (define_insn_and_split "*fnma"
>>>     [(const_int 0)]
>>>     {
>>>   riscv_vector::emit_vlmax_vsetvl (mode, operands[4]);
>>> -    if (which_alternative == 2)
>>> -  emit_insn (gen_rtx_SET (operands[0], operands[3]));
>>>   rtx ops[] = {operands[0], operands[1], operands[2], operands[3], 
>>> operands[0]};
>>>   riscv_vector::emit_vlmax_fp_ternary_insn (code_for_pred_mul_neg 
>>> (PLUS, mode),
>>>    riscv_vector::RVV_TERNOP, ops, operands[4]);
>>> @@ -1194,8 +1186,6 @@ (define_insn_and_split "*fms"
>>>     [(const_int 0)]
>>>   

RE: [PATCH 0/5] RISC-V: Support vf and vx for autovec comparison of

2024-02-29 Thread Demin Han 
Sorry for the unexpected truncation.

Hi,
vf and vx are not supported well when comparing vector and
immediate in current autovec.
For example, following insts generated for float type:
flw
vsetvli
vfmv.v.f
...
vmfxx.vv
Two issues:
  1. Additional vsetvl and vfmv instructions
  2. Occupy one vector register and may results in smaller lmul

We expect:
flw
...
vmfxx.vf

For simplicity of supporting vx and vf, two refactors completed first.
1. remove eqne pattern; any special case or reason for eqne when first added?
2. refactor duplicate code.

RE: Re:[PATCH 1/5] RISC-V: Remove float vector eqne pattern

2024-03-01 Thread Demin Han 
Hi juzhe,

I also thought it’s related to commutive firstly.

Following things make me to do the removal:

1.  No tests fails in regression

2.  When I write if (a == 2) and if (2 == a), the results are same

3.  The vec_duplicate operand  is the 5th operand in both cmp and eqne 
patterns. I think they are equal.


From: 钟居哲 
Sent: 2024年3月1日 15:24
To: Demin Han ; gcc-patches 

Cc: kito.cheng ; Li, Pan2 ; 
jeffreyalaw ; Robin Dapp 
Subject: Re:[PATCH 1/5] RISC-V: Remove float vector eqne pattern

Hello, han.  Thanks for trying to optimize the codes.

But I believe those vector-scalar patterns (eq/ne) you remove in this patch are 
necessary.

This is the story:
1. For commutative RTL code in GCC like plus, eq, ne, ... etc,
we known in semantic Both (eq: (reg) (vec_duplicate ... ) and (eq: 
(vec_duplicate ... ) (reg)) are right.
However, GCC prefer this order as I remembered - (eq: (vec_duplicate ... ) 
(reg)).

2. Before this patch, the order of the comparison as follows (take eq and lt as 
an example):

1). (eq: (vec_duplicate ... ) (reg))  --> commutative
2). (lt: (reg) (vec_duplicate ... ) --> non-commutative

   These patterns order are different.

   So, you see we have dedicated patterns (seems duplicate patterns) for 
vector-scalar eq/ne, whereas, we unify eq/ne into other comparisons for 
vector-vector instructions.
   If we unify eq/ne into other comparisons for vector-scalar instructions 
(like your patch does), we will end up have:

   (eq: (reg) (vec_duplicate ... ) [after this patch] instead of (eq: 
(vec_duplicate ... ) (reg)) [Before this patch].

So, I think this patch may not be right.
I may be wrong, Robin/Jerff/kito feel free to correct me if I am wrong.


-- Original --
From:  
"demin.han"mailto:demin@starfivetech.com>>;
Date:  Fri, Mar 1, 2024 02:27 PM
To:  "gcc-patches"mailto:gcc-patches@gcc.gnu.org>>;
Cc:  "juzhe.zhong"mailto:juzhe.zh...@rivai.ai>>; 
"kito.cheng"mailto:kito.ch...@gmail.com>>; "Li, 
Pan2"mailto:pan2...@intel.com>>; 
"jeffreyalaw"mailto:jeffreya...@gmail.com>>;
Subject:  [PATCH 1/5] RISC-V: Remove float vector eqne pattern

We can unify eqne and other comparison operations.

Tested on RV32 and RV64

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-bases.cc: Remove eqne cond
* config/riscv/vector.md (@pred_eqne_scalar): Remove patterns
(*pred_eqne_scalar_merge_tie_mask): Ditto
(*pred_eqne_scalar): Ditto
(*pred_eqne_scalar_narrow): Ditto

Signed-off-by: demin.han 
mailto:demin@starfivetech.com>>
---
 .../riscv/riscv-vector-builtins-bases.cc  |  4 -
 gcc/config/riscv/vector.md| 86 ---
 2 files changed, 90 deletions(-)

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index b6f6e4ff37e..d414721ede8 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1420,10 +1420,6 @@ public:
 switch (e.op_info->op)
   {
  case OP_TYPE_vf: {
-   if (CODE == EQ || CODE == NE)
- return e.use_compare_insn (CODE, code_for_pred_eqne_scalar (
-e.vector_mode ()));
-   else
  return e.use_compare_insn (CODE, code_for_pred_cmp_scalar (
 e.vector_mode ()));
  }
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index ab6e099852d..9210d7c28ad 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7520,92 +7520,6 @@ (define_insn "*pred_cmp_scalar_narrow"
(set_attr "mode" "")
(set_attr "spec_restriction" "none,thv,thv,none,none")])

-(define_expand "@pred_eqne_scalar"
-  [(set (match_operand: 0 "register_operand")
- (if_then_else:
-   (unspec:
- [(match_operand: 1 "vector_mask_operand")
-  (match_operand 6 "vector_length_operand")
-  (match_operand 7 "const_int_operand")
-  (match_operand 8 "const_int_operand")
-  (reg:SI VL_REGNUM)
-  (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-   (match_operator: 3 "equality_operator"
-  [(vec_duplicate:V_VLSF
- (match_operand: 5 "register_operand"))
-   (match_operand:V_VLSF 4 "register_operand")])
-   (match_operand: 2 "vector_merge_operand")))]
-  "TARGET_VECTOR"
-  {})
-
-(define_insn "*pred_eqne_scalar_merge_tie_mask"
-  [(set (match_operand: 0 "register_operand"  "=vm")
- (if_then_else:
-   (unspec:
- [(match_operand: 1 "register_operand" "  0")
-  (match_operand 5 "vector_length_operand" " rK")
-  (match_operand 6 "const_int_operand" "  i")
-  (match_operand 7 "const_int_operand"

RE: Re:[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm

2024-03-01 Thread Demin Han 
Hi juzhe,

Yes, for comparison between vector and scalar variable, this patch is not work, 
because the scalar is duplicated in loop vectorize pass.
I have not found idea for this situation, so solve vector-imm comparison first.
Thanks for remind this, I will try that patch.

Thanks.

From: 钟居哲 
Sent: 2024年3月1日 15:49
To: Demin Han ; gcc-patches 

Cc: kito.cheng ; Li, Pan2 ; 
jeffreyalaw ; Robin Dapp ; 
richard.sandiford 
Subject: Re:[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec 
and imm

Hi, han. I understand you are trying to support optimize vector-splat_vector 
into vector-scalar in "expand" stage, that is,

vv -> vx or vv -> vf.

It's a known issue that we know for a long time.

This patch is trying to transform vv->vf when the splat vector is duplicate 
from a constant (by recognize it is a CONST_VECTOR in expand stage),
but can't transform vv->vf when splat vector is duplicate from a register.

For example, like a[i] = b[i] > x ? c[i] : d[i], the x is a register, this case 
can not be optimized with your patch.

Actually, we have a solution to do all possible transformation (including the 
case I mentioned above) from vv to vx or vf by late-combine PASS which
is contributed by ARM Richard Sandiford: 
https://patchwork.ozlabs.org/project/gcc/patch/mptr0ljn9eh@arm.com/
You can try to apply this patch and experiment it locally yourself.

And I believe it will be landed in GCC-15. So I don't think we need this patch 
to do the optimization.

Thanks.

-- Original --
From:  
"demin.han"mailto:demin@starfivetech.com>>;
Date:  Fri, Mar 1, 2024 02:27 PM
To:  "gcc-patches"mailto:gcc-patches@gcc.gnu.org>>;
Cc:  "juzhe.zhong"mailto:juzhe.zh...@rivai.ai>>; 
"kito.cheng"mailto:kito.ch...@gmail.com>>; "Li, 
Pan2"mailto:pan2...@intel.com>>; 
"jeffreyalaw"mailto:jeffreya...@gmail.com>>;
Subject:  [PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec 
and imm

Currently, following instructions generated in autovector:
flw
vsetvli
vfmv.v.f
...
vmfxx.vv
Two issues:
  1. Additional vsetvl and vfmv instructions
  2. Occupy one vector register and may results in smaller lmul

We expect:
flw
...
vmfxx.vf

Tested on RV32 and RV64

gcc/ChangeLog:

* config/riscv/autovec.md: Accept imm
* config/riscv/riscv-v.cc (get_cmp_insn_code): Select scalar pattern
(expand_vec_cmp): Ditto
* config/riscv/riscv.cc (riscv_const_insns): Exclude float mode

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Add new tests

Signed-off-by: demin.han 
mailto:demin@starfivetech.com>>
---
 gcc/config/riscv/autovec.md   |  2 +-
 gcc/config/riscv/riscv-v.cc   | 23 +
 gcc/config/riscv/riscv.cc |  2 +-
 .../riscv/rvv/autovec/cmp/vcond-1.c   | 34 +++
 4 files changed, 52 insertions(+), 9 deletions(-)

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 3b32369f68c..6cfb0800c45 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -690,7 +690,7 @@ (define_expand "vec_cmp"
   [(set (match_operand: 0 "register_operand")
  (match_operator: 1 "comparison_operator"
[(match_operand:V_VLSF 2 "register_operand")
-(match_operand:V_VLSF 3 "register_operand")]))]
+(match_operand:V_VLSF 3 "nonmemory_operand")]))]
   "TARGET_VECTOR"
   {
 riscv_vector::expand_vec_cmp_float (operands[0], GET_CODE (operands[1]),
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 14e75b9a117..2a188ac78e0 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2610,9 +2610,15 @@ expand_vec_init (rtx target, rtx vals)
 /* Get insn code for corresponding comparison.  */

 static insn_code
-get_cmp_insn_code (rtx_code code, machine_mode mode)
+get_cmp_insn_code (rtx_code code, machine_mode mode, bool scalar_p)
 {
   insn_code icode;
+  if (FLOAT_MODE_P (mode))
+{
+  icode = !scalar_p ? code_for_pred_cmp (mode)
+ : code_for_pred_cmp_scalar (mode);
+  return icode;
+}
   switch (code)
 {
 case EQ:
@@ -2628,10 +2634,7 @@ get_cmp_insn_code (rtx_code code, machine_mode mode)
 case LTU:
 case GE:
 case GEU:
-  if (FLOAT_MODE_P (mode))
- icode = code_for_pred_cmp (mode);
-  else
- icode = code_for_pred_ltge (mode);
+  icode = code_for_pred_ltge (mode);
   break;
 default:
   gcc_unreachable ();
@@ -2757,7 +2760,6 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx 
op1, rtx mask,
 {
   machine_mode mask_mode = GET_MODE (target);
   machine_mode data_mode = GET_MODE (op0);
-  insn_code icode = get_cmp_insn_code (code, data_mode);

   if (code == LTGT)
 {
@@ -2765,12 +2767,19 @@ expand_vec_c

RE: Re:[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm

2024-03-05 Thread Demin Han 
Hi,

I applied the mentioned last_combine 
patch(https://patchwork.ozlabs.org/project/gcc/patch/mptbka7em9w@arm.com/).
And did some initial tests.

Found that:

1.  Float vector-scalar and vector-imm are OK

2.  Integer vector-scalar is OK

3.  Integer vector-imm(e.g. a[i] > 16) is not OK.

When reaches last_combine pass, vec_duplicate(0x10) form is still kept, but no 
pattern match this now,

because  all scalar patterns  have “register_operand” predication.


I think MD file or expand function of rvv need to change for this situation.

Regards,
Demin

RE: RE:[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm

2024-03-05 Thread Demin Han 
OK, I will solve the comparison operation first and then do some check over 
other operations.



Regards,

Demin


From: juzhe.zh...@rivai.ai 
Sent: 2024年3月5日 17:02
To: Demin Han ; gcc-patches 

Cc: kito.cheng ; pan2.li ; jeffreyalaw 
; Robin Dapp ; richard.sandiford 

Subject: Re: RE:[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of 
vec and imm

Yes. I think we are lacking some combine patterns to do all vector-scalar 
combinations.

If you are interested at this topic, you can do some investigations on that (I 
believe currently no body works on it for now).
I bet we should add some patterns for late-combine PASS for example:

(set (plus : (vec_duplicate) (reg)))


juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>

From: Demin Han<mailto:demin@starfivetech.com>
Date: 2024-03-05 16:40
To: 钟居哲<mailto:juzhe.zh...@rivai.ai>; 
gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: kito.cheng<mailto:kito.ch...@gmail.com>; Li, 
Pan2<mailto:pan2...@intel.com>; jeffreyalaw<mailto:jeffreya...@gmail.com>; 
Robin Dapp<mailto:rdapp@gmail.com>; 
richard.sandiford<mailto:richard.sandif...@arm.com>
Subject: RE: Re:[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of 
vec and imm
Hi,

I applied the mentioned last_combine 
patch(https://patchwork.ozlabs.org/project/gcc/patch/mptbka7em9w@arm.com/).
And did some initial tests.

Found that:

1.  Float vector-scalar and vector-imm are OK

2.  Integer vector-scalar is OK

3.  Integer vector-imm(e.g. a[i] > 16) is not OK.

When reaches last_combine pass, vec_duplicate(0x10) form is still kept, but no 
pattern match this now,

because  all scalar patterns  have “register_operand” predication.


I think MD file or expand function of rvv need to change for this situation.

Regards,
Demin

RE: [PATCH] MAINTAINERS: Add myself to write after approval

2024-03-06 Thread Demin Han 
Hi,

I will commit the patch you mentioned with [NFC] added.
And split and resubmit other patches after more check and discussion.

Regards,
Demin

From: juzhe.zh...@rivai.ai 
Sent: 2024年3月6日 10:13
To: Demin Han ; gcc-patches 

Cc: kito.cheng 
Subject: Re: [PATCH] MAINTAINERS: Add myself to write after approval

Hi, han.

I think you can commit this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2024-March/646931.html
RISC-V: Refactor expand_vec_cmp
It's an NFC patch that I approved.

juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>

From: demin.han<mailto:demin@starfivetech.com>
Date: 2024-03-04 14:51
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; 
kito.cheng<mailto:kito.ch...@gmail.com>
Subject: [PATCH] MAINTAINERS: Add myself to write after approval
ChangeLog:

* MAINTAINERS: Add myself

Signed-off-by: demin.han 
mailto:demin@starfivetech.com>>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index b01fab16061..a681518d704 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -448,6 +448,7 @@ Wei Guozhi mailto:car...@google.com>>
Vineet Gupta mailto:vine...@rivosinc.com>>
Naveen H.S mailto:nave...@marvell.com>>
Mostafa Hagog mailto:ha...@gcc.gnu.org>>
+Demin Han mailto:demin@starfivetech.com>>
Jivan Hakobyan mailto:jivanhakoby...@gmail.com>>
Andrew Haley mailto:a...@redhat.com>>
Frederik Harwath mailto:frede...@harwath.name>>
--
2.43.2

RE: [PATCH] RISC-V: Fix ICE in riscv vector costs

2024-03-06 Thread Demin Han 
OK.
Which is better for testcase name?

1.  ice-biggestmode.c or

2.  Report a bug and name the testcase with PR id

From: juzhe.zh...@rivai.ai 
Sent: 2024年3月7日 15:20
To: Demin Han ; gcc-patches 

Cc: kito.cheng ; pan2.li ; jeffreyalaw 

Subject: Re: [PATCH] RISC-V: Fix ICE in riscv vector costs

Could you plz add testcase ? I just noticed you didn't append a testcase (jpeg) 
in this patch.


juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>

From: demin.han<mailto:demin@starfivetech.com>
Date: 2024-03-07 13:54
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; 
kito.cheng<mailto:kito.ch...@gmail.com>; pan2.li<mailto:pan2...@intel.com>; 
jeffreyalaw<mailto:jeffreya...@gmail.com>
Subject: [PATCH] RISC-V: Fix ICE in riscv vector costs
The following code can result in ICE:
-march=rv64gcv_zba_zbb --param riscv-autovec-lmul=dynamic -O3

char *jpeg_difference7_input_buf;
void jpeg_difference7(int *diff_buf) {
  unsigned width;
  int samp, Rb;
  while (--width) {
Rb = samp = *jpeg_difference7_input_buf;
*diff_buf++ = -(int)(samp + (long)Rb >> 1);
  }
}

One biggest_mode update missed in one branch and trigger assertion fail.
gcc_assert (biggest_size >= mode_size);

Tested On RV64 and no regression.

gcc/ChangeLog:

* config/riscv/riscv-vector-costs.cc: Fix ICE

Signed-off-by: demin.han 
mailto:demin@starfivetech.com>>
---
gcc/config/riscv/riscv-vector-costs.cc | 2 ++
1 file changed, 2 insertions(+)

diff --git a/gcc/config/riscv/riscv-vector-costs.cc 
b/gcc/config/riscv/riscv-vector-costs.cc
index 7c9840df4e9..f13a1296b31 100644
--- a/gcc/config/riscv/riscv-vector-costs.cc
+++ b/gcc/config/riscv/riscv-vector-costs.cc
@@ -413,6 +413,8 @@ compute_local_live_ranges (
  auto *r = get_live_range (live_ranges, arg);
  gcc_assert (r);
  (*r).second = MAX (point, (*r).second);
+   biggest_mode = get_biggest_mode (
+ biggest_mode, TYPE_MODE (TREE_TYPE (arg)));
}
}
  else
--
2.44.0

RE: [PATCH] RISC-V: Refine the condition for add additional vars in RVV cost model

2024-03-28 Thread Demin Han 
Hi,
the point starts from 1. the max_point should equal to length();

Should I prepare an individual patch for this?

From: juzhe.zh...@rivai.ai 
Sent: 2024年3月28日 18:45
To: Demin Han ; gcc-patches 

Cc: kito.cheng ; pan2.li ; jeffreyalaw 
; Robin Dapp 
Subject: Re: [PATCH] RISC-V: Refine the condition for add additional vars in 
RVV cost model

Thanks a lot for trying to optimize the dynamic LMUL cost model.

The need_additional_vector_vars_p looks good to me.


But

-  = (*program_points_per_bb.get (bb)).length () - 1;

+  = (*program_points_per_bb.get (bb)).length ();
I wonder why you remove - 1?


juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>

From: demin.han<mailto:demin@starfivetech.com>
Date: 2024-03-28 18:31
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; 
kito.cheng<mailto:kito.ch...@gmail.com>; pan2.li<mailto:pan2...@intel.com>; 
jeffreyalaw<mailto:jeffreya...@gmail.com>; rdapp.gcc<mailto:rdapp@gmail.com>
Subject: [PATCH] RISC-V: Refine the condition for add additional vars in RVV 
cost model
The adjacent_dr_p is sufficient and unnecessary condition for contiguous access.
So unnecessary live-ranges are added and result in spill.

This patch uses MEMORY_ACCESS_TYPE as condition and constrains segment
load/store.

Tested on RV64 and no regression.

PR target/114506

gcc/ChangeLog:

* config/riscv/riscv-vector-costs.cc (non_contiguous_memory_access_p): Rename
(need_additional_vector_vars_p): Rename and refine condition

gcc/testsuite/ChangeLog:

* gcc.dg/vect/costmodel/riscv/rvv/pr114506.c: New test.

Signed-off-by: demin.han 
mailto:demin@starfivetech.com>>
---
gcc/config/riscv/riscv-vector-costs.cc| 25 ---
.../vect/costmodel/riscv/rvv/pr114506.c   | 23 +
2 files changed, 39 insertions(+), 9 deletions(-)
create mode 100644 gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114506.c

diff --git a/gcc/config/riscv/riscv-vector-costs.cc 
b/gcc/config/riscv/riscv-vector-costs.cc
index f462c272a6e..9f7fe936a29 100644
--- a/gcc/config/riscv/riscv-vector-costs.cc
+++ b/gcc/config/riscv/riscv-vector-costs.cc
@@ -563,14 +563,24 @@ get_store_value (gimple *stmt)
 return gimple_assign_rhs1 (stmt);
}
-/* Return true if it is non-contiguous load/store.  */
+/* Return true if addtional vector vars needed.  */
static bool
-non_contiguous_memory_access_p (stmt_vec_info stmt_info)
+need_additional_vector_vars_p (stmt_vec_info stmt_info)
{
   enum stmt_vec_info_type type
 = STMT_VINFO_TYPE (vect_stmt_to_vectorize (stmt_info));
-  return ((type == load_vec_info_type || type == store_vec_info_type)
-   && !adjacent_dr_p (STMT_VINFO_DATA_REF (stmt_info)));
+  if (type == load_vec_info_type || type == store_vec_info_type)
+{
+  if (STMT_VINFO_GATHER_SCATTER_P (stmt_info)
+   && STMT_VINFO_MEMORY_ACCESS_TYPE (stmt_info) == VMAT_GATHER_SCATTER)
+ return true;
+
+  machine_mode mode = TYPE_MODE (STMT_VINFO_VECTYPE (stmt_info));
+  int lmul = riscv_get_v_regno_alignment (mode);
+  if (DR_GROUP_SIZE (stmt_info) * lmul > RVV_M8)
+ return true;
+}
+  return false;
}
/* Return the LMUL of the current analysis.  */
@@ -739,10 +749,7 @@ update_local_live_ranges (
  stmt_vec_info stmt_info = vinfo->lookup_stmt (gsi_stmt (si));
  enum stmt_vec_info_type type
= STMT_VINFO_TYPE (vect_stmt_to_vectorize (stmt_info));
-   if (non_contiguous_memory_access_p (stmt_info)
-   /* LOAD_LANES/STORE_LANES doesn't need a perm indice.  */
-   && STMT_VINFO_MEMORY_ACCESS_TYPE (stmt_info)
-!= VMAT_LOAD_STORE_LANES)
+   if (need_additional_vector_vars_p (stmt_info))
{
  /* For non-adjacent load/store STMT, we will potentially
convert it into:
@@ -752,7 +759,7 @@ update_local_live_ranges (
We will be likely using one more vector variable.  */
  unsigned int max_point
- = (*program_points_per_bb.get (bb)).length () - 1;
+ = (*program_points_per_bb.get (bb)).length ();
  auto *live_ranges = live_ranges_per_bb.get (bb);
  bool existed_p = false;
  tree var = type == load_vec_info_type
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114506.c 
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114506.c
new file mode 100644
index 000..a88d24b2d2d
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114506.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
+
+float a[32000], b[32000], c[32000], d[32000];
+float aa[256][256], bb[256][256], cc[256][256];
+
+void
+s2275 ()
+{
+  for (int i = 0; i < 256; i++)
+{
+  for (int j = 0; j < 256; j++)
+ {
+   aa[j][i] = aa[j][i] + bb[j][i] * cc[j][i];
+ }
+  a[i] = b[i] + c[i] * d[i];
+}
+}
+
+/* { dg-final { scan-assembler-ti

RE: RE: [PATCH] RISC-V: Refine the condition for add additional vars in RVV cost model

2024-03-28 Thread Demin Han 
OK，I will spilt them.

Thanks.

From: juzhe.zh...@rivai.ai 
Sent: 2024年3月28日 19:11
To: Demin Han ; gcc-patches 

Cc: kito.cheng ; pan2.li ; jeffreyalaw 
; Robin Dapp 
Subject: 回复: RE: [PATCH] RISC-V: Refine the condition for add additional vars 
in RVV cost model

OK. It's an obvious fix but it seems to be unrelated to the PR.

Could you split it 2 separate patches ?

Thanks.


juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>

发件人： Demin Han<mailto:demin@starfivetech.com>
发送时间： 2024-03-28 19:06
收件人： juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>; 
gcc-patches<mailto:gcc-patches@gcc.gnu.org>
抄送： kito.cheng<mailto:kito.ch...@gmail.com>; pan2.li<mailto:pan2...@intel.com>; 
jeffreyalaw<mailto:jeffreya...@gmail.com>; Robin 
Dapp<mailto:rdapp@gmail.com>
主题： RE: [PATCH] RISC-V: Refine the condition for add additional vars in RVV 
cost model
Hi,
the point starts from 1. the max_point should equal to length();

Should I prepare an individual patch for this?

From: juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai> 
mailto:juzhe.zh...@rivai.ai>>
Sent: 2024年3月28日 18:45
To: Demin Han mailto:demin@starfivetech.com>>; 
gcc-patches mailto:gcc-patches@gcc.gnu.org>>
Cc: kito.cheng mailto:kito.ch...@gmail.com>>; pan2.li 
mailto:pan2...@intel.com>>; jeffreyalaw 
mailto:jeffreya...@gmail.com>>; Robin Dapp 
mailto:rdapp@gmail.com>>
Subject: Re: [PATCH] RISC-V: Refine the condition for add additional vars in 
RVV cost model

Thanks a lot for trying to optimize the dynamic LMUL cost model.

The need_additional_vector_vars_p looks good to me.



But

-  = (*program_points_per_bb.get (bb)).length () - 1;

+  = (*program_points_per_bb.get (bb)).length ();
I wonder why you remove - 1?


juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>

From: demin.han<mailto:demin@starfivetech.com>
Date: 2024-03-28 18:31
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; 
kito.cheng<mailto:kito.ch...@gmail.com>; pan2.li<mailto:pan2...@intel.com>; 
jeffreyalaw<mailto:jeffreya...@gmail.com>; rdapp.gcc<mailto:rdapp@gmail.com>
Subject: [PATCH] RISC-V: Refine the condition for add additional vars in RVV 
cost model
The adjacent_dr_p is sufficient and unnecessary condition for contiguous access.
So unnecessary live-ranges are added and result in spill.

This patch uses MEMORY_ACCESS_TYPE as condition and constrains segment
load/store.

Tested on RV64 and no regression.

PR target/114506

gcc/ChangeLog:

* config/riscv/riscv-vector-costs.cc (non_contiguous_memory_access_p): Rename
(need_additional_vector_vars_p): Rename and refine condition

gcc/testsuite/ChangeLog:

* gcc.dg/vect/costmodel/riscv/rvv/pr114506.c: New test.

Signed-off-by: demin.han 
mailto:demin@starfivetech.com>>
---
gcc/config/riscv/riscv-vector-costs.cc| 25 ---
.../vect/costmodel/riscv/rvv/pr114506.c   | 23 +
2 files changed, 39 insertions(+), 9 deletions(-)
create mode 100644 gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114506.c

diff --git a/gcc/config/riscv/riscv-vector-costs.cc 
b/gcc/config/riscv/riscv-vector-costs.cc
index f462c272a6e..9f7fe936a29 100644
--- a/gcc/config/riscv/riscv-vector-costs.cc
+++ b/gcc/config/riscv/riscv-vector-costs.cc
@@ -563,14 +563,24 @@ get_store_value (gimple *stmt)
 return gimple_assign_rhs1 (stmt);
}
-/* Return true if it is non-contiguous load/store.  */
+/* Return true if addtional vector vars needed.  */
static bool
-non_contiguous_memory_access_p (stmt_vec_info stmt_info)
+need_additional_vector_vars_p (stmt_vec_info stmt_info)
{
   enum stmt_vec_info_type type
 = STMT_VINFO_TYPE (vect_stmt_to_vectorize (stmt_info));
-  return ((type == load_vec_info_type || type == store_vec_info_type)
-   && !adjacent_dr_p (STMT_VINFO_DATA_REF (stmt_info)));
+  if (type == load_vec_info_type || type == store_vec_info_type)
+{
+  if (STMT_VINFO_GATHER_SCATTER_P (stmt_info)
+   && STMT_VINFO_MEMORY_ACCESS_TYPE (stmt_info) == VMAT_GATHER_SCATTER)
+ return true;
+
+  machine_mode mode = TYPE_MODE (STMT_VINFO_VECTYPE (stmt_info));
+  int lmul = riscv_get_v_regno_alignment (mode);
+  if (DR_GROUP_SIZE (stmt_info) * lmul > RVV_M8)
+ return true;
+}
+  return false;
}
/* Return the LMUL of the current analysis.  */
@@ -739,10 +749,7 @@ update_local_live_ranges (
  stmt_vec_info stmt_info = vinfo->lookup_stmt (gsi_stmt (si));
  enum stmt_vec_info_type type
= STMT_VINFO_TYPE (vect_stmt_to_vectorize (stmt_info));
-   if (non_contiguous_memory_access_p (stmt_info)
-   /* LOAD_LANES/STORE_LANES doesn't need a perm indice.  */
-   && STMT_VINFO_MEMORY_ACCESS_TYPE (stmt_info)
-!= VMAT_LOAD_STORE_LANES)
+   if (need_additional_vector_va

[PATCH v2] RISC-V: Fix dynamic lmul tests depended on abi

2023-12-13 Thread demin . han 
Some toolchain configs would report:
fatal error: gnu/stubs-ilp32.h: No such file or directory

Fix method suggested by Juzhe-Zhong

gcc/testsuite/ChangeLog:

* gcc.dg/vect/costmodel/riscv/rvv/riscv_vector.h: New file.

Signed-off-by: demin.han 
---
 .../gcc.dg/vect/costmodel/riscv/rvv/riscv_vector.h| 11 +++
 1 file changed, 11 insertions(+)
 create mode 100644 gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/riscv_vector.h

diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/riscv_vector.h 
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/riscv_vector.h
new file mode 100644
index 000..fbb4858fc86
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/riscv_vector.h
@@ -0,0 +1,11 @@
+/* Wrapper of riscv_vector.h, prevent riscv_vector.h including stdint.h from
+   C library, that might cause problem on testing RV32 related testcase when
+   we disable multilib.  */
+#ifndef _RISCV_VECTOR_WRAP_H
+
+#define _GCC_WRAP_STDINT_H
+#include "stdint-gcc.h"
+#include_next 
+#define _RISCV_VECTOR_WRAP_H
+
+#endif
-- 
2.43.0

[PATCH] RISC-V: Fix calculation of max live vregs

2023-12-20 Thread demin . han 
For the stmt _1 = _2 + _3, assume that _2 or _3 not used after this stmt.
_1 can use same register with _2 or _3 if without early clobber.
Two registers are needed, but current calculation is three.

This patch preserves point 0 for bb entry and excludes its def when
calculates live regs of certain point.

Signed-off-by: demin.han 

gcc/ChangeLog:

* config/riscv/riscv-vector-costs.cc (max_number_of_live_regs): Fix 
max live vregs calc
(preferred_new_lmul_p): Ditto

gcc/testsuite/ChangeLog:

* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c: Moved to...
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-10.c: ...here.
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-4.c: Moved to...
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c: ...here.

---
 gcc/config/riscv/riscv-vector-costs.cc | 10 +-
 .../rvv/{dynamic-lmul2-7.c => dynamic-lmul4-10.c}  |  6 +++---
 .../rvv/{dynamic-lmul4-4.c => dynamic-lmul8-11.c}  |  6 +++---
 3 files changed, 11 insertions(+), 11 deletions(-)
 rename gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/{dynamic-lmul2-7.c => 
dynamic-lmul4-10.c} (79%)
 rename gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/{dynamic-lmul4-4.c => 
dynamic-lmul8-11.c} (87%)

diff --git a/gcc/config/riscv/riscv-vector-costs.cc 
b/gcc/config/riscv/riscv-vector-costs.cc
index e7bc9ed5233..a316603e207 100644
--- a/gcc/config/riscv/riscv-vector-costs.cc
+++ b/gcc/config/riscv/riscv-vector-costs.cc
@@ -123,7 +123,7 @@ compute_local_program_points (
   /* Collect the stmts that is vectorized and mark their program point.  */
   for (i = 0; i < nbbs; i++)
{
- int point = 0;
+ int point = 1;
  basic_block bb = bbs[i];
  vec program_points = vNULL;
  if (dump_enabled_p ())
@@ -300,13 +300,13 @@ max_number_of_live_regs (const basic_block bb,
   unsigned int i;
   unsigned int live_point = 0;
   auto_vec live_vars_vec;
-  live_vars_vec.safe_grow_cleared (max_point + 1, true);
+  live_vars_vec.safe_grow_cleared (max_point, true);
   for (hash_map::iterator iter = live_ranges.begin ();
iter != live_ranges.end (); ++iter)
 {
   tree var = (*iter).first;
   pair live_range = (*iter).second;
-  for (i = live_range.first; i <= live_range.second; i++)
+  for (i = live_range.first + 1; i <= live_range.second; i++)
{
  machine_mode mode = TYPE_MODE (TREE_TYPE (var));
  unsigned int nregs
@@ -485,7 +485,7 @@ update_local_live_ranges (
  if (!program_points_per_bb.get (e->src))
continue;
  unsigned int max_point
-   = (*program_points_per_bb.get (e->src)).length () - 1;
+   = (*program_points_per_bb.get (e->src)).length ();
  live_range = live_ranges->get (def);
  if (!live_range)
continue;
@@ -571,7 +571,7 @@ preferred_new_lmul_p (loop_vec_info other_loop_vinfo)
{
  basic_block bb = (*iter).first;
  unsigned int max_point
-   = (*program_points_per_bb.get (bb)).length () - 1;
+   = (*program_points_per_bb.get (bb)).length () + 1;
  if ((*iter).second.is_empty ())
continue;
  /* We prefer larger LMUL unless it causes register spillings.  */
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c 
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-10.c
similarity index 79%
rename from gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c
rename to gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-10.c
index 636332dbb62..74e629168f8 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-10.c
@@ -17,10 +17,10 @@ bar (int *x, int a, int b, int n)
   return sum1 + sum2;
 }
 
-/* { dg-final { scan-assembler {e32,m2} } } */
+/* { dg-final { scan-assembler {e32,m4} } } */
 /* { dg-final { scan-assembler-not {jr} } } */
 /* { dg-final { scan-assembler-times {ret} 2 } } *
 /* { dg-final { scan-tree-dump-times "Maximum lmul = 8" 1 "vect" } } */
-/* { dg-final { scan-tree-dump-times "Maximum lmul = 4" 1 "vect" } } */
-/* { dg-final { scan-tree-dump "Maximum lmul = 2" "vect" } } */
+/* { dg-final { scan-tree-dump "Maximum lmul = 4" "vect" } } */
+/* { dg-final { scan-tree-dump-not "Maximum lmul = 2" "vect" } } */
 /* { dg-final { scan-tree-dump-not "Maximum lmul = 1" "vect" } } */
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-4.c 
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c
similarity index 87%
rename from gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-4.c
rename to gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c
index 01a359bc7c8..01c976dd67b 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-4.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv

Re: [PATCH] RISC-V: Fix calculation of max live vregs

2023-12-20 Thread Demin Han 
Hi juzhe,

The live ranges are represented as [def_point, last_use_point] in code.

For example:
0: _2 = _x1 + _x2
1: _3 = _y1 + _y2
2: _1 = _2 + _3
3: _4 = _1 + x1


Origin:
 
live ranges:
_1: [2, 3]
_2: [0, 2]
_3: [1, 2]
_x1:[0, 3]

max live regs calc:
   _1  _2  _3 _x1
0   x  x
1   x   x  x
2  xx   x  x
3  x   x

program point 2 would have max live regs of 4.

_3 or _2 is dead after point 2, and _1 is defined.
_1 and _3 can use same register if without early clobber.
Three registers are enough on point 2.

Our program points are encoded continously.
The def is live after the point actually, (def_point, last_use_point].
>From patch view, the def is ignored for that program point.
In this patch, we also preserve program point 0 for bb entry,
and used for start point of those variable(such as _x1) lived in to this bb.
 
After patch:
 
0: 
1: _2 = _x1 + _x2
2: _3 = _y1 + _y2
3: _1 = _2 + _3
4: _4 = _1 + x1

live ranges:
_1: [3, 4]
_2: [1, 3]
_3: [2, 3]
_x1:[0, 4]

max live regs calc excluding def point:
   _1  _2  _3 _x1
0 
1  x  
2   x  x
3   x   x  x
4  x   x

for _1 = _2 + _3 program point, max live regs of 3 is got.

Regards,
Han

On 2023/12/20 17:56, juzhe.zh...@rivai.ai wrote:
> Hi, Han.
> 
> It's awesome that some one want to optimize dynamic LMUL feature of GCC.
> 
> I knew this feature is not stable yet and I failed to find the time to 
> optimize it (Still busy with fixing bugs).
> 
> Could you give me more details why this patch can refine those 2 cases with 
> picking larger LMUL (I am happy with those 2 cases be changed as using larger 
> LMUL )?
> 
> It seems this patch is ignoring the first vectorized statement during the 
> live calculation ?
> 
> Thanks. 
> 
> 
> 
> juzhe.zh...@rivai.ai
>  
> From: demin.han
> Date: 2023-12-20 16:15
> To: gcc-patches@gcc.gnu.org
> CC: juzhe.zh...@rivai.ai; pan2...@intel.com
> Subject: [PATCH] RISC-V: Fix calculation of max live vregs
> For the stmt _1 = _2 + _3, assume that _2 or _3 not used after this stmt.
> _1 can use same register with _2 or _3 if without early clobber.
> Two registers are needed, but current calculation is three.
>  
> This patch preserves point 0 for bb entry and excludes its def when
> calculates live regs of certain point.
>  
> Signed-off-by: demin.han 
>  
> gcc/ChangeLog:
>  
> * config/riscv/riscv-vector-costs.cc (max_number_of_live_regs): Fix 
> max live vregs calc
> (preferred_new_lmul_p): Ditto
>  
> gcc/testsuite/ChangeLog:
>  
> * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c: Moved to...
> * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-10.c: ...here.
> * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-4.c: Moved to...
> * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c: ...here.
>  
> ---
> gcc/config/riscv/riscv-vector-costs.cc | 10 +-
> .../rvv/{dynamic-lmul2-7.c => dynamic-lmul4-10.c}  |  6 +++---
> .../rvv/{dynamic-lmul4-4.c => dynamic-lmul8-11.c}  |  6 +++---
> 3 files changed, 11 insertions(+), 11 deletions(-)
> rename gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/{dynamic-lmul2-7.c => 
> dynamic-lmul4-10.c} (79%)
> rename gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/{dynamic-lmul4-4.c => 
> dynamic-lmul8-11.c} (87%)
>  
> diff --git a/gcc/config/riscv/riscv-vector-costs.cc 
> b/gcc/config/riscv/riscv-vector-costs.cc
> index e7bc9ed5233..a316603e207 100644
> --- a/gcc/config/riscv/riscv-vector-costs.cc
> +++ b/gcc/config/riscv/riscv-vector-costs.cc
> @@ -123,7 +123,7 @@ compute_local_program_points (
>/* Collect the stmts that is vectorized and mark their program point.  
> */
>for (i = 0; i < nbbs; i++)
> {
> -   int point = 0;
> +   int point = 1;
>   basic_block bb = bbs[i];
>   vec program_points = vNULL;
>   if (dump_enabled_p ())
> @@ -300,13 +300,13 @@ max_number_of_live_regs (const basic_block bb,
>unsigned int i;
>unsigned int live_point = 0;
>auto_vec live_vars_vec;
> -  live_vars_vec.safe_grow_cleared (max_point + 1, true);
> +  live_vars_vec.safe_grow_cleared (max_point, true);
>for (hash_map::iterator iter = live_ranges.begin ();
> iter != live_ranges.end (); ++iter)
>  {
>tree var = (*iter).first;
>pair live_range = (*iter).second;
> -  for (i = live_range.first; i <= live_range.second; i++)
> +  for (i = live_range.first + 1; i <= live_range.second; i++)
> {
>   machine_mode mode = TYPE_MODE (TREE_TYPE (var));
>   unsigned int nregs
> @@ -485,7 +485,7 @@ update_local_live_ranges (
>   if (!program_points_per_bb.get (e->src))
> continue;
>   unsigned int max_point
> - = (*program_points_per_bb.get (e->src)).length () - 1;
> + = (*program_points_per_bb.get (e->src)).length ();
>   live_range = live_ranges->get (def);
>   if (!live_range)
> continue;
> @@ -571,7 +571,7 @@ preferred_new_lmul_p (loop_vec_info other_loop_vinfo)
> {
>   basic_block bb = (*iter).first;
>   unsigned int max_point
> - = (*program_points_per_

Re: [PATCH] RISC-V: Fix calculation of max live vregs

2023-12-20 Thread Demin Han 
Hi Jeff,

Thanks for reminding this.
Regression test info will be added to commit log in following patches.

Demin

On 2023/12/20 23:28, Jeff Law wrote:
> 
> 
> On 12/20/23 04:17, juzhe.zh...@rivai.ai wrote:
>> I see. LGTM. Thanks for explanation.
>>
>> I will ask Li Pan commit it for you.
> The patch from Demin didn't specify if it had been regression tested.
> 
> All patches must be regression tested and an indication that the test passed 
> and on what target must be included in the patch email thread.
> 
> Please don't ACK patches that haven't followed this policy. It's OK with 
> conditions like "OK after verifying this patch doesn't cause regressions in 
> the testsuite on rv64gc" or something similar.
> 
> jeff

[PATCH] RISC-V: Fix dynamic lmul tests depended on abi

2023-12-12 Thread demin . han 
These two tests depend on -mabi.
Other toolchain configs would report:
fatal error: gnu/stubs-ilp32.h: No such file or directory

gcc/testsuite/ChangeLog:

* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c: Fix abi issue
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c: Ditto

Signed-off-by: demin.han 
---
 .../gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c | 4 +++-
 .../gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c 
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c
index 8e6610b0e11..7fd397b782e 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param 
riscv-autovec-lmul=dynamic -Wno-psabi -fdump-tree-vect-details" } */
+/* { dg-options "-O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic 
-Wno-psabi -fdump-tree-vect-details" } */
+/* { dg-additional-options "-march=rv32gcv" { target riscv32*-*-* } } */
+/* { dg-additional-options "-march=rv64gcv" { target riscv64*-*-* } } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c 
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c
index b3498ad8210..5fd27cb01e1 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param 
riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic 
-fdump-tree-vect-details" } */
+/* { dg-additional-options "-march=rv32gcv" { target riscv32*-*-* } } */
+/* { dg-additional-options "-march=rv64gcv" { target riscv64*-*-* } } */
 
 #include "riscv_vector.h"
 
-- 
2.43.0

[PATCH] RISC-V: Fix dynamic lmul tests depended on abi

2023-12-12 Thread demin . han 
These two tests depend on -mabi.
Other toolchain configs would report:
fatal error: gnu/stubs-ilp32.h: No such file or directory

gcc/testsuite/ChangeLog:

* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c: Fix abi issue
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c: Ditto

Signed-off-by: demin.han 
---
 .../gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c | 4 +++-
 .../gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c 
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c
index 8e6610b0e11..7fd397b782e 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param 
riscv-autovec-lmul=dynamic -Wno-psabi -fdump-tree-vect-details" } */
+/* { dg-options "-O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic 
-Wno-psabi -fdump-tree-vect-details" } */
+/* { dg-additional-options "-march=rv32gcv" { target riscv32*-*-* } } */
+/* { dg-additional-options "-march=rv64gcv" { target riscv64*-*-* } } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c 
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c
index b3498ad8210..5fd27cb01e1 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param 
riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
+/* { dg-options "-O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic 
-fdump-tree-vect-details" } */
+/* { dg-additional-options "-march=rv32gcv" { target riscv32*-*-* } } */
+/* { dg-additional-options "-march=rv64gcv" { target riscv64*-*-* } } */
 
 #include "riscv_vector.h"
 
-- 
2.43.0

Re: [PATCH] RISC-V: Fix dynamic lmul tests depended on abi

2023-12-13 Thread Demin Han 
Thanks for the suggestion.
The target selector method can not cover some cases.


On 2023/12/12 18:05, juzhe.zh...@rivai.ai wrote:
> A more reasonable solution is the add riscv_vector.h into 
> gcc.dg/vect/costmodel/riscv/rvv
> with the following codes in riscv_vector.h:
> 
> /* Wrapper of riscv_vector.h, prevent riscv_vector.h including stdint.h from
>C library, that might cause problem on testing RV32 related testcase when
>we disable multilib.  */
> #ifndef _RISCV_VECTOR_WRAP_H
> 
> #define _GCC_WRAP_STDINT_H
> #include "stdint-gcc.h"
> #include_next 
> #define _RISCV_VECTOR_WRAP_H
> 
> #endif
> 
> 
> 
> juzhe.zh...@rivai.ai
>  
> From: demin.han
> Date: 2023-12-12 18:01
> To: gcc-patches@gcc.gnu.org
> CC: juzhe.zh...@rivai.ai; pan2...@intel.com
> Subject: [PATCH] RISC-V: Fix dynamic lmul tests depended on abi
> These two tests depend on -mabi.
> Other toolchain configs would report:
> fatal error: gnu/stubs-ilp32.h: No such file or directory
>  
> gcc/testsuite/ChangeLog:
>  
> * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c: Fix abi issue
> * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c: Ditto
>  
> Signed-off-by: demin.han 
> ---
> .../gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c | 4 +++-
> .../gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c | 4 +++-
> 2 files changed, 6 insertions(+), 2 deletions(-)
>  
> diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c 
> b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c
> index 8e6610b0e11..7fd397b782e 100644
> --- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c
> +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c
> @@ -1,5 +1,7 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param 
> riscv-autovec-lmul=dynamic -Wno-psabi -fdump-tree-vect-details" } */
> +/* { dg-options "-O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic 
> -Wno-psabi -fdump-tree-vect-details" } */
> +/* { dg-additional-options "-march=rv32gcv" { target riscv32*-*-* } } */
> +/* { dg-additional-options "-march=rv64gcv" { target riscv64*-*-* } } */
> #include "riscv_vector.h"
> diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c 
> b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c
> index b3498ad8210..5fd27cb01e1 100644
> --- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c
> +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c
> @@ -1,5 +1,7 @@
> /* { dg-do compile } */
> -/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -ftree-vectorize --param 
> riscv-autovec-lmul=dynamic -fdump-tree-vect-details" } */
> +/* { dg-options "-O3 -ftree-vectorize --param riscv-autovec-lmul=dynamic 
> -fdump-tree-vect-details" } */
> +/* { dg-additional-options "-march=rv32gcv" { target riscv32*-*-* } } */
> +/* { dg-additional-options "-march=rv64gcv" { target riscv64*-*-* } } */
> #include "riscv_vector.h"

RE: [PATCH] RISC-V: More support of vx and vf for autovec comparison

2024-07-18 Thread Demin Han 
> > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> > index d5793acc999..a772153 100644
> > --- a/gcc/config/riscv/autovec.md
> > +++ b/gcc/config/riscv/autovec.md
> > @@ -690,7 +690,7 @@ (define_expand "vec_cmp"
> > [(set (match_operand: 0 "register_operand")
> > (match_operator: 1 "comparison_operator"
> >   [(match_operand:V_VLSF 2 "register_operand")
> > -  (match_operand:V_VLSF 3 "register_operand")]))]
> > +  (match_operand:V_VLSF 3 "nonmemory_operand")]))]
> Note this may be too loose.  Do we really want to allow any non-memory
> operand or are you just trying to allow a few additional constants?
> 
> If the latter, then we should create a suitable predicate that allows a 
> register
> or just that set of constants rather than using nonmemory_operand.

Register or any const vector are allowed.
Same with integer conterpart:
(define_expand "vec_cmpu"
  [(set (match_operand: 0 "register_operand")
(match_operator: 1 "comparison_operator"
  [(match_operand:V_VLSI 2 "register_operand")
   (match_operand:V_VLSI 3 "nonmemory_operand")]))]
  "TARGET_VECTOR"
  {
riscv_vector::expand_vec_cmp (operands[0], GET_CODE (operands[1]),
  operands[2], operands[3]);
DONE;
  }
)


> Robin may have further comments.
> 
> jeff

Demin

RE: [PATCH] RISC-V: More support of vx and vf for autovec comparison

2024-07-18 Thread Demin Han 


> -Original Message-
> From: Robin Dapp 
> Sent: 2024年7月17日 22:43
> To: Demin Han ; gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; pan2...@intel.com;
> jeffreya...@gmail.com
> Subject: Re: [PATCH] RISC-V: More support of vx and vf for autovec
> comparison
> 
> Hi Demin,
> 
> > +  void add_integer_operand (rtx x)
> > +  {
> > +create_integer_operand (&m_ops[m_opno++], INTVAL (x));
> > +gcc_assert (m_opno <= MAX_OPERANDS);  }
> 
> Can that be folded into add_input_operand somehow?

It's really redundant now. Firstly I want to follow rvv intrinsic. 

> >void add_input_operand (rtx x, machine_mode mode)
> >{
> >  create_input_operand (&m_ops[m_opno++], x, mode); @@ -284,12
> > +289,13 @@ public:
> >  for (; num_ops; num_ops--, opno++)
> >{
> > any_mem_p |= MEM_P (ops[opno]);
> > -   machine_mode mode = insn_data[(int) icode].operand[m_opno].mode;
> > +   machine_mode orig_mode = insn_data[(int)
> icode].operand[m_opno].mode;
> > +   machine_mode mode = orig_mode;
> > /* 'create_input_operand doesn't allow VOIDmode.
> >According to vector.md, we may have some patterns that do not have
> >explicit machine mode specifying the operand. Such operands are
> >always Pmode.  */
> > -   if (mode == VOIDmode)
> > +   if (orig_mode == VOIDmode)
> >   mode = Pmode;
> 
> Maybe source_mode and dest_mode would be a bit clearer.

Without add_integer_operand, this change can be removed.

> > -   add_input_operand (ops[opno], mode);
> > +   if (CONST_INT_P (ops[opno]) && orig_mode != E_VOIDmode)
> > + add_integer_operand (ops[opno]);
> > +   else
> > + add_input_operand (ops[opno], mode);
> 
> Indents look odd from here.  Could you double-check with clang-format?

There are two additional spaces.

> > -   icode = code_for_pred_cmp (mode);
> > +  icode = !scalar_p ? code_for_pred_cmp (mode)
> > + icode = code_for_pred_cmp_scalar (mode);
> 
> Ditto.
This is ok.

> > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > index 19b9b2daa95..ad5668b2c5a 100644
> > --- a/gcc/config/riscv/riscv.cc
> > +++ b/gcc/config/riscv/riscv.cc
> > @@ -2140,7 +2140,7 @@ riscv_const_insns (rtx x)
> >register vec_duplicate into vmv.v.x.  */
> > scalar_mode smode = GET_MODE_INNER (GET_MODE (x));
> > if (maybe_gt (GET_MODE_SIZE (smode), UNITS_PER_WORD)
> > -   && !immediate_operand (elt, Pmode))
> > +   && !FLOAT_MODE_P (smode) && !immediate_operand (elt,
> Pmode))
> 
> FLOAT_MODE is a bit broad here.  Maybe rather add a case before all others
> that always allows zero constants for any mode (as well as a comment)?
>
> > -if (maybe_gt (GET_MODE_SIZE (mode), GET_MODE_SIZE
> (Pmode)))
> > +bool gt_p = maybe_gt (GET_MODE_SIZE (mode),
> GET_MODE_SIZE (Pmode));
> > +if (!FLOAT_MODE_P (mode) && gt_p)
> >{
> >  riscv_vector::emit_vlmax_insn (code_for_pred_broadcast
> (mode),
> >riscv_vector::UNARY_OP, operands);
> 
> Same here basically.  Isn't it just the zero constant?

Integer mode need special process under RV32. 
I think this additional constrain is not harmful. 
Once double float operand enter these two branches and expanded to broadcast, 
then last_conbine can't work.
After the processing in expand_vec_cmp, this change actually don't affect cmp 
operation.
I will split this patch.

> > diff --git
> > a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
> > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
> > index db8c653b179..b9a040f2f78 100644
> 
> I suppose the -rv64 tests also need adjustment?

RV64 is OK, gt_p is false.

> Regards
>  Robin

Regards,
Demin

RE: [PATCH v2] RISC-V: More support of vx and vf for autovec comparison

2024-07-19 Thread Demin Han 

> -Original Message-
> From: Li, Pan2 
> Sent: 2024年7月19日 18:33
> To: Demin Han ; gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com;
> rdapp@gmail.com
> Subject: RE: [PATCH v2] RISC-V: More support of vx and vf for autovec
> comparison
> 
> > +  TEST_COND_IMM_FLOAT (T, >, 0.0, _gt) 
> > \
> >  +  TEST_COND_IMM_FLOAT (T, <, 0.0, _lt)
> > \
> >  +  TEST_COND_IMM_FLOAT (T, >=, 0.0, _ge)   
> > \
> >  +  TEST_COND_IMM_FLOAT (T, <=, 0.0, _le)   
> > \
> >  +  TEST_COND_IMM_FLOAT (T, ==, 0.0, _eq)   
> > \
> >  +  TEST_COND_IMM_FLOAT (T, !=, 0.0, _ne)   
> > \
> 
> Just curious, does this patch covered float imm is -0.0 (notice only +0.0 is
> mentioned)?
> If so we can have similar tests as +0.0 here.
> 
> It is totally Ok if -0.0f is not applicable here.

I have a test. 
The backend can't see -0.0 and It becomes 0.0 when translate to gimple.

> Pan
> 
Regards,
Demin

RE: [PATCH 1/5] RISC-V: Remove float vector eqne pattern

2024-05-15 Thread Demin Han 
Hi Robin,

Yes.
Can eqne pattern removal patches be committed firstly?

Regards,
Demin

> -Original Message-
> From: Robin Dapp 
> Sent: 2024年5月16日 3:49
> To: Demin Han ; 钟居哲
> ; gcc-patches 
> Cc: rdapp@gmail.com; kito.cheng ; Li, Pan2
> ; jeffreyalaw 
> Subject: Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern
> 
> Hi Demin,
> 
> are you still going to continue with this?
> 
> Regards
>  Robin

RE: [PATCH 1/5] RISC-V: Remove float vector eqne pattern

2024-05-15 Thread Demin Han 
Hi Juzhe,

There are two eqne pattern removal patches, one for float, another for integer.

https://patchwork.sourceware.org/project/gcc/patch/20240301062711.207137-5-demin@starfivetech.com/

https://patchwork.sourceware.org/project/gcc/patch/20240301062711.207137-2-demin@starfivetech.com/


Regards,
Demin
From: 钟居哲 
Sent: 2024年5月16日 10:02
To: Robin Dapp ; Demin Han ; 
gcc-patches 
Cc: rdapp.gcc ; kito.cheng ; Li, 
Pan2 ; jeffreyalaw 
Subject: Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern

Would you minding sending this patch again？
I can not find the patch now.



--Reply to Message--
On Thu, May 16, 2024 03:48 AM Robin 
Dappmailto:rdapp@gmail.com>> wrote:
Hi Demin,

are you still going to continue with this?

Regards
 Robin

RE: [PATCH] RISC-V: Fix double mode under RV32 not utilize vf

2024-08-27 Thread Demin Han 
Hi Jeff,

Yes, there are some tests fails after the last_combine pass introduced.
I remember these tests still have vv format which not become vf after 
last_combine.

I’ll update the testcase based on my local branch after your push.

Regards,
Demin

From: Jeff Law 
Sent: 2024年8月26日 5:59
To: Demin Han ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; pan2...@intel.com; 
rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Fix double mode under RV32 not utilize vf



On Fri, Jul 19, 2024 at 12:07 PM Jeff Law 
mailto:jeffreya...@gmail.com>> wrote:


On 7/19/24 2:55 AM, demin.han wrote:
> Currently, some binops of vector vs double scalar under RV32 can't
> translated to vf but vfmv+vxx.vv.
>
> The cause is that vec_duplicate is also expanded to broadcast for double mode
> under RV32. last-combine can't process expanded broadcast.
>
> gcc/ChangeLog:
>
>   * config/riscv/vector.md: Add !FLOAT_MODE_P constrain
>
> gcc/testsuite/ChangeLog:
>
>   * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c: Fix test
>   * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c: Ditto
>   * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c: Ditto
>   * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c: Ditto
>   * gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c: Ditto
It looks like vadd-rv32gcv-nofm still isn't quite right according to the
pre-commit testing:

  >
https://github.com/ewlu/gcc-precommit-ci/issues/1931#issuecomment-2238752679


OK once that's fixed.  No need to wait for another review cycle.
There's a reasonable chance late-combine was catching more cases that could be 
turned into .vf forms.  That was pretty common when I first looked at the 
late-combine changes.

Regardless,  I adjusted the vadd/vsub tests and pushed this to the trunk.

Thanks,
jeff

Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern

2024-06-10 Thread Demin Han 
Hi，

I‘m on vacation rencently.
I will return in a few days and summit new patch with the test.

Regards，
Demin







发件人: Jeff Law 
发送时间: 星期一, 六月 10, 2024 9:49 下午
收件人: Robin Dapp ; Demin Han ; 
钟居哲 ; gcc-patches 
抄送: kito.cheng ; Li, Pan2 
主题: Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern



On 6/10/24 1:33 AM, Robin Dapp wrote:
>> But isn't canonicalization of EQ/NE safe, even for IEEE NaN and +-0.0?
>>
>> target = (a == b) ? x : y
>> target = (a != b) ? y : x
>>
>> Are equivalent, even for IEEE IIRC.
>
> Yes, that should be fine.  My concern was not that we do a
> canonicalization but that we might not do it for some of the
> vector cases.  In particular when one of the operands is wrapped
> in a vec_duplicate and we end up with it first rather than
> second.
>
> My general feeling is that the patch is good but I wasn't entirely
> sure about all cases (in particular in case we transform something
> after expand).  That's why I would have liked to see at least some
> small test cases for it along with the patch (for the combinations
> we don't test yet).
Ah, OK.

Demin, can you some additional test coverage, guided by Robin's concerns
above?

Thanks,
jeff

RE: [PATCH v2] RISC-V: Remove float vector eqne pattern

2024-06-19 Thread Demin Han 
Hi Jeff,

Thanks for fixing that.

Regards,
Demin

> -Original Message-
> From: Jeff Law 
> Sent: 2024年6月19日 22:33
> To: Demin Han ; gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; pan2...@intel.com;
> rdapp@gmail.com
> Subject: Re: [PATCH v2] RISC-V: Remove float vector eqne pattern
> 
> 
> 
> On 6/19/24 6:30 AM, demin.han wrote:
> > We can unify eqne and other comparison operations.
> >
> > Tested on RV32 and RV64
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/riscv-vector-builtins-bases.cc: Remove eqne cond
> > * config/riscv/vector.md (@pred_eqne_scalar): Remove patterns
> > (*pred_eqne_scalar_merge_tie_mask): Ditto
> > (*pred_eqne_scalar): Ditto
> > (*pred_eqne_scalar_narrow): Ditto
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/rvv/base/float-point-cmp-eqne.c: New test.
> >
> > Signed-off-by: demin.han 
> > ---
> >
> > v2 changes:
> >1. add test
> >
> >Only intrinsics utilize those removed vf patterns.
> >Auto vectorization use vv format now.
> >The NaN will optimized out before expand in autovec as I tested.
> >
> >   .../riscv/riscv-vector-builtins-bases.cc  |  4 -
> >   gcc/config/riscv/vector.md| 86 ---
> >   .../riscv/rvv/base/float-point-cmp-eqne.c | 54 
> >   3 files changed, 54 insertions(+), 90 deletions(-)
> >   create mode 100644
> > gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cmp-eqne.c
> >
> > diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> > b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> > index b6f6e4ff37e..d414721ede8 100644
> > --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> > +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> > @@ -1420,10 +1420,6 @@ public:
> >   switch (e.op_info->op)
> > {
> > case OP_TYPE_vf: {
> > - if (CODE == EQ || CODE == NE)
> > -   return e.use_compare_insn (CODE, code_for_pred_eqne_scalar (
> > -  e.vector_mode ()));
> > - else
> > return e.use_compare_insn (CODE, code_for_pred_cmp_scalar
> (
> >e.vector_mode ()));
> Formatting nit.  You removed the IF-THEN-ELSE construct, leaving just the
> ELSE's body.  You need to reindent that body, both lines of which would move
> left by two spaces.
> 
> I'll fix and push it momentarily.
> 
> jeff

RE: [PATCH v2] RISC-V: Refine the condition for add additional vars in RVV cost model

2024-04-29 Thread Demin Han 
Hi, Juzhe.

Thanks for reminding.
I did regression again and committed.

Regard,
Demin
From: juzhe.zh...@rivai.ai 
Sent: 2024年4月29日 13:10
To: Demin Han ; gcc-patches 

Cc: kito.cheng ; pan2.li ; jeffreyalaw 
; Robin Dapp 
Subject: Re: [PATCH v2] RISC-V: Refine the condition for add additional vars in 
RVV cost model

Hi, Han.

GCC 14 is branch out. You can commit it to trunk (GCC 15).


juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>

From: demin.han<mailto:demin@starfivetech.com>
Date: 2024-04-02 16:30
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; 
kito.cheng<mailto:kito.ch...@gmail.com>; pan2.li<mailto:pan2...@intel.com>; 
jeffreyalaw<mailto:jeffreya...@gmail.com>; rdapp.gcc<mailto:rdapp@gmail.com>
Subject: [PATCH v2] RISC-V: Refine the condition for add additional vars in RVV 
cost model
The adjacent_dr_p is sufficient and unnecessary condition for contiguous access.
So unnecessary live-ranges are added and result in smaller LMUL.

This patch uses MEMORY_ACCESS_TYPE as condition and constrains segment
load/store.

Tested on RV64 and no regression.

PR target/114506

gcc/ChangeLog:

* config/riscv/riscv-vector-costs.cc (non_contiguous_memory_access_p): Rename
(need_additional_vector_vars_p): Rename and refine condition

gcc/testsuite/ChangeLog:

* gcc.dg/vect/costmodel/riscv/rvv/pr114506.c: New test.

Signed-off-by: demin.han 
mailto:demin@starfivetech.com>>
---
V2 changes:
  1. remove max_point issue
  2. minor change in commit message

gcc/config/riscv/riscv-vector-costs.cc| 23 ---
.../vect/costmodel/riscv/rvv/pr114506.c   | 23 +++
2 files changed, 38 insertions(+), 8 deletions(-)
create mode 100644 gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114506.c

diff --git a/gcc/config/riscv/riscv-vector-costs.cc 
b/gcc/config/riscv/riscv-vector-costs.cc
index f462c272a6e..484196b15b4 100644
--- a/gcc/config/riscv/riscv-vector-costs.cc
+++ b/gcc/config/riscv/riscv-vector-costs.cc
@@ -563,14 +563,24 @@ get_store_value (gimple *stmt)
 return gimple_assign_rhs1 (stmt);
}
-/* Return true if it is non-contiguous load/store.  */
+/* Return true if addtional vector vars needed.  */
static bool
-non_contiguous_memory_access_p (stmt_vec_info stmt_info)
+need_additional_vector_vars_p (stmt_vec_info stmt_info)
{
   enum stmt_vec_info_type type
 = STMT_VINFO_TYPE (vect_stmt_to_vectorize (stmt_info));
-  return ((type == load_vec_info_type || type == store_vec_info_type)
-   && !adjacent_dr_p (STMT_VINFO_DATA_REF (stmt_info)));
+  if (type == load_vec_info_type || type == store_vec_info_type)
+{
+  if (STMT_VINFO_GATHER_SCATTER_P (stmt_info)
+   && STMT_VINFO_MEMORY_ACCESS_TYPE (stmt_info) == VMAT_GATHER_SCATTER)
+ return true;
+
+  machine_mode mode = TYPE_MODE (STMT_VINFO_VECTYPE (stmt_info));
+  int lmul = riscv_get_v_regno_alignment (mode);
+  if (DR_GROUP_SIZE (stmt_info) * lmul > RVV_M8)
+ return true;
+}
+  return false;
}
/* Return the LMUL of the current analysis.  */
@@ -739,10 +749,7 @@ update_local_live_ranges (
  stmt_vec_info stmt_info = vinfo->lookup_stmt (gsi_stmt (si));
  enum stmt_vec_info_type type
= STMT_VINFO_TYPE (vect_stmt_to_vectorize (stmt_info));
-   if (non_contiguous_memory_access_p (stmt_info)
-   /* LOAD_LANES/STORE_LANES doesn't need a perm indice.  */
-   && STMT_VINFO_MEMORY_ACCESS_TYPE (stmt_info)
-!= VMAT_LOAD_STORE_LANES)
+   if (need_additional_vector_vars_p (stmt_info))
{
  /* For non-adjacent load/store STMT, we will potentially
convert it into:
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114506.c 
b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114506.c
new file mode 100644
index 000..a88d24b2d2d
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114506.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize 
-mrvv-max-lmul=dynamic -fdump-tree-vect-details" } */
+
+float a[32000], b[32000], c[32000], d[32000];
+float aa[256][256], bb[256][256], cc[256][256];
+
+void
+s2275 ()
+{
+  for (int i = 0; i < 256; i++)
+{
+  for (int j = 0; j < 256; j++)
+ {
+   aa[j][i] = aa[j][i] + bb[j][i] * cc[j][i];
+ }
+  a[i] = b[i] + c[i] * d[i];
+}
+}
+
+/* { dg-final { scan-assembler-times {e32,m8} 1 } } */
+/* { dg-final { scan-assembler-not {e32,m4} } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+/* { dg-final { scan-tree-dump-not "Preferring smaller LMUL loop because it 
has unexpected spills" "vect" } } */
--
2.44.0