[PATCH] Add VXRM enum

[chenyixuan]

From: XYenChi 

Noticed that the rvv-intrinsic-doc updated the __RISCV_VXRM.
gcc/ChangeLog:Add __RISCV_VXRM enum to riscv_vector.h

2023-07-13  XYenChi  

* config/riscv/riscv_vector.h (enum __RISCV_VXRM):Add an enum 
__RISCV_VXRM to help express the rounding modes.


---
 gcc/config/riscv/riscv_vector.h | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/gcc/config/riscv/riscv_vector.h b/gcc/config/riscv/riscv_vector.h
index ff54b6be863..0a90816be1a 100644
--- a/gcc/config/riscv/riscv_vector.h
+++ b/gcc/config/riscv/riscv_vector.h
@@ -42,6 +42,13 @@ enum RVV_CSR {
   RVV_VCSR,
 };
 
+enum __RISCV_VXRM {
+  __RISCV_VXRM_RNU = 0,
+  __RISCV_VXRM_RNE = 1,
+  __RISCV_VXRM_RDN = 2,
+  __RISCV_VXRM_ROD = 3,
+};
+
 __extension__ extern __inline unsigned long
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 vread_csr(enum RVV_CSR csr)
-- 
2.41.0

[PATCH] minimal support for xtheadv

[chenyixuan]

From: XYenChi 

This patch is for support xtheadv.

gcc/ChangeLog:

2023-11-08  Chen Yixuan  

* common/config/riscv/riscv-common.cc: Add xthead minimal support.

gcc/config/ChangeLog:

2023-11-08  Chen Yixuan  

* riscv/riscv.opt: Add xthead minimal support.
---
 gcc/common/config/riscv/riscv-common.cc | 2 ++
 gcc/config/riscv/riscv.opt  | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 526dbb7603b..d5ea0ee9b70 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -325,6 +325,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xtheadv",ISA_SPEC_CLASS_NONE, 0, 7},
 
   {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
 
@@ -1680,6 +1681,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"xtheadmemidx",  &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX},
   {"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
   {"xtheadsync",&gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
+  {"xtheadv",   &gcc_options::x_riscv_xthead_subext, MASK_XTHEADV},
 
   {"xventanacondops", &gcc_options::x_riscv_xventana_subext, 
MASK_XVENTANACONDOPS},
 
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 70d78151cee..2bbdf680fa2 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -438,6 +438,8 @@ Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext)
 
 Mask(XTHEADSYNC)Var(riscv_xthead_subext)
 
+Mask(XTHEADV)   Var(riscv_xthead_subext)
+
 TargetVariable
 int riscv_xventana_subext
 
-- 
2.42.0

[PATCH] Changed vector size

[chenyixuan]

From: Yixuan Chen 

Observed a vint type "ABS_EXPR" followed by extra 3 int type "ABS_EXPR". If 
want to test absolute value optimization for vector, maybe don't need 4 times.

gcc/testsuite/ChangeLog:

2023-03-27  Yixuan Chen  

* g++.dg/pr94920.C: Declare the vector size as long as int.

---
 gcc/testsuite/g++.dg/pr94920.C | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/g++.dg/pr94920.C b/gcc/testsuite/g++.dg/pr94920.C
index 126b00478d2..498bef93b3a 100644
--- a/gcc/testsuite/g++.dg/pr94920.C
+++ b/gcc/testsuite/g++.dg/pr94920.C
@@ -2,7 +2,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O2 -Wno-psabi -fdump-tree-optimized" } */
 
-typedef int __attribute__((vector_size(4*sizeof(int vint;
+typedef int __attribute__((vector_size(sizeof(int vint;
 
 /* Same form as PR.  */
 __attribute__((noipa)) unsigned int foo(int x) {
-- 
2.40.0

[PATCH] RISC-V: Fix FIXED_REGISTERS comment missing return address register

[chenyixuan]

From: Yixuan Chen 

gcc/config/ChangeLog:

2024-09-24  Yixuan Chen  

* riscv/riscv.h: Fix FIXED_REGISTERS comment missing return address 
register.
---
 gcc/config/riscv/riscv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index ead97867eb8..3aecb43f831 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -316,7 +316,7 @@ ASM_MISA_SPEC
 
 #define FIRST_PSEUDO_REGISTER 128
 
-/* x0, sp, gp, and tp are fixed.  */
+/* x0, ra, sp, gp, and tp are fixed.  */
 
 #define FIXED_REGISTERS
\
 { /* General registers.  */\
-- 
2.45.2