[PATCH v1 0/4] Add Loongson SX/ASX instruction support to LoongArch

[Xiaolong Chen]

In order to better test the function of the vector instruction, the 128 and 256 
bit test cases are further split according to the function of the instruction.

Xiaolong Chen (4):
  LoongArch: Add tests of -mstrict-align option.
  LoongArch: Add testsuite framework for Loongson SX/ASX.
  LoongArch: Add tests for Loongson SX builtin functions.
  LoongArch: Add tests for Loongson SX floating-point conversion
instructions.

 .../gcc.target/loongarch/strict-align.c   |   13 +
 .../loongarch/vector/loongarch-vector.exp |   42 +
 .../loongarch/vector/lsx/lsx-builtin.c| 1461 +
 .../loongarch/vector/lsx/lsx-vfcvt-1.c|  397 +
 .../loongarch/vector/lsx/lsx-vfcvt-2.c|  277 
 .../loongarch/vector/lsx/lsx-vffint-1.c   |  160 ++
 .../loongarch/vector/lsx/lsx-vffint-2.c   |  263 +++
 .../loongarch/vector/lsx/lsx-vffint-3.c   |  101 ++
 .../loongarch/vector/lsx/lsx-vfrint_d.c   |  229 +++
 .../loongarch/vector/lsx/lsx-vfrint_s.c   |  349 
 .../loongarch/vector/lsx/lsx-vftint-1.c   |  348 
 .../loongarch/vector/lsx/lsx-vftint-2.c   |  694 
 .../loongarch/vector/lsx/lsx-vftint-3.c   | 1027 
 .../loongarch/vector/lsx/lsx-vftint-4.c   |  344 
 .../loongarch/vector/simd_correctness_check.h |   39 +
 15 files changed, 5744 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/strict-align.c
 create mode 100644 
gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcvt-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcvt-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-3.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrint_d.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrint_s.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-3.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-4.c
 create mode 100644 
gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h

-- 
2.20.1

[PATCH v1 1/4] LoongArch: Add tests of -mstrict-align option.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/strict-align.c: New test.
---
 gcc/testsuite/gcc.target/loongarch/strict-align.c | 13 +
 1 file changed, 13 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/strict-align.c

diff --git a/gcc/testsuite/gcc.target/loongarch/strict-align.c 
b/gcc/testsuite/gcc.target/loongarch/strict-align.c
new file mode 100644
index 000..bcad2b84f68
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/strict-align.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-Ofast -mstrict-align -mlasx" } */
+/* { dg-final { scan-assembler-not "vfadd.s" } } */
+
+void
+foo (float* restrict x, float* restrict y)
+{
+  x[0] = x[0] + y[0];
+  x[1] = x[1] + y[1];
+  x[2] = x[2] + y[2];
+  x[3] = x[3] + y[3];
+}
+
-- 
2.20.1

[PATCH v1 2/4] LoongArch: Add testsuite framework for Loongson SX/ASX.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/loongarch-vector.exp: New test.
* gcc.target/loongarch/vector/simd_correctness_check.h: New test.
---
 .../loongarch/vector/loongarch-vector.exp | 42 +++
 .../loongarch/vector/simd_correctness_check.h | 39 +
 2 files changed, 81 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
 create mode 100644 
gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp 
b/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
new file mode 100644
index 000..b0616a26b0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
@@ -0,0 +1,42 @@
+# Copyright (C) 2021-2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# .
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a LoongArch target.
+if ![istarget loongarch*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+set DEFAULT_CFLAGS " -mlasx"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/lsx/*.\[cS\]]] \
+   "" $DEFAULT_CFLAGS
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/lasx/*.\[cS\]]] \
+   "" $DEFAULT_CFLAGS
+# All done.
+dg-finish
diff --git a/gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h 
b/gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h
new file mode 100644
index 000..7be199ee3a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h
@@ -0,0 +1,39 @@
+#include 
+#include 
+#include 
+
+#define ASSERTEQ_64(line, ref, res)
\
+do{
\
+int fail = 0;  
\
+for(size_t i = 0; i < sizeof(res)/sizeof(res[0]); ++i){
\
+   long *temp_ref = &ref[i], *temp_res = &res[i];  
\
+   if(abs(*temp_ref - *temp_res) > 0){ 
\
+   printf(" error: %s at line %ld , expected "#ref"[%ld]:0x%lx, got: 
0x%lx\n", \
+   __FILE__, line, i, *temp_ref, *temp_res);   
\
+   fail = 1;   
\
+   }   
\
+}  
\
+if(fail == 1) abort(); 
\
+}while(0) 
+
+#define ASSERTEQ_32(line, ref, res)
\
+do{
\
+int fail = 0;  
\
+for(size_t i = 0; i < sizeof(res)/sizeof(res[0]); ++i){
\
+   int *temp_ref = &ref[i], *temp_res = &res[i];   
\
+   if(abs(*temp_ref - *temp_res) > 0){ 
\
+   printf(" error: %s at line %ld , expected "#ref"[%ld]:0x%x, got: 
0x%x\n",   \
+  __FILE__, line, i, *temp_ref, *temp_res);
\
+   fail = 1;   
\
+   }   
\
+}  
\
+if(fail == 1) abort(); 
\
+}while(0) 
+
+#define ASSERTEQ_int(line, ref, res)   
\
+do{
\
+if (ref != res){   
\
+  

[PATCH v1 3/4] LoongArch: Add tests for Loongson SX builtin functions.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lsx/lsx-builtin.c: New test.
---
 .../loongarch/vector/lsx/lsx-builtin.c| 1461 +
 1 file changed, 1461 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c
new file mode 100644
index 000..70f5000b29f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c
@@ -0,0 +1,1461 @@
+/* Test builtins for LOONGARCH LSX ASE instructions */
+/* { dg-do compile } */
+/* { dg-options "-mlsx" } */
+/* { dg-final { scan-assembler-times "lsx_vsll_b:.*vsll\\.b.*lsx_vsll_b" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsll_h:.*vsll\\.h.*lsx_vsll_h" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsll_w:.*vsll\\.w.*lsx_vsll_w" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsll_d:.*vsll\\.d.*lsx_vsll_d" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vslli_b:.*vslli\\.b.*lsx_vslli_b" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vslli_h:.*vslli\\.h.*lsx_vslli_h" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vslli_w:.*vslli\\.w.*lsx_vslli_w" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vslli_d:.*vslli\\.d.*lsx_vslli_d" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsra_b:.*vsra\\.b.*lsx_vsra_b" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsra_h:.*vsra\\.h.*lsx_vsra_h" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsra_w:.*vsra\\.w.*lsx_vsra_w" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsra_d:.*vsra\\.d.*lsx_vsra_d" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsrai_b:.*vsrai\\.b.*lsx_vsrai_b" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrai_h:.*vsrai\\.h.*lsx_vsrai_h" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrai_w:.*vsrai\\.w.*lsx_vsrai_w" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrai_d:.*vsrai\\.d.*lsx_vsrai_d" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrar_b:.*vsrar\\.b.*lsx_vsrar_b" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrar_h:.*vsrar\\.h.*lsx_vsrar_h" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrar_w:.*vsrar\\.w.*lsx_vsrar_w" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrar_d:.*vsrar\\.d.*lsx_vsrar_d" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrari_b:.*vsrari\\.b.*lsx_vsrari_b" 
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrari_h:.*vsrari\\.h.*lsx_vsrari_h" 
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrari_w:.*vsrari\\.w.*lsx_vsrari_w" 
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrari_d:.*vsrari\\.d.*lsx_vsrari_d" 
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrl_b:.*vsrl\\.b.*lsx_vsrl_b" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsrl_h:.*vsrl\\.h.*lsx_vsrl_h" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsrl_w:.*vsrl\\.w.*lsx_vsrl_w" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsrl_d:.*vsrl\\.d.*lsx_vsrl_d" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsrli_b:.*vsrli\\.b.*lsx_vsrli_b" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrli_h:.*vsrli\\.h.*lsx_vsrli_h" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrli_w:.*vsrli\\.w.*lsx_vsrli_w" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrli_d:.*vsrli\\.d.*lsx_vsrli_d" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrlr_b:.*vsrlr\\.b.*lsx_vsrlr_b" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrlr_h:.*vsrlr\\.h.*lsx_vsrlr_h" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrlr_w:.*vsrlr\\.w.*lsx_vsrlr_w" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrlr_d:.*vsrlr\\.d.*lsx_vsrlr_d" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrlri_b:.*vsrlri\\.b.*lsx_vsrlri_b" 
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrlri_h:.*vsrlri\\.h.*lsx_vsrlri_h" 
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrlri_w:.*vsrlri\\.w.*lsx_vsrlri_w" 
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrlri_d:.*vsrlri\\.d.*lsx_vsrlri_d" 
1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclr_b:.*vbitclr\\.b.*lsx_vbitclr_b" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclr_h:.*vbitclr\\.h.*lsx_vbitclr_h" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclr_w:.*vbitclr\\.w.*lsx_vbitclr_w" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclr_d:.*vbitclr\\.d.*lsx_vbitclr_d" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclri_b:.*vbitclri\\.b.*lsx_vbitclri_b" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclri_h:.*vbitclri\\.h.*lsx_vbitclri_h" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclri_w:.*vbitclri\\.w.*lsx_vbitclri_w" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclri_d:.*vbitclri\\.d.*lsx_vbitclri_d" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitset_b:.*vbitset\\.b.*lsx_vbitset_b" 1 } } *

[PATCH v2 1/4] LoongArch: Add tests of -mstrict-align option.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/strict-align.c: New test.
---
 gcc/testsuite/gcc.target/loongarch/strict-align.c | 13 +
 1 file changed, 13 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/strict-align.c

diff --git a/gcc/testsuite/gcc.target/loongarch/strict-align.c 
b/gcc/testsuite/gcc.target/loongarch/strict-align.c
new file mode 100644
index 000..bcad2b84f68
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/strict-align.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-Ofast -mstrict-align -mlasx" } */
+/* { dg-final { scan-assembler-not "vfadd.s" } } */
+
+void
+foo (float* restrict x, float* restrict y)
+{
+  x[0] = x[0] + y[0];
+  x[1] = x[1] + y[1];
+  x[2] = x[2] + y[2];
+  x[3] = x[3] + y[3];
+}
+
-- 
2.20.1

[PATCH v2 0/4] Add Loongson SX/ASX instruction support to

[Xiaolong Chen]

In order to better test the function of the vector instruction, the 128 and 256 
bit test cases are further split according to the function of the instruction.

Xiaolong Chen (4):
  LoongArch: Add tests of -mstrict-align option.
  LoongArch: Add testsuite framework for Loongson SX/ASX.
  LoongArch: Add tests for Loongson SX builtin functions.
  LoongArch:Add Loongson SX/ASX instruction support to LoongArch

 .../gcc.target/loongarch/strict-align.c   |   13 +
 .../loongarch/vector/loongarch-vector.exp |   42 +
 .../loongarch/vector/lsx/lsx-builtin.c| 1461 +
 .../loongarch/vector/lsx/lsx-vfcvt-1.c|  397 +
 .../loongarch/vector/lsx/lsx-vfcvt-2.c|  277 
 .../loongarch/vector/lsx/lsx-vffint-1.c   |  160 ++
 .../loongarch/vector/lsx/lsx-vffint-2.c   |  263 +++
 .../loongarch/vector/lsx/lsx-vffint-3.c   |  101 ++
 .../loongarch/vector/lsx/lsx-vfrint_d.c   |  229 +++
 .../loongarch/vector/lsx/lsx-vfrint_s.c   |  349 
 .../loongarch/vector/lsx/lsx-vftint-1.c   |  348 
 .../loongarch/vector/lsx/lsx-vftint-2.c   |  694 
 .../loongarch/vector/lsx/lsx-vftint-3.c   | 1027 
 .../loongarch/vector/lsx/lsx-vftint-4.c   |  344 
 .../loongarch/vector/simd_correctness_check.h |   39 +
 15 files changed, 5744 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/strict-align.c
 create mode 100644 
gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcvt-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfcvt-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vffint-3.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrint_d.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfrint_s.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-3.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vftint-4.c
 create mode 100644 
gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h

-- 
2.20.1

[PATCH v2 2/4] LoongArch: Add testsuite framework for Loongson SX/ASX.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/loongarch-vector.exp: New test.
* gcc.target/loongarch/vector/simd_correctness_check.h: New test.
---
 .../loongarch/vector/loongarch-vector.exp | 42 +++
 .../loongarch/vector/simd_correctness_check.h | 39 +
 2 files changed, 81 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
 create mode 100644 
gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp 
b/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
new file mode 100644
index 000..b0616a26b0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
@@ -0,0 +1,42 @@
+# Copyright (C) 2021-2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# .
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a LoongArch target.
+if ![istarget loongarch*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+set DEFAULT_CFLAGS " -mlasx"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/lsx/*.\[cS\]]] \
+   "" $DEFAULT_CFLAGS
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/lasx/*.\[cS\]]] \
+   "" $DEFAULT_CFLAGS
+# All done.
+dg-finish
diff --git a/gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h 
b/gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h
new file mode 100644
index 000..7be199ee3a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h
@@ -0,0 +1,39 @@
+#include 
+#include 
+#include 
+
+#define ASSERTEQ_64(line, ref, res)
\
+do{
\
+int fail = 0;  
\
+for(size_t i = 0; i < sizeof(res)/sizeof(res[0]); ++i){
\
+   long *temp_ref = &ref[i], *temp_res = &res[i];  
\
+   if(abs(*temp_ref - *temp_res) > 0){ 
\
+   printf(" error: %s at line %ld , expected "#ref"[%ld]:0x%lx, got: 
0x%lx\n", \
+   __FILE__, line, i, *temp_ref, *temp_res);   
\
+   fail = 1;   
\
+   }   
\
+}  
\
+if(fail == 1) abort(); 
\
+}while(0) 
+
+#define ASSERTEQ_32(line, ref, res)
\
+do{
\
+int fail = 0;  
\
+for(size_t i = 0; i < sizeof(res)/sizeof(res[0]); ++i){
\
+   int *temp_ref = &ref[i], *temp_res = &res[i];   
\
+   if(abs(*temp_ref - *temp_res) > 0){ 
\
+   printf(" error: %s at line %ld , expected "#ref"[%ld]:0x%x, got: 
0x%x\n",   \
+  __FILE__, line, i, *temp_ref, *temp_res);
\
+   fail = 1;   
\
+   }   
\
+}  
\
+if(fail == 1) abort(); 
\
+}while(0) 
+
+#define ASSERTEQ_int(line, ref, res)   
\
+do{
\
+if (ref != res){   
\
+  

[PATCH v2 3/4] LoongArch: Add tests for Loongson SX builtin functions.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lsx/lsx-builtin.c: New test.
---
 .../loongarch/vector/lsx/lsx-builtin.c| 1461 +
 1 file changed, 1461 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c
new file mode 100644
index 000..70f5000b29f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c
@@ -0,0 +1,1461 @@
+/* Test builtins for LOONGARCH LSX ASE instructions */
+/* { dg-do compile } */
+/* { dg-options "-mlsx" } */
+/* { dg-final { scan-assembler-times "lsx_vsll_b:.*vsll\\.b.*lsx_vsll_b" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsll_h:.*vsll\\.h.*lsx_vsll_h" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsll_w:.*vsll\\.w.*lsx_vsll_w" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsll_d:.*vsll\\.d.*lsx_vsll_d" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vslli_b:.*vslli\\.b.*lsx_vslli_b" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vslli_h:.*vslli\\.h.*lsx_vslli_h" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vslli_w:.*vslli\\.w.*lsx_vslli_w" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vslli_d:.*vslli\\.d.*lsx_vslli_d" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsra_b:.*vsra\\.b.*lsx_vsra_b" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsra_h:.*vsra\\.h.*lsx_vsra_h" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsra_w:.*vsra\\.w.*lsx_vsra_w" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsra_d:.*vsra\\.d.*lsx_vsra_d" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsrai_b:.*vsrai\\.b.*lsx_vsrai_b" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrai_h:.*vsrai\\.h.*lsx_vsrai_h" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrai_w:.*vsrai\\.w.*lsx_vsrai_w" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrai_d:.*vsrai\\.d.*lsx_vsrai_d" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrar_b:.*vsrar\\.b.*lsx_vsrar_b" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrar_h:.*vsrar\\.h.*lsx_vsrar_h" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrar_w:.*vsrar\\.w.*lsx_vsrar_w" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrar_d:.*vsrar\\.d.*lsx_vsrar_d" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrari_b:.*vsrari\\.b.*lsx_vsrari_b" 
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrari_h:.*vsrari\\.h.*lsx_vsrari_h" 
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrari_w:.*vsrari\\.w.*lsx_vsrari_w" 
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrari_d:.*vsrari\\.d.*lsx_vsrari_d" 
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrl_b:.*vsrl\\.b.*lsx_vsrl_b" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsrl_h:.*vsrl\\.h.*lsx_vsrl_h" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsrl_w:.*vsrl\\.w.*lsx_vsrl_w" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsrl_d:.*vsrl\\.d.*lsx_vsrl_d" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsrli_b:.*vsrli\\.b.*lsx_vsrli_b" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrli_h:.*vsrli\\.h.*lsx_vsrli_h" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrli_w:.*vsrli\\.w.*lsx_vsrli_w" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrli_d:.*vsrli\\.d.*lsx_vsrli_d" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrlr_b:.*vsrlr\\.b.*lsx_vsrlr_b" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrlr_h:.*vsrlr\\.h.*lsx_vsrlr_h" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrlr_w:.*vsrlr\\.w.*lsx_vsrlr_w" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrlr_d:.*vsrlr\\.d.*lsx_vsrlr_d" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrlri_b:.*vsrlri\\.b.*lsx_vsrlri_b" 
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrlri_h:.*vsrlri\\.h.*lsx_vsrlri_h" 
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrlri_w:.*vsrlri\\.w.*lsx_vsrlri_w" 
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrlri_d:.*vsrlri\\.d.*lsx_vsrlri_d" 
1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclr_b:.*vbitclr\\.b.*lsx_vbitclr_b" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclr_h:.*vbitclr\\.h.*lsx_vbitclr_h" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclr_w:.*vbitclr\\.w.*lsx_vbitclr_w" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclr_d:.*vbitclr\\.d.*lsx_vbitclr_d" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclri_b:.*vbitclri\\.b.*lsx_vbitclri_b" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclri_h:.*vbitclri\\.h.*lsx_vbitclri_h" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclri_w:.*vbitclri\\.w.*lsx_vbitclri_w" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclri_d:.*vbitclri\\.d.*lsx_vbitclri_d" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitset_b:.*vbitset\\.b.*lsx_vbitset_b" 1 } } *

[PATCH v3 0/9] Added support for SX/LSX vector instructions.

[Xiaolong Chen]

v2 -> v3:
  Standardize the code using the GNU format.

  In order to better test the function of the vector instruction, the 128 and 
256 
bit test cases are further split according to the function of the instruction.

Xiaolong Chen (9):
  LoongArch: Add tests of -mstrict-align option.
  LoongArch: Add testsuite framework for Loongson SX/ASX.
  LoongArch: Add tests for Loongson SX builtin functions.
  LoongArch:Added support for SX vector floating-point instructions.
  LoongArch:Add SX instructions for vector arithmetic addition
operations.
  LoongArch:Add vector subtraction arithmetic operation SX instruction.
  LoongArch:Add vector arithmetic addition vsadd instruction.
  LoongArch:Added SX vector arithmetic multiplication instruction.
  LoongArch:Add SX instructions for vector arithmetic operations other
than multiplication, addition, and subtraction.

 .../gcc.target/loongarch/strict-align.c   |   12 +
 .../loongarch/vector/loongarch-vector.exp |   42 +
 .../loongarch/vector/lsx/lsx-builtin.c| 5038 +
 .../loongarch/vector/lsx/lsx-vadd.c   |  416 ++
 .../loongarch/vector/lsx/lsx-vadda.c  |  344 ++
 .../loongarch/vector/lsx/lsx-vaddi.c  |  251 +
 .../loongarch/vector/lsx/lsx-vaddwev-1.c  |  335 ++
 .../loongarch/vector/lsx/lsx-vaddwev-2.c  |  344 ++
 .../loongarch/vector/lsx/lsx-vaddwev-3.c  |  425 ++
 .../loongarch/vector/lsx/lsx-vaddwod-1.c  |  408 ++
 .../loongarch/vector/lsx/lsx-vaddwod-2.c  |  344 ++
 .../loongarch/vector/lsx/lsx-vaddwod-3.c  |  237 +
 .../loongarch/vector/lsx/lsx-vavg-1.c |  398 ++
 .../loongarch/vector/lsx/lsx-vavg-2.c |  308 +
 .../loongarch/vector/lsx/lsx-vavgr-1.c|  299 +
 .../loongarch/vector/lsx/lsx-vavgr-2.c|  317 ++
 .../loongarch/vector/lsx/lsx-vdiv-1.c |  299 +
 .../loongarch/vector/lsx/lsx-vdiv-2.c |  254 +
 .../loongarch/vector/lsx/lsx-vexth-1.c|  342 ++
 .../loongarch/vector/lsx/lsx-vexth-2.c|  182 +
 .../loongarch/vector/lsx/lsx-vfcvt-1.c|  398 ++
 .../loongarch/vector/lsx/lsx-vfcvt-2.c|  278 +
 .../loongarch/vector/lsx/lsx-vffint-1.c   |  161 +
 .../loongarch/vector/lsx/lsx-vffint-2.c   |  264 +
 .../loongarch/vector/lsx/lsx-vffint-3.c   |  102 +
 .../loongarch/vector/lsx/lsx-vfrint_d.c   |  230 +
 .../loongarch/vector/lsx/lsx-vfrint_s.c   |  350 ++
 .../loongarch/vector/lsx/lsx-vftint-1.c   |  349 ++
 .../loongarch/vector/lsx/lsx-vftint-2.c   |  695 +++
 .../loongarch/vector/lsx/lsx-vftint-3.c   | 1028 
 .../loongarch/vector/lsx/lsx-vftint-4.c   |  345 ++
 .../loongarch/vector/lsx/lsx-vhaddw-1.c   |  488 ++
 .../loongarch/vector/lsx/lsx-vhaddw-2.c   |  452 ++
 .../loongarch/vector/lsx/lsx-vhsubw-1.c   |  327 ++
 .../loongarch/vector/lsx/lsx-vhsubw-2.c   |  353 ++
 .../loongarch/vector/lsx/lsx-vldi.c   |   61 +
 .../loongarch/vector/lsx/lsx-vmadd.c  |  450 ++
 .../loongarch/vector/lsx/lsx-vmaddwev-1.c |  472 ++
 .../loongarch/vector/lsx/lsx-vmaddwev-2.c |  383 ++
 .../loongarch/vector/lsx/lsx-vmaddwev-3.c |  383 ++
 .../loongarch/vector/lsx/lsx-vmaddwod-1.c |  372 ++
 .../loongarch/vector/lsx/lsx-vmaddwod-2.c |  438 ++
 .../loongarch/vector/lsx/lsx-vmaddwod-3.c |  460 ++
 .../loongarch/vector/lsx/lsx-vmax-1.c |  317 ++
 .../loongarch/vector/lsx/lsx-vmax-2.c |  362 ++
 .../loongarch/vector/lsx/lsx-vmaxi-1.c|  279 +
 .../loongarch/vector/lsx/lsx-vmaxi-2.c|  223 +
 .../loongarch/vector/lsx/lsx-vmin-1.c |  434 ++
 .../loongarch/vector/lsx/lsx-vmin-2.c |  344 ++
 .../loongarch/vector/lsx/lsx-vmini-1.c|  314 +
 .../loongarch/vector/lsx/lsx-vmini-2.c|  216 +
 .../loongarch/vector/lsx/lsx-vmskgez.c|  119 +
 .../loongarch/vector/lsx/lsx-vmskltz.c|  321 ++
 .../loongarch/vector/lsx/lsx-vmsknz.c |  104 +
 .../loongarch/vector/lsx/lsx-vmsub.c  |  461 ++
 .../loongarch/vector/lsx/lsx-vmuh-1.c |  353 ++
 .../loongarch/vector/lsx/lsx-vmuh-2.c |  372 ++
 .../loongarch/vector/lsx/lsx-vmul.c   |  282 +
 .../loongarch/vector/lsx/lsx-vmulwev-1.c  |  434 ++
 .../loongarch/vector/lsx/lsx-vmulwev-2.c  |  344 ++
 .../loongarch/vector/lsx/lsx-vmulwev-3.c  |  245 +
 .../loongarch/vector/lsx/lsx-vmulwod-1.c  |  272 +
 .../loongarch/vector/lsx/lsx-vmulwod-2.c  |  282 +
 .../loongarch/vector/lsx/lsx-vmulwod-3.c  |  308 +
 .../loongarch/vector/lsx/lsx-vneg.c   |  321 ++
 .../loongarch/vector/lsx/lsx-vsadd-1.c|  335 ++
 .../loongarch/vector/lsx/lsx-vsadd-2.c|  345 ++
 .../loongarch/vector/lsx/lsx-vsat-1.c |  231 +
 .../loongarch/vector/lsx/lsx-vsat-2.c |  272 +
 .../loongarch/vector/lsx/lsx-vsigncov.c   |  425 ++
 .../loongarch/vector/lsx/lsx-vssub-1.c|  398 ++
 .../loongarch/vector/lsx/lsx-vssub-2.c|  408 ++
 .../loongarch/vector/

[PATCH v3 2/9] LoongArch: Add testsuite framework for Loongson SX/ASX.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/loongarch-vector.exp: New test.
* gcc.target/loongarch/vector/simd_correctness_check.h: New test.
---
 .../loongarch/vector/loongarch-vector.exp | 42 +++
 .../loongarch/vector/simd_correctness_check.h | 54 +++
 2 files changed, 96 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
 create mode 100644 
gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp 
b/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
new file mode 100644
index 000..f33bad82cb2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
@@ -0,0 +1,42 @@
+#Copyright(C) 2021 - 2023 Free Software Foundation, Inc.
+
+#This program is free software; you can redistribute it and / or modify
+#it under the terms of the GNU General Public License as published by
+#the Free Software Foundation; either version 3 of the License, or
+#(at your option) any later version.
+#
+#This program is distributed in the hope that it will be useful,
+#but WITHOUT ANY WARRANTY; without even the implied warranty of
+#MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+#GNU General Public License for more details.
+#
+#You should have received a copy of the GNU General Public License
+#along with GCC; see the file COPYING3.If not see
+# .
+
+#GCC testsuite that uses the `dg.exp' driver.
+
+#Exit immediately if this isn't a LoongArch target.
+if ![istarget loongarch*-*-*] then {
+return
+}
+
+#Load support procs.
+load_lib gcc-dg.exp
+
+#If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+set DEFAULT_CFLAGS " -mlasx"
+}
+
+#Initialize `dg'.
+dg-init
+
+#Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/lsx/*.\[cS\]]] \
+   "" $DEFAULT_CFLAGS
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/lasx/*.\[cS\]]] \
+   "" $DEFAULT_CFLAGS
+# All done.
+dg-finish
diff --git a/gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h 
b/gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h
new file mode 100644
index 000..eb7fbd59cc7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h
@@ -0,0 +1,54 @@
+#include 
+#include 
+#include 
+
+#define ASSERTEQ_64(line, ref, res)   \
+  do  \
+{ \
+  int fail = 0;   \
+  for (size_t i = 0; i < sizeof (res) / sizeof (res[0]); ++i) \
+{ \
+  long *temp_ref = &ref[i], *temp_res = &res[i];  \
+  if (abs (*temp_ref - *temp_res) > 0)\
+{ \
+  printf (" error: %s at line %ld , expected " #ref   \
+  "[%ld]:0x%lx, got: 0x%lx\n",\
+  __FILE__, line, i, *temp_ref, *temp_res);   \
+  fail = 1;   \
+} \
+} \
+  if (fail == 1)  \
+abort (); \
+} \
+  while (0)
+
+#define ASSERTEQ_32(line, ref, res)   \
+  do  \
+{ \
+  int fail = 0;   \
+  for (size_t i = 0; i < sizeof (res) / sizeof (res[0]); ++i) \
+{ \
+  int *temp_ref = &ref[i], *temp_res = &res[i];   \
+  if (abs (*temp_ref - *temp_res) > 0)\
+{ \
+  printf (" error: %s at line %ld , expected " #ref   \
+  "[%ld]:0x%x, got: 0x%x\n",  \
+  __FILE__, line, i, *temp_ref, *temp_res);   \
+  fail = 1;   \
+ 

[PATCH v3 1/9] LoongArch: Add tests of -mstrict-align option.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/strict-align.c: New test.
---
 gcc/testsuite/gcc.target/loongarch/strict-align.c | 12 
 1 file changed, 12 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/strict-align.c

diff --git a/gcc/testsuite/gcc.target/loongarch/strict-align.c 
b/gcc/testsuite/gcc.target/loongarch/strict-align.c
new file mode 100644
index 000..040d849584b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/strict-align.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-Ofast -mstrict-align -mlasx" } */
+/* { dg-final { scan-assembler-not "vfadd.s" } } */
+
+void
+foo (float *restrict x, float *restrict y)
+{
+  x[0] = x[0] + y[0];
+  x[1] = x[1] + y[1];
+  x[2] = x[2] + y[2];
+  x[3] = x[3] + y[3];
+}
-- 
2.20.1

[PATCH v3 3/9] LoongArch: Add tests for Loongson SX builtin functions.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lsx/lsx-builtin.c: New test.
---
 .../loongarch/vector/lsx/lsx-builtin.c| 5038 +
 1 file changed, 5038 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c
new file mode 100644
index 000..dcc8f9211bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c
@@ -0,0 +1,5038 @@
+/* Test builtins for LOONGARCH LSX ASE instructions */
+/* { dg-do compile } */
+/* { dg-options "-mlsx" } */
+/* { dg-final { scan-assembler-times "lsx_vsll_b:.*vsll\\.b.*lsx_vsll_b" 1 } }
+ */
+/* { dg-final { scan-assembler-times "lsx_vsll_h:.*vsll\\.h.*lsx_vsll_h" 1 } }
+ */
+/* { dg-final { scan-assembler-times "lsx_vsll_w:.*vsll\\.w.*lsx_vsll_w" 1 } }
+ */
+/* { dg-final { scan-assembler-times "lsx_vsll_d:.*vsll\\.d.*lsx_vsll_d" 1 } }
+ */
+/* { dg-final { scan-assembler-times "lsx_vslli_b:.*vslli\\.b.*lsx_vslli_b" 1 }
+ * } */
+/* { dg-final { scan-assembler-times "lsx_vslli_h:.*vslli\\.h.*lsx_vslli_h" 1 }
+ * } */
+/* { dg-final { scan-assembler-times "lsx_vslli_w:.*vslli\\.w.*lsx_vslli_w" 1 }
+ * } */
+/* { dg-final { scan-assembler-times "lsx_vslli_d:.*vslli\\.d.*lsx_vslli_d" 1 }
+ * } */
+/* { dg-final { scan-assembler-times "lsx_vsra_b:.*vsra\\.b.*lsx_vsra_b" 1 } }
+ */
+/* { dg-final { scan-assembler-times "lsx_vsra_h:.*vsra\\.h.*lsx_vsra_h" 1 } }
+ */
+/* { dg-final { scan-assembler-times "lsx_vsra_w:.*vsra\\.w.*lsx_vsra_w" 1 } }
+ */
+/* { dg-final { scan-assembler-times "lsx_vsra_d:.*vsra\\.d.*lsx_vsra_d" 1 } }
+ */
+/* { dg-final { scan-assembler-times "lsx_vsrai_b:.*vsrai\\.b.*lsx_vsrai_b" 1 }
+ * } */
+/* { dg-final { scan-assembler-times "lsx_vsrai_h:.*vsrai\\.h.*lsx_vsrai_h" 1 }
+ * } */
+/* { dg-final { scan-assembler-times "lsx_vsrai_w:.*vsrai\\.w.*lsx_vsrai_w" 1 }
+ * } */
+/* { dg-final { scan-assembler-times "lsx_vsrai_d:.*vsrai\\.d.*lsx_vsrai_d" 1 }
+ * } */
+/* { dg-final { scan-assembler-times "lsx_vsrar_b:.*vsrar\\.b.*lsx_vsrar_b" 1 }
+ * } */
+/* { dg-final { scan-assembler-times "lsx_vsrar_h:.*vsrar\\.h.*lsx_vsrar_h" 1 }
+ * } */
+/* { dg-final { scan-assembler-times "lsx_vsrar_w:.*vsrar\\.w.*lsx_vsrar_w" 1 }
+ * } */
+/* { dg-final { scan-assembler-times "lsx_vsrar_d:.*vsrar\\.d.*lsx_vsrar_d" 1 }
+ * } */
+/* { dg-final { scan-assembler-times "lsx_vsrari_b:.*vsrari\\.b.*lsx_vsrari_b"
+ * 1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrari_h:.*vsrari\\.h.*lsx_vsrari_h"
+ * 1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrari_w:.*vsrari\\.w.*lsx_vsrari_w"
+ * 1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrari_d:.*vsrari\\.d.*lsx_vsrari_d"
+ * 1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrl_b:.*vsrl\\.b.*lsx_vsrl_b" 1 } }
+ */
+/* { dg-final { scan-assembler-times "lsx_vsrl_h:.*vsrl\\.h.*lsx_vsrl_h" 1 } }
+ */
+/* { dg-final { scan-assembler-times "lsx_vsrl_w:.*vsrl\\.w.*lsx_vsrl_w" 1 } }
+ */
+/* { dg-final { scan-assembler-times "lsx_vsrl_d:.*vsrl\\.d.*lsx_vsrl_d" 1 } }
+ */
+/* { dg-final { scan-assembler-times "lsx_vsrli_b:.*vsrli\\.b.*lsx_vsrli_b" 1 }
+ * } */
+/* { dg-final { scan-assembler-times "lsx_vsrli_h:.*vsrli\\.h.*lsx_vsrli_h" 1 }
+ * } */
+/* { dg-final { scan-assembler-times "lsx_vsrli_w:.*vsrli\\.w.*lsx_vsrli_w" 1 }
+ * } */
+/* { dg-final { scan-assembler-times "lsx_vsrli_d:.*vsrli\\.d.*lsx_vsrli_d" 1 }
+ * } */
+/* { dg-final { scan-assembler-times "lsx_vsrlr_b:.*vsrlr\\.b.*lsx_vsrlr_b" 1 }
+ * } */
+/* { dg-final { scan-assembler-times "lsx_vsrlr_h:.*vsrlr\\.h.*lsx_vsrlr_h" 1 }
+ * } */
+/* { dg-final { scan-assembler-times "lsx_vsrlr_w:.*vsrlr\\.w.*lsx_vsrlr_w" 1 }
+ * } */
+/* { dg-final { scan-assembler-times "lsx_vsrlr_d:.*vsrlr\\.d.*lsx_vsrlr_d" 1 }
+ * } */
+/* { dg-final { scan-assembler-times "lsx_vsrlri_b:.*vsrlri\\.b.*lsx_vsrlri_b"
+ * 1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrlri_h:.*vsrlri\\.h.*lsx_vsrlri_h"
+ * 1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrlri_w:.*vsrlri\\.w.*lsx_vsrlri_w"
+ * 1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrlri_d:.*vsrlri\\.d.*lsx_vsrlri_d"
+ * 1 } } */
+/* { dg-final { scan-assembler-times
+ * "lsx_vbitclr_b:.*vbitclr\\.b.*lsx_vbitclr_b" 1 } } */
+/* { dg-final { scan-assembler-times
+ * "lsx_vbitclr_h:.*vbitclr\\.h.*lsx_vbitclr_h" 1 } } */
+/* { dg-final { scan-assembler-times
+ * "lsx_vbitclr_w:.*vbitclr\\.w.*lsx_vbitclr_w" 1 } } */
+/* { dg-final { scan-assembler-times
+ * "lsx_vbitclr_d:.*vbitclr\\.d.*lsx_vbitclr_d" 1 } } */
+/* { dg-final { scan-assembler-times
+ * "lsx_vbitclri_b:.*vbitclri\\.b.*lsx_vbitclri_b" 1 } } */
+/* { dg-final { scan-assembler-times
+ * "lsx_vbitclri_h:.*vbitclri\\.h.*lsx_vbitclri_h" 1 } } */
+/* { dg-final { scan-assembler-times
+ * "lsx_vbitclri_w:.*vbitclri\\.w.*lsx_vbitclri_w" 1 } } */
+/* { dg-final { scan-assembler-times
+ * "lsx_vbitclri_d:.*vbitclri\\

[PATCH v3 7/9] LoongArch:Add vector arithmetic addition vsadd instruction.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lsx/lsx-vsadd-1.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vsadd-2.c: New test.
---
 .../loongarch/vector/lsx/lsx-vsadd-1.c| 335 +
 .../loongarch/vector/lsx/lsx-vsadd-2.c| 345 ++
 2 files changed, 680 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsadd-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsadd-2.c

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsadd-1.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsadd-1.c
new file mode 100644
index 000..1bc27c983bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsadd-1.c
@@ -0,0 +1,335 @@
+/* { dg-do run } */
+/* { dg-options "-mlsx -w -fno-strict-aliasing" } */
+#include "../simd_correctness_check.h"
+#include 
+
+int
+main ()
+{
+  __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result;
+  __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result;
+  __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result;
+
+  int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail;
+  long int long_op0, long_op1, long_op2, lont_out, lont_result;
+  long int long_int_out, long_int_result;
+  unsigned int unsigned_int_out, unsigned_int_result;
+  unsigned long int unsigned_long_int_out, unsigned_long_int_result;
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0xfefefefefefefefe;
+  __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x3c992b2e;
+  *((unsigned long *)&__m128i_op1[0]) = 0x730f;
+  *((unsigned long *)&__m128i_result[1]) = 0x3c992b2e;
+  *((unsigned long *)&__m128i_result[0]) = 0x730f;
+  __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x7fff7fff;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x2bfd9461;
+  *((unsigned long *)&__m128i_result[1]) = 0x7fff7fff;
+  *((unsigned long *)&__m128i_result[0]) = 0x2bfd9461;
+  __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x00d3012acc56f9bb;
+  *((unsigned long *)&__m128i_op0[0]) = 0x1021;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x00d3012acc56f9bb;
+  *((unsigned long *)&__m128i_result[0]) = 0x1021;
+  __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x1000;
+  *((unsigned long *)&__m128i_op0[0]) = 0x0

[PATCH v4 01/23] LoongArch: Add tests of -mstrict-align option.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/strict-align.c: New test.
---
 gcc/testsuite/gcc.target/loongarch/strict-align.c | 12 
 1 file changed, 12 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/strict-align.c

diff --git a/gcc/testsuite/gcc.target/loongarch/strict-align.c 
b/gcc/testsuite/gcc.target/loongarch/strict-align.c
new file mode 100644
index 000..040d849584b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/strict-align.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-Ofast -mstrict-align -mlasx" } */
+/* { dg-final { scan-assembler-not "vfadd.s" } } */
+
+void
+foo (float *restrict x, float *restrict y)
+{
+  x[0] = x[0] + y[0];
+  x[1] = x[1] + y[1];
+  x[2] = x[2] + y[2];
+  x[3] = x[3] + y[3];
+}
-- 
2.20.1

[PATCH v4 02/23] LoongArch: Add testsuite framework for Loongson SX/ASX.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/loongarch-vector.exp: New test.
* gcc.target/loongarch/vector/simd_correctness_check.h: New test.
---
 .../loongarch/vector/loongarch-vector.exp | 42 +++
 .../loongarch/vector/simd_correctness_check.h | 54 +++
 2 files changed, 96 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
 create mode 100644 
gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp 
b/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
new file mode 100644
index 000..2cbf9ac6ac1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/loongarch-vector.exp
@@ -0,0 +1,42 @@
+#Copyright(C) 2021 - 2023 Free Software Foundation, Inc.
+
+#This program is free software; you can redistribute it and / or modify
+#it under the terms of the GNU General Public License as published by
+#the Free Software Foundation; either version 3 of the License, or
+#(at your option) any later version.
+#
+#This program is distributed in the hope that it will be useful,
+#but WITHOUT ANY WARRANTY; without even the implied warranty of
+#MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+#GNU General Public License for more details.
+#
+#You should have received a copy of the GNU General Public License
+#along with GCC; see the file COPYING3.If not see
+# .
+
+#GCC testsuite that uses the `dg.exp' driver.
+
+#Exit immediately if this isn't a LoongArch target.
+if ![istarget loongarch*-*-*] then {
+return
+}
+
+#Load support procs.
+load_lib gcc-dg.exp
+
+#If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+set DEFAULT_CFLAGS ""
+}
+
+#Initialize `dg'.
+dg-init
+
+#Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/lsx/*.\[cS\]]] \
+   "-mlsx" $DEFAULT_CFLAGS
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/lasx/*.\[cS\]]] \
+   "-mlasx" $DEFAULT_CFLAGS
+# All done.
+dg-finish
diff --git a/gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h 
b/gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h
new file mode 100644
index 000..eb7fbd59cc7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/simd_correctness_check.h
@@ -0,0 +1,54 @@
+#include 
+#include 
+#include 
+
+#define ASSERTEQ_64(line, ref, res)   \
+  do  \
+{ \
+  int fail = 0;   \
+  for (size_t i = 0; i < sizeof (res) / sizeof (res[0]); ++i) \
+{ \
+  long *temp_ref = &ref[i], *temp_res = &res[i];  \
+  if (abs (*temp_ref - *temp_res) > 0)\
+{ \
+  printf (" error: %s at line %ld , expected " #ref   \
+  "[%ld]:0x%lx, got: 0x%lx\n",\
+  __FILE__, line, i, *temp_ref, *temp_res);   \
+  fail = 1;   \
+} \
+} \
+  if (fail == 1)  \
+abort (); \
+} \
+  while (0)
+
+#define ASSERTEQ_32(line, ref, res)   \
+  do  \
+{ \
+  int fail = 0;   \
+  for (size_t i = 0; i < sizeof (res) / sizeof (res[0]); ++i) \
+{ \
+  int *temp_ref = &ref[i], *temp_res = &res[i];   \
+  if (abs (*temp_ref - *temp_res) > 0)\
+{ \
+  printf (" error: %s at line %ld , expected " #ref   \
+  "[%ld]:0x%x, got: 0x%x\n",  \
+  __FILE__, line, i, *temp_ref, *temp_res);   \
+  fail = 1;   \
+ 

[PATCH v4 03/23] LoongArch: Add tests for Loongson SX builtin functions.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lsx/lsx-builtin.c: New test.
---
 .../loongarch/vector/lsx/lsx-builtin.c| 1461 +
 1 file changed, 1461 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c
new file mode 100644
index 000..70f5000b29f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-builtin.c
@@ -0,0 +1,1461 @@
+/* Test builtins for LOONGARCH LSX ASE instructions */
+/* { dg-do compile } */
+/* { dg-options "-mlsx" } */
+/* { dg-final { scan-assembler-times "lsx_vsll_b:.*vsll\\.b.*lsx_vsll_b" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsll_h:.*vsll\\.h.*lsx_vsll_h" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsll_w:.*vsll\\.w.*lsx_vsll_w" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsll_d:.*vsll\\.d.*lsx_vsll_d" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vslli_b:.*vslli\\.b.*lsx_vslli_b" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vslli_h:.*vslli\\.h.*lsx_vslli_h" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vslli_w:.*vslli\\.w.*lsx_vslli_w" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vslli_d:.*vslli\\.d.*lsx_vslli_d" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsra_b:.*vsra\\.b.*lsx_vsra_b" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsra_h:.*vsra\\.h.*lsx_vsra_h" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsra_w:.*vsra\\.w.*lsx_vsra_w" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsra_d:.*vsra\\.d.*lsx_vsra_d" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsrai_b:.*vsrai\\.b.*lsx_vsrai_b" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrai_h:.*vsrai\\.h.*lsx_vsrai_h" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrai_w:.*vsrai\\.w.*lsx_vsrai_w" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrai_d:.*vsrai\\.d.*lsx_vsrai_d" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrar_b:.*vsrar\\.b.*lsx_vsrar_b" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrar_h:.*vsrar\\.h.*lsx_vsrar_h" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrar_w:.*vsrar\\.w.*lsx_vsrar_w" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrar_d:.*vsrar\\.d.*lsx_vsrar_d" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrari_b:.*vsrari\\.b.*lsx_vsrari_b" 
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrari_h:.*vsrari\\.h.*lsx_vsrari_h" 
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrari_w:.*vsrari\\.w.*lsx_vsrari_w" 
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrari_d:.*vsrari\\.d.*lsx_vsrari_d" 
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrl_b:.*vsrl\\.b.*lsx_vsrl_b" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsrl_h:.*vsrl\\.h.*lsx_vsrl_h" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsrl_w:.*vsrl\\.w.*lsx_vsrl_w" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsrl_d:.*vsrl\\.d.*lsx_vsrl_d" 1 } } 
*/
+/* { dg-final { scan-assembler-times "lsx_vsrli_b:.*vsrli\\.b.*lsx_vsrli_b" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrli_h:.*vsrli\\.h.*lsx_vsrli_h" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrli_w:.*vsrli\\.w.*lsx_vsrli_w" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrli_d:.*vsrli\\.d.*lsx_vsrli_d" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrlr_b:.*vsrlr\\.b.*lsx_vsrlr_b" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrlr_h:.*vsrlr\\.h.*lsx_vsrlr_h" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrlr_w:.*vsrlr\\.w.*lsx_vsrlr_w" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrlr_d:.*vsrlr\\.d.*lsx_vsrlr_d" 1 
} } */
+/* { dg-final { scan-assembler-times "lsx_vsrlri_b:.*vsrlri\\.b.*lsx_vsrlri_b" 
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrlri_h:.*vsrlri\\.h.*lsx_vsrlri_h" 
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrlri_w:.*vsrlri\\.w.*lsx_vsrlri_w" 
1 } } */
+/* { dg-final { scan-assembler-times "lsx_vsrlri_d:.*vsrlri\\.d.*lsx_vsrlri_d" 
1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclr_b:.*vbitclr\\.b.*lsx_vbitclr_b" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclr_h:.*vbitclr\\.h.*lsx_vbitclr_h" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclr_w:.*vbitclr\\.w.*lsx_vbitclr_w" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclr_d:.*vbitclr\\.d.*lsx_vbitclr_d" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclri_b:.*vbitclri\\.b.*lsx_vbitclri_b" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclri_h:.*vbitclri\\.h.*lsx_vbitclri_h" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclri_w:.*vbitclri\\.w.*lsx_vbitclri_w" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitclri_d:.*vbitclri\\.d.*lsx_vbitclri_d" 1 } } */
+/* { dg-final { scan-assembler-times 
"lsx_vbitset_b:.*vbitset\\.b.*lsx_vbitset_b" 1 } } *

[PATCH v4 00/23] Add tests for SX vector instructions.

[Xiaolong Chen]

v3 -> v4:
  Modify the name of the patch file.

  In order to better test the function of the vector instruction, the 128 bit
test cases are further split according to the function of the instruction.


Xiaolong Chen (23):
  LoongArch: Add tests of -mstrict-align option.
  LoongArch: Add testsuite framework for Loongson SX/ASX.
  LoongArch: Add tests for Loongson SX builtin functions.
  LoongArch: Add tests for SX vector floating-point instructions.
  LoongArch: Add tests for SX vector addition instructions.
  LoongArch: Add tests for SX vector subtraction instructions.
  LoongArch: Add tests for SX vector addition vsadd instructions.
  LoongArch: Add tests for the SX vector multiplication instruction.
  LoongArch: Add tests for SX vector vavg/vavgr instructions.
  LoongArch: Add tests for SX vector vmax/vmaxi/vmin/vmini instructions.
  LoongArch: Add tests for SX vector vexth/vextl/vldi/vneg/vsat
instructions.
  LoongArch: Add tests for SX vector
vabsd/vmskgez/vmskltz/vmsknz/vsigncov instructions.
  LoongArch: Add tests for SX vector vdiv/vmod instructions.
  LoongArch: Add tests for SX vector
vsll/vslli/vsrl/vsrli/vsrln/vsrlni/vsrlr /vsrlri/vslrlrn/vsrlrni 
instructions.
  LoongArch: Add tests for SX vector
vrotr/vrotri/vsra/vsrai/vsran/vsrani /vsrarn/vsrarni instructions.
  LoongArch: Add tests for SX vector
vssran/vssrani/vssrarn/vssrarni/vssrln /vssrlni/vssrlrn/vssrlrni
instructions.
  LoongArch: Add tests for SX vector vbitclr/vbitclri/vbitrev/vbitrevi/
vbitsel/vbitseli/vbitset/vbitseti/vclo/vclz/vpcnt instructions.
  LoongArch: Add tests for SX vector floating point arithmetic
instructions.
  LoongArch: Add tests for SX vector vfrstp/vfrstpi/vseq/vseqi/vsle
/vslei/vslt/vslti instructions.
  LoongArch: Add tests for SX vector vfcmp instructions.
  LoongArch: Add tests for SX vector handling and shuffle instructions.
  LoongArch: Add tests for SX vector vand/vandi/vandn/vor/vori/vnor/
vnori/vxor/vxori instructions.
  LoongArch: Add tests for SX vector vfmadd/vfnmadd/vld/vst
instructions.

 .../gcc.target/loongarch/strict-align.c   |   12 +
 .../loongarch/vector/loongarch-vector.exp |   42 +
 .../loongarch/vector/lsx/lsx-builtin.c| 1461 +
 .../loongarch/vector/lsx/lsx-vabsd-1.c|  272 +++
 .../loongarch/vector/lsx/lsx-vabsd-2.c|  398 +
 .../loongarch/vector/lsx/lsx-vadd.c   |  416 +
 .../loongarch/vector/lsx/lsx-vadda.c  |  344 
 .../loongarch/vector/lsx/lsx-vaddi.c  |  251 +++
 .../loongarch/vector/lsx/lsx-vaddwev-1.c  |  335 
 .../loongarch/vector/lsx/lsx-vaddwev-2.c  |  344 
 .../loongarch/vector/lsx/lsx-vaddwev-3.c  |  425 +
 .../loongarch/vector/lsx/lsx-vaddwod-1.c  |  408 +
 .../loongarch/vector/lsx/lsx-vaddwod-2.c  |  344 
 .../loongarch/vector/lsx/lsx-vaddwod-3.c  |  237 +++
 .../loongarch/vector/lsx/lsx-vand.c   |  159 ++
 .../loongarch/vector/lsx/lsx-vandi.c  |   67 +
 .../loongarch/vector/lsx/lsx-vandn.c  |  129 ++
 .../loongarch/vector/lsx/lsx-vavg-1.c |  398 +
 .../loongarch/vector/lsx/lsx-vavg-2.c |  308 
 .../loongarch/vector/lsx/lsx-vavgr-1.c|  299 
 .../loongarch/vector/lsx/lsx-vavgr-2.c|  317 
 .../loongarch/vector/lsx/lsx-vbitclr.c|  461 ++
 .../loongarch/vector/lsx/lsx-vbitclri.c   |  279 
 .../loongarch/vector/lsx/lsx-vbitrev.c|  407 +
 .../loongarch/vector/lsx/lsx-vbitrevi.c   |  336 
 .../loongarch/vector/lsx/lsx-vbitsel.c|  109 ++
 .../loongarch/vector/lsx/lsx-vbitseli.c   |   84 +
 .../loongarch/vector/lsx/lsx-vbitset.c|  371 +
 .../loongarch/vector/lsx/lsx-vbitseti.c   |  279 
 .../loongarch/vector/lsx/lsx-vbsll.c  |   83 +
 .../loongarch/vector/lsx/lsx-vbsrl.c  |   55 +
 .../loongarch/vector/lsx/lsx-vclo.c   |  266 +++
 .../loongarch/vector/lsx/lsx-vclz.c   |  265 +++
 .../loongarch/vector/lsx/lsx-vdiv-1.c |  299 
 .../loongarch/vector/lsx/lsx-vdiv-2.c |  254 +++
 .../loongarch/vector/lsx/lsx-vexth-1.c|  342 
 .../loongarch/vector/lsx/lsx-vexth-2.c|  182 ++
 .../loongarch/vector/lsx/lsx-vextl-1.c|   83 +
 .../loongarch/vector/lsx/lsx-vextl-2.c|   83 +
 .../loongarch/vector/lsx/lsx-vextrins.c   |  479 ++
 .../loongarch/vector/lsx/lsx-vfadd_d.c|  407 +
 .../loongarch/vector/lsx/lsx-vfadd_s.c|  470 ++
 .../loongarch/vector/lsx/lsx-vfclass_d.c  |   83 +
 .../loongarch/vector/lsx/lsx-vfclass_s.c  |   74 +
 .../loongarch/vector/lsx/lsx-vfcmp_caf.c  |  244 +++
 .../loongarch/vector/lsx/lsx-vfcmp_ceq.c  |  516 ++
 .../loongarch/vector/lsx/lsx-vfcmp_cle.c  |  530 ++
 .../loongarch/vector/lsx/lsx-vfcmp_clt.c  |  476 ++
 .../loongarch/vector/lsx/lsx-vfcmp_cne.c  |  378 +
 .../loongarch/vector/lsx/lsx-vfcmp_co

[PATCH v4 07/23] LoongArch: Add tests for SX vector addition vsadd instructions.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lsx/lsx-vsadd-1.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vsadd-2.c: New test.
---
 .../loongarch/vector/lsx/lsx-vsadd-1.c| 335 +
 .../loongarch/vector/lsx/lsx-vsadd-2.c| 345 ++
 2 files changed, 680 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsadd-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsadd-2.c

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsadd-1.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsadd-1.c
new file mode 100644
index 000..1bc27c983bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsadd-1.c
@@ -0,0 +1,335 @@
+/* { dg-do run } */
+/* { dg-options "-mlsx -w -fno-strict-aliasing" } */
+#include "../simd_correctness_check.h"
+#include 
+
+int
+main ()
+{
+  __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result;
+  __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result;
+  __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result;
+
+  int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail;
+  long int long_op0, long_op1, long_op2, lont_out, lont_result;
+  long int long_int_out, long_int_result;
+  unsigned int unsigned_int_out, unsigned_int_result;
+  unsigned long int unsigned_long_int_out, unsigned_long_int_result;
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0xfefefefefefefefe;
+  __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x3c992b2e;
+  *((unsigned long *)&__m128i_op1[0]) = 0x730f;
+  *((unsigned long *)&__m128i_result[1]) = 0x3c992b2e;
+  *((unsigned long *)&__m128i_result[0]) = 0x730f;
+  __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x7fff7fff;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x2bfd9461;
+  *((unsigned long *)&__m128i_result[1]) = 0x7fff7fff;
+  *((unsigned long *)&__m128i_result[0]) = 0x2bfd9461;
+  __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x00d3012acc56f9bb;
+  *((unsigned long *)&__m128i_op0[0]) = 0x1021;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x00d3012acc56f9bb;
+  *((unsigned long *)&__m128i_result[0]) = 0x1021;
+  __m128i_out = __lsx_vsadd_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x1000;
+  *((unsigned long *)&__m128i_op0[0]) = 0x0

[PATCH v4 09/23] LoongArch: Add tests for SX vector vavg/vavgr instructions.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lsx/lsx-vavg-1.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vavg-2.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vavgr-1.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vavgr-2.c: New test.
---
 .../loongarch/vector/lsx/lsx-vavg-1.c | 398 ++
 .../loongarch/vector/lsx/lsx-vavg-2.c | 308 ++
 .../loongarch/vector/lsx/lsx-vavgr-1.c| 299 +
 .../loongarch/vector/lsx/lsx-vavgr-2.c| 317 ++
 4 files changed, 1322 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavg-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavg-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavgr-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavgr-2.c

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavg-1.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavg-1.c
new file mode 100644
index 000..2177ca3f6f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vavg-1.c
@@ -0,0 +1,398 @@
+/* { dg-do run } */
+/* { dg-options "-mlsx -w -fno-strict-aliasing" } */
+#include "../simd_correctness_check.h"
+#include 
+
+int
+main ()
+{
+  __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result;
+  __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result;
+  __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result;
+
+  int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail;
+  long int long_op0, long_op1, long_op2, lont_out, lont_result;
+  long int long_int_out, long_int_result;
+  unsigned int unsigned_int_out, unsigned_int_result;
+  unsigned long int unsigned_long_int_out, unsigned_long_int_result;
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vavg_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0xfff8fff8fff8fff8;
+  *((unsigned long *)&__m128i_op0[0]) = 0xfff8fff8fff8fff8;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0xfffcfffcfffcfffc;
+  *((unsigned long *)&__m128i_result[0]) = 0xfffcfffcfffcfffc;
+  __m128i_out = __lsx_vavg_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vavg_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vavg_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x4050;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x2028;
+  __m128i_out = __lsx_vavg_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vavg_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0xfff

[PATCH v4 13/23] LoongArch: Add tests for SX vector vdiv/vmod instructions.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lsx/lsx-vdiv-1.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vdiv-2.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vmod-1.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vmod-2.c: New test.
---
 .../loongarch/vector/lsx/lsx-vdiv-1.c | 299 ++
 .../loongarch/vector/lsx/lsx-vdiv-2.c | 254 +++
 .../loongarch/vector/lsx/lsx-vmod-1.c | 254 +++
 .../loongarch/vector/lsx/lsx-vmod-2.c | 254 +++
 4 files changed, 1061 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vdiv-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vdiv-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmod-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmod-2.c

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vdiv-1.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vdiv-1.c
new file mode 100644
index 000..cb4be04757c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vdiv-1.c
@@ -0,0 +1,299 @@
+/* { dg-do run } */
+/* { dg-options "-mlsx -w -fno-strict-aliasing" } */
+#include "../simd_correctness_check.h"
+#include 
+
+int
+main ()
+{
+  __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result;
+  __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result;
+  __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result;
+
+  int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail;
+  long int long_op0, long_op1, long_op2, lont_out, lont_result;
+  long int long_int_out, long_int_result;
+  unsigned int unsigned_int_out, unsigned_int_result;
+  unsigned long int unsigned_long_int_out, unsigned_long_int_result;
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vdiv_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x3ff0;
+  *((unsigned long *)&__m128i_op0[0]) = 0x40f3fa00;
+  *((unsigned long *)&__m128i_op1[1]) = 0xb4ff;
+  *((unsigned long *)&__m128i_op1[0]) = 0xb4ff;
+  *((unsigned long *)&__m128i_result[1]) = 0xc110;
+  *((unsigned long *)&__m128i_result[0]) = 0xc00d0600;
+  __m128i_out = __lsx_vdiv_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x0101010101010101;
+  __m128i_out = __lsx_vdiv_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x0002;
+  *((unsigned long *)&__m128i_op0[0]) = 0x0101000101010001;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x00fe;
+  *((unsigned long *)&__m128i_result[0]) = 0x00ff00ff;
+  __m128i_out = __lsx_vdiv_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x01010101;
+  *((unsigned long *)&__m128i_result[0]) = 0x01010101;
+  __m128i_out = __lsx_vdiv_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0xd3259a2984048c23;
+  *((unsigned long *)&__m128i_op1[0]) = 0xf9796558e39953fd;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vdiv_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x97279727;
+  *((unsigned long *)&__m128i_op0[0]) = 0xfe79ba5f;
+  *((unsigned long *)&__m128i_op1[1]) = 0xfff

[PATCH v4 12/23] LoongArch: Add tests for SX vector vabsd/vmskgez/vmskltz/vmsknz/vsigncov instructions.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lsx/lsx-vabsd-1.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vabsd-2.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vmskgez.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vmskltz.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vmsknz.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vsigncov.c: New test.
---
 .../loongarch/vector/lsx/lsx-vabsd-1.c| 272 +++
 .../loongarch/vector/lsx/lsx-vabsd-2.c| 398 
 .../loongarch/vector/lsx/lsx-vmskgez.c| 119 +
 .../loongarch/vector/lsx/lsx-vmskltz.c| 321 +
 .../loongarch/vector/lsx/lsx-vmsknz.c | 104 +
 .../loongarch/vector/lsx/lsx-vsigncov.c   | 425 ++
 6 files changed, 1639 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vabsd-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vabsd-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmskgez.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmskltz.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmsknz.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsigncov.c

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vabsd-1.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vabsd-1.c
new file mode 100644
index 000..e336581f3b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vabsd-1.c
@@ -0,0 +1,272 @@
+/* { dg-do run } */
+/* { dg-options "-mlsx -w -fno-strict-aliasing" } */
+#include "../simd_correctness_check.h"
+#include 
+
+int
+main ()
+{
+  __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result;
+  __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result;
+  __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result;
+
+  int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail;
+  long int long_op0, long_op1, long_op2, lont_out, lont_result;
+  long int long_int_out, long_int_result;
+  unsigned int unsigned_int_out, unsigned_int_result;
+  unsigned long int unsigned_long_int_out, unsigned_long_int_result;
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vabsd_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0xfda9b23a624082fd;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x03574e3a62407e03;
+  *((unsigned long *)&__m128i_result[0]) = 0x0101;
+  __m128i_out = __lsx_vabsd_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x80008000;
+  *((unsigned long *)&__m128i_op0[0]) = 0x7fff7fff;
+  *((unsigned long *)&__m128i_op1[1]) = 0xfffd0007;
+  *((unsigned long *)&__m128i_op1[0]) = 0x0014fff5;
+  *((unsigned long *)&__m128i_result[1]) = 0x7f0300078000;
+  *((unsigned long *)&__m128i_result[0]) = 0x7f15000a7f010101;
+  __m128i_out = __lsx_vabsd_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vabsd_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x7fff;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x0006000e;
+  *((unsigned long *)&__m128i_op1[0]) = 0x00127fea;
+  *((unsigned long *)&__m128i_result[1]) = 0x7f0101070101010f;
+  *((unsigned long *)&__m128i_result[0]) = 0x00127f010116;
+  __m128i_out = __lsx_vabsd_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x000b;
+  *((unsigned long *)&__m128i_op0[0]) = 0x000b;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+

[PATCH v4 10/23] LoongArch: Add tests for SX vector vmax/vmaxi/vmin/vmini instructions.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lsx/lsx-vmax-1.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vmax-2.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vmaxi-1.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vmaxi-2.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vmin-1.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vmin-2.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vmini-1.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vmini-2.c: New test.
---
 .../loongarch/vector/lsx/lsx-vmax-1.c | 317 +
 .../loongarch/vector/lsx/lsx-vmax-2.c | 362 +++
 .../loongarch/vector/lsx/lsx-vmaxi-1.c| 279 +++
 .../loongarch/vector/lsx/lsx-vmaxi-2.c| 223 +
 .../loongarch/vector/lsx/lsx-vmin-1.c | 434 ++
 .../loongarch/vector/lsx/lsx-vmin-2.c | 344 ++
 .../loongarch/vector/lsx/lsx-vmini-1.c| 314 +
 .../loongarch/vector/lsx/lsx-vmini-2.c| 216 +
 8 files changed, 2489 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmax-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmax-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaxi-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmaxi-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmin-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmin-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmini-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmini-2.c

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmax-1.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmax-1.c
new file mode 100644
index 000..b0e22f955b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vmax-1.c
@@ -0,0 +1,317 @@
+/* { dg-do run } */
+/* { dg-options "-mlsx -w -fno-strict-aliasing" } */
+#include "../simd_correctness_check.h"
+#include 
+
+int
+main ()
+{
+  __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result;
+  __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result;
+  __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result;
+
+  int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail;
+  long int long_op0, long_op1, long_op2, lont_out, lont_result;
+  long int long_int_out, long_int_result;
+  unsigned int unsigned_int_out, unsigned_int_result;
+  unsigned long int unsigned_long_int_out, unsigned_long_int_result;
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vmax_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vmax_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vmax_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x7fff7fff7fff7fff;
+  *((unsigned long *)&__m128i_op0[0]) = 0x0001003f;
+  *((unsigned long *)&__m128i_op1[1]) = 0x;
+  *((unsigned long *)&__m128i_op1[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x7f007f007f007f00;
+  *((unsigned long *)&__m128i_result[0]) = 0x0001003f;
+  __m128i_out = __lsx_vmax_b (__m128i_op0, __m128i_op1);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x0001;
+  *((unsigned long *)&__m128i_op1[1]) = 0xf0001fff;
+  *((unsigned long *)&__m128i_op1[0]) = 0xf0001fff;
+  *((unsigned long *)&__m128i_result[1]) = 0x1f00;
+  *(

[PATCH v4 18/23] LoongArch: Add tests for SX vector floating point arithmetic instructions.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lsx/lsx-vfadd_d.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vfadd_s.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vfclass_d.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vfclass_s.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vflogb_d.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vflogb_s.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vfmax_d.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vfmax_s.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vfmaxa_d.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vfmaxa_s.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vfsqrt_d.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vfsqrt_s.c: New test.
---
 .../loongarch/vector/lsx/lsx-vfadd_d.c| 407 +++
 .../loongarch/vector/lsx/lsx-vfadd_s.c| 470 ++
 .../loongarch/vector/lsx/lsx-vfclass_d.c  |  83 
 .../loongarch/vector/lsx/lsx-vfclass_s.c  |  74 +++
 .../loongarch/vector/lsx/lsx-vflogb_d.c   |  76 +++
 .../loongarch/vector/lsx/lsx-vflogb_s.c   | 185 +++
 .../loongarch/vector/lsx/lsx-vfmax_d.c| 200 
 .../loongarch/vector/lsx/lsx-vfmax_s.c| 335 +
 .../loongarch/vector/lsx/lsx-vfmaxa_d.c   | 155 ++
 .../loongarch/vector/lsx/lsx-vfmaxa_s.c   | 230 +
 .../loongarch/vector/lsx/lsx-vfsqrt_d.c   | 216 
 .../loongarch/vector/lsx/lsx-vfsqrt_s.c   | 372 ++
 12 files changed, 2803 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfadd_d.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfadd_s.c
 create mode 100644 
gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfclass_d.c
 create mode 100644 
gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfclass_s.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vflogb_d.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vflogb_s.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmax_d.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmax_s.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmaxa_d.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmaxa_s.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfsqrt_d.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfsqrt_s.c

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfadd_d.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfadd_d.c
new file mode 100644
index 000..7ffbd385ee0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfadd_d.c
@@ -0,0 +1,407 @@
+/* { dg-do run } */
+/* { dg-options "-mlsx -w -fno-strict-aliasing" } */
+#include "../simd_correctness_check.h"
+#include 
+
+int
+main ()
+{
+  __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result;
+  __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result;
+  __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result;
+
+  int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail;
+  long int long_op0, long_op1, long_op2, lont_out, lont_result;
+  long int long_int_out, long_int_result;
+  unsigned int unsigned_int_out, unsigned_int_result;
+  unsigned long int unsigned_long_int_out, unsigned_long_int_result;
+
+  *((unsigned long *)&__m128d_op0[1]) = 0x;
+  *((unsigned long *)&__m128d_op0[0]) = 0x;
+  *((unsigned long *)&__m128d_op1[1]) = 0x;
+  *((unsigned long *)&__m128d_op1[0]) = 0x;
+  *((unsigned long *)&__m128d_result[1]) = 0x;
+  *((unsigned long *)&__m128d_result[0]) = 0x;
+  __m128d_out = __lsx_vfadd_d (__m128d_op0, __m128d_op1);
+  ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out);
+
+  *((unsigned long *)&__m128d_op0[1]) = 0x;
+  *((unsigned long *)&__m128d_op0[0]) = 0xfea8ff44;
+  *((unsigned long *)&__m128d_op1[1]) = 0x2020202020202020;
+  *((unsigned long *)&__m128d_op1[0]) = 0x2020202020202020;
+  *((unsigned long *)&__m128d_result[1]) = 0x2020202020202020;
+  *((unsigned long *)&__m128d_result[0]) = 0x2020202020202020;
+  __m128d_out = __lsx_vfadd_d (__m128d_op0, __m128d_op1);
+  ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out);
+
+  *((unsigned long *)&__m128d_op0[1]) = 0x1000100010001000;
+  *((unsigned long *)&__m128d_op0[0]) = 0x1000100010001000;
+  *((unsigned long *)&__m128d_op1[1]) = 0x;
+  *((unsigned long *)&__m128d_op1[0]) = 0x;
+  *((unsigned long *)&__m128d_result[1]) = 0x1000100010001000;
+  *((unsigned long *)&__m128d_result[0]) = 0x1000100010001000;
+  __m128d_out = __lsx_vfadd_d (__m128d_op0, __m128d_op1);
+  ASSERTEQ_

[PATCH v4 11/23] LoongArch: Add tests for SX vector vexth/vextl/vldi/vneg/vsat instructions.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lsx/lsx-vexth-1.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vexth-2.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vextl-1.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vextl-2.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vldi.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vneg.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vsat-1.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vsat-2.c: New test.
---
 .../loongarch/vector/lsx/lsx-vexth-1.c| 342 ++
 .../loongarch/vector/lsx/lsx-vexth-2.c| 182 ++
 .../loongarch/vector/lsx/lsx-vextl-1.c|  83 +
 .../loongarch/vector/lsx/lsx-vextl-2.c|  83 +
 .../loongarch/vector/lsx/lsx-vldi.c   |  61 
 .../loongarch/vector/lsx/lsx-vneg.c   | 321 
 .../loongarch/vector/lsx/lsx-vsat-1.c | 231 
 .../loongarch/vector/lsx/lsx-vsat-2.c | 272 ++
 8 files changed, 1575 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vexth-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vexth-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vextl-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vextl-2.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vldi.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vneg.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsat-1.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vsat-2.c

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vexth-1.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vexth-1.c
new file mode 100644
index 000..f6390800d82
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vexth-1.c
@@ -0,0 +1,342 @@
+/* { dg-do run } */
+/* { dg-options "-mlsx -w -fno-strict-aliasing" } */
+#include "../simd_correctness_check.h"
+#include 
+
+int
+main ()
+{
+  __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result;
+  __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result;
+  __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result;
+
+  int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail;
+  long int long_op0, long_op1, long_op2, lont_out, lont_result;
+  long int long_int_out, long_int_result;
+  unsigned int unsigned_int_out, unsigned_int_result;
+  unsigned long int unsigned_long_int_out, unsigned_long_int_result;
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vexth_h_b (__m128i_op0);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x7fff;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x007f;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vexth_h_b (__m128i_op0);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vexth_h_b (__m128i_op0);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vexth_h_b (__m128i_op0);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0xf909;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vexth_h_b (__m128i_op0);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0x;
+  *((unsigned long *)&__m128i_result[1]) = 0x;
+  *((unsigned long *)&__m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vexth_h_b (__m128i_op0);
+  ASSERTEQ_64 (__LINE__, __m128i_result, __m128i_out);
+
+  *((unsigned long *)&__m128i_op0[1]) = 0x;
+  *((unsigned long *)&__m128i_op0[0]) = 0xff01ff01;
+  *((unsigned long *)&__m128i

[PATCH v4 22/23] LoongArch: Add tests for SX vector vand/vandi/vandn/vor/vori/vnor/ vnori/vxor/vxori instructions.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lsx/lsx-vand.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vandi.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vandn.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vnor.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vnori.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vor.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vori.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vorn.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vxor.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vxori.c: New test.
---
 .../loongarch/vector/lsx/lsx-vand.c   | 159 
 .../loongarch/vector/lsx/lsx-vandi.c  |  67 +++
 .../loongarch/vector/lsx/lsx-vandn.c  | 129 +
 .../loongarch/vector/lsx/lsx-vnor.c   | 109 +++
 .../loongarch/vector/lsx/lsx-vnori.c  |  91 ++
 .../gcc.target/loongarch/vector/lsx/lsx-vor.c | 169 ++
 .../loongarch/vector/lsx/lsx-vori.c   | 123 +
 .../loongarch/vector/lsx/lsx-vorn.c   | 109 +++
 .../loongarch/vector/lsx/lsx-vxor.c   |  79 
 .../loongarch/vector/lsx/lsx-vxori.c  |  67 +++
 10 files changed, 1102 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vand.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vandi.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vandn.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vnor.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vnori.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vor.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vori.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vorn.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vxor.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vxori.c

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vand.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vand.c
new file mode 100644
index 000..1597749b546
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vand.c
@@ -0,0 +1,159 @@
+/* { dg-do run } */
+/* { dg-options "-mlsx -w -fno-strict-aliasing" } */
+#include "../simd_correctness_check.h"
+#include 
+
+int main ()
+{
+  __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result;
+  __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result;
+  __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result;
+
+  int int_op0, int_op1, int_op2, int_out, int_result, i=1, fail;
+  long int long_op0, long_op1, long_op2, lont_out, lont_result;
+  long int long_int_out, long_int_result;
+  unsigned int unsigned_int_out, unsigned_int_result;
+  unsigned long int unsigned_long_int_out, unsigned_long_int_result;
+
+  *((unsigned long*)& __m128i_op0[1]) = 0x;
+  *((unsigned long*)& __m128i_op0[0]) = 0x;
+  *((unsigned long*)& __m128i_op1[1]) = 0x;
+  *((unsigned long*)& __m128i_op1[0]) = 0x;
+  *((unsigned long*)& __m128i_result[1]) = 0x;
+  *((unsigned long*)& __m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vand_v(__m128i_op0,__m128i_op1);
+  ASSERTEQ_64(__LINE__, __m128i_result, __m128i_out);
+
+
+  *((unsigned long*)& __m128i_op0[1]) = 0x;
+  *((unsigned long*)& __m128i_op0[0]) = 0x;
+  *((unsigned long*)& __m128i_op1[1]) = 0x03574e3a62407e03;
+  *((unsigned long*)& __m128i_op1[0]) = 0x0101;
+  *((unsigned long*)& __m128i_result[1]) = 0x03574e3a62407e03;
+  *((unsigned long*)& __m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vand_v(__m128i_op0,__m128i_op1);
+  ASSERTEQ_64(__LINE__, __m128i_result, __m128i_out);
+
+
+  *((unsigned long*)& __m128i_op0[1]) = 0x;
+  *((unsigned long*)& __m128i_op0[0]) = 0x;
+  *((unsigned long*)& __m128i_op1[1]) = 0x001f001f;
+  *((unsigned long*)& __m128i_op1[0]) = 0x001f001f;
+  *((unsigned long*)& __m128i_result[1]) = 0x001f001f;
+  *((unsigned long*)& __m128i_result[0]) = 0x001f001f;
+  __m128i_out = __lsx_vand_v(__m128i_op0,__m128i_op1);
+  ASSERTEQ_64(__LINE__, __m128i_result, __m128i_out);
+
+
+  *((unsigned long*)& __m128i_op0[1]) = 0x003dffc2;
+  *((unsigned long*)& __m128i_op0[0]) = 0x003dffc2;
+  *((unsigned long*)& __m128i_op1[1]) = 0x0008;
+  *((unsigned long*)& __m128i_op1[0]) = 0x;
+  *((unsigned long*)& __m128i_result[1]) = 0x;
+  *((unsigned long*)& __m128i_result[0]) = 0x;
+  __m128i_out = __lsx_vand_v(__m128i_op0,__m128i_op1);
+  ASSERTEQ_64(_

[PATCH v4 23/23] LoongArch: Add tests for SX vector vfmadd/vfnmadd/vld/vst instructions.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lsx/lsx-vfmadd_d.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vfmadd_s.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vfnmadd_d.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vfnmadd_s.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vld.c: New test.
* gcc.target/loongarch/vector/lsx/lsx-vst.c: New test.
---
 .../loongarch/vector/lsx/lsx-vfmadd_d.c   | 251 
 .../loongarch/vector/lsx/lsx-vfmadd_s.c   | 381 ++
 .../loongarch/vector/lsx/lsx-vfnmadd_d.c  | 196 +
 .../loongarch/vector/lsx/lsx-vfnmadd_s.c  | 381 ++
 .../gcc.target/loongarch/vector/lsx/lsx-vld.c |  62 +++
 .../gcc.target/loongarch/vector/lsx/lsx-vst.c |  70 
 6 files changed, 1341 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmadd_d.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmadd_s.c
 create mode 100644 
gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfnmadd_d.c
 create mode 100644 
gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfnmadd_s.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vld.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vst.c

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmadd_d.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmadd_d.c
new file mode 100644
index 000..c5de1ac7ae9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-vfmadd_d.c
@@ -0,0 +1,251 @@
+/* { dg-do run } */
+/* { dg-options "-mlsx -w -fno-strict-aliasing" } */
+#include "../simd_correctness_check.h"
+#include 
+
+int
+main ()
+{
+  __m128i __m128i_op0, __m128i_op1, __m128i_op2, __m128i_out, __m128i_result;
+  __m128 __m128_op0, __m128_op1, __m128_op2, __m128_out, __m128_result;
+  __m128d __m128d_op0, __m128d_op1, __m128d_op2, __m128d_out, __m128d_result;
+
+  int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail;
+  long int long_op0, long_op1, long_op2, lont_out, lont_result;
+  long int long_int_out, long_int_result;
+  unsigned int unsigned_int_out, unsigned_int_result;
+  unsigned long int unsigned_long_int_out, unsigned_long_int_result;
+
+  *((unsigned long *)&__m128d_op0[1]) = 0x;
+  *((unsigned long *)&__m128d_op0[0]) = 0x;
+  *((unsigned long *)&__m128d_op1[1]) = 0x8a228acac14e440a;
+  *((unsigned long *)&__m128d_op1[0]) = 0xc77c47cdc0f16549;
+  *((unsigned long *)&__m128d_op2[1]) = 0xd24271c4;
+  *((unsigned long *)&__m128d_op2[0]) = 0x2711bad1e8e309ed;
+  *((unsigned long *)&__m128d_result[1]) = 0xd24271c4;
+  *((unsigned long *)&__m128d_result[0]) = 0x2711bad1e8e309ed;
+  __m128d_out = __lsx_vfmadd_d (__m128d_op0, __m128d_op1, __m128d_op2);
+  ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out);
+
+  *((unsigned long *)&__m128d_op0[1]) = 0x;
+  *((unsigned long *)&__m128d_op0[0]) = 0x;
+  *((unsigned long *)&__m128d_op1[1]) = 0x;
+  *((unsigned long *)&__m128d_op1[0]) = 0x;
+  *((unsigned long *)&__m128d_op2[1]) = 0x;
+  *((unsigned long *)&__m128d_op2[0]) = 0x;
+  *((unsigned long *)&__m128d_result[1]) = 0x;
+  *((unsigned long *)&__m128d_result[0]) = 0x;
+  __m128d_out = __lsx_vfmadd_d (__m128d_op0, __m128d_op1, __m128d_op2);
+  ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out);
+
+  *((unsigned long *)&__m128d_op0[1]) = 0x04040383;
+  *((unsigned long *)&__m128d_op0[0]) = 0xe0001fff;
+  *((unsigned long *)&__m128d_op1[1]) = 0x04040383;
+  *((unsigned long *)&__m128d_op1[0]) = 0xe0001fff;
+  *((unsigned long *)&__m128d_op2[1]) = 0x0101;
+  *((unsigned long *)&__m128d_op2[0]) = 0x00010001;
+  *((unsigned long *)&__m128d_result[1]) = 0x0101;
+  *((unsigned long *)&__m128d_result[0]) = 0xe0001fff;
+  __m128d_out = __lsx_vfmadd_d (__m128d_op0, __m128d_op1, __m128d_op2);
+  ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out);
+
+  *((unsigned long *)&__m128d_op0[1]) = 0x;
+  *((unsigned long *)&__m128d_op0[0]) = 0x;
+  *((unsigned long *)&__m128d_op1[1]) = 0x003f80b0;
+  *((unsigned long *)&__m128d_op1[0]) = 0xff80;
+  *((unsigned long *)&__m128d_op2[1]) = 0x;
+  *((unsigned long *)&__m128d_op2[0]) = 0x;
+  *((unsigned long *)&__m128d_result[1]) = 0x;
+  *((unsigned long *)&__m128d_result[0]) = 0x;
+  __m128d_out = __lsx_vfmadd_d (__m128d_op0, __m128d_op1, __m128d_op2);
+  ASSERTEQ_64 (__LINE__, __m128d_result, __m128d_out);
+
+  *((unsigned long *)&__m128d_op0[1]) = 0x;
+  *((unsigned long *)&__m128d_op0[0]) = 0x00802000;
+  *((unsigned long *)&__m128d_op1[1]) = 0x00401000;
+  *((unsi

[PATCH v4 00/22] Added support for ASX vector instructions.

[Xiaolong Chen]

  In order to better test the function of the vector instruction, the 256
bit test cases are further split according to the function of the instruction.


Xiaolong Chen (22):
  LoongArch: Add tests for ASX vector xvadd/xvadda/xvaddi/xvaddwev/
xvaddwodxvsadd instructions.
  LoongArch: Add tests for ASX vector xvhadd/xvhaddw/xvmaddwev/xvmaddwod
instructions.
  LoongArch: Add tests for ASX vector subtraction instructions.
  LoongArch: Add tests for ASX vector xvmul/xvmod/xvdiv instructions.
  LoongArch: Add tests for ASX vector xvmax/xvmaxi/xvmin/xvmini
instructions.
  LoongArch: Add tests for ASX vector
xvldi/xvmskgez/xvmskltz/xvmsknz/xvmuh /xvsigncov instructions.
  LoongArch: Add tests for ASX vector xvand/xvandi/xvandn/xvor/xvori/
xvnor/xvnori/xvxor/xvxori instructions.
  LoongArch: Add tests for ASX vector xvsll/xvsrl instructions.
  LoongArch: Add tests for ASX vector xvextl/xvsra/xvsran/xvsrarn
instructions.
  LoongArch: Add tests for ASX vector
xvssran/xvssrani/xvssrarn/xvssrarni/xvssrln/
xvssrlni/xvssrlrn/xvssrlrni instructions.
  LoongArch: Add tests for ASX vector
xvbitclr/xvbitclri/xvbitrev/xvbitrevi/
xvbitsel/xvbitseli/xvbitset/xvbitseti/xvclo/xvclz/xvpcnt
instructions.
  LoongArch: Add tests for ASX builtin functions.
  LoongArch: Add tests for ASX xvldrepl/xvstelm instruction generation.
  LoongArch: Add tests for ASX vector floating-point operation
instruction.
  LoongArch: Add tests for ASX vector floating-point conversion
instruction.
  LoongArch: Add tests for ASX vector comparison and selection
instruction.
  LoongArch: Add tests for ASX vector xvfnmadd/xvfrstp/xvfstpi/xvhsubw/
xvmsub/xvrotr/xvrotri/xvld/xvst instructions.
  LoongArch: Add tests for ASX vector
xvabsd/xvavg/xvavgr/xvbsll/xvbsrl/xvneg/ xvsat instructions.
  LoongArch: Add tests for ASX vector
xvfcmp{caf/ceq/cle/clt/cne/cor/cun} instructions.
  LoongArch: Add tests for ASX vector
xvfcmp{saf/seq/sle/slt/sne/sor/sun} instructions.
  LoongArch: Add tests for ASX vector
xvext2xv/xvexth/xvextins/xvilvh/xvilvl/xvinsgr2vr/
xvinsve0/xvprem/xvpremi instructions.
  LoongArch: Add tests for ASX vector
xvpackev/xvpackod/xvpickev/xvpickod/
xvpickve2gr/xvreplgr2vr/xvreplve/xvreplve0/xvreplvei/xvshuf4i/xvshuf
instructions.

 .../loongarch/vector/lasx/lasx-builtin.c  | 1509 
 .../loongarch/vector/lasx/lasx-xvabsd-1.c |  485 +
 .../loongarch/vector/lasx/lasx-xvabsd-2.c |  650 +++
 .../loongarch/vector/lasx/lasx-xvadd.c|  725 
 .../loongarch/vector/lasx/lasx-xvadda.c   |  785 
 .../loongarch/vector/lasx/lasx-xvaddi.c   |  427 +
 .../loongarch/vector/lasx/lasx-xvaddwev-1.c   |  740 
 .../loongarch/vector/lasx/lasx-xvaddwev-2.c   |  485 +
 .../loongarch/vector/lasx/lasx-xvaddwev-3.c   |  515 ++
 .../loongarch/vector/lasx/lasx-xvaddwod-1.c   |  530 ++
 .../loongarch/vector/lasx/lasx-xvaddwod-2.c   |  560 ++
 .../loongarch/vector/lasx/lasx-xvaddwod-3.c   |  485 +
 .../loongarch/vector/lasx/lasx-xvand.c|  155 ++
 .../loongarch/vector/lasx/lasx-xvandi.c   |  196 ++
 .../loongarch/vector/lasx/lasx-xvandn.c   |  125 ++
 .../loongarch/vector/lasx/lasx-xvavg-1.c  |  680 +++
 .../loongarch/vector/lasx/lasx-xvavg-2.c  |  560 ++
 .../loongarch/vector/lasx/lasx-xvavgr-1.c |  770 
 .../loongarch/vector/lasx/lasx-xvavgr-2.c |  650 +++
 .../loongarch/vector/lasx/lasx-xvbitclr.c |  635 +++
 .../loongarch/vector/lasx/lasx-xvbitclri.c|  515 ++
 .../loongarch/vector/lasx/lasx-xvbitrev.c |  650 +++
 .../loongarch/vector/lasx/lasx-xvbitrevi.c|  317 
 .../loongarch/vector/lasx/lasx-xvbitsel.c |  134 ++
 .../loongarch/vector/lasx/lasx-xvbitseli.c|  185 ++
 .../loongarch/vector/lasx/lasx-xvbitset.c |  620 +++
 .../loongarch/vector/lasx/lasx-xvbitseti.c|  405 +
 .../loongarch/vector/lasx/lasx-xvbsll_v.c |  130 ++
 .../loongarch/vector/lasx/lasx-xvbsrl_v.c |   64 +
 .../loongarch/vector/lasx/lasx-xvclo.c|  449 +
 .../loongarch/vector/lasx/lasx-xvclz.c|  504 ++
 .../loongarch/vector/lasx/lasx-xvdiv-1.c  |  485 +
 .../loongarch/vector/lasx/lasx-xvdiv-2.c  |  500 ++
 .../loongarch/vector/lasx/lasx-xvext2xv-1.c   |  515 ++
 .../loongarch/vector/lasx/lasx-xvext2xv-2.c   |  669 +++
 .../loongarch/vector/lasx/lasx-xvexth-1.c |  350 
 .../loongarch/vector/lasx/lasx-xvexth-2.c |  592 ++
 .../loongarch/vector/lasx/lasx-xvextl-1.c |   86 +
 .../loongarch/vector/lasx/lasx-xvextl-2.c |  163 ++
 .../loongarch/vector/lasx/lasx-xvextrins.c|  515 ++
 .../loongarch/vector/lasx/lasx-xvfadd_d.c |  545 ++
 .../loongarch/vector/lasx/lasx-xvfadd_s.c |  911 ++
 .../loongarch/vector/lasx/lasx-xvfclass_d.c   |  152 ++
 .../loongarch/vector/lasx/lasx-xvfclass_s.c   |   95 +
 .../loongarch/vector

[PATCH v4 07/22] LoongArch: Add tests for ASX vector xvand/xvandi/xvandn/xvor/xvori/ xvnor/xvnori/xvxor/xvxori instructions.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lasx/lasx-xvand.c: New test.
* gcc.target/loongarch/vector/lasx/lasx-xvandi.c: New test.
* gcc.target/loongarch/vector/lasx/lasx-xvandn.c: New test.
* gcc.target/loongarch/vector/lasx/lasx-xvnor.c: New test.
* gcc.target/loongarch/vector/lasx/lasx-xvnori.c: New test.
* gcc.target/loongarch/vector/lasx/lasx-xvor.c: New test.
* gcc.target/loongarch/vector/lasx/lasx-xvori.c: New test.
* gcc.target/loongarch/vector/lasx/lasx-xvorn.c: New test.
* gcc.target/loongarch/vector/lasx/lasx-xvxor.c: New test.
* gcc.target/loongarch/vector/lasx/lasx-xvxori.c: New test.
---
 .../loongarch/vector/lasx/lasx-xvand.c| 155 +++
 .../loongarch/vector/lasx/lasx-xvandi.c   | 196 ++
 .../loongarch/vector/lasx/lasx-xvandn.c   | 125 +
 .../loongarch/vector/lasx/lasx-xvnor.c| 170 
 .../loongarch/vector/lasx/lasx-xvnori.c   | 152 +++
 .../loongarch/vector/lasx/lasx-xvor.c | 215 +++
 .../loongarch/vector/lasx/lasx-xvori.c| 141 ++
 .../loongarch/vector/lasx/lasx-xvorn.c| 245 ++
 .../loongarch/vector/lasx/lasx-xvxor.c| 185 +
 .../loongarch/vector/lasx/lasx-xvxori.c   | 163 
 10 files changed, 1747 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvand.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvandi.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvandn.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvnor.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvnori.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvor.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvori.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvorn.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvxor.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvxori.c

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvand.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvand.c
new file mode 100644
index 000..e485786dd3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvand.c
@@ -0,0 +1,155 @@
+/* { dg-do run } */
+/* { dg-options "-mlasx -w -fno-strict-aliasing" } */
+#include "../simd_correctness_check.h"
+#include 
+
+int
+main ()
+{
+  __m256i __m256i_op0, __m256i_op1, __m256i_op2, __m256i_out, __m256i_result;
+  __m256 __m256_op0, __m256_op1, __m256_op2, __m256_out, __m256_result;
+  __m256d __m256d_op0, __m256d_op1, __m256d_op2, __m256d_out, __m256d_result;
+
+  int int_op0, int_op1, int_op2, int_out, int_result, i = 1, fail;
+  long int long_op0, long_op1, long_op2, lont_out, lont_result;
+  long int long_int_out, long_int_result;
+  unsigned int unsigned_int_out, unsigned_int_result;
+  unsigned long int unsigned_long_int_out, unsigned_long_int_result;
+
+  *((unsigned long *)&__m256i_op0[3]) = 0x;
+  *((unsigned long *)&__m256i_op0[2]) = 0x;
+  *((unsigned long *)&__m256i_op0[1]) = 0x;
+  *((unsigned long *)&__m256i_op0[0]) = 0x;
+  *((unsigned long *)&__m256i_op1[3]) = 0x0010001000100010;
+  *((unsigned long *)&__m256i_op1[2]) = 0x0010001000100010;
+  *((unsigned long *)&__m256i_op1[1]) = 0x0010001000100010;
+  *((unsigned long *)&__m256i_op1[0]) = 0x0010001000100010;
+  *((unsigned long *)&__m256i_result[3]) = 0x;
+  *((unsigned long *)&__m256i_result[2]) = 0x;
+  *((unsigned long *)&__m256i_result[1]) = 0x;
+  *((unsigned long *)&__m256i_result[0]) = 0x;
+  __m256i_out = __lasx_xvand_v (__m256i_op0, __m256i_op1);
+  ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out);
+
+  *((unsigned long *)&__m256i_op0[3]) = 0x;
+  *((unsigned long *)&__m256i_op0[2]) = 0x;
+  *((unsigned long *)&__m256i_op0[1]) = 0x;
+  *((unsigned long *)&__m256i_op0[0]) = 0x;
+  *((unsigned long *)&__m256i_op1[3]) = 0x;
+  *((unsigned long *)&__m256i_op1[2]) = 0x;
+  *((unsigned long *)&__m256i_op1[1]) = 0x;
+  *((unsigned long *)&__m256i_op1[0]) = 0x;
+  *((unsigned long *)&__m256i_result[3]) = 0x;
+  *((unsigned long *)&__m256i_result[2]) = 0x;
+  *((unsigned long *)&__m256i_result[1]) = 0x;
+  *((unsigned long *)&__m256i_result[0]) = 0x;
+  __m256i_out = __lasx_xvand_v (__m256i_op0, __m256i_op1);
+  ASSERTEQ_64 (__LINE__, __m256i_result, __m256i_out);
+
+  *((unsigned long *)&__m256i_op0[3]) = 0x;
+  *((unsigned long *)&__m256i_op0[2

[PATCH v4 13/22] LoongArch: Add tests for ASX xvldrepl/xvstelm instruction generation.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lasx/lasx-xvldrepl.c: New test.
* gcc.target/loongarch/vector/lasx/lasx-xvstelm.c: New test.
---
 .../loongarch/vector/lasx/lasx-xvldrepl.c| 16 
 .../loongarch/vector/lasx/lasx-xvstelm.c | 14 ++
 2 files changed, 30 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvldrepl.c
 create mode 100644 
gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvstelm.c

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvldrepl.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvldrepl.c
new file mode 100644
index 000..10556795119
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvldrepl.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mlasx" } */
+/* { dg-final { scan-assembler-times "xvldrepl.w" 2} } */
+
+#define N 258
+
+float a[N], b[N], c[N];
+
+void
+test ()
+{
+  for (int i = 0; i < 256; i++)
+{
+  a[i] = c[0] * b[i] + c[1];
+}
+}
diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvstelm.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvstelm.c
new file mode 100644
index 000..1a7b0e86f8b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvstelm.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mlasx" } */
+/* { dg-final { scan-assembler-times "xvstelm.w" 8} } */
+
+#define LEN 256
+
+float a[LEN], b[LEN], c[LEN];
+
+void
+test ()
+{
+  for (int i = 0; i < LEN; i += 2)
+a[i] = b[i] + c[i];
+}
-- 
2.20.1

[PATCH v4 12/22] LoongArch: Add tests for ASX builtin functions.

[Xiaolong Chen]

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/vector/lasx/lasx-builtin.c: New test.
---
 .../loongarch/vector/lasx/lasx-builtin.c  | 1509 +
 1 file changed, 1509 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c

diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c 
b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c
new file mode 100644
index 000..ecb8d639bdd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-builtin.c
@@ -0,0 +1,1509 @@
+/* Test builtins for LOONGARCH LASX ASE instructions */
+/* { dg-do compile } */
+/* { dg-options "-mlasx" } */
+/* { dg-final { scan-assembler-times "lasx_xvsll_b:.*xvsll\\.b.*lasx_xvsll_b" 
1 } } */
+/* { dg-final { scan-assembler-times "lasx_xvsll_h:.*xvsll\\.h.*lasx_xvsll_h" 
1 } } */
+/* { dg-final { scan-assembler-times "lasx_xvsll_w:.*xvsll\\.w.*lasx_xvsll_w" 
1 } } */
+/* { dg-final { scan-assembler-times "lasx_xvsll_d:.*xvsll\\.d.*lasx_xvsll_d" 
1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvslli_b:.*xvslli\\.b.*lasx_xvslli_b" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvslli_h:.*xvslli\\.h.*lasx_xvslli_h" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvslli_w:.*xvslli\\.w.*lasx_xvslli_w" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvslli_d:.*xvslli\\.d.*lasx_xvslli_d" 1 } } */
+/* { dg-final { scan-assembler-times "lasx_xvsra_b:.*xvsra\\.b.*lasx_xvsra_b" 
1 } } */
+/* { dg-final { scan-assembler-times "lasx_xvsra_h:.*xvsra\\.h.*lasx_xvsra_h" 
1 } } */
+/* { dg-final { scan-assembler-times "lasx_xvsra_w:.*xvsra\\.w.*lasx_xvsra_w" 
1 } } */
+/* { dg-final { scan-assembler-times "lasx_xvsra_d:.*xvsra\\.d.*lasx_xvsra_d" 
1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrai_b:.*xvsrai\\.b.*lasx_xvsrai_b" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrai_h:.*xvsrai\\.h.*lasx_xvsrai_h" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrai_w:.*xvsrai\\.w.*lasx_xvsrai_w" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrai_d:.*xvsrai\\.d.*lasx_xvsrai_d" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrar_b:.*xvsrar\\.b.*lasx_xvsrar_b" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrar_h:.*xvsrar\\.h.*lasx_xvsrar_h" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrar_w:.*xvsrar\\.w.*lasx_xvsrar_w" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrar_d:.*xvsrar\\.d.*lasx_xvsrar_d" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrari_b:.*xvsrari\\.b.*lasx_xvsrari_b" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrari_h:.*xvsrari\\.h.*lasx_xvsrari_h" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrari_w:.*xvsrari\\.w.*lasx_xvsrari_w" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrari_d:.*xvsrari\\.d.*lasx_xvsrari_d" 1 } } */
+/* { dg-final { scan-assembler-times "lasx_xvsrl_b:.*xvsrl\\.b.*lasx_xvsrl_b" 
1 } } */
+/* { dg-final { scan-assembler-times "lasx_xvsrl_h:.*xvsrl\\.h.*lasx_xvsrl_h" 
1 } } */
+/* { dg-final { scan-assembler-times "lasx_xvsrl_w:.*xvsrl\\.w.*lasx_xvsrl_w" 
1 } } */
+/* { dg-final { scan-assembler-times "lasx_xvsrl_d:.*xvsrl\\.d.*lasx_xvsrl_d" 
1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrli_b:.*xvsrli\\.b.*lasx_xvsrli_b" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrli_h:.*xvsrli\\.h.*lasx_xvsrli_h" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrli_w:.*xvsrli\\.w.*lasx_xvsrli_w" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrli_d:.*xvsrli\\.d.*lasx_xvsrli_d" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrlr_b:.*xvsrlr\\.b.*lasx_xvsrlr_b" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrlr_h:.*xvsrlr\\.h.*lasx_xvsrlr_h" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrlr_w:.*xvsrlr\\.w.*lasx_xvsrlr_w" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrlr_d:.*xvsrlr\\.d.*lasx_xvsrlr_d" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrlri_b:.*xvsrlri\\.b.*lasx_xvsrlri_b" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrlri_h:.*xvsrlri\\.h.*lasx_xvsrlri_h" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrlri_w:.*xvsrlri\\.w.*lasx_xvsrlri_w" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvsrlri_d:.*xvsrlri\\.d.*lasx_xvsrlri_d" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvbitclr_b:.*xvbitclr\\.b.*lasx_xvbitclr_b" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvbitclr_h:.*xvbitclr\\.h.*lasx_xvbitclr_h" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvbitclr_w:.*xvbitclr\\.w.*lasx_xvbitclr_w" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvbitclr_d:.*xvbitclr\\.d.*lasx_xvbitclr_d" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvbitclri_b:.*xvbitclri\\.b.*lasx_xvbitclri_b" 1 } } */
+/* { dg-final { scan-assembler-times 
"lasx_xvbitclri_h:.*xvbitclri\\.h.*lasx_xvbitclri_h" 1 } } */
+/* { dg-final { scan-assembler-times 
"