[PATCH 1/4] Fix typo in config/sparc/sol2.h

2017-05-17 Thread Sheldon Lobo
* config/sparc/sol2.h: Fix a ASM_CPU32_DEFAULT_SPEC typo.
---
 gcc/config/sparc/sol2.h |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/gcc/config/sparc/sol2.h b/gcc/config/sparc/sol2.h
index db24ca3..8a50bfe 100644
--- a/gcc/config/sparc/sol2.h
+++ b/gcc/config/sparc/sol2.h
@@ -169,7 +169,7 @@ along with GCC; see the file COPYING3.  If not see
 #undef CPP_CPU64_DEFAULT_SPEC
 #define CPP_CPU64_DEFAULT_SPEC ""
 #undef ASM_CPU32_DEFAULT_SPEC
-#define ASM_CPU32_DEFAUILT_SPEC AS_SPARC32_FLAG AS_NIAGARA7_FLAG
+#define ASM_CPU32_DEFAULT_SPEC AS_SPARC32_FLAG AS_NIAGARA7_FLAG
 #undef ASM_CPU64_DEFAULT_SPEC
 #define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG AS_NIAGARA7_FLAG
 #endif
-- 
1.7.1



[PATCH 0/4] Minor SPARC T4 and M7 fixes and additions

2017-05-17 Thread Sheldon Lobo
This patch series contains small fixes and updates for the SPARC 
platform.

Patch 1 fixes a small typo in sol2.h

Patch 2 sets a branch cost for the SPARC T4 processor.

Patch 3 sets a branch cost for the SPARC M7 processor.

Patch 4 changes the function alignment for the M7 processor from 4 to 8 bytes.

Thanks!

Sheldon Lobo (4):
  Fix typo in config/sparc/sol2.h
  Add a branch cost for SPARC T4.
  Add a branch cost for SPARC M7.
  Set function alignment for M7 to 8 bytes.

 gcc/config/sparc/sol2.h |2 +-
 gcc/config/sparc/sparc.c|   13 -
 gcc/config/sparc/sparc.h|   11 +--
 gcc/testsuite/gcc.target/sparc/niagara7-align.c |4 
 4 files changed, 22 insertions(+), 8 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/sparc/niagara7-align.c



[PATCH 4/4] Set function alignment for M7 to 8 bytes.

2017-05-17 Thread Sheldon Lobo
* config/sparc/sparc.c (sparc_option_override): Set function
alignment for -mcpu=niagara7 to 64 to match the I$ line.
* testsuite/gcc.target/sparc/niagara7-align.c: Test case with
-mcpu=niagara7 -falign-functions.
---
 gcc/config/sparc/sparc.c|   13 -
 gcc/testsuite/gcc.target/sparc/niagara7-align.c |4 
 2 files changed, 12 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/sparc/niagara7-align.c

diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 8277496..6dfb269 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -1528,15 +1528,18 @@ sparc_option_override (void)
 target_flags |= MASK_LRA;
 
   /* Supply a default value for align_functions.  */
-  if (align_functions == 0
-  && (sparc_cpu == PROCESSOR_ULTRASPARC
+  if (align_functions == 0)
+{
+  if (sparc_cpu == PROCESSOR_ULTRASPARC
  || sparc_cpu == PROCESSOR_ULTRASPARC3
  || sparc_cpu == PROCESSOR_NIAGARA
  || sparc_cpu == PROCESSOR_NIAGARA2
  || sparc_cpu == PROCESSOR_NIAGARA3
- || sparc_cpu == PROCESSOR_NIAGARA4
- || sparc_cpu == PROCESSOR_NIAGARA7))
-align_functions = 32;
+ || sparc_cpu == PROCESSOR_NIAGARA4)
+   align_functions = 32;
+  else if (sparc_cpu == PROCESSOR_NIAGARA7)
+   align_functions = 64;
+}
 
   /* Validate PCC_STRUCT_RETURN.  */
   if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
diff --git a/gcc/testsuite/gcc.target/sparc/niagara7-align.c 
b/gcc/testsuite/gcc.target/sparc/niagara7-align.c
new file mode 100644
index 000..a46aac1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/niagara7-align.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-falign-functions -mcpu=niagara7" } */
+/* { dg-final { scan-assembler "\.align 64" } } */
+void foo(void) {}
-- 
1.7.1



[PATCH 2/4] Add a branch cost for SPARC T4.

2017-05-17 Thread Sheldon Lobo
* config/sparc/sparc.h (BRANCH_COST): Set the SPARC T4 branch
latency to 2.
---
 gcc/config/sparc/sparc.h |8 ++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index 590a5f4..6277738 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -1566,7 +1566,9 @@ do {  
   \
and annulled branches insert 4 bubbles.
 
On Niagara-2 and Niagara-3, a not-taken branch costs 1 cycle whereas
-   a taken branch costs 6 cycles.  */
+   a taken branch costs 6 cycles.
+
+   The T4 Supplement specifies the branch latency at 2 cycles. */
 
 #define BRANCH_COST(speed_p, predictable_p) \
((sparc_cpu == PROCESSOR_V9 \
@@ -1579,7 +1581,9 @@ do {  
   \
 : ((sparc_cpu == PROCESSOR_NIAGARA2 \
 || sparc_cpu == PROCESSOR_NIAGARA3) \
? 5 \
-: 3
+: (sparc_cpu == PROCESSOR_NIAGARA4 \
+   ? 2 \
+: 3)
 
 /* Control the assembler format that we output.  */
 
-- 
1.7.1



[PATCH 3/4] Add a branch cost for SPARC M7.

2017-05-17 Thread Sheldon Lobo
* config/sparc/sparc.h (BRANCH_COST): Set the SPARC M7 branch
latency to 1.
---
 gcc/config/sparc/sparc.h |7 +--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index 6277738..686a3d5 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -1568,7 +1568,8 @@ do {  
   \
On Niagara-2 and Niagara-3, a not-taken branch costs 1 cycle whereas
a taken branch costs 6 cycles.
 
-   The T4 Supplement specifies the branch latency at 2 cycles. */
+   The T4 Supplement specifies the branch latency at 2 cycles.
+   The M7 Supplement specifies the branch latency at 1 cycle. */
 
 #define BRANCH_COST(speed_p, predictable_p) \
((sparc_cpu == PROCESSOR_V9 \
@@ -1583,7 +1584,9 @@ do {  
   \
? 5 \
 : (sparc_cpu == PROCESSOR_NIAGARA4 \
? 2 \
-: 3)
+: (sparc_cpu == PROCESSOR_NIAGARA7 \
+   ? 1 \
+: 3))
 
 /* Control the assembler format that we output.  */
 
-- 
1.7.1



Re: [PATCH 4/4] Set function alignment for M7 to 8 bytes.

2017-05-17 Thread Sheldon Lobo


On 05/17/2017 04:11 PM, Eric Botcazou wrote:

* config/sparc/sparc.c (sparc_option_override): Set function
alignment for -mcpu=niagara7 to 64 to match the I$ line.
* testsuite/gcc.target/sparc/niagara7-align.c: Test case with
-mcpu=niagara7 -falign-functions.


The testsuite directory has its own ChangeLog file so the second item must go
there without the testsuite/ prefix (and "New test" is enough in this case):

* gcc.target/sparc/niagara7-align.c: New test.



Thanks for the feedback!

Just so I am clear, gcc/testsuite/ChangeLog needs to be
checked into the patch (but gcc/ChangeLog is not)?

Sorry for the newbie question,
Sheldon


Re: [PATCH 4/4] Set function alignment for M7 to 8 bytes.

2017-05-19 Thread Sheldon Lobo


On 05/19/2017 02:45 PM, Eric Botcazou wrote:


This 4/4 commit needs to contain gcc/config/sparc/sparc.c, gcc/ChangeLog,
gcc/testsuite/gcc.target/sparc/niagara7-align.c and gcc/testsuite/ChangeLog.

The rule is that you put the ChangeLog entry into the ChangeLog file of the
directory where the change is made, or that of the parent directory if there
is none, recursively.  The filename in that ChangeLog file must be relative to
the directory when the ChangeLog file is.



Thanks, Eric. I did do that when I went ahead with the
'svn commit' yesterday. That is, gcc/ChangeLog and
gcc/testsuite/ChangeLog have the correct information.

The gcc source tree is as desired, but I may have made
2 inadvertent process mistakes:
* did not send a revised PATCH to gcc-patches
* made the 4 changes with 1 commit

Apologies,
Sheldon


[PATCH] Fix a SPARC -mcbcond compare-and-branch out of range failure.

2017-05-23 Thread Sheldon Lobo
The compare-and-branch distance was calculated incorrectly. This occurred
because a -mflat sibcall returned an instruction count of 2 instead of 3.
Fix sparc.md to match the output_sibcall() code in sparc.c.

* config/sparc/sparc.md: Set the number of instructions correctly
for -mflat sibcalls, to match output_sibcall().
---
 gcc/ChangeLog |5 +
 gcc/config/sparc/sparc.md |3 ++-
 2 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7ed62bc..5836ac1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2017-05-23  Sheldon Lobo  
+
+   * config/sparc/sparc.md: Set the number of instructions correctly
+   for -mflat sibcalls, to match output_sibcall().
+
 2017-05-18  Michael Meissner  
 
PR target/80510
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 29a8bcf..3f970f7 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -338,7 +338,8 @@
 (const_int 2)
 (const_int 1))
 (eq_attr "type" "sibcall")
-  (if_then_else (eq_attr "leaf_function" "true")
+  (if_then_else (ior (eq_attr "leaf_function" "true")
+ (eq_attr "flat" "true"))
 (if_then_else (eq_attr "empty_delay_slot" "true")
   (const_int 3)
   (const_int 2))
-- 
1.7.1



Re: [PATCH] Fix a SPARC -mcbcond compare-and-branch out of range failure.

2017-05-24 Thread Sheldon Lobo

Thanks for the review.

On 05/24/2017 02:52 AM, Eric Botcazou wrote:


OK for all active branches, but the ChangeLog entry should be something like:

* config/sparc/sparc.md (length): Return the correct value for -mflat
sibcalls to match output_sibcall.


Will do.



Note that we *never* use a pair of parentheses after function names.



Noted for future reference.

Thanks again,
Sheldon